* [U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode
@ 2017-06-06 9:48 Kever Yang
2017-06-06 21:09 ` Simon Glass
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Kever Yang @ 2017-06-06 9:48 UTC (permalink / raw)
To: u-boot
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
interger mode, while the '0' means the frac mode.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/clk/rockchip/clk_rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index d866d0b..8fefa19 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -62,7 +62,7 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
/* use interger mode */
- rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+ rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_clrsetreg(&pll->con0,
PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode
2017-06-06 9:48 [U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode Kever Yang
@ 2017-06-06 21:09 ` Simon Glass
2017-06-12 10:50 ` [U-Boot] " Philipp Tomsich
2017-06-21 16:12 ` Philipp Tomsich
2 siblings, 0 replies; 5+ messages in thread
From: Simon Glass @ 2017-06-06 21:09 UTC (permalink / raw)
To: u-boot
On 6 June 2017 at 03:48, Kever Yang <kever.yang@rock-chips.com> wrote:
> According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
> interger mode, while the '0' means the frac mode.
Should that be 'integer' ?
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> drivers/clk/rockchip/clk_rk3036.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Simon Glass <sjg@chromium.org>
>
> diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
> index d866d0b..8fefa19 100644
> --- a/drivers/clk/rockchip/clk_rk3036.c
> +++ b/drivers/clk/rockchip/clk_rk3036.c
> @@ -62,7 +62,7 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
> output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
>
> /* use interger mode */
and here too
> - rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
> + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
>
> rk_clrsetreg(&pll->con0,
> PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] rockchip: clk: rk3036: correct setting for pll integer mode
2017-06-06 9:48 [U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode Kever Yang
2017-06-06 21:09 ` Simon Glass
@ 2017-06-12 10:50 ` Philipp Tomsich
2017-06-21 16:12 ` Philipp Tomsich
2 siblings, 0 replies; 5+ messages in thread
From: Philipp Tomsich @ 2017-06-12 10:50 UTC (permalink / raw)
To: u-boot
On Tue, 6 Jun 2017, Kever Yang wrote:
> According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
> interger mode, while the '0' means the frac mode.
Typo: interger -> integer
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
>
> drivers/clk/rockchip/clk_rk3036.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
> index d866d0b..8fefa19 100644
> --- a/drivers/clk/rockchip/clk_rk3036.c
> +++ b/drivers/clk/rockchip/clk_rk3036.c
> @@ -62,7 +62,7 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
> output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
>
> /* use interger mode */
Same typo.
> - rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
> + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
>
> rk_clrsetreg(&pll->con0,
> PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] rockchip: clk: rk3036: correct setting for pll integer mode
2017-06-06 9:48 [U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode Kever Yang
2017-06-06 21:09 ` Simon Glass
2017-06-12 10:50 ` [U-Boot] " Philipp Tomsich
@ 2017-06-21 16:12 ` Philipp Tomsich
2 siblings, 0 replies; 5+ messages in thread
From: Philipp Tomsich @ 2017-06-21 16:12 UTC (permalink / raw)
To: u-boot
On Tue, 6 Jun 2017, Kever Yang wrote:
> According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
> interger mode, while the '0' means the frac mode.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
Applied to u-boot-rockchip/master, thanks!
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode
@ 2017-06-13 2:03 Kever Yang
0 siblings, 0 replies; 5+ messages in thread
From: Kever Yang @ 2017-06-13 2:03 UTC (permalink / raw)
To: u-boot
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.
series-version: 2
series-changes: 2
- fix tpyo interger/integer
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
drivers/clk/rockchip/clk_rk3036.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 28652df..5ecf512 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -40,7 +40,7 @@ enum {
#hz "Hz cannot be hit with PLL "\
"divisors on line " __stringify(__LINE__));
-/* use interge mode*/
+/* use integer mode*/
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
@@ -61,8 +61,8 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
- /* use interger mode */
- rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+ /* use integer mode */
+ rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_clrsetreg(&pll->con0,
PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-06-21 16:12 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-06 9:48 [U-Boot] [PATCH] rockchip: clk: rk3036: correct setting for pll integer mode Kever Yang
2017-06-06 21:09 ` Simon Glass
2017-06-12 10:50 ` [U-Boot] " Philipp Tomsich
2017-06-21 16:12 ` Philipp Tomsich
2017-06-13 2:03 [U-Boot] [PATCH] " Kever Yang
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.