* [PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write
@ 2017-06-21 19:37 Manasi Navare
2017-06-21 19:52 ` ✗ Fi.CI.BAT: warning for " Patchwork
2017-06-21 20:03 ` [PATCH] " Ville Syrjälä
0 siblings, 2 replies; 5+ messages in thread
From: Manasi Navare @ 2017-06-21 19:37 UTC (permalink / raw)
To: intel-gfx
According to the eDP spec the minimum value for panel power cycle delay
(t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle
delay field should be programmed to "+1" value. Eg: To have a delay
of 500ms this should be programmed to 6. This patch fixes the write
by adding +1 to the pp_div value so it programs the correct min
required panel power cycle delay.
Since we program it to +1 value, when we perform HW readout, this
value should subtract 1 before verifying pps state. This patch makes
this correction as well to avoid "PPS state mismatch" error.
This patch also adds a case where if the readout is 0 for the first readout,
then read it as 0, dont subtract.
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bca4ac1..089e373 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
struct intel_dp *intel_dp, struct edp_power_seq *seq)
{
u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
+ u16 pp_cycle_delay = 0;
struct pps_registers regs;
intel_pps_get_registers(dev_priv, intel_dp, ®s);
@@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
PANEL_POWER_DOWN_DELAY_SHIFT;
- if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
- u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
+ if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
+ pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
BXT_POWER_CYCLE_DELAY_SHIFT;
- if (tmp > 0)
- seq->t11_t12 = (tmp - 1) * 1000;
- else
- seq->t11_t12 = 0;
- } else {
- seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
- PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
- }
+ else
+ pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
+ PANEL_POWER_CYCLE_DELAY_SHIFT;
+ if (pp_cycle_delay > 0)
+ seq->t11_t12 = (pp_cycle_delay - 1) * 1000;
+ else
+ seq->t11_t12 = 0;
}
static void
@@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
<< BXT_POWER_CYCLE_DELAY_SHIFT);
} else {
pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
- pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
+ pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000)
<< PANEL_POWER_CYCLE_DELAY_SHIFT);
}
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✗ Fi.CI.BAT: warning for drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write
2017-06-21 19:37 [PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write Manasi Navare
@ 2017-06-21 19:52 ` Patchwork
2017-06-21 20:03 ` [PATCH] " Ville Syrjälä
1 sibling, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-06-21 19:52 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write
URL : https://patchwork.freedesktop.org/series/26175/
State : warning
== Summary ==
Series 26175v1 drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write
https://patchwork.freedesktop.org/api/1.0/series/26175/revisions/1/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
pass -> FAIL (fi-snb-2600) fdo#100007
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-kbl-7560u) fdo#100125
Test gem_ringfill:
Subgroup basic-default:
pass -> SKIP (fi-bsw-n3050)
Test kms_busy:
Subgroup basic-flip-default-b:
fail -> DMESG-WARN (fi-skl-6700hq) fdo#101144
Test prime_busy:
Subgroup basic-wait-after-default:
pass -> DMESG-WARN (fi-skl-6700hq) fdo#101515 +1
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fdo#101515 https://bugs.freedesktop.org/show_bug.cgi?id=101515
fi-bdw-5557u total:278 pass:267 dwarn:0 dfail:0 fail:0 skip:11 time:439s
fi-bdw-gvtdvm total:278 pass:256 dwarn:8 dfail:0 fail:0 skip:14 time:425s
fi-bsw-n3050 total:278 pass:240 dwarn:1 dfail:0 fail:0 skip:37 time:536s
fi-bxt-j4205 total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:499s
fi-byt-j1900 total:278 pass:252 dwarn:2 dfail:0 fail:0 skip:24 time:498s
fi-byt-n2820 total:278 pass:248 dwarn:2 dfail:0 fail:0 skip:28 time:489s
fi-glk-2a total:278 pass:259 dwarn:0 dfail:0 fail:0 skip:19 time:599s
fi-hsw-4770 total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:435s
fi-hsw-4770r total:278 pass:262 dwarn:0 dfail:0 fail:0 skip:16 time:414s
fi-ilk-650 total:278 pass:228 dwarn:0 dfail:0 fail:0 skip:50 time:422s
fi-ivb-3520m total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:502s
fi-ivb-3770 total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:472s
fi-kbl-7500u total:278 pass:260 dwarn:0 dfail:0 fail:0 skip:18 time:470s
fi-kbl-7560u total:278 pass:267 dwarn:1 dfail:0 fail:0 skip:10 time:580s
fi-kbl-r total:278 pass:259 dwarn:1 dfail:0 fail:0 skip:18 time:570s
fi-skl-6260u total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:462s
fi-skl-6700hq total:278 pass:220 dwarn:4 dfail:0 fail:29 skip:24 time:346s
fi-skl-6700k total:278 pass:256 dwarn:4 dfail:0 fail:0 skip:18 time:466s
fi-skl-6770hq total:278 pass:268 dwarn:0 dfail:0 fail:0 skip:10 time:477s
fi-skl-gvtdvm total:278 pass:265 dwarn:0 dfail:0 fail:0 skip:13 time:434s
fi-snb-2520m total:278 pass:250 dwarn:0 dfail:0 fail:0 skip:28 time:542s
fi-snb-2600 total:278 pass:248 dwarn:0 dfail:0 fail:1 skip:29 time:402s
0a9fd1712c87aac1b6065a58cb46582a6a117cee drm-tip: 2017y-06m-21d-15h-44m-13s UTC integration manifest
bf11018 drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5019/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write
2017-06-21 19:37 [PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write Manasi Navare
2017-06-21 19:52 ` ✗ Fi.CI.BAT: warning for " Patchwork
@ 2017-06-21 20:03 ` Ville Syrjälä
2017-06-22 1:32 ` Manasi Navare
1 sibling, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2017-06-21 20:03 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Jun 21, 2017 at 12:37:43PM -0700, Manasi Navare wrote:
> According to the eDP spec the minimum value for panel power cycle delay
> (t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle
> delay field should be programmed to "+1" value. Eg: To have a delay
> of 500ms this should be programmed to 6. This patch fixes the write
> by adding +1 to the pp_div value so it programs the correct min
> required panel power cycle delay.
> Since we program it to +1 value, when we perform HW readout, this
> value should subtract 1 before verifying pps state. This patch makes
> this correction as well to avoid "PPS state mismatch" error.
> This patch also adds a case where if the readout is 0 for the first readout,
> then read it as 0, dont subtract.
>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index bca4ac1..089e373 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
> struct intel_dp *intel_dp, struct edp_power_seq *seq)
> {
> u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
> + u16 pp_cycle_delay = 0;
> struct pps_registers regs;
>
> intel_pps_get_registers(dev_priv, intel_dp, ®s);
> @@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
> seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> PANEL_POWER_DOWN_DELAY_SHIFT;
>
> - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> + pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> BXT_POWER_CYCLE_DELAY_SHIFT;
> - if (tmp > 0)
> - seq->t11_t12 = (tmp - 1) * 1000;
> - else
> - seq->t11_t12 = 0;
> - } else {
> - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> - }
> + else
> + pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> + PANEL_POWER_CYCLE_DELAY_SHIFT;
> + if (pp_cycle_delay > 0)
> + seq->t11_t12 = (pp_cycle_delay - 1) * 1000;
> + else
> + seq->t11_t12 = 0;
I think it's probably easier to go the other way and just add the +100
msec to the vbt delay, and nuke the BXT/CNP special casing in the code.
> }
>
> static void
> @@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> << BXT_POWER_CYCLE_DELAY_SHIFT);
> } else {
> pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
> - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
> + pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000)
> << PANEL_POWER_CYCLE_DELAY_SHIFT);
> }
>
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write
2017-06-21 20:03 ` [PATCH] " Ville Syrjälä
@ 2017-06-22 1:32 ` Manasi Navare
2017-06-22 12:36 ` Ville Syrjälä
0 siblings, 1 reply; 5+ messages in thread
From: Manasi Navare @ 2017-06-22 1:32 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Jun 21, 2017 at 11:03:58PM +0300, Ville Syrjälä wrote:
> On Wed, Jun 21, 2017 at 12:37:43PM -0700, Manasi Navare wrote:
> > According to the eDP spec the minimum value for panel power cycle delay
> > (t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle
> > delay field should be programmed to "+1" value. Eg: To have a delay
> > of 500ms this should be programmed to 6. This patch fixes the write
> > by adding +1 to the pp_div value so it programs the correct min
> > required panel power cycle delay.
> > Since we program it to +1 value, when we perform HW readout, this
> > value should subtract 1 before verifying pps state. This patch makes
> > this correction as well to avoid "PPS state mismatch" error.
> > This patch also adds a case where if the readout is 0 for the first readout,
> > then read it as 0, dont subtract.
> >
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++-----------
> > 1 file changed, 11 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index bca4ac1..089e373 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
> > struct intel_dp *intel_dp, struct edp_power_seq *seq)
> > {
> > u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
> > + u16 pp_cycle_delay = 0;
> > struct pps_registers regs;
> >
> > intel_pps_get_registers(dev_priv, intel_dp, ®s);
> > @@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
> > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > PANEL_POWER_DOWN_DELAY_SHIFT;
> >
> > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> > + pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > BXT_POWER_CYCLE_DELAY_SHIFT;
> > - if (tmp > 0)
> > - seq->t11_t12 = (tmp - 1) * 1000;
> > - else
> > - seq->t11_t12 = 0;
> > - } else {
> > - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> > - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> > - }
> > + else
> > + pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> > + PANEL_POWER_CYCLE_DELAY_SHIFT;
> > + if (pp_cycle_delay > 0)
> > + seq->t11_t12 = (pp_cycle_delay - 1) * 1000;
> > + else
> > + seq->t11_t12 = 0;
>
> I think it's probably easier to go the other way and just add the +100
> msec to the vbt delay, and nuke the BXT/CNP special casing in the code.
>
The reason I am doing the -1 here is that this hw_readout gets called
in intel_dp_pps_verify each time during edp_panel_on and it reads the
values written into the register so lets say we wrote 6 into the register for
500ms then it will read 6 so we need to subtract 1 and multiply by 1000 to actually
get 5000 that gets written into intel->pps_delays.
Also keeping it at 5000 makes more sense because thats the number in edp spec.
rather than (adding 100ms to 500) * 1000 so storing 6000.
Manasi
> > }
> >
> > static void
> > @@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> > << BXT_POWER_CYCLE_DELAY_SHIFT);
> > } else {
> > pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
> > - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
> > + pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000)
> > << PANEL_POWER_CYCLE_DELAY_SHIFT);
> > }
> >
> > --
> > 2.1.4
>
> --
> Ville Syrjälä
> Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write
2017-06-22 1:32 ` Manasi Navare
@ 2017-06-22 12:36 ` Ville Syrjälä
0 siblings, 0 replies; 5+ messages in thread
From: Ville Syrjälä @ 2017-06-22 12:36 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Wed, Jun 21, 2017 at 06:32:09PM -0700, Manasi Navare wrote:
> On Wed, Jun 21, 2017 at 11:03:58PM +0300, Ville Syrjälä wrote:
> > On Wed, Jun 21, 2017 at 12:37:43PM -0700, Manasi Navare wrote:
> > > According to the eDP spec the minimum value for panel power cycle delay
> > > (t11_t12) is 500ms and as per the Bspec, PP_DIVISOR panel power cycle
> > > delay field should be programmed to "+1" value. Eg: To have a delay
> > > of 500ms this should be programmed to 6. This patch fixes the write
> > > by adding +1 to the pp_div value so it programs the correct min
> > > required panel power cycle delay.
> > > Since we program it to +1 value, when we perform HW readout, this
> > > value should subtract 1 before verifying pps state. This patch makes
> > > this correction as well to avoid "PPS state mismatch" error.
> > > This patch also adds a case where if the readout is 0 for the first readout,
> > > then read it as 0, dont subtract.
> > >
> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > > Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_dp.c | 22 +++++++++++-----------
> > > 1 file changed, 11 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > > index bca4ac1..089e373 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -5149,6 +5149,7 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
> > > struct intel_dp *intel_dp, struct edp_power_seq *seq)
> > > {
> > > u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
> > > + u16 pp_cycle_delay = 0;
> > > struct pps_registers regs;
> > >
> > > intel_pps_get_registers(dev_priv, intel_dp, ®s);
> > > @@ -5177,17 +5178,16 @@ intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
> > > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
> > > PANEL_POWER_DOWN_DELAY_SHIFT;
> > >
> > > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) {
> > > - u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > > + if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv))
> > > + pp_cycle_delay = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
> > > BXT_POWER_CYCLE_DELAY_SHIFT;
> > > - if (tmp > 0)
> > > - seq->t11_t12 = (tmp - 1) * 1000;
> > > - else
> > > - seq->t11_t12 = 0;
> > > - } else {
> > > - seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> > > - PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
> > > - }
> > > + else
> > > + pp_cycle_delay = (pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
> > > + PANEL_POWER_CYCLE_DELAY_SHIFT;
> > > + if (pp_cycle_delay > 0)
> > > + seq->t11_t12 = (pp_cycle_delay - 1) * 1000;
> > > + else
> > > + seq->t11_t12 = 0;
> >
> > I think it's probably easier to go the other way and just add the +100
> > msec to the vbt delay, and nuke the BXT/CNP special casing in the code.
> >
>
> The reason I am doing the -1 here is that this hw_readout gets called
> in intel_dp_pps_verify each time during edp_panel_on and it reads the
> values written into the register so lets say we wrote 6 into the register for
> 500ms then it will read 6 so we need to subtract 1 and multiply by 1000 to actually
> get 5000 that gets written into intel->pps_delays.
We should just doe the /1000 *1000. The +1 is bogus and it's not there
in the pre-BXT code.
>
> Also keeping it at 5000 makes more sense because thats the number in edp spec.
> rather than (adding 100ms to 500) * 1000 so storing 6000.
But that's what we do on most platforms. So IMO just go with it.
>
> Manasi
>
> > > }
> > >
> > > static void
> > > @@ -5341,7 +5341,7 @@ intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
> > > << BXT_POWER_CYCLE_DELAY_SHIFT);
> > > } else {
> > > pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
> > > - pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
> > > + pp_div |= (DIV_ROUND_UP(seq->t11_t12 + 1, 1000)
> > > << PANEL_POWER_CYCLE_DELAY_SHIFT);
> > > }
> > >
> > > --
> > > 2.1.4
> >
> > --
> > Ville Syrjälä
> > Intel OTC
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-06-22 12:36 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-21 19:37 [PATCH] drm/i915/dp: Fix the t11_t12 delay for non GEN 9 LP platforms at HW readout and HW write Manasi Navare
2017-06-21 19:52 ` ✗ Fi.CI.BAT: warning for " Patchwork
2017-06-21 20:03 ` [PATCH] " Ville Syrjälä
2017-06-22 1:32 ` Manasi Navare
2017-06-22 12:36 ` Ville Syrjälä
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.