[PATCH] drm/amd/powerplay/cz: print message if smc message fails

[PATCH] drm/amd/powerplay/cz: print message if smc message fails

[Alex Deucher]

Helpful in debugging.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 39c7091..652aaa4 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -72,7 +72,7 @@ static int cz_send_msg_to_smc_async(struct pp_smumgr *smumgr,
 	result = SMUM_WAIT_FIELD_UNEQUAL(smumgr,
 					SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
 	if (result != 0) {
-		pr_err("cz_send_msg_to_smc_async failed\n");
+		pr_err("cz_send_msg_to_smc_async (0x%04x) failed\n", msg);
 		return result;
 	}
 
-- 
2.5.5

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[PATCH] drm/amdgpu/psp: upper_32_bits/lower_32_bits for address setup

[Alex Deucher]

Rather than casting and shifting.  Fixes sparse case warnings.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 12 ++++++------
 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 12 ++++++------
 3 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c224c5c..0b5f533 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -152,8 +152,8 @@ static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 				 uint64_t tmr_mc, uint32_t size)
 {
 	cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
-	cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
-	cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
+	cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
+	cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 	cmd->cmd.cmd_setup_tmr.buf_size = size;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 20c1e53..2258323 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -96,8 +96,8 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
 	header = (struct common_firmware_header *)ucode->fw;
 
 	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
-	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;
-	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
+	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
+	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 	cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
 
 	ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
@@ -172,10 +172,10 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
 		write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
 
 	/* Update KM RB frame */
-	write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);
-	write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);
-	write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
-	write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
+	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 	write_frame->fence_value = index;
 
 	/* Update the write Pointer in DWORDs */
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index 6e5c6ed..c98d77d 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -254,8 +254,8 @@ int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd
 	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 
 	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
-	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = (uint32_t)fw_mem_mc_addr;
-	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
+	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
+	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
 	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
 
 	ret = psp_v3_1_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
@@ -375,10 +375,10 @@ int psp_v3_1_cmd_submit(struct psp_context *psp,
 	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
 
 	/* Update KM RB frame */
-	write_frame->cmd_buf_addr_hi = (unsigned int)(cmd_buf_mc_addr >> 32);
-	write_frame->cmd_buf_addr_lo = (unsigned int)(cmd_buf_mc_addr);
-	write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
-	write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
+	write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
+	write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
+	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
+	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
 	write_frame->fence_value = index;
 
 	/* Update the write Pointer in DWORDs */
-- 
2.5.5

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RE: [PATCH] drm/amdgpu/psp: upper_32_bits/lower_32_bits for address setup

[Li, Samuel]

Reviewed-by: Samuel Li <samuel.li@amd.com>

Sam

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Alex Deucher
> Sent: Thursday, June 22, 2017 6:29 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
> Subject: [PATCH] drm/amdgpu/psp: upper_32_bits/lower_32_bits for
> address setup
> 
> Rather than casting and shifting.  Fixes sparse case warnings.
> 
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  4 ++--
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 12 ++++++------
>  drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 12 ++++++------
>  3 files changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index c224c5c..0b5f533 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -152,8 +152,8 @@ static void psp_prep_tmr_cmd_buf(struct
> psp_gfx_cmd_resp *cmd,
>  				 uint64_t tmr_mc, uint32_t size)
>  {
>  	cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
> -	cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
> -	cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >>
> 32);
> +	cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo =
> lower_32_bits(tmr_mc);
> +	cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi =
> upper_32_bits(tmr_mc);
>  	cmd->cmd.cmd_setup_tmr.buf_size = size;  }
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 20c1e53..2258323 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -96,8 +96,8 @@ int psp_v10_0_prep_cmd_buf(struct
> amdgpu_firmware_info *ucode, struct psp_gfx_cm
>  	header = (struct common_firmware_header *)ucode->fw;
> 
>  	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
> -	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo =
> (uint32_t)fw_mem_mc_addr;
> -	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi =
> (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
> +	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo =
> lower_32_bits(fw_mem_mc_addr);
> +	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi =
> +upper_32_bits(fw_mem_mc_addr);
>  	cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header-
> >ucode_size_bytes);
> 
>  	ret = psp_v10_0_get_fw_type(ucode, &cmd-
> >cmd.cmd_load_ip_fw.fw_type);
> @@ -172,10 +172,10 @@ int psp_v10_0_cmd_submit(struct psp_context
> *psp,
>  		write_frame = ring->ring_mem + (psp_write_ptr_reg /
> (sizeof(struct psp_gfx_rb_frame) / 4));
> 
>  	/* Update KM RB frame */
> -	write_frame->cmd_buf_addr_hi = (unsigned
> int)(cmd_buf_mc_addr >> 32);
> -	write_frame->cmd_buf_addr_lo = (unsigned
> int)(cmd_buf_mc_addr);
> -	write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
> -	write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
> +	write_frame->cmd_buf_addr_hi =
> upper_32_bits(cmd_buf_mc_addr);
> +	write_frame->cmd_buf_addr_lo =
> lower_32_bits(cmd_buf_mc_addr);
> +	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
> +	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
>  	write_frame->fence_value = index;
> 
>  	/* Update the write Pointer in DWORDs */ diff --git
> a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index 6e5c6ed..c98d77d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -254,8 +254,8 @@ int psp_v3_1_prep_cmd_buf(struct
> amdgpu_firmware_info *ucode, struct psp_gfx_cmd
>  	memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
> 
>  	cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
> -	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo =
> (uint32_t)fw_mem_mc_addr;
> -	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi =
> (uint32_t)((uint64_t)fw_mem_mc_addr >> 32);
> +	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo =
> lower_32_bits(fw_mem_mc_addr);
> +	cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi =
> +upper_32_bits(fw_mem_mc_addr);
>  	cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
> 
>  	ret = psp_v3_1_get_fw_type(ucode, &cmd-
> >cmd.cmd_load_ip_fw.fw_type);
> @@ -375,10 +375,10 @@ int psp_v3_1_cmd_submit(struct psp_context *psp,
>  	memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
> 
>  	/* Update KM RB frame */
> -	write_frame->cmd_buf_addr_hi = (unsigned
> int)(cmd_buf_mc_addr >> 32);
> -	write_frame->cmd_buf_addr_lo = (unsigned
> int)(cmd_buf_mc_addr);
> -	write_frame->fence_addr_hi = (unsigned int)(fence_mc_addr >> 32);
> -	write_frame->fence_addr_lo = (unsigned int)(fence_mc_addr);
> +	write_frame->cmd_buf_addr_hi =
> upper_32_bits(cmd_buf_mc_addr);
> +	write_frame->cmd_buf_addr_lo =
> lower_32_bits(cmd_buf_mc_addr);
> +	write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
> +	write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
>  	write_frame->fence_value = index;
> 
>  	/* Update the write Pointer in DWORDs */
> --
> 2.5.5
> 
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> amd-gfx@lists.freedesktop.org
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