* [PATCH v2 0/2] libxl: cpuid bits
@ 2017-06-28 10:10 Marek Marczykowski-Górecki
2017-06-28 10:10 ` [PATCH v2 1/2] libxl: add more cpuid flags handling Marek Marczykowski-Górecki
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Marek Marczykowski-Górecki @ 2017-06-28 10:10 UTC (permalink / raw)
To: xen-devel; +Cc: Wei Liu, Ian Jackson, Marek Marczykowski-Górecki
This adds handling more cpuid bits by name. Mostly based on cpu_map.xml from
libvirt.
Marek Marczykowski-Górecki (2):
libxl: add more cpuid flags handling
libxl: drop osvw cpuid flag
docs/man/xl.cfg.pod.5.in | 20 ++++++++++++--------
tools/libxl/libxl_cpuid.c | 38 +++++++++++++++++++++++++++++++++++++-
2 files changed, 49 insertions(+), 9 deletions(-)
--
2.7.4
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/2] libxl: add more cpuid flags handling
2017-06-28 10:10 [PATCH v2 0/2] libxl: cpuid bits Marek Marczykowski-Górecki
@ 2017-06-28 10:10 ` Marek Marczykowski-Górecki
2017-06-28 17:53 ` Wei Liu
2017-06-28 18:16 ` Andrew Cooper
2017-06-28 10:10 ` [PATCH v2 2/2] libxl: drop osvw cpuid flag Marek Marczykowski-Górecki
2017-06-28 17:55 ` [PATCH v2 0/2] libxl: cpuid bits Wei Liu
2 siblings, 2 replies; 9+ messages in thread
From: Marek Marczykowski-Górecki @ 2017-06-28 10:10 UTC (permalink / raw)
To: xen-devel; +Cc: Wei Liu, Ian Jackson, Marek Marczykowski-Górecki
This is result of parsing cpu_map.xml from libvirt.
The most important part is handling leaf 0x00000007, but while at it add
other bits too.
Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
---
docs/man/xl.cfg.pod.5.in | 20 ++++++++++++--------
tools/libxl/libxl_cpuid.c | 37 +++++++++++++++++++++++++++++++++++++
2 files changed, 49 insertions(+), 8 deletions(-)
Changes since v1:
- set sub-leaf to 0 for leaf 7
diff --git a/docs/man/xl.cfg.pod.5.in b/docs/man/xl.cfg.pod.5.in
index 38084c7..51361c4 100644
--- a/docs/man/xl.cfg.pod.5.in
+++ b/docs/man/xl.cfg.pod.5.in
@@ -1464,14 +1464,18 @@ apicidsize brandid clflush family localapicid maxleaf maxhvleaf model nc
proccount procpkg stepping
List of keys taking a character:
-3dnow 3dnowext 3dnowprefetch abm acpi aes altmovcr8 apic avx clfsh cmov
-cmplegacy cmpxchg16 cmpxchg8 cntxid dca de ds dscpl dtes64 est extapic f16c
-ffxsr fma4 fpu fxsr htt hypervisor ia64 ibs lahfsahf lm lwp mca mce misalignsse
-mmx mmxext monitor movbe msr mtrr nodeid nx osvw osxsave pae page1gb pat pbe
-pclmulqdq pdcm pge popcnt pse pse36 psn rdtscp skinit smx ss sse sse2 sse3
-sse4_1 sse4_2 sse4a ssse3 svm svm_decode svm_lbrv svm_npt svm_nrips
-svm_pausefilt svm_tscrate svm_vmcbclean syscall sysenter tbm tm tm2 topoext tsc
-vme vmx wdt x2apic xop xsave xtpr
+3dnow 3dnowext 3dnowprefetch abm acpi adx aes altmovcr8 apic arat avx avx2
+avx512-4fmaps avx512-4vnniw avx512bw avx512cd avx512dq avx512er avx512f
+avx512ifma avx512pf avx512vbmi avx512vl bmi1 bmi2 clflushopt clfsh cmov
+cmplegacy cmpxchg16 cmpxchg8 cmt cntxid dca de ds dscpl dtes64 erms est extapic
+f16c ffxsr fma fma4 fpu fsgsbase fxsr hle htt hypervisor ia64 ibs invpcid
+invtsc lahfsahf lm lwp mca mce misalignsse mmx mmxext monitor movbe mpx msr
+mtrr nodeid nx ospke osvw osxsave pae page1gb pat pbe pcid pclmulqdq pdcm
+perfctr_core perfctr_nb pge pku popcnt pse pse36 psn rdrand rdseed rdtscp rtm
+skinit smap smep smx ss sse sse2 sse3 sse4_1 sse4_2 sse4a ssse3 svm svm_decode
+svm_lbrv svm_npt svm_nrips svm_pausefilt svm_tscrate svm_vmcbclean syscall
+sysenter tbm tm tm2 topoext tsc tsc-deadline tsc_adjust vme vmx wdt x2apic xop
+xsave xtpr
The xend syntax is a list of values in the form of
'leafnum:register=bitstring,register=bitstring'
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index 24591e2..8bcdb29 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -100,11 +100,13 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"clflush", 0x00000001, NA, CPUID_REG_EBX, 8, 8},
{"brandid", 0x00000001, NA, CPUID_REG_EBX, 0, 8},
{"hypervisor", 0x00000001, NA, CPUID_REG_ECX, 31, 1},
+ {"rdrand", 0x00000001, NA, CPUID_REG_ECX, 30, 1},
{"f16c", 0x00000001, NA, CPUID_REG_ECX, 29, 1},
{"avx", 0x00000001, NA, CPUID_REG_ECX, 28, 1},
{"osxsave", 0x00000001, NA, CPUID_REG_ECX, 27, 1},
{"xsave", 0x00000001, NA, CPUID_REG_ECX, 26, 1},
{"aes", 0x00000001, NA, CPUID_REG_ECX, 25, 1},
+ {"tsc-deadline", 0x00000001, NA, CPUID_REG_ECX, 24, 1},
{"popcnt", 0x00000001, NA, CPUID_REG_ECX, 23, 1},
{"movbe", 0x00000001, NA, CPUID_REG_ECX, 22, 1},
{"x2apic", 0x00000001, NA, CPUID_REG_ECX, 21, 1},
@@ -114,9 +116,11 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"sse4.1", 0x00000001, NA, CPUID_REG_ECX, 19, 1},
{"sse4_1", 0x00000001, NA, CPUID_REG_ECX, 19, 1},
{"dca", 0x00000001, NA, CPUID_REG_ECX, 18, 1},
+ {"pcid", 0x00000001, NA, CPUID_REG_ECX, 17, 1},
{"pdcm", 0x00000001, NA, CPUID_REG_ECX, 15, 1},
{"xtpr", 0x00000001, NA, CPUID_REG_ECX, 14, 1},
{"cmpxchg16", 0x00000001, NA, CPUID_REG_ECX, 13, 1},
+ {"fma", 0x00000001, NA, CPUID_REG_ECX, 12, 1},
{"cntxid", 0x00000001, NA, CPUID_REG_ECX, 10, 1},
{"ssse3", 0x00000001, NA, CPUID_REG_ECX, 9, 1},
{"tm2", 0x00000001, NA, CPUID_REG_ECX, 8, 1},
@@ -158,6 +162,38 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"de", 0x00000001, NA, CPUID_REG_EDX, 2, 1},
{"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
{"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
+ {"arat", 0x00000006, NA, CPUID_REG_EAX, 2, 1},
+ {"avx512vl", 0x00000007, 0, CPUID_REG_EBX, 31, 1},
+ {"avx512bw", 0x00000007, 0, CPUID_REG_EBX, 30, 1},
+ {"avx512cd", 0x00000007, 0, CPUID_REG_EBX, 28, 1},
+ {"avx512er", 0x00000007, 0, CPUID_REG_EBX, 27, 1},
+ {"avx512pf", 0x00000007, 0, CPUID_REG_EBX, 26, 1},
+ {"clflushopt", 0x00000007, 0, CPUID_REG_EBX, 23, 1},
+ {"avx512ifma", 0x00000007, 0, CPUID_REG_EBX, 21, 1},
+ {"smap", 0x00000007, 0, CPUID_REG_EBX, 20, 1},
+ {"adx", 0x00000007, 0, CPUID_REG_EBX, 19, 1},
+ {"rdseed", 0x00000007, 0, CPUID_REG_EBX, 18, 1},
+ {"avx512dq", 0x00000007, 0, CPUID_REG_EBX, 17, 1},
+ {"avx512f", 0x00000007, 0, CPUID_REG_EBX, 16, 1},
+ {"mpx", 0x00000007, 0, CPUID_REG_EBX, 14, 1},
+ {"cmt", 0x00000007, 0, CPUID_REG_EBX, 12, 1},
+ {"rtm", 0x00000007, 0, CPUID_REG_EBX, 11, 1},
+ {"invpcid", 0x00000007, 0, CPUID_REG_EBX, 10, 1},
+ {"erms", 0x00000007, 0, CPUID_REG_EBX, 9, 1},
+ {"bmi2", 0x00000007, 0, CPUID_REG_EBX, 8, 1},
+ {"smep", 0x00000007, 0, CPUID_REG_EBX, 7, 1},
+ {"avx2", 0x00000007, 0, CPUID_REG_EBX, 5, 1},
+ {"hle", 0x00000007, 0, CPUID_REG_EBX, 4, 1},
+ {"bmi1", 0x00000007, 0, CPUID_REG_EBX, 3, 1},
+ {"tsc_adjust", 0x00000007, 0, CPUID_REG_EBX, 1, 1},
+ {"fsgsbase", 0x00000007, 0, CPUID_REG_EBX, 0, 1},
+ {"ospke", 0x00000007, 0, CPUID_REG_ECX, 4, 1},
+ {"pku", 0x00000007, 0, CPUID_REG_ECX, 3, 1},
+ {"avx512vbmi", 0x00000007, 0, CPUID_REG_ECX, 1, 1},
+ {"avx512-4fmaps",0x00000007, 0, CPUID_REG_EDX, 3, 1},
+ {"avx512-4vnniw",0x00000007, 0, CPUID_REG_EDX, 2, 1},
+ {"perfctr_nb", 0x80000001, NA, CPUID_REG_ECX, 24, 1},
+ {"perfctr_core", 0x80000001, NA, CPUID_REG_ECX, 23, 1},
{"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
{"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
{"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
@@ -187,6 +223,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"nx", 0x80000001, NA, CPUID_REG_EDX, 20, 1},
{"syscall", 0x80000001, NA, CPUID_REG_EDX, 11, 1},
{"procpkg", 0x00000004, 0, CPUID_REG_EAX, 26, 6},
+ {"invtsc", 0x80000007, NA, CPUID_REG_EDX, 8, 1},
{"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4},
{"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8},
{"svm_npt", 0x8000000a, NA, CPUID_REG_EDX, 0, 1},
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] libxl: drop osvw cpuid flag
2017-06-28 10:10 [PATCH v2 0/2] libxl: cpuid bits Marek Marczykowski-Górecki
2017-06-28 10:10 ` [PATCH v2 1/2] libxl: add more cpuid flags handling Marek Marczykowski-Górecki
@ 2017-06-28 10:10 ` Marek Marczykowski-Górecki
2017-06-28 17:55 ` [PATCH v2 0/2] libxl: cpuid bits Wei Liu
2 siblings, 0 replies; 9+ messages in thread
From: Marek Marczykowski-Górecki @ 2017-06-28 10:10 UTC (permalink / raw)
To: xen-devel; +Cc: Wei Liu, Ian Jackson, Marek Marczykowski-Górecki
It was wrong (should be bit 9), but instead of fixing, simply remove it
because it isn't exposed by hypervisor at all.
Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
---
tools/libxl/libxl_cpuid.c | 1 -
1 file changed, 1 deletion(-)
Changes since v1:
- drop it instead of fixing it
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index 8bcdb29..d95eeb7 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -203,7 +203,6 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
{"skinit", 0x80000001, NA, CPUID_REG_ECX, 12, 1},
{"xop", 0x80000001, NA, CPUID_REG_ECX, 11, 1},
{"ibs", 0x80000001, NA, CPUID_REG_ECX, 10, 1},
- {"osvw", 0x80000001, NA, CPUID_REG_ECX, 10, 1},
{"3dnowprefetch",0x80000001, NA, CPUID_REG_ECX, 8, 1},
{"misalignsse", 0x80000001, NA, CPUID_REG_ECX, 7, 1},
{"sse4a", 0x80000001, NA, CPUID_REG_ECX, 6, 1},
--
2.7.4
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] libxl: add more cpuid flags handling
2017-06-28 10:10 ` [PATCH v2 1/2] libxl: add more cpuid flags handling Marek Marczykowski-Górecki
@ 2017-06-28 17:53 ` Wei Liu
2017-06-28 18:16 ` Andrew Cooper
1 sibling, 0 replies; 9+ messages in thread
From: Wei Liu @ 2017-06-28 17:53 UTC (permalink / raw)
To: Marek Marczykowski-Górecki; +Cc: Wei Liu, Ian Jackson, xen-devel
On Wed, Jun 28, 2017 at 12:10:21PM +0200, Marek Marczykowski-Górecki wrote:
> This is result of parsing cpu_map.xml from libvirt.
> The most important part is handling leaf 0x00000007, but while at it add
> other bits too.
>
> Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Subject to an ack from x86 maintainers:
Acked-by: Wei Liu <wei.liu2@citrix.com>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/2] libxl: cpuid bits
2017-06-28 10:10 [PATCH v2 0/2] libxl: cpuid bits Marek Marczykowski-Górecki
2017-06-28 10:10 ` [PATCH v2 1/2] libxl: add more cpuid flags handling Marek Marczykowski-Górecki
2017-06-28 10:10 ` [PATCH v2 2/2] libxl: drop osvw cpuid flag Marek Marczykowski-Górecki
@ 2017-06-28 17:55 ` Wei Liu
2017-06-29 23:12 ` Marek Marczykowski-Górecki
2 siblings, 1 reply; 9+ messages in thread
From: Wei Liu @ 2017-06-28 17:55 UTC (permalink / raw)
To: Marek Marczykowski-Górecki; +Cc: Wei Liu, Ian Jackson, xen-devel
On Wed, Jun 28, 2017 at 12:10:20PM +0200, Marek Marczykowski-Górecki wrote:
> This adds handling more cpuid bits by name. Mostly based on cpu_map.xml from
> libvirt.
>
> Marek Marczykowski-Górecki (2):
> libxl: add more cpuid flags handling
> libxl: drop osvw cpuid flag
Given that I prefer to have v1 of the second patch, please resubmit a
final version when you collect all the acks. Thanks.
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] libxl: add more cpuid flags handling
2017-06-28 10:10 ` [PATCH v2 1/2] libxl: add more cpuid flags handling Marek Marczykowski-Górecki
2017-06-28 17:53 ` Wei Liu
@ 2017-06-28 18:16 ` Andrew Cooper
2017-06-28 20:53 ` Marek Marczykowski-Górecki
1 sibling, 1 reply; 9+ messages in thread
From: Andrew Cooper @ 2017-06-28 18:16 UTC (permalink / raw)
To: Marek Marczykowski-Górecki, xen-devel; +Cc: Ian Jackson, Wei Liu
On 28/06/17 11:10, Marek Marczykowski-Górecki wrote:
> This is result of parsing cpu_map.xml from libvirt.
> The most important part is handling leaf 0x00000007, but while at it add
> other bits too.
>
> Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Xen's canonical reference is include/asm-x86/cpufeatures.h from which
the hypervisor logic is derived.
> ---
> docs/man/xl.cfg.pod.5.in | 20 ++++++++++++--------
> tools/libxl/libxl_cpuid.c | 37 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 49 insertions(+), 8 deletions(-)
>
> Changes since v1:
> - set sub-leaf to 0 for leaf 7
>
> diff --git a/docs/man/xl.cfg.pod.5.in b/docs/man/xl.cfg.pod.5.in
> index 38084c7..51361c4 100644
> --- a/docs/man/xl.cfg.pod.5.in
> +++ b/docs/man/xl.cfg.pod.5.in
> @@ -1464,14 +1464,18 @@ apicidsize brandid clflush family localapicid maxleaf maxhvleaf model nc
> proccount procpkg stepping
>
> List of keys taking a character:
> -3dnow 3dnowext 3dnowprefetch abm acpi aes altmovcr8 apic avx clfsh cmov
> -cmplegacy cmpxchg16 cmpxchg8 cntxid dca de ds dscpl dtes64 est extapic f16c
> -ffxsr fma4 fpu fxsr htt hypervisor ia64 ibs lahfsahf lm lwp mca mce misalignsse
> -mmx mmxext monitor movbe msr mtrr nodeid nx osvw osxsave pae page1gb pat pbe
> -pclmulqdq pdcm pge popcnt pse pse36 psn rdtscp skinit smx ss sse sse2 sse3
> -sse4_1 sse4_2 sse4a ssse3 svm svm_decode svm_lbrv svm_npt svm_nrips
> -svm_pausefilt svm_tscrate svm_vmcbclean syscall sysenter tbm tm tm2 topoext tsc
> -vme vmx wdt x2apic xop xsave xtpr
> +3dnow 3dnowext 3dnowprefetch abm acpi adx aes altmovcr8 apic arat avx avx2
> +avx512-4fmaps avx512-4vnniw avx512bw avx512cd avx512dq avx512er avx512f
> +avx512ifma avx512pf avx512vbmi avx512vl bmi1 bmi2 clflushopt clfsh cmov
> +cmplegacy cmpxchg16 cmpxchg8 cmt cntxid dca de ds dscpl dtes64 erms est extapic
> +f16c ffxsr fma fma4 fpu fsgsbase fxsr hle htt hypervisor ia64 ibs invpcid
> +invtsc lahfsahf lm lwp mca mce misalignsse mmx mmxext monitor movbe mpx msr
> +mtrr nodeid nx ospke osvw osxsave pae page1gb pat pbe pcid pclmulqdq pdcm
> +perfctr_core perfctr_nb pge pku popcnt pse pse36 psn rdrand rdseed rdtscp rtm
> +skinit smap smep smx ss sse sse2 sse3 sse4_1 sse4_2 sse4a ssse3 svm svm_decode
> +svm_lbrv svm_npt svm_nrips svm_pausefilt svm_tscrate svm_vmcbclean syscall
> +sysenter tbm tm tm2 topoext tsc tsc-deadline tsc_adjust vme vmx wdt x2apic xop
> +xsave xtpr
>
> The xend syntax is a list of values in the form of
> 'leafnum:register=bitstring,register=bitstring'
> diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
> index 24591e2..8bcdb29 100644
> --- a/tools/libxl/libxl_cpuid.c
> +++ b/tools/libxl/libxl_cpuid.c
> @@ -100,11 +100,13 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
As some general points, it would be helpful to add newlines for clarity
between the CPUID_REG_* changes. It is weird being sorted by bit index
in descending order, although perhaps just me.
The structure really wants to be static const (so living in .rodata).
At the moment, it is being reconstructed on the stack by prologue code
every time the function is called.
> {"clflush", 0x00000001, NA, CPUID_REG_EBX, 8, 8},
> {"brandid", 0x00000001, NA, CPUID_REG_EBX, 0, 8},
> {"hypervisor", 0x00000001, NA, CPUID_REG_ECX, 31, 1},
> + {"rdrand", 0x00000001, NA, CPUID_REG_ECX, 30, 1},
> {"f16c", 0x00000001, NA, CPUID_REG_ECX, 29, 1},
> {"avx", 0x00000001, NA, CPUID_REG_ECX, 28, 1},
> {"osxsave", 0x00000001, NA, CPUID_REG_ECX, 27, 1},
> {"xsave", 0x00000001, NA, CPUID_REG_ECX, 26, 1},
> {"aes", 0x00000001, NA, CPUID_REG_ECX, 25, 1},
> + {"tsc-deadline", 0x00000001, NA, CPUID_REG_ECX, 24, 1},
> {"popcnt", 0x00000001, NA, CPUID_REG_ECX, 23, 1},
> {"movbe", 0x00000001, NA, CPUID_REG_ECX, 22, 1},
> {"x2apic", 0x00000001, NA, CPUID_REG_ECX, 21, 1},
> @@ -114,9 +116,11 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
> {"sse4.1", 0x00000001, NA, CPUID_REG_ECX, 19, 1},
> {"sse4_1", 0x00000001, NA, CPUID_REG_ECX, 19, 1},
> {"dca", 0x00000001, NA, CPUID_REG_ECX, 18, 1},
> + {"pcid", 0x00000001, NA, CPUID_REG_ECX, 17, 1},
> {"pdcm", 0x00000001, NA, CPUID_REG_ECX, 15, 1},
> {"xtpr", 0x00000001, NA, CPUID_REG_ECX, 14, 1},
> {"cmpxchg16", 0x00000001, NA, CPUID_REG_ECX, 13, 1},
> + {"fma", 0x00000001, NA, CPUID_REG_ECX, 12, 1},
> {"cntxid", 0x00000001, NA, CPUID_REG_ECX, 10, 1},
> {"ssse3", 0x00000001, NA, CPUID_REG_ECX, 9, 1},
> {"tm2", 0x00000001, NA, CPUID_REG_ECX, 8, 1},
> @@ -158,6 +162,38 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
> {"de", 0x00000001, NA, CPUID_REG_EDX, 2, 1},
> {"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
> {"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
> + {"arat", 0x00000006, NA, CPUID_REG_EAX, 2, 1},
> + {"avx512vl", 0x00000007, 0, CPUID_REG_EBX, 31, 1},
> + {"avx512bw", 0x00000007, 0, CPUID_REG_EBX, 30, 1},
sha at 29
> + {"avx512cd", 0x00000007, 0, CPUID_REG_EBX, 28, 1},
> + {"avx512er", 0x00000007, 0, CPUID_REG_EBX, 27, 1},
> + {"avx512pf", 0x00000007, 0, CPUID_REG_EBX, 26, 1},
clwb at 24
> + {"clflushopt", 0x00000007, 0, CPUID_REG_EBX, 23, 1},
> + {"avx512ifma", 0x00000007, 0, CPUID_REG_EBX, 21, 1},
> + {"smap", 0x00000007, 0, CPUID_REG_EBX, 20, 1},
> + {"adx", 0x00000007, 0, CPUID_REG_EBX, 19, 1},
> + {"rdseed", 0x00000007, 0, CPUID_REG_EBX, 18, 1},
> + {"avx512dq", 0x00000007, 0, CPUID_REG_EBX, 17, 1},
> + {"avx512f", 0x00000007, 0, CPUID_REG_EBX, 16, 1},
> + {"mpx", 0x00000007, 0, CPUID_REG_EBX, 14, 1},
> + {"cmt", 0x00000007, 0, CPUID_REG_EBX, 12, 1},
> + {"rtm", 0x00000007, 0, CPUID_REG_EBX, 11, 1},
> + {"invpcid", 0x00000007, 0, CPUID_REG_EBX, 10, 1},
> + {"erms", 0x00000007, 0, CPUID_REG_EBX, 9, 1},
> + {"bmi2", 0x00000007, 0, CPUID_REG_EBX, 8, 1},
> + {"smep", 0x00000007, 0, CPUID_REG_EBX, 7, 1},
> + {"avx2", 0x00000007, 0, CPUID_REG_EBX, 5, 1},
> + {"hle", 0x00000007, 0, CPUID_REG_EBX, 4, 1},
> + {"bmi1", 0x00000007, 0, CPUID_REG_EBX, 3, 1},
> + {"tsc_adjust", 0x00000007, 0, CPUID_REG_EBX, 1, 1},
> + {"fsgsbase", 0x00000007, 0, CPUID_REG_EBX, 0, 1},
> + {"ospke", 0x00000007, 0, CPUID_REG_ECX, 4, 1},
I'm not sure having ospke able to be controlled in this way is useful.
It is a fast-forward of CR4.PKE, which is gated on PKU below, and
handled entirely by Xen.
> + {"pku", 0x00000007, 0, CPUID_REG_ECX, 3, 1},
umip at 2
> + {"avx512vbmi", 0x00000007, 0, CPUID_REG_ECX, 1, 1},
> + {"avx512-4fmaps",0x00000007, 0, CPUID_REG_EDX, 3, 1},
> + {"avx512-4vnniw",0x00000007, 0, CPUID_REG_EDX, 2, 1},
> + {"perfctr_nb", 0x80000001, NA, CPUID_REG_ECX, 24, 1},
> + {"perfctr_core", 0x80000001, NA, CPUID_REG_ECX, 23, 1},
> {"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
> {"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
> {"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
> @@ -187,6 +223,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
> {"nx", 0x80000001, NA, CPUID_REG_EDX, 20, 1},
> {"syscall", 0x80000001, NA, CPUID_REG_EDX, 11, 1},
> {"procpkg", 0x00000004, 0, CPUID_REG_EAX, 26, 6},
> + {"invtsc", 0x80000007, NA, CPUID_REG_EDX, 8, 1},
> {"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4},
> {"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8},
> {"svm_npt", 0x8000000a, NA, CPUID_REG_EDX, 0, 1},
Otherwise, all of the added values look to correct in their bit-positions.
~Andrew
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/2] libxl: add more cpuid flags handling
2017-06-28 18:16 ` Andrew Cooper
@ 2017-06-28 20:53 ` Marek Marczykowski-Górecki
0 siblings, 0 replies; 9+ messages in thread
From: Marek Marczykowski-Górecki @ 2017-06-28 20:53 UTC (permalink / raw)
To: Andrew Cooper; +Cc: Ian Jackson, Wei Liu, xen-devel
[-- Attachment #1.1: Type: text/plain, Size: 9434 bytes --]
On Wed, Jun 28, 2017 at 07:16:18PM +0100, Andrew Cooper wrote:
> On 28/06/17 11:10, Marek Marczykowski-Górecki wrote:
> > This is result of parsing cpu_map.xml from libvirt.
> > The most important part is handling leaf 0x00000007, but while at it add
> > other bits too.
> >
> > Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
>
> Xen's canonical reference is include/asm-x86/cpufeatures.h from which
> the hypervisor logic is derived.
>
> > ---
> > docs/man/xl.cfg.pod.5.in | 20 ++++++++++++--------
> > tools/libxl/libxl_cpuid.c | 37 +++++++++++++++++++++++++++++++++++++
> > 2 files changed, 49 insertions(+), 8 deletions(-)
> >
> > Changes since v1:
> > - set sub-leaf to 0 for leaf 7
> >
> > diff --git a/docs/man/xl.cfg.pod.5.in b/docs/man/xl.cfg.pod.5.in
> > index 38084c7..51361c4 100644
> > --- a/docs/man/xl.cfg.pod.5.in
> > +++ b/docs/man/xl.cfg.pod.5.in
> > @@ -1464,14 +1464,18 @@ apicidsize brandid clflush family localapicid maxleaf maxhvleaf model nc
> > proccount procpkg stepping
> >
> > List of keys taking a character:
> > -3dnow 3dnowext 3dnowprefetch abm acpi aes altmovcr8 apic avx clfsh cmov
> > -cmplegacy cmpxchg16 cmpxchg8 cntxid dca de ds dscpl dtes64 est extapic f16c
> > -ffxsr fma4 fpu fxsr htt hypervisor ia64 ibs lahfsahf lm lwp mca mce misalignsse
> > -mmx mmxext monitor movbe msr mtrr nodeid nx osvw osxsave pae page1gb pat pbe
> > -pclmulqdq pdcm pge popcnt pse pse36 psn rdtscp skinit smx ss sse sse2 sse3
> > -sse4_1 sse4_2 sse4a ssse3 svm svm_decode svm_lbrv svm_npt svm_nrips
> > -svm_pausefilt svm_tscrate svm_vmcbclean syscall sysenter tbm tm tm2 topoext tsc
> > -vme vmx wdt x2apic xop xsave xtpr
> > +3dnow 3dnowext 3dnowprefetch abm acpi adx aes altmovcr8 apic arat avx avx2
> > +avx512-4fmaps avx512-4vnniw avx512bw avx512cd avx512dq avx512er avx512f
> > +avx512ifma avx512pf avx512vbmi avx512vl bmi1 bmi2 clflushopt clfsh cmov
> > +cmplegacy cmpxchg16 cmpxchg8 cmt cntxid dca de ds dscpl dtes64 erms est extapic
> > +f16c ffxsr fma fma4 fpu fsgsbase fxsr hle htt hypervisor ia64 ibs invpcid
> > +invtsc lahfsahf lm lwp mca mce misalignsse mmx mmxext monitor movbe mpx msr
> > +mtrr nodeid nx ospke osvw osxsave pae page1gb pat pbe pcid pclmulqdq pdcm
> > +perfctr_core perfctr_nb pge pku popcnt pse pse36 psn rdrand rdseed rdtscp rtm
> > +skinit smap smep smx ss sse sse2 sse3 sse4_1 sse4_2 sse4a ssse3 svm svm_decode
> > +svm_lbrv svm_npt svm_nrips svm_pausefilt svm_tscrate svm_vmcbclean syscall
> > +sysenter tbm tm tm2 topoext tsc tsc-deadline tsc_adjust vme vmx wdt x2apic xop
> > +xsave xtpr
> >
> > The xend syntax is a list of values in the form of
> > 'leafnum:register=bitstring,register=bitstring'
> > diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
> > index 24591e2..8bcdb29 100644
> > --- a/tools/libxl/libxl_cpuid.c
> > +++ b/tools/libxl/libxl_cpuid.c
> > @@ -100,11 +100,13 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
>
> As some general points, it would be helpful to add newlines for clarity
> between the CPUID_REG_* changes. It is weird being sorted by bit index
> in descending order, although perhaps just me.
It is weird for me too, but I didn't wanted to reformat the whole list.
If there is no real reason for this order, I can change that too.
> The structure really wants to be static const (so living in .rodata).
> At the moment, it is being reconstructed on the stack by prologue code
> every time the function is called.
Good idea.
> > {"clflush", 0x00000001, NA, CPUID_REG_EBX, 8, 8},
> > {"brandid", 0x00000001, NA, CPUID_REG_EBX, 0, 8},
> > {"hypervisor", 0x00000001, NA, CPUID_REG_ECX, 31, 1},
> > + {"rdrand", 0x00000001, NA, CPUID_REG_ECX, 30, 1},
> > {"f16c", 0x00000001, NA, CPUID_REG_ECX, 29, 1},
> > {"avx", 0x00000001, NA, CPUID_REG_ECX, 28, 1},
> > {"osxsave", 0x00000001, NA, CPUID_REG_ECX, 27, 1},
> > {"xsave", 0x00000001, NA, CPUID_REG_ECX, 26, 1},
> > {"aes", 0x00000001, NA, CPUID_REG_ECX, 25, 1},
> > + {"tsc-deadline", 0x00000001, NA, CPUID_REG_ECX, 24, 1},
> > {"popcnt", 0x00000001, NA, CPUID_REG_ECX, 23, 1},
> > {"movbe", 0x00000001, NA, CPUID_REG_ECX, 22, 1},
> > {"x2apic", 0x00000001, NA, CPUID_REG_ECX, 21, 1},
> > @@ -114,9 +116,11 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
> > {"sse4.1", 0x00000001, NA, CPUID_REG_ECX, 19, 1},
> > {"sse4_1", 0x00000001, NA, CPUID_REG_ECX, 19, 1},
> > {"dca", 0x00000001, NA, CPUID_REG_ECX, 18, 1},
> > + {"pcid", 0x00000001, NA, CPUID_REG_ECX, 17, 1},
> > {"pdcm", 0x00000001, NA, CPUID_REG_ECX, 15, 1},
> > {"xtpr", 0x00000001, NA, CPUID_REG_ECX, 14, 1},
> > {"cmpxchg16", 0x00000001, NA, CPUID_REG_ECX, 13, 1},
> > + {"fma", 0x00000001, NA, CPUID_REG_ECX, 12, 1},
> > {"cntxid", 0x00000001, NA, CPUID_REG_ECX, 10, 1},
> > {"ssse3", 0x00000001, NA, CPUID_REG_ECX, 9, 1},
> > {"tm2", 0x00000001, NA, CPUID_REG_ECX, 8, 1},
> > @@ -158,6 +162,38 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
> > {"de", 0x00000001, NA, CPUID_REG_EDX, 2, 1},
> > {"vme", 0x00000001, NA, CPUID_REG_EDX, 1, 1},
> > {"fpu", 0x00000001, NA, CPUID_REG_EDX, 0, 1},
> > + {"arat", 0x00000006, NA, CPUID_REG_EAX, 2, 1},
> > + {"avx512vl", 0x00000007, 0, CPUID_REG_EBX, 31, 1},
> > + {"avx512bw", 0x00000007, 0, CPUID_REG_EBX, 30, 1},
>
> sha at 29
>
> > + {"avx512cd", 0x00000007, 0, CPUID_REG_EBX, 28, 1},
> > + {"avx512er", 0x00000007, 0, CPUID_REG_EBX, 27, 1},
> > + {"avx512pf", 0x00000007, 0, CPUID_REG_EBX, 26, 1},
>
> clwb at 24
>
> > + {"clflushopt", 0x00000007, 0, CPUID_REG_EBX, 23, 1},
> > + {"avx512ifma", 0x00000007, 0, CPUID_REG_EBX, 21, 1},
> > + {"smap", 0x00000007, 0, CPUID_REG_EBX, 20, 1},
> > + {"adx", 0x00000007, 0, CPUID_REG_EBX, 19, 1},
> > + {"rdseed", 0x00000007, 0, CPUID_REG_EBX, 18, 1},
> > + {"avx512dq", 0x00000007, 0, CPUID_REG_EBX, 17, 1},
> > + {"avx512f", 0x00000007, 0, CPUID_REG_EBX, 16, 1},
> > + {"mpx", 0x00000007, 0, CPUID_REG_EBX, 14, 1},
> > + {"cmt", 0x00000007, 0, CPUID_REG_EBX, 12, 1},
> > + {"rtm", 0x00000007, 0, CPUID_REG_EBX, 11, 1},
> > + {"invpcid", 0x00000007, 0, CPUID_REG_EBX, 10, 1},
> > + {"erms", 0x00000007, 0, CPUID_REG_EBX, 9, 1},
> > + {"bmi2", 0x00000007, 0, CPUID_REG_EBX, 8, 1},
> > + {"smep", 0x00000007, 0, CPUID_REG_EBX, 7, 1},
> > + {"avx2", 0x00000007, 0, CPUID_REG_EBX, 5, 1},
> > + {"hle", 0x00000007, 0, CPUID_REG_EBX, 4, 1},
> > + {"bmi1", 0x00000007, 0, CPUID_REG_EBX, 3, 1},
> > + {"tsc_adjust", 0x00000007, 0, CPUID_REG_EBX, 1, 1},
> > + {"fsgsbase", 0x00000007, 0, CPUID_REG_EBX, 0, 1},
> > + {"ospke", 0x00000007, 0, CPUID_REG_ECX, 4, 1},
>
> I'm not sure having ospke able to be controlled in this way is useful.
> It is a fast-forward of CR4.PKE, which is gated on PKU below, and
> handled entirely by Xen.
Well, you can adjust any bit using old ("xend") syntax anyway, at least
from toolstack point of view...
>
> > + {"pku", 0x00000007, 0, CPUID_REG_ECX, 3, 1},
>
> umip at 2
>
> > + {"avx512vbmi", 0x00000007, 0, CPUID_REG_ECX, 1, 1},
> > + {"avx512-4fmaps",0x00000007, 0, CPUID_REG_EDX, 3, 1},
> > + {"avx512-4vnniw",0x00000007, 0, CPUID_REG_EDX, 2, 1},
> > + {"perfctr_nb", 0x80000001, NA, CPUID_REG_ECX, 24, 1},
> > + {"perfctr_core", 0x80000001, NA, CPUID_REG_ECX, 23, 1},
> > {"topoext", 0x80000001, NA, CPUID_REG_ECX, 22, 1},
> > {"tbm", 0x80000001, NA, CPUID_REG_ECX, 21, 1},
> > {"nodeid", 0x80000001, NA, CPUID_REG_ECX, 19, 1},
> > @@ -187,6 +223,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str)
> > {"nx", 0x80000001, NA, CPUID_REG_EDX, 20, 1},
> > {"syscall", 0x80000001, NA, CPUID_REG_EDX, 11, 1},
> > {"procpkg", 0x00000004, 0, CPUID_REG_EAX, 26, 6},
> > + {"invtsc", 0x80000007, NA, CPUID_REG_EDX, 8, 1},
> > {"apicidsize", 0x80000008, NA, CPUID_REG_ECX, 12, 4},
> > {"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8},
> > {"svm_npt", 0x8000000a, NA, CPUID_REG_EDX, 0, 1},
>
> Otherwise, all of the added values look to correct in their bit-positions.
>
> ~Andrew
--
Best Regards,
Marek Marczykowski-Górecki
Invisible Things Lab
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/2] libxl: cpuid bits
2017-06-28 17:55 ` [PATCH v2 0/2] libxl: cpuid bits Wei Liu
@ 2017-06-29 23:12 ` Marek Marczykowski-Górecki
2017-06-30 10:21 ` Wei Liu
0 siblings, 1 reply; 9+ messages in thread
From: Marek Marczykowski-Górecki @ 2017-06-29 23:12 UTC (permalink / raw)
To: Wei Liu; +Cc: Ian Jackson, xen-devel
[-- Attachment #1.1: Type: text/plain, Size: 770 bytes --]
On Wed, Jun 28, 2017 at 06:55:58PM +0100, Wei Liu wrote:
> On Wed, Jun 28, 2017 at 12:10:20PM +0200, Marek Marczykowski-Górecki wrote:
> > This adds handling more cpuid bits by name. Mostly based on cpu_map.xml from
> > libvirt.
> >
> > Marek Marczykowski-Górecki (2):
> > libxl: add more cpuid flags handling
> > libxl: drop osvw cpuid flag
>
> Given that I prefer to have v1 of the second patch, please resubmit a
> final version when you collect all the acks. Thanks.
Should I read this as "Acked-by: Wei Liu <wei.liu2@citrix.com>" on v1 of
the second patch?
--
Best Regards,
Marek Marczykowski-Górecki
Invisible Things Lab
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 0/2] libxl: cpuid bits
2017-06-29 23:12 ` Marek Marczykowski-Górecki
@ 2017-06-30 10:21 ` Wei Liu
0 siblings, 0 replies; 9+ messages in thread
From: Wei Liu @ 2017-06-30 10:21 UTC (permalink / raw)
To: Marek Marczykowski-Górecki; +Cc: Ian Jackson, Wei Liu, xen-devel
On Fri, Jun 30, 2017 at 01:12:48AM +0200, Marek Marczykowski-Górecki wrote:
> On Wed, Jun 28, 2017 at 06:55:58PM +0100, Wei Liu wrote:
> > On Wed, Jun 28, 2017 at 12:10:20PM +0200, Marek Marczykowski-Górecki wrote:
> > > This adds handling more cpuid bits by name. Mostly based on cpu_map.xml from
> > > libvirt.
> > >
> > > Marek Marczykowski-Górecki (2):
> > > libxl: add more cpuid flags handling
> > > libxl: drop osvw cpuid flag
> >
> > Given that I prefer to have v1 of the second patch, please resubmit a
> > final version when you collect all the acks. Thanks.
>
> Should I read this as "Acked-by: Wei Liu <wei.liu2@citrix.com>" on v1 of
> the second patch?
Yes. But I will need an ack from x86 maintainers before applying.
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-06-30 10:21 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-28 10:10 [PATCH v2 0/2] libxl: cpuid bits Marek Marczykowski-Górecki
2017-06-28 10:10 ` [PATCH v2 1/2] libxl: add more cpuid flags handling Marek Marczykowski-Górecki
2017-06-28 17:53 ` Wei Liu
2017-06-28 18:16 ` Andrew Cooper
2017-06-28 20:53 ` Marek Marczykowski-Górecki
2017-06-28 10:10 ` [PATCH v2 2/2] libxl: drop osvw cpuid flag Marek Marczykowski-Górecki
2017-06-28 17:55 ` [PATCH v2 0/2] libxl: cpuid bits Wei Liu
2017-06-29 23:12 ` Marek Marczykowski-Górecki
2017-06-30 10:21 ` Wei Liu
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