* [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle
@ 2017-06-28 23:24 Michel Thierry
2017-06-28 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-06-29 13:05 ` [PATCH] " Ville Syrjälä
0 siblings, 2 replies; 5+ messages in thread
From: Michel Thierry @ 2017-06-28 23:24 UTC (permalink / raw)
To: intel-gfx
There's no need to keep reading random registers in i915_swizzle_info if
the platform is not doing GPU side swizzling.
After HSW, swizzling is not used, and the CPU's memory controller
performs all the address swizzling modifications, commit be292e1563ac5b
("drm/i915/bdw: Let the memory controller do all the swizzling").
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 87e13131f6ea..e82f503389fb 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2152,6 +2152,11 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
+ seq_puts(m, "not supported - CPU does all the swizzling\n");
+ return 0;
+ }
+
intel_runtime_pm_get(dev_priv);
seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
--
2.11.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle
2017-06-28 23:24 [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle Michel Thierry
@ 2017-06-28 23:43 ` Patchwork
2017-06-29 13:05 ` [PATCH] " Ville Syrjälä
1 sibling, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-06-28 23:43 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle
URL : https://patchwork.freedesktop.org/series/26517/
State : success
== Summary ==
Series 26517v1 drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle
https://patchwork.freedesktop.org/api/1.0/series/26517/revisions/1/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
fail -> PASS (fi-snb-2600) fdo#100007
Test kms_pipe_crc_basic:
Subgroup hang-read-crc-pipe-a:
pass -> DMESG-WARN (fi-pnv-d510) fdo#101597
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:453s
fi-bdw-gvtdvm total:279 pass:257 dwarn:8 dfail:0 fail:0 skip:14 time:424s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:350s
fi-bsw-n3050 total:279 pass:242 dwarn:1 dfail:0 fail:0 skip:36 time:531s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:505s
fi-byt-j1900 total:279 pass:253 dwarn:2 dfail:0 fail:0 skip:24 time:484s
fi-byt-n2820 total:279 pass:249 dwarn:2 dfail:0 fail:0 skip:28 time:483s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:593s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:436s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:414s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:423s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:492s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:475s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:465s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:570s
fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:585s
fi-pnv-d510 total:279 pass:222 dwarn:2 dfail:0 fail:0 skip:55 time:556s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:453s
fi-skl-6700hq total:279 pass:223 dwarn:1 dfail:0 fail:30 skip:24 time:339s
fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:464s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:478s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:435s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:542s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:403s
85a692e2c6a7cf93082044d776e838cb9e9b2146 drm-tip: 2017y-06m-28d-14h-24m-59s UTC integration manifest
77e2a75 drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5064/
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle
2017-06-28 23:24 [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle Michel Thierry
2017-06-28 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-06-29 13:05 ` Ville Syrjälä
2017-06-29 13:07 ` Chris Wilson
1 sibling, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2017-06-29 13:05 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote:
> There's no need to keep reading random registers in i915_swizzle_info if
> the platform is not doing GPU side swizzling.
>
> After HSW, swizzling is not used, and the CPU's memory controller
> performs all the address swizzling modifications, commit be292e1563ac5b
> ("drm/i915/bdw: Let the memory controller do all the swizzling").
But BDW still contains the registers and hardware capability no? So
might be a good idea to be able to check that it's not misconfigured.
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 87e13131f6ea..e82f503389fb 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2152,6 +2152,11 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>
> + if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
> + seq_puts(m, "not supported - CPU does all the swizzling\n");
> + return 0;
> + }
> +
> intel_runtime_pm_get(dev_priv);
>
> seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle
2017-06-29 13:05 ` [PATCH] " Ville Syrjälä
@ 2017-06-29 13:07 ` Chris Wilson
2017-06-29 16:55 ` Michel Thierry
0 siblings, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2017-06-29 13:07 UTC (permalink / raw)
To: Ville Syrjälä, Michel Thierry; +Cc: intel-gfx
Quoting Ville Syrjälä (2017-06-29 14:05:25)
> On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote:
> > There's no need to keep reading random registers in i915_swizzle_info if
> > the platform is not doing GPU side swizzling.
> >
> > After HSW, swizzling is not used, and the CPU's memory controller
> > performs all the address swizzling modifications, commit be292e1563ac5b
> > ("drm/i915/bdw: Let the memory controller do all the swizzling").
>
> But BDW still contains the registers and hardware capability no? So
> might be a good idea to be able to check that it's not misconfigured.
Especially in debugfs where it is useful to show both the hw state and
what we thought it should be.
-Chris
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle
2017-06-29 13:07 ` Chris Wilson
@ 2017-06-29 16:55 ` Michel Thierry
0 siblings, 0 replies; 5+ messages in thread
From: Michel Thierry @ 2017-06-29 16:55 UTC (permalink / raw)
To: Chris Wilson, Ville Syrjälä; +Cc: intel-gfx
On 6/29/2017 6:07 AM, Chris Wilson wrote:
> Quoting Ville Syrjälä (2017-06-29 14:05:25)
>> On Wed, Jun 28, 2017 at 04:24:27PM -0700, Michel Thierry wrote:
>>> There's no need to keep reading random registers in i915_swizzle_info if
>>> the platform is not doing GPU side swizzling.
>>>
>>> After HSW, swizzling is not used, and the CPU's memory controller
>>> performs all the address swizzling modifications, commit be292e1563ac5b
>>> ("drm/i915/bdw: Let the memory controller do all the swizzling").
>>
>> But BDW still contains the registers and hardware capability no? So
>> might be a good idea to be able to check that it's not misconfigured.
>
> Especially in debugfs where it is useful to show both the hw state and
> what we thought it should be.
Hi,
Yes, the registers are still there (but this may change). Are you ok if
I change this to apply only to GEN9+?
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2017-06-28 23:24 [PATCH] drm/i915: Skip i915_swizzle_info in platforms without GPU side swizzle Michel Thierry
2017-06-28 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-06-29 13:05 ` [PATCH] " Ville Syrjälä
2017-06-29 13:07 ` Chris Wilson
2017-06-29 16:55 ` Michel Thierry
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