[PATCH V4 0/2] timer: add imx tpm timer support

[PATCH V4 0/2] timer: add imx tpm timer support

[Dong Aisheng]

The Timer/PWM Module (TPM) supports input capture, output compare,
and the generation of PWM signals to control electric motor and power
management applications. The counter, compare and capture registers
are clocked by an asynchronous clock that can remain enabled in low
power modes. TPM can support global counter bus where one TPM drives
the counter bus for the others, provided bit width is the same.

This patch only adds the timer support. PWM would be added later.

ChangeLog:
v3->v4:
 * also add ETIME explanation in function
v2->v3:
 * address a few minor comments from Daniel Lezcano
 * add more explaination on ETIME check in commit message
v1->v2:
 * change to readl/writel from __raw_readl/writel according to Arnd's
   suggestion to avoid endian issue
 * add help information in Kconfig
 * add more error checking

Dong Aisheng (2):
  dt-bindings: timer: add nxp tpm timer binding doc
  timer: imx-tpm: add imx tpm timer support

 .../devicetree/bindings/timer/nxp,tpm-timer.txt    |  28 +++
 drivers/clocksource/Kconfig                        |   8 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/timer-imx-tpm.c                | 239 +++++++++++++++++++++
 4 files changed, 276 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
 create mode 100644 drivers/clocksource/timer-imx-tpm.c

-- 
2.7.4

[PATCH V4 0/2] timer: add imx tpm timer support

[Dong Aisheng]

The Timer/PWM Module (TPM) supports input capture, output compare,
and the generation of PWM signals to control electric motor and power
management applications. The counter, compare and capture registers
are clocked by an asynchronous clock that can remain enabled in low
power modes. TPM can support global counter bus where one TPM drives
the counter bus for the others, provided bit width is the same.

This patch only adds the timer support. PWM would be added later.

ChangeLog:
v3->v4:
 * also add ETIME explanation in function
v2->v3:
 * address a few minor comments from Daniel Lezcano
 * add more explaination on ETIME check in commit message
v1->v2:
 * change to readl/writel from __raw_readl/writel according to Arnd's
   suggestion to avoid endian issue
 * add help information in Kconfig
 * add more error checking

Dong Aisheng (2):
  dt-bindings: timer: add nxp tpm timer binding doc
  timer: imx-tpm: add imx tpm timer support

 .../devicetree/bindings/timer/nxp,tpm-timer.txt    |  28 +++
 drivers/clocksource/Kconfig                        |   8 +
 drivers/clocksource/Makefile                       |   1 +
 drivers/clocksource/timer-imx-tpm.c                | 239 +++++++++++++++++++++
 4 files changed, 276 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
 create mode 100644 drivers/clocksource/timer-imx-tpm.c

-- 
2.7.4

[PATCH V4 1/2] dt-bindings: timer: add nxp tpm timer binding doc

[Dong Aisheng]

Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM)
binding doc.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Bai Ping <ping.bai@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

---
ChangeLog:
 v1->v4:
 * No changes
---
 .../devicetree/bindings/timer/nxp,tpm-timer.txt    | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
new file mode 100644
index 0000000..b4aa7dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
@@ -0,0 +1,28 @@
+NXP Low Power Timer/Pulse Width Modulation Module (TPM)
+
+The Timer/PWM Module (TPM) supports input capture, output compare,
+and the generation of PWM signals to control electric motor and power
+management applications. The counter, compare and capture registers
+are clocked by an asynchronous clock that can remain enabled in low
+power modes. TPM can support global counter bus where one TPM drives
+the counter bus for the others, provided bit width is the same.
+
+Required properties:
+
+- compatible :	should be "fsl,imx7ulp-tpm"
+- reg :		Specifies base physical address and size of the register sets
+		for the clock event device and clock source device.
+- interrupts :	Should be the clock event device interrupt.
+- clocks :	The clocks provided by the SoC to drive the timer, must contain
+		an entry for each entry in clock-names.
+- clock-names : Must include the following entries: "igp" and "per".
+
+Example:
+tpm5: tpm@40260000 {
+	compatible = "fsl,imx7ulp-tpm";
+	reg = <0x40260000 0x1000>;
+	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+		 <&clks IMX7ULP_CLK_LPTPM5>;
+	clock-names = "ipg", "per";
+};
-- 
2.7.4

[PATCH V4 1/2] dt-bindings: timer: add nxp tpm timer binding doc

[Dong Aisheng]

Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM)
binding doc.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Bai Ping <ping.bai@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

---
ChangeLog:
 v1->v4:
 * No changes
---
 .../devicetree/bindings/timer/nxp,tpm-timer.txt    | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
new file mode 100644
index 0000000..b4aa7dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
@@ -0,0 +1,28 @@
+NXP Low Power Timer/Pulse Width Modulation Module (TPM)
+
+The Timer/PWM Module (TPM) supports input capture, output compare,
+and the generation of PWM signals to control electric motor and power
+management applications. The counter, compare and capture registers
+are clocked by an asynchronous clock that can remain enabled in low
+power modes. TPM can support global counter bus where one TPM drives
+the counter bus for the others, provided bit width is the same.
+
+Required properties:
+
+- compatible :	should be "fsl,imx7ulp-tpm"
+- reg :		Specifies base physical address and size of the register sets
+		for the clock event device and clock source device.
+- interrupts :	Should be the clock event device interrupt.
+- clocks :	The clocks provided by the SoC to drive the timer, must contain
+		an entry for each entry in clock-names.
+- clock-names : Must include the following entries: "igp" and "per".
+
+Example:
+tpm5: tpm@40260000 {
+	compatible = "fsl,imx7ulp-tpm";
+	reg = <0x40260000 0x1000>;
+	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+		 <&clks IMX7ULP_CLK_LPTPM5>;
+	clock-names = "ipg", "per";
+};
-- 
2.7.4

[PATCH V4 1/2] dt-bindings: timer: add nxp tpm timer binding doc

[Dong Aisheng]

Adding NXP Low Power Timer/Pulse Width Modulation Module (TPM)
binding doc.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree at vger.kernel.org
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Bai Ping <ping.bai@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

---
ChangeLog:
 v1->v4:
 * No changes
---
 .../devicetree/bindings/timer/nxp,tpm-timer.txt    | 28 ++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt

diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
new file mode 100644
index 0000000..b4aa7dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt
@@ -0,0 +1,28 @@
+NXP Low Power Timer/Pulse Width Modulation Module (TPM)
+
+The Timer/PWM Module (TPM) supports input capture, output compare,
+and the generation of PWM signals to control electric motor and power
+management applications. The counter, compare and capture registers
+are clocked by an asynchronous clock that can remain enabled in low
+power modes. TPM can support global counter bus where one TPM drives
+the counter bus for the others, provided bit width is the same.
+
+Required properties:
+
+- compatible :	should be "fsl,imx7ulp-tpm"
+- reg :		Specifies base physical address and size of the register sets
+		for the clock event device and clock source device.
+- interrupts :	Should be the clock event device interrupt.
+- clocks :	The clocks provided by the SoC to drive the timer, must contain
+		an entry for each entry in clock-names.
+- clock-names : Must include the following entries: "igp" and "per".
+
+Example:
+tpm5: tpm at 40260000 {
+	compatible = "fsl,imx7ulp-tpm";
+	reg = <0x40260000 0x1000>;
+	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
+		 <&clks IMX7ULP_CLK_LPTPM5>;
+	clock-names = "ipg", "per";
+};
-- 
2.7.4

[PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support

[Dong Aisheng]

IMX Timer/PWM Module (TPM) supports both timer and pwm function while
this patch only adds the timer support. PWM would be added later.

The TPM counter, compare and capture registers are clocked by an
asynchronous clock that can remain enabled in low power modes.

NOTE: We observed in a very small probability, the bus fabric
contention between GPU and A7 may results a few cycles delay
of writing CNT registers which may cause the min_delta event got
missed, so we need add a ETIME check here in case it happened.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

---
ChangeLog:
v3->v4: 
 * also add ETIME explanation in function
v2->v3:
 * address all comments from Daniel Lezcano
 * add more explaination on ETIME check in commit message
v1->v2:
 * change to readl/writel from __raw_readl/writel according to Arnd's
   suggestion to avoid endian issue
 * add help information in Kconfig
 * add more error checking
---
 drivers/clocksource/Kconfig         |   8 ++
 drivers/clocksource/Makefile        |   1 +
 drivers/clocksource/timer-imx-tpm.c | 239 ++++++++++++++++++++++++++++++++++++
 3 files changed, 248 insertions(+)
 create mode 100644 drivers/clocksource/timer-imx-tpm.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 88818a4..a4a1ff3 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -591,6 +591,14 @@ config CLKSRC_IMX_GPT
 	depends on ARM && CLKDEV_LOOKUP
 	select CLKSRC_MMIO
 
+config CLKSRC_IMX_TPM
+	bool "Clocksource using i.MX TPM" if COMPILE_TEST
+	depends on ARM && CLKDEV_LOOKUP && GENERIC_CLOCKEVENTS
+	select CLKSRC_MMIO
+	help
+	  Enable this option to use IMX Timer/PWM Module (TPM) timer as
+	  clocksource.
+
 config CLKSRC_ST_LPC
 	bool "Low power clocksource found in the LPC" if COMPILE_TEST
 	select TIMER_OF if OF
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 72bfd00..1631a84 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_CLKSRC_VERSATILE)		+= versatile.o
 obj-$(CONFIG_CLKSRC_MIPS_GIC)		+= mips-gic-timer.o
 obj-$(CONFIG_CLKSRC_TANGO_XTAL)		+= tango_xtal.o
 obj-$(CONFIG_CLKSRC_IMX_GPT)		+= timer-imx-gpt.o
+obj-$(CONFIG_CLKSRC_IMX_TPM)		+= timer-imx-tpm.o
 obj-$(CONFIG_ASM9260_TIMER)		+= asm9260_timer.o
 obj-$(CONFIG_H8300_TMR8)		+= h8300_timer8.o
 obj-$(CONFIG_H8300_TMR16)		+= h8300_timer16.o
diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c
new file mode 100644
index 0000000..86567cb
--- /dev/null
+++ b/drivers/clocksource/timer-imx-tpm.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+
+#define TPM_SC				0x10
+#define TPM_SC_CMOD_INC_PER_CNT		(0x1 << 3)
+#define TPM_SC_CMOD_DIV_DEFAULT		0x3
+#define TPM_CNT				0x14
+#define TPM_MOD				0x18
+#define TPM_STATUS			0x1c
+#define TPM_STATUS_CH0F			BIT(0)
+#define TPM_C0SC			0x20
+#define TPM_C0SC_CHIE			BIT(6)
+#define TPM_C0SC_MODE_SHIFT		2
+#define TPM_C0SC_MODE_MASK		0x3c
+#define TPM_C0SC_MODE_SW_COMPARE	0x4
+#define TPM_C0V				0x24
+
+static void __iomem *timer_base;
+static struct clock_event_device clockevent_tpm;
+
+static inline void tpm_timer_disable(void)
+{
+	unsigned int val;
+
+	/* channel disable */
+	val = readl(timer_base + TPM_C0SC);
+	val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE);
+	writel(val, timer_base + TPM_C0SC);
+}
+
+static inline void tpm_timer_enable(void)
+{
+	unsigned int val;
+
+	/* channel enabled in sw compare mode */
+	val = readl(timer_base + TPM_C0SC);
+	val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) |
+	       TPM_C0SC_CHIE;
+	writel(val, timer_base + TPM_C0SC);
+}
+
+static inline void tpm_irq_acknowledge(void)
+{
+	writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
+}
+
+static struct delay_timer tpm_delay_timer;
+
+static inline unsigned long tpm_read_counter(void)
+{
+	return readl(timer_base + TPM_CNT);
+}
+
+static unsigned long tpm_read_current_timer(void)
+{
+	return tpm_read_counter();
+}
+
+static u64 notrace tpm_read_sched_clock(void)
+{
+	return tpm_read_counter();
+}
+
+static int __init tpm_clocksource_init(unsigned long rate)
+{
+	tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
+	tpm_delay_timer.freq = rate;
+	register_current_timer_delay(&tpm_delay_timer);
+
+	sched_clock_register(tpm_read_sched_clock, 32, rate);
+
+	return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
+				     rate, 200, 32, clocksource_mmio_readl_up);
+}
+
+static int tpm_set_next_event(unsigned long delta,
+				struct clock_event_device *evt)
+{
+	unsigned long next, now;
+
+	next = tpm_read_counter();
+	next += delta;
+	writel(next, timer_base + TPM_C0V);
+	now = tpm_read_counter();
+
+	/*
+	 * NOTE: We observed in a very small probability, the bus fabric
+	 * contention between GPU and A7 may results a few cycles delay
+	 * of writing CNT registers which may cause the min_delta event got
+	 * missed, so we need add a ETIME check here in case it happened.
+	 */
+	return (int)((next - now) <= 0) ? -ETIME : 0;
+}
+
+static int tpm_set_state_oneshot(struct clock_event_device *evt)
+{
+	tpm_timer_enable();
+
+	return 0;
+}
+
+static int tpm_set_state_shutdown(struct clock_event_device *evt)
+{
+	tpm_timer_disable();
+
+	return 0;
+}
+
+static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	tpm_irq_acknowledge();
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct clock_event_device clockevent_tpm = {
+	.name			= "i.MX7ULP TPM Timer",
+	.features		= CLOCK_EVT_FEAT_ONESHOT,
+	.set_state_oneshot	= tpm_set_state_oneshot,
+	.set_next_event		= tpm_set_next_event,
+	.set_state_shutdown	= tpm_set_state_shutdown,
+	.rating			= 200,
+};
+
+static struct irqaction tpm_timer_irq = {
+	.name		= "i.MX7ULP TPM Timer",
+	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= tpm_timer_interrupt,
+	.dev_id		= &clockevent_tpm,
+};
+
+static int __init tpm_clockevent_init(unsigned long rate, int irq)
+{
+	setup_irq(irq, &tpm_timer_irq);
+
+	clockevent_tpm.cpumask = cpumask_of(0);
+	clockevent_tpm.irq = irq;
+	clockevents_config_and_register(&clockevent_tpm,
+					rate, 300, 0xfffffffe);
+
+	return 0;
+}
+
+static int __init tpm_timer_init(struct device_node *np)
+{
+	struct clk *ipg, *per;
+	int irq, ret;
+	u32 rate;
+
+	timer_base = of_iomap(np, 0);
+	if (!timer_base) {
+		pr_err("tpm: failed to get base address\n");
+		return -ENXIO;
+	}
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (!irq) {
+		pr_err("tpm: failed to get irq\n");
+		ret = -ENOENT;
+		goto err_iomap;
+	}
+
+	ipg = of_clk_get_by_name(np, "ipg");
+	per = of_clk_get_by_name(np, "per");
+	if (IS_ERR(ipg) || IS_ERR(per)) {
+		pr_err("tpm: failed to get igp or per clk\n");
+		ret = -ENODEV;
+		goto err_clk_get;
+	}
+
+	/* enable clk before accessing registers */
+	ret = clk_prepare_enable(ipg);
+	if (ret) {
+		pr_err("tpm: ipg clock enable failed (%d)\n", ret);
+		goto err_ipg_clk_enable;
+	}
+
+	ret = clk_prepare_enable(per);
+	if (ret) {
+		pr_err("tpm: per clock enable failed (%d)\n", ret);
+		goto err_per_clk_enable;
+	}
+
+	/*
+	 * Initialize tpm module to a known state
+	 * 1) Counter disabled
+	 * 2) TPM counter operates in up counting mode
+	 * 3) Timer Overflow Interrupt disabled
+	 * 4) Channel0 disabled
+	 * 5) DMA transfers disabled
+	 */
+	writel(0, timer_base + TPM_SC);
+	writel(0, timer_base + TPM_CNT);
+	writel(0, timer_base + TPM_C0SC);
+
+	/* increase per cnt, div 8 by default */
+	writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
+		     timer_base + TPM_SC);
+
+	/* set MOD register to maximum for free running mode */
+	writel(0xffffffff, timer_base + TPM_MOD);
+
+	rate = clk_get_rate(per) >> 3;
+	tpm_clocksource_init(rate);
+	tpm_clockevent_init(rate, irq);
+
+	return 0;
+
+err_per_clk_enable:
+	clk_disable_unprepare(ipg);
+err_ipg_clk_enable:
+err_clk_get:
+	clk_put(per);
+	clk_put(ipg);
+err_iomap:
+	iounmap(timer_base);
+	return ret;
+}
+CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);
-- 
2.7.4

[PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support

[Dong Aisheng]

IMX Timer/PWM Module (TPM) supports both timer and pwm function while
this patch only adds the timer support. PWM would be added later.

The TPM counter, compare and capture registers are clocked by an
asynchronous clock that can remain enabled in low power modes.

NOTE: We observed in a very small probability, the bus fabric
contention between GPU and A7 may results a few cycles delay
of writing CNT registers which may cause the min_delta event got
missed, so we need add a ETIME check here in case it happened.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>

---
ChangeLog:
v3->v4: 
 * also add ETIME explanation in function
v2->v3:
 * address all comments from Daniel Lezcano
 * add more explaination on ETIME check in commit message
v1->v2:
 * change to readl/writel from __raw_readl/writel according to Arnd's
   suggestion to avoid endian issue
 * add help information in Kconfig
 * add more error checking
---
 drivers/clocksource/Kconfig         |   8 ++
 drivers/clocksource/Makefile        |   1 +
 drivers/clocksource/timer-imx-tpm.c | 239 ++++++++++++++++++++++++++++++++++++
 3 files changed, 248 insertions(+)
 create mode 100644 drivers/clocksource/timer-imx-tpm.c

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 88818a4..a4a1ff3 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -591,6 +591,14 @@ config CLKSRC_IMX_GPT
 	depends on ARM && CLKDEV_LOOKUP
 	select CLKSRC_MMIO
 
+config CLKSRC_IMX_TPM
+	bool "Clocksource using i.MX TPM" if COMPILE_TEST
+	depends on ARM && CLKDEV_LOOKUP && GENERIC_CLOCKEVENTS
+	select CLKSRC_MMIO
+	help
+	  Enable this option to use IMX Timer/PWM Module (TPM) timer as
+	  clocksource.
+
 config CLKSRC_ST_LPC
 	bool "Low power clocksource found in the LPC" if COMPILE_TEST
 	select TIMER_OF if OF
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 72bfd00..1631a84 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_CLKSRC_VERSATILE)		+= versatile.o
 obj-$(CONFIG_CLKSRC_MIPS_GIC)		+= mips-gic-timer.o
 obj-$(CONFIG_CLKSRC_TANGO_XTAL)		+= tango_xtal.o
 obj-$(CONFIG_CLKSRC_IMX_GPT)		+= timer-imx-gpt.o
+obj-$(CONFIG_CLKSRC_IMX_TPM)		+= timer-imx-tpm.o
 obj-$(CONFIG_ASM9260_TIMER)		+= asm9260_timer.o
 obj-$(CONFIG_H8300_TMR8)		+= h8300_timer8.o
 obj-$(CONFIG_H8300_TMR16)		+= h8300_timer16.o
diff --git a/drivers/clocksource/timer-imx-tpm.c b/drivers/clocksource/timer-imx-tpm.c
new file mode 100644
index 0000000..86567cb
--- /dev/null
+++ b/drivers/clocksource/timer-imx-tpm.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+
+#define TPM_SC				0x10
+#define TPM_SC_CMOD_INC_PER_CNT		(0x1 << 3)
+#define TPM_SC_CMOD_DIV_DEFAULT		0x3
+#define TPM_CNT				0x14
+#define TPM_MOD				0x18
+#define TPM_STATUS			0x1c
+#define TPM_STATUS_CH0F			BIT(0)
+#define TPM_C0SC			0x20
+#define TPM_C0SC_CHIE			BIT(6)
+#define TPM_C0SC_MODE_SHIFT		2
+#define TPM_C0SC_MODE_MASK		0x3c
+#define TPM_C0SC_MODE_SW_COMPARE	0x4
+#define TPM_C0V				0x24
+
+static void __iomem *timer_base;
+static struct clock_event_device clockevent_tpm;
+
+static inline void tpm_timer_disable(void)
+{
+	unsigned int val;
+
+	/* channel disable */
+	val = readl(timer_base + TPM_C0SC);
+	val &= ~(TPM_C0SC_MODE_MASK | TPM_C0SC_CHIE);
+	writel(val, timer_base + TPM_C0SC);
+}
+
+static inline void tpm_timer_enable(void)
+{
+	unsigned int val;
+
+	/* channel enabled in sw compare mode */
+	val = readl(timer_base + TPM_C0SC);
+	val |= (TPM_C0SC_MODE_SW_COMPARE << TPM_C0SC_MODE_SHIFT) |
+	       TPM_C0SC_CHIE;
+	writel(val, timer_base + TPM_C0SC);
+}
+
+static inline void tpm_irq_acknowledge(void)
+{
+	writel(TPM_STATUS_CH0F, timer_base + TPM_STATUS);
+}
+
+static struct delay_timer tpm_delay_timer;
+
+static inline unsigned long tpm_read_counter(void)
+{
+	return readl(timer_base + TPM_CNT);
+}
+
+static unsigned long tpm_read_current_timer(void)
+{
+	return tpm_read_counter();
+}
+
+static u64 notrace tpm_read_sched_clock(void)
+{
+	return tpm_read_counter();
+}
+
+static int __init tpm_clocksource_init(unsigned long rate)
+{
+	tpm_delay_timer.read_current_timer = &tpm_read_current_timer;
+	tpm_delay_timer.freq = rate;
+	register_current_timer_delay(&tpm_delay_timer);
+
+	sched_clock_register(tpm_read_sched_clock, 32, rate);
+
+	return clocksource_mmio_init(timer_base + TPM_CNT, "imx-tpm",
+				     rate, 200, 32, clocksource_mmio_readl_up);
+}
+
+static int tpm_set_next_event(unsigned long delta,
+				struct clock_event_device *evt)
+{
+	unsigned long next, now;
+
+	next = tpm_read_counter();
+	next += delta;
+	writel(next, timer_base + TPM_C0V);
+	now = tpm_read_counter();
+
+	/*
+	 * NOTE: We observed in a very small probability, the bus fabric
+	 * contention between GPU and A7 may results a few cycles delay
+	 * of writing CNT registers which may cause the min_delta event got
+	 * missed, so we need add a ETIME check here in case it happened.
+	 */
+	return (int)((next - now) <= 0) ? -ETIME : 0;
+}
+
+static int tpm_set_state_oneshot(struct clock_event_device *evt)
+{
+	tpm_timer_enable();
+
+	return 0;
+}
+
+static int tpm_set_state_shutdown(struct clock_event_device *evt)
+{
+	tpm_timer_disable();
+
+	return 0;
+}
+
+static irqreturn_t tpm_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = dev_id;
+
+	tpm_irq_acknowledge();
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct clock_event_device clockevent_tpm = {
+	.name			= "i.MX7ULP TPM Timer",
+	.features		= CLOCK_EVT_FEAT_ONESHOT,
+	.set_state_oneshot	= tpm_set_state_oneshot,
+	.set_next_event		= tpm_set_next_event,
+	.set_state_shutdown	= tpm_set_state_shutdown,
+	.rating			= 200,
+};
+
+static struct irqaction tpm_timer_irq = {
+	.name		= "i.MX7ULP TPM Timer",
+	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= tpm_timer_interrupt,
+	.dev_id		= &clockevent_tpm,
+};
+
+static int __init tpm_clockevent_init(unsigned long rate, int irq)
+{
+	setup_irq(irq, &tpm_timer_irq);
+
+	clockevent_tpm.cpumask = cpumask_of(0);
+	clockevent_tpm.irq = irq;
+	clockevents_config_and_register(&clockevent_tpm,
+					rate, 300, 0xfffffffe);
+
+	return 0;
+}
+
+static int __init tpm_timer_init(struct device_node *np)
+{
+	struct clk *ipg, *per;
+	int irq, ret;
+	u32 rate;
+
+	timer_base = of_iomap(np, 0);
+	if (!timer_base) {
+		pr_err("tpm: failed to get base address\n");
+		return -ENXIO;
+	}
+
+	irq = irq_of_parse_and_map(np, 0);
+	if (!irq) {
+		pr_err("tpm: failed to get irq\n");
+		ret = -ENOENT;
+		goto err_iomap;
+	}
+
+	ipg = of_clk_get_by_name(np, "ipg");
+	per = of_clk_get_by_name(np, "per");
+	if (IS_ERR(ipg) || IS_ERR(per)) {
+		pr_err("tpm: failed to get igp or per clk\n");
+		ret = -ENODEV;
+		goto err_clk_get;
+	}
+
+	/* enable clk before accessing registers */
+	ret = clk_prepare_enable(ipg);
+	if (ret) {
+		pr_err("tpm: ipg clock enable failed (%d)\n", ret);
+		goto err_ipg_clk_enable;
+	}
+
+	ret = clk_prepare_enable(per);
+	if (ret) {
+		pr_err("tpm: per clock enable failed (%d)\n", ret);
+		goto err_per_clk_enable;
+	}
+
+	/*
+	 * Initialize tpm module to a known state
+	 * 1) Counter disabled
+	 * 2) TPM counter operates in up counting mode
+	 * 3) Timer Overflow Interrupt disabled
+	 * 4) Channel0 disabled
+	 * 5) DMA transfers disabled
+	 */
+	writel(0, timer_base + TPM_SC);
+	writel(0, timer_base + TPM_CNT);
+	writel(0, timer_base + TPM_C0SC);
+
+	/* increase per cnt, div 8 by default */
+	writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
+		     timer_base + TPM_SC);
+
+	/* set MOD register to maximum for free running mode */
+	writel(0xffffffff, timer_base + TPM_MOD);
+
+	rate = clk_get_rate(per) >> 3;
+	tpm_clocksource_init(rate);
+	tpm_clockevent_init(rate, irq);
+
+	return 0;
+
+err_per_clk_enable:
+	clk_disable_unprepare(ipg);
+err_ipg_clk_enable:
+err_clk_get:
+	clk_put(per);
+	clk_put(ipg);
+err_iomap:
+	iounmap(timer_base);
+	return ret;
+}
+CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);
-- 
2.7.4

Re: [PATCH V4 0/2] timer: add imx tpm timer support

[Jonathan Cameron]

On Wed, 5 Jul 2017 10:35:10 +0800
Dong Aisheng <aisheng.dong@nxp.com> wrote:

> The Timer/PWM Module (TPM) supports input capture, output compare,
> and the generation of PWM signals to control electric motor and power
> management applications. The counter, compare and capture registers
> are clocked by an asynchronous clock that can remain enabled in low
> power modes. TPM can support global counter bus where one TPM drives
> the counter bus for the others, provided bit width is the same.
> 
> This patch only adds the timer support. PWM would be added later.
Hi Dong,

Not relevant to this patch - just an observation!

Just came across this thread and took a look at the hardware. I see
some of the timers (particularly the flextimers) support quadrature
encoder modes.  Just thought I'd point you at some on going discussions
on the IIO list (linux-iio@vger.kernel.org) trying to improve the
interface for such devices.  Might be of interest (or not depending on
whether support for that functionality is of interest!)

http://marc.info/?l=linux-iio&m=149904379731556&w=2

Jonathan
> 
> ChangeLog:
> v3->v4:
>  * also add ETIME explanation in function
> v2->v3:
>  * address a few minor comments from Daniel Lezcano
>  * add more explaination on ETIME check in commit message
> v1->v2:
>  * change to readl/writel from __raw_readl/writel according to Arnd's
>    suggestion to avoid endian issue
>  * add help information in Kconfig
>  * add more error checking
> 
> Dong Aisheng (2):
>   dt-bindings: timer: add nxp tpm timer binding doc
>   timer: imx-tpm: add imx tpm timer support
> 
>  .../devicetree/bindings/timer/nxp,tpm-timer.txt    |  28 +++
>  drivers/clocksource/Kconfig                        |   8 +
>  drivers/clocksource/Makefile                       |   1 +
>  drivers/clocksource/timer-imx-tpm.c                | 239
> +++++++++++++++++++++ 4 files changed, 276 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt create mode
> 100644 drivers/clocksource/timer-imx-tpm.c
> 

[PATCH V4 0/2] timer: add imx tpm timer support

[Jonathan Cameron]

On Wed, 5 Jul 2017 10:35:10 +0800
Dong Aisheng <aisheng.dong@nxp.com> wrote:

> The Timer/PWM Module (TPM) supports input capture, output compare,
> and the generation of PWM signals to control electric motor and power
> management applications. The counter, compare and capture registers
> are clocked by an asynchronous clock that can remain enabled in low
> power modes. TPM can support global counter bus where one TPM drives
> the counter bus for the others, provided bit width is the same.
> 
> This patch only adds the timer support. PWM would be added later.
Hi Dong,

Not relevant to this patch - just an observation!

Just came across this thread and took a look at the hardware. I see
some of the timers (particularly the flextimers) support quadrature
encoder modes.  Just thought I'd point you at some on going discussions
on the IIO list (linux-iio at vger.kernel.org) trying to improve the
interface for such devices.  Might be of interest (or not depending on
whether support for that functionality is of interest!)

http://marc.info/?l=linux-iio&m=149904379731556&w=2

Jonathan
> 
> ChangeLog:
> v3->v4:
>  * also add ETIME explanation in function
> v2->v3:
>  * address a few minor comments from Daniel Lezcano
>  * add more explaination on ETIME check in commit message
> v1->v2:
>  * change to readl/writel from __raw_readl/writel according to Arnd's
>    suggestion to avoid endian issue
>  * add help information in Kconfig
>  * add more error checking
> 
> Dong Aisheng (2):
>   dt-bindings: timer: add nxp tpm timer binding doc
>   timer: imx-tpm: add imx tpm timer support
> 
>  .../devicetree/bindings/timer/nxp,tpm-timer.txt    |  28 +++
>  drivers/clocksource/Kconfig                        |   8 +
>  drivers/clocksource/Makefile                       |   1 +
>  drivers/clocksource/timer-imx-tpm.c                | 239
> +++++++++++++++++++++ 4 files changed, 276 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt create mode
> 100644 drivers/clocksource/timer-imx-tpm.c
> 

RE: [PATCH V4 0/2] timer: add imx tpm timer support

[A.s. Dong]

> -----Original Message-----
> From: Jonathan Cameron [mailto:Jonathan.Cameron@huawei.com]
> Sent: Wednesday, July 05, 2017 4:24 PM
> To: A.s. Dong
> Cc: linux-kernel@vger.kernel.org; Jacky Bai; Anson Huang;
> daniel.lezcano@linaro.org; kernel@pengutronix.de; tglx@linutronix.de;
> shawnguo@kernel.org; linux-arm-kernel@lists.infradead.org;
> dongas86@gmail.com
> Subject: Re: [PATCH V4 0/2] timer: add imx tpm timer support
> 
> On Wed, 5 Jul 2017 10:35:10 +0800
> Dong Aisheng <aisheng.dong@nxp.com> wrote:
> 
> > The Timer/PWM Module (TPM) supports input capture, output compare, and
> > the generation of PWM signals to control electric motor and power
> > management applications. The counter, compare and capture registers
> > are clocked by an asynchronous clock that can remain enabled in low
> > power modes. TPM can support global counter bus where one TPM drives
> > the counter bus for the others, provided bit width is the same.
> >
> > This patch only adds the timer support. PWM would be added later.
> Hi Dong,
> 
> Not relevant to this patch - just an observation!
> 
> Just came across this thread and took a look at the hardware. I see some
> of the timers (particularly the flextimers) support quadrature encoder
> modes.  Just thought I'd point you at some on going discussions on the
> IIO list (linux-iio@vger.kernel.org) trying to improve the interface for
> such devices.  Might be of interest (or not depending on whether support
> for that functionality is of interest!)
> 
> http://marc.info/?l=linux-iio&m=149904379731556&w=2
> 

Hi Jonathan,

Thanks for the info.
I will find time to check it later.

Regards
Dong Aisheng

[PATCH V4 0/2] timer: add imx tpm timer support

[A.s. Dong]

> -----Original Message-----
> From: Jonathan Cameron [mailto:Jonathan.Cameron at huawei.com]
> Sent: Wednesday, July 05, 2017 4:24 PM
> To: A.s. Dong
> Cc: linux-kernel at vger.kernel.org; Jacky Bai; Anson Huang;
> daniel.lezcano at linaro.org; kernel at pengutronix.de; tglx at linutronix.de;
> shawnguo at kernel.org; linux-arm-kernel at lists.infradead.org;
> dongas86 at gmail.com
> Subject: Re: [PATCH V4 0/2] timer: add imx tpm timer support
> 
> On Wed, 5 Jul 2017 10:35:10 +0800
> Dong Aisheng <aisheng.dong@nxp.com> wrote:
> 
> > The Timer/PWM Module (TPM) supports input capture, output compare, and
> > the generation of PWM signals to control electric motor and power
> > management applications. The counter, compare and capture registers
> > are clocked by an asynchronous clock that can remain enabled in low
> > power modes. TPM can support global counter bus where one TPM drives
> > the counter bus for the others, provided bit width is the same.
> >
> > This patch only adds the timer support. PWM would be added later.
> Hi Dong,
> 
> Not relevant to this patch - just an observation!
> 
> Just came across this thread and took a look at the hardware. I see some
> of the timers (particularly the flextimers) support quadrature encoder
> modes.  Just thought I'd point you at some on going discussions on the
> IIO list (linux-iio at vger.kernel.org) trying to improve the interface for
> such devices.  Might be of interest (or not depending on whether support
> for that functionality is of interest!)
> 
> http://marc.info/?l=linux-iio&m=149904379731556&w=2
> 

Hi Jonathan,

Thanks for the info.
I will find time to check it later.

Regards
Dong Aisheng

RE: [PATCH V4 0/2] timer: add imx tpm timer support

[A.s. Dong]

Gently Ping...

It's been two weeks.

> -----Original Message-----
> From: Dong Aisheng [mailto:aisheng.dong@nxp.com]
> Sent: Wednesday, July 05, 2017 10:35 AM
> To: linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org; daniel.lezcano@linaro.org;
> tglx@linutronix.de; shawnguo@kernel.org; Jacky Bai; Anson Huang;
> dongas86@gmail.com; kernel@pengutronix.de; A.s. Dong
> Subject: [PATCH V4 0/2] timer: add imx tpm timer support
> 
> The Timer/PWM Module (TPM) supports input capture, output compare, and the
> generation of PWM signals to control electric motor and power management
> applications. The counter, compare and capture registers are clocked by an
> asynchronous clock that can remain enabled in low power modes. TPM can
> support global counter bus where one TPM drives the counter bus for the
> others, provided bit width is the same.
> 
> This patch only adds the timer support. PWM would be added later.
> 
> ChangeLog:
> v3->v4:
>  * also add ETIME explanation in function
> v2->v3:
>  * address a few minor comments from Daniel Lezcano
>  * add more explaination on ETIME check in commit message
> v1->v2:
>  * change to readl/writel from __raw_readl/writel according to Arnd's
>    suggestion to avoid endian issue
>  * add help information in Kconfig
>  * add more error checking
> 
> Dong Aisheng (2):
>   dt-bindings: timer: add nxp tpm timer binding doc
>   timer: imx-tpm: add imx tpm timer support
> 
>  .../devicetree/bindings/timer/nxp,tpm-timer.txt    |  28 +++
>  drivers/clocksource/Kconfig                        |   8 +
>  drivers/clocksource/Makefile                       |   1 +
>  drivers/clocksource/timer-imx-tpm.c                | 239
> +++++++++++++++++++++
>  4 files changed, 276 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-
> timer.txt
>  create mode 100644 drivers/clocksource/timer-imx-tpm.c
> 
> --
> 2.7.4

[PATCH V4 0/2] timer: add imx tpm timer support

[A.s. Dong]

Gently Ping...

It's been two weeks.

> -----Original Message-----
> From: Dong Aisheng [mailto:aisheng.dong at nxp.com]
> Sent: Wednesday, July 05, 2017 10:35 AM
> To: linux-kernel at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org; daniel.lezcano at linaro.org;
> tglx at linutronix.de; shawnguo at kernel.org; Jacky Bai; Anson Huang;
> dongas86 at gmail.com; kernel at pengutronix.de; A.s. Dong
> Subject: [PATCH V4 0/2] timer: add imx tpm timer support
> 
> The Timer/PWM Module (TPM) supports input capture, output compare, and the
> generation of PWM signals to control electric motor and power management
> applications. The counter, compare and capture registers are clocked by an
> asynchronous clock that can remain enabled in low power modes. TPM can
> support global counter bus where one TPM drives the counter bus for the
> others, provided bit width is the same.
> 
> This patch only adds the timer support. PWM would be added later.
> 
> ChangeLog:
> v3->v4:
>  * also add ETIME explanation in function
> v2->v3:
>  * address a few minor comments from Daniel Lezcano
>  * add more explaination on ETIME check in commit message
> v1->v2:
>  * change to readl/writel from __raw_readl/writel according to Arnd's
>    suggestion to avoid endian issue
>  * add help information in Kconfig
>  * add more error checking
> 
> Dong Aisheng (2):
>   dt-bindings: timer: add nxp tpm timer binding doc
>   timer: imx-tpm: add imx tpm timer support
> 
>  .../devicetree/bindings/timer/nxp,tpm-timer.txt    |  28 +++
>  drivers/clocksource/Kconfig                        |   8 +
>  drivers/clocksource/Makefile                       |   1 +
>  drivers/clocksource/timer-imx-tpm.c                | 239
> +++++++++++++++++++++
>  4 files changed, 276 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-
> timer.txt
>  create mode 100644 drivers/clocksource/timer-imx-tpm.c
> 
> --
> 2.7.4

Re: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support

[Daniel Lezcano]

On 05/07/2017 04:35, Dong Aisheng wrote:
> IMX Timer/PWM Module (TPM) supports both timer and pwm function while
> this patch only adds the timer support. PWM would be added later.
> 
> The TPM counter, compare and capture registers are clocked by an
> asynchronous clock that can remain enabled in low power modes.
> 
> NOTE: We observed in a very small probability, the bus fabric
> contention between GPU and A7 may results a few cycles delay
> of writing CNT registers which may cause the min_delta event got
> missed, so we need add a ETIME check here in case it happened.
> 
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Anson Huang <Anson.Huang@nxp.com>
> Cc: Bai Ping <ping.bai@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> 
> ---
> ChangeLog:
> v3->v4: 
>  * also add ETIME explanation in function
> v2->v3:
>  * address all comments from Daniel Lezcano
>  * add more explaination on ETIME check in commit message
> v1->v2:
>  * change to readl/writel from __raw_readl/writel according to Arnd's
>    suggestion to avoid endian issue
>  * add help information in Kconfig
>  * add more error checking
> ---
>  drivers/clocksource/Kconfig         |   8 ++
>  drivers/clocksource/Makefile        |   1 +
>  drivers/clocksource/timer-imx-tpm.c | 239 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 248 insertions(+)
>  create mode 100644 drivers/clocksource/timer-imx-tpm.c

[ ... ]

> +static struct irqaction tpm_timer_irq = {
> +	.name		= "i.MX7ULP TPM Timer",
> +	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
> +	.handler	= tpm_timer_interrupt,
> +	.dev_id		= &clockevent_tpm,
> +};
>

Please remove the structure above and use request_irq instead of
setup_irq below + return code checking.

> +static int __init tpm_clockevent_init(unsigned long rate, int irq)
> +{
> +	setup_irq(irq, &tpm_timer_irq);
> +
> +	clockevent_tpm.cpumask = cpumask_of(0);
> +	clockevent_tpm.irq = irq;
> +	clockevents_config_and_register(&clockevent_tpm,
> +					rate, 300, 0xfffffffe);
> +
> +	return 0;
> +}
> +
> +static int __init tpm_timer_init(struct device_node *np)
> +{

[ ... ]

> +	rate = clk_get_rate(per) >> 3;

Why ?

> +	tpm_clocksource_init(rate);
> +	tpm_clockevent_init(rate, irq);

Check.

> +	return 0;
> +
> +err_per_clk_enable:
> +	clk_disable_unprepare(ipg);
> +err_ipg_clk_enable:

No need to add an extra label.

> +err_clk_get:
> +	clk_put(per);
> +	clk_put(ipg);
> +err_iomap:
> +	iounmap(timer_base);
> +	return ret;
> +}
> +CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);

CLOCKSOURCE_OF_DECLARE is renamed to TIMER_OF_DECLARE.

Thanks!

  -- Daniel


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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[PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support

[Daniel Lezcano]

On 05/07/2017 04:35, Dong Aisheng wrote:
> IMX Timer/PWM Module (TPM) supports both timer and pwm function while
> this patch only adds the timer support. PWM would be added later.
> 
> The TPM counter, compare and capture registers are clocked by an
> asynchronous clock that can remain enabled in low power modes.
> 
> NOTE: We observed in a very small probability, the bus fabric
> contention between GPU and A7 may results a few cycles delay
> of writing CNT registers which may cause the min_delta event got
> missed, so we need add a ETIME check here in case it happened.
> 
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Anson Huang <Anson.Huang@nxp.com>
> Cc: Bai Ping <ping.bai@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> 
> ---
> ChangeLog:
> v3->v4: 
>  * also add ETIME explanation in function
> v2->v3:
>  * address all comments from Daniel Lezcano
>  * add more explaination on ETIME check in commit message
> v1->v2:
>  * change to readl/writel from __raw_readl/writel according to Arnd's
>    suggestion to avoid endian issue
>  * add help information in Kconfig
>  * add more error checking
> ---
>  drivers/clocksource/Kconfig         |   8 ++
>  drivers/clocksource/Makefile        |   1 +
>  drivers/clocksource/timer-imx-tpm.c | 239 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 248 insertions(+)
>  create mode 100644 drivers/clocksource/timer-imx-tpm.c

[ ... ]

> +static struct irqaction tpm_timer_irq = {
> +	.name		= "i.MX7ULP TPM Timer",
> +	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
> +	.handler	= tpm_timer_interrupt,
> +	.dev_id		= &clockevent_tpm,
> +};
>

Please remove the structure above and use request_irq instead of
setup_irq below + return code checking.

> +static int __init tpm_clockevent_init(unsigned long rate, int irq)
> +{
> +	setup_irq(irq, &tpm_timer_irq);
> +
> +	clockevent_tpm.cpumask = cpumask_of(0);
> +	clockevent_tpm.irq = irq;
> +	clockevents_config_and_register(&clockevent_tpm,
> +					rate, 300, 0xfffffffe);
> +
> +	return 0;
> +}
> +
> +static int __init tpm_timer_init(struct device_node *np)
> +{

[ ... ]

> +	rate = clk_get_rate(per) >> 3;

Why ?

> +	tpm_clocksource_init(rate);
> +	tpm_clockevent_init(rate, irq);

Check.

> +	return 0;
> +
> +err_per_clk_enable:
> +	clk_disable_unprepare(ipg);
> +err_ipg_clk_enable:

No need to add an extra label.

> +err_clk_get:
> +	clk_put(per);
> +	clk_put(ipg);
> +err_iomap:
> +	iounmap(timer_base);
> +	return ret;
> +}
> +CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);

CLOCKSOURCE_OF_DECLARE is renamed to TIMER_OF_DECLARE.

Thanks!

  -- Daniel


-- 
 <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
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RE: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support

[A.s. Dong]

Hi Daniel,

> -----Original Message-----
> From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org]
> Sent: Monday, July 31, 2017 10:29 PM
> To: A.s. Dong; linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org; tglx@linutronix.de;
> shawnguo@kernel.org; Jacky Bai; Anson Huang; dongas86@gmail.com;
> kernel@pengutronix.de; Arnd Bergmann
> Subject: Re: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support
> 
> On 05/07/2017 04:35, Dong Aisheng wrote:
> > IMX Timer/PWM Module (TPM) supports both timer and pwm function while
> > this patch only adds the timer support. PWM would be added later.
> >
> > The TPM counter, compare and capture registers are clocked by an
> > asynchronous clock that can remain enabled in low power modes.
> >
> > NOTE: We observed in a very small probability, the bus fabric
> > contention between GPU and A7 may results a few cycles delay of
> > writing CNT registers which may cause the min_delta event got missed,
> > so we need add a ETIME check here in case it happened.
> >
> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Anson Huang <Anson.Huang@nxp.com>
> > Cc: Bai Ping <ping.bai@nxp.com>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > ---
> > ChangeLog:
> > v3->v4:
> >  * also add ETIME explanation in function
> > v2->v3:
> >  * address all comments from Daniel Lezcano
> >  * add more explaination on ETIME check in commit message
> > v1->v2:
> >  * change to readl/writel from __raw_readl/writel according to Arnd's
> >    suggestion to avoid endian issue
> >  * add help information in Kconfig
> >  * add more error checking
> > ---
> >  drivers/clocksource/Kconfig         |   8 ++
> >  drivers/clocksource/Makefile        |   1 +
> >  drivers/clocksource/timer-imx-tpm.c | 239
> > ++++++++++++++++++++++++++++++++++++
> >  3 files changed, 248 insertions(+)
> >  create mode 100644 drivers/clocksource/timer-imx-tpm.c
> 
> [ ... ]
> 
> > +static struct irqaction tpm_timer_irq = {
> > +	.name		= "i.MX7ULP TPM Timer",
> > +	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
> > +	.handler	= tpm_timer_interrupt,
> > +	.dev_id		= &clockevent_tpm,
> > +};
> >
> 
> Please remove the structure above and use request_irq instead of setup_irq
> below + return code checking.
> 

Okay, will switch to it.

> > +static int __init tpm_clockevent_init(unsigned long rate, int irq) {
> > +	setup_irq(irq, &tpm_timer_irq);
> > +
> > +	clockevent_tpm.cpumask = cpumask_of(0);
> > +	clockevent_tpm.irq = irq;
> > +	clockevents_config_and_register(&clockevent_tpm,
> > +					rate, 300, 0xfffffffe);
> > +
> > +	return 0;
> > +}
> > +
> > +static int __init tpm_timer_init(struct device_node *np) {
> 
> [ ... ]
> 
> > +	rate = clk_get_rate(per) >> 3;
> 
> Why ?
> 

Because TPM internally is configured to divide 8.

The full context is:
/* increase per cnt, div 8 by default */
writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
             timer_base + TPM_SC);

/* set MOD register to maximum for free running mode */
writel(0xffffffff, timer_base + TPM_MOD);

rate = clk_get_rate(per) >> 3;


> > +	tpm_clocksource_init(rate);
> > +	tpm_clockevent_init(rate, irq);
> 
> Check.
> 

Currently non of them return error code, do I still need to check?

> > +	return 0;
> > +
> > +err_per_clk_enable:
> > +	clk_disable_unprepare(ipg);
> > +err_ipg_clk_enable:
> 
> No need to add an extra label.
> 

Okay, will remove one.

> > +err_clk_get:
> > +	clk_put(per);
> > +	clk_put(ipg);
> > +err_iomap:
> > +	iounmap(timer_base);
> > +	return ret;
> > +}
> > +CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);
> 
> CLOCKSOURCE_OF_DECLARE is renamed to TIMER_OF_DECLARE.
> 

Looks new, will change to it.

Thanks!

Regards
Dong Aisheng

> Thanks!
> 
>   -- Daniel
> 
> 
> --
>  <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
> 
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-
> blog/> Blog

[PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support

[A.s. Dong]

Hi Daniel,

> -----Original Message-----
> From: Daniel Lezcano [mailto:daniel.lezcano at linaro.org]
> Sent: Monday, July 31, 2017 10:29 PM
> To: A.s. Dong; linux-kernel at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org; tglx at linutronix.de;
> shawnguo at kernel.org; Jacky Bai; Anson Huang; dongas86 at gmail.com;
> kernel at pengutronix.de; Arnd Bergmann
> Subject: Re: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support
> 
> On 05/07/2017 04:35, Dong Aisheng wrote:
> > IMX Timer/PWM Module (TPM) supports both timer and pwm function while
> > this patch only adds the timer support. PWM would be added later.
> >
> > The TPM counter, compare and capture registers are clocked by an
> > asynchronous clock that can remain enabled in low power modes.
> >
> > NOTE: We observed in a very small probability, the bus fabric
> > contention between GPU and A7 may results a few cycles delay of
> > writing CNT registers which may cause the min_delta event got missed,
> > so we need add a ETIME check here in case it happened.
> >
> > Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Thomas Gleixner <tglx@linutronix.de>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Anson Huang <Anson.Huang@nxp.com>
> > Cc: Bai Ping <ping.bai@nxp.com>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > ---
> > ChangeLog:
> > v3->v4:
> >  * also add ETIME explanation in function
> > v2->v3:
> >  * address all comments from Daniel Lezcano
> >  * add more explaination on ETIME check in commit message
> > v1->v2:
> >  * change to readl/writel from __raw_readl/writel according to Arnd's
> >    suggestion to avoid endian issue
> >  * add help information in Kconfig
> >  * add more error checking
> > ---
> >  drivers/clocksource/Kconfig         |   8 ++
> >  drivers/clocksource/Makefile        |   1 +
> >  drivers/clocksource/timer-imx-tpm.c | 239
> > ++++++++++++++++++++++++++++++++++++
> >  3 files changed, 248 insertions(+)
> >  create mode 100644 drivers/clocksource/timer-imx-tpm.c
> 
> [ ... ]
> 
> > +static struct irqaction tpm_timer_irq = {
> > +	.name		= "i.MX7ULP TPM Timer",
> > +	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
> > +	.handler	= tpm_timer_interrupt,
> > +	.dev_id		= &clockevent_tpm,
> > +};
> >
> 
> Please remove the structure above and use request_irq instead of setup_irq
> below + return code checking.
> 

Okay, will switch to it.

> > +static int __init tpm_clockevent_init(unsigned long rate, int irq) {
> > +	setup_irq(irq, &tpm_timer_irq);
> > +
> > +	clockevent_tpm.cpumask = cpumask_of(0);
> > +	clockevent_tpm.irq = irq;
> > +	clockevents_config_and_register(&clockevent_tpm,
> > +					rate, 300, 0xfffffffe);
> > +
> > +	return 0;
> > +}
> > +
> > +static int __init tpm_timer_init(struct device_node *np) {
> 
> [ ... ]
> 
> > +	rate = clk_get_rate(per) >> 3;
> 
> Why ?
> 

Because TPM internally is configured to divide 8.

The full context is:
/* increase per cnt, div 8 by default */
writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,
             timer_base + TPM_SC);

/* set MOD register to maximum for free running mode */
writel(0xffffffff, timer_base + TPM_MOD);

rate = clk_get_rate(per) >> 3;


> > +	tpm_clocksource_init(rate);
> > +	tpm_clockevent_init(rate, irq);
> 
> Check.
> 

Currently non of them return error code, do I still need to check?

> > +	return 0;
> > +
> > +err_per_clk_enable:
> > +	clk_disable_unprepare(ipg);
> > +err_ipg_clk_enable:
> 
> No need to add an extra label.
> 

Okay, will remove one.

> > +err_clk_get:
> > +	clk_put(per);
> > +	clk_put(ipg);
> > +err_iomap:
> > +	iounmap(timer_base);
> > +	return ret;
> > +}
> > +CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init);
> 
> CLOCKSOURCE_OF_DECLARE is renamed to TIMER_OF_DECLARE.
> 

Looks new, will change to it.

Thanks!

Regards
Dong Aisheng

> Thanks!
> 
>   -- Daniel
> 
> 
> --
>  <http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
> 
> Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
> <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-
> blog/> Blog