[PATCH 0/4] *** Prepare to support PSP v10 for Raven ***

[PATCH 0/4] *** Prepare to support PSP v10 for Raven ***

[Junwei Zhang]

Junwei Zhang (4):
  drm/amdgpu: remove unncessary code in psp v10 ring init func
  drm/amdgpu: add init microcode function for psp v10
  drm/amdgpu: add ring_create function for psp v10
  drm/amdgpu: add ring_destroy for psp v10

 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  3 ++
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 96 ++++++++++++++++++++++++++++++---
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  |  5 ++
 3 files changed, 98 insertions(+), 6 deletions(-)

-- 
1.9.1

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[PATCH 1/4] drm/amdgpu: remove unncessary code in psp v10 ring init func

[Junwei Zhang]

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 8e0a24f..328c6f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -111,7 +111,6 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
 int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
 {
 	int ret = 0;
-	unsigned int psp_ring_reg = 0;
 	struct psp_ring *ring;
 	struct amdgpu_device *adev = psp->adev;
 
@@ -131,25 +130,6 @@ int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
 		return ret;
 	}
 
-	/* Write low address of the ring to C2PMSG_69 */
-	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
-	/* Write high address of the ring to C2PMSG_70 */
-	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
-	/* Write size of ring to C2PMSG_71 */
-	psp_ring_reg = ring->ring_size;
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
-	/* Write the ring initialization command to C2PMSG_64 */
-	psp_ring_reg = ring_type;
-	psp_ring_reg = psp_ring_reg << 16;
-	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
-	/* Wait for response flag (bit 31) in C2PMSG_64 */
-	psp_ring_reg = 0;
-	while ((psp_ring_reg & 0x80000000) == 0) {
-		psp_ring_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64);
-	}
-
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 2/4] drm/amdgpu: add init microcode function for psp v10

[Junwei Zhang]

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  1 +
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 46 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  |  1 +
 3 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 71ce3ee..dc95633 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -63,6 +63,7 @@ static int psp_sw_init(void *handle)
 		psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
 		break;
 	case CHIP_RAVEN:
+		psp->init_microcode = psp_v10_0_init_microcode;
 		psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
 		psp->ring_init = psp_v10_0_ring_init;
 		psp->cmd_submit = psp_v10_0_cmd_submit;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 328c6f5..7513f9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -87,6 +87,52 @@
 	return 0;
 }
 
+int psp_v10_0_init_microcode(struct psp_context *psp)
+{
+	struct amdgpu_device *adev = psp->adev;
+	const char *chip_name;
+	char fw_name[30];
+	int err = 0;
+	const struct psp_firmware_header_v1_0 *hdr;
+
+	DRM_DEBUG("\n");
+
+	switch (adev->asic_type) {
+	case CHIP_RAVEN:
+		chip_name = "raven";
+		break;
+	default: BUG();
+	}
+
+	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
+	err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
+	if (err)
+		goto out;
+
+	err = amdgpu_ucode_validate(adev->psp.asd_fw);
+	if (err)
+		goto out;
+
+	hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
+	adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
+	adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
+	adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
+	adev->psp.asd_start_addr = (uint8_t *)hdr +
+				le32_to_cpu(hdr->header.ucode_array_offset_bytes);
+
+	return 0;
+out:
+	if (err) {
+		dev_err(adev->dev,
+			"psp v10.0: Failed to load firmware \"%s\"\n",
+			fw_name);
+		release_firmware(adev->psp.asd_fw);
+		adev->psp.asd_fw = NULL;
+	}
+
+	return err;
+}
+
 int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
 {
 	int ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
index 2022b7b..2f5a314e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -27,6 +27,7 @@
 
 #include "amdgpu_psp.h"
 
+extern int psp_v10_0_init_microcode(struct psp_context *psp);
 extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
 				 struct psp_gfx_cmd_resp *cmd);
 extern int psp_v10_0_ring_init(struct psp_context *psp,
-- 
1.9.1

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[PATCH 3/4] drm/amdgpu: add ring_create function for psp v10

[Junwei Zhang]

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  1 +
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 31 +++++++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  |  2 ++
 3 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index dc95633..8f4eafc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -66,6 +66,7 @@ static int psp_sw_init(void *handle)
 		psp->init_microcode = psp_v10_0_init_microcode;
 		psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
 		psp->ring_init = psp_v10_0_ring_init;
+		psp->ring_create = psp_v10_0_ring_create;
 		psp->cmd_submit = psp_v10_0_cmd_submit;
 		psp->compare_sram_data = psp_v10_0_compare_sram_data;
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 7513f9c..fb29cd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -179,6 +179,37 @@ int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
 	return 0;
 }
 
+int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
+{
+	int ret = 0;
+	unsigned int psp_ring_reg = 0;
+	struct psp_ring *ring = &psp->km_ring;
+	struct amdgpu_device *adev = psp->adev;
+
+	/* Write low address of the ring to C2PMSG_69 */
+	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
+	/* Write high address of the ring to C2PMSG_70 */
+	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
+	/* Write size of ring to C2PMSG_71 */
+	psp_ring_reg = ring->ring_size;
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
+	/* Write the ring initialization command to C2PMSG_64 */
+	psp_ring_reg = ring_type;
+	psp_ring_reg = psp_ring_reg << 16;
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+	/* There might be handshake issue with hardware which needs delay */
+	mdelay(20);
+
+	/* Wait for response flag (bit 31) in C2PMSG_64 */
+	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+			   0x80000000, 0x8000FFFF, false);
+
+	return ret;
+}
+
 int psp_v10_0_cmd_submit(struct psp_context *psp,
 		        struct amdgpu_firmware_info *ucode,
 		        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
index 2f5a314e..7e9a8cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -32,6 +32,8 @@ extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
 				 struct psp_gfx_cmd_resp *cmd);
 extern int psp_v10_0_ring_init(struct psp_context *psp,
 			      enum psp_ring_type ring_type);
+extern int psp_v10_0_ring_create(struct psp_context *psp,
+				 enum psp_ring_type ring_type);
 extern int psp_v10_0_cmd_submit(struct psp_context *psp,
 			       struct amdgpu_firmware_info *ucode,
 			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
-- 
1.9.1

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[PATCH 4/4] drm/amdgpu: add ring_destroy for psp v10

[Junwei Zhang]

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  1 +
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  |  2 ++
 3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8f4eafc..644941d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -67,6 +67,7 @@ static int psp_sw_init(void *handle)
 		psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
 		psp->ring_init = psp_v10_0_ring_init;
 		psp->ring_create = psp_v10_0_ring_create;
+		psp->ring_destroy = psp_v10_0_ring_destroy;
 		psp->cmd_submit = psp_v10_0_cmd_submit;
 		psp->compare_sram_data = psp_v10_0_compare_sram_data;
 		break;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index fb29cd4..b4af32a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -210,6 +210,33 @@ int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
 	return ret;
 }
 
+int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
+{
+	int ret = 0;
+	struct psp_ring *ring;
+	unsigned int psp_ring_reg = 0;
+	struct amdgpu_device *adev = psp->adev;
+
+	ring = &psp->km_ring;
+
+	/* Write the ring destroy command to C2PMSG_64 */
+	psp_ring_reg = 3 << 16;
+	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
+
+	/* There might be handshake issue with hardware which needs delay */
+	mdelay(20);
+
+	/* Wait for response flag (bit 31) in C2PMSG_64 */
+	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+			   0x80000000, 0x80000000, false);
+
+	if (ring->ring_mem)
+		amdgpu_bo_free_kernel(&adev->firmware.rbuf,
+				      &ring->ring_mem_mc_addr,
+				      (void **)&ring->ring_mem);
+	return ret;
+}
+
 int psp_v10_0_cmd_submit(struct psp_context *psp,
 		        struct amdgpu_firmware_info *ucode,
 		        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
index 7e9a8cd..e76cde2 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
@@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct psp_context *psp,
 			      enum psp_ring_type ring_type);
 extern int psp_v10_0_ring_create(struct psp_context *psp,
 				 enum psp_ring_type ring_type);
+extern int psp_v10_0_ring_destroy(struct psp_context *psp,
+				  enum psp_ring_type ring_type);
 extern int psp_v10_0_cmd_submit(struct psp_context *psp,
 			       struct amdgpu_firmware_info *ucode,
 			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
-- 
1.9.1

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RE: [PATCH 1/4] drm/amdgpu: remove unncessary code in psp v10 ring init func

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Junwei Zhang
> Sent: Friday, July 14, 2017 6:42 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Jerry
> Subject: [PATCH 1/4] drm/amdgpu: remove unncessary code in psp v10 ring
> init func
> 
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 20 --------------------
>  1 file changed, 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 8e0a24f..328c6f5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -111,7 +111,6 @@ int psp_v10_0_prep_cmd_buf(struct
> amdgpu_firmware_info *ucode, struct psp_gfx_cm
>  int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type
> ring_type)
>  {
>  	int ret = 0;
> -	unsigned int psp_ring_reg = 0;
>  	struct psp_ring *ring;
>  	struct amdgpu_device *adev = psp->adev;
> 
> @@ -131,25 +130,6 @@ int psp_v10_0_ring_init(struct psp_context *psp,
> enum psp_ring_type ring_type)
>  		return ret;
>  	}
> 
> -	/* Write low address of the ring to C2PMSG_69 */
> -	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> -	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69,
> psp_ring_reg);
> -	/* Write high address of the ring to C2PMSG_70 */
> -	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
> -	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70,
> psp_ring_reg);
> -	/* Write size of ring to C2PMSG_71 */
> -	psp_ring_reg = ring->ring_size;
> -	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71,
> psp_ring_reg);
> -	/* Write the ring initialization command to C2PMSG_64 */
> -	psp_ring_reg = ring_type;
> -	psp_ring_reg = psp_ring_reg << 16;
> -	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
> psp_ring_reg);
> -	/* Wait for response flag (bit 31) in C2PMSG_64 */
> -	psp_ring_reg = 0;
> -	while ((psp_ring_reg & 0x80000000) == 0) {
> -		psp_ring_reg = RREG32_SOC15(MP0, 0,
> mmMP0_SMN_C2PMSG_64);
> -	}
> -
>  	return 0;
>  }
> 
> --
> 1.9.1
> 
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RE: [PATCH 2/4] drm/amdgpu: add init microcode function for psp v10

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Junwei Zhang
> Sent: Friday, July 14, 2017 6:42 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Jerry
> Subject: [PATCH 2/4] drm/amdgpu: add init microcode function for psp v10
> 
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  1 +
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 46
> +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  |  1 +
>  3 files changed, 48 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 71ce3ee..dc95633 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -63,6 +63,7 @@ static int psp_sw_init(void *handle)
>  		psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
>  		break;
>  	case CHIP_RAVEN:
> +		psp->init_microcode = psp_v10_0_init_microcode;
>  		psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
>  		psp->ring_init = psp_v10_0_ring_init;
>  		psp->cmd_submit = psp_v10_0_cmd_submit;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 328c6f5..7513f9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -87,6 +87,52 @@
>  	return 0;
>  }
> 
> +int psp_v10_0_init_microcode(struct psp_context *psp)
> +{
> +	struct amdgpu_device *adev = psp->adev;
> +	const char *chip_name;
> +	char fw_name[30];
> +	int err = 0;
> +	const struct psp_firmware_header_v1_0 *hdr;
> +
> +	DRM_DEBUG("\n");
> +
> +	switch (adev->asic_type) {
> +	case CHIP_RAVEN:
> +		chip_name = "raven";
> +		break;
> +	default: BUG();
> +	}
> +
> +	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin",
> chip_name);
> +	err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
> +	if (err)
> +		goto out;
> +
> +	err = amdgpu_ucode_validate(adev->psp.asd_fw);
> +	if (err)
> +		goto out;
> +
> +	hdr = (const struct psp_firmware_header_v1_0 *)adev-
> >psp.asd_fw->data;
> +	adev->psp.asd_fw_version = le32_to_cpu(hdr-
> >header.ucode_version);
> +	adev->psp.asd_feature_version = le32_to_cpu(hdr-
> >ucode_feature_version);
> +	adev->psp.asd_ucode_size = le32_to_cpu(hdr-
> >header.ucode_size_bytes);
> +	adev->psp.asd_start_addr = (uint8_t *)hdr +
> +				le32_to_cpu(hdr-
> >header.ucode_array_offset_bytes);
> +
> +	return 0;
> +out:
> +	if (err) {
> +		dev_err(adev->dev,
> +			"psp v10.0: Failed to load firmware \"%s\"\n",
> +			fw_name);
> +		release_firmware(adev->psp.asd_fw);
> +		adev->psp.asd_fw = NULL;
> +	}
> +
> +	return err;
> +}
> +
>  int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct
> psp_gfx_cmd_resp *cmd)
>  {
>  	int ret;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> index 2022b7b..2f5a314e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> @@ -27,6 +27,7 @@
> 
>  #include "amdgpu_psp.h"
> 
> +extern int psp_v10_0_init_microcode(struct psp_context *psp);
>  extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info
> *ucode,
>  				 struct psp_gfx_cmd_resp *cmd);
>  extern int psp_v10_0_ring_init(struct psp_context *psp,
> --
> 1.9.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 3/4] drm/amdgpu: add ring_create function for psp v10

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Junwei Zhang
> Sent: Friday, July 14, 2017 6:42 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Jerry
> Subject: [PATCH 3/4] drm/amdgpu: add ring_create function for psp v10
> 
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  1 +
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 31
> +++++++++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  |  2 ++
>  3 files changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index dc95633..8f4eafc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -66,6 +66,7 @@ static int psp_sw_init(void *handle)
>  		psp->init_microcode = psp_v10_0_init_microcode;
>  		psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
>  		psp->ring_init = psp_v10_0_ring_init;
> +		psp->ring_create = psp_v10_0_ring_create;
>  		psp->cmd_submit = psp_v10_0_cmd_submit;
>  		psp->compare_sram_data =
> psp_v10_0_compare_sram_data;
>  		break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 7513f9c..fb29cd4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -179,6 +179,37 @@ int psp_v10_0_ring_init(struct psp_context *psp,
> enum psp_ring_type ring_type)
>  	return 0;
>  }
> 
> +int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type
> ring_type)
> +{
> +	int ret = 0;
> +	unsigned int psp_ring_reg = 0;
> +	struct psp_ring *ring = &psp->km_ring;
> +	struct amdgpu_device *adev = psp->adev;
> +
> +	/* Write low address of the ring to C2PMSG_69 */
> +	psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69,
> psp_ring_reg);
> +	/* Write high address of the ring to C2PMSG_70 */
> +	psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70,
> psp_ring_reg);
> +	/* Write size of ring to C2PMSG_71 */
> +	psp_ring_reg = ring->ring_size;
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71,
> psp_ring_reg);
> +	/* Write the ring initialization command to C2PMSG_64 */
> +	psp_ring_reg = ring_type;
> +	psp_ring_reg = psp_ring_reg << 16;
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
> psp_ring_reg);
> +
> +	/* There might be handshake issue with hardware which needs delay
> */
> +	mdelay(20);
> +
> +	/* Wait for response flag (bit 31) in C2PMSG_64 */
> +	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
> mmMP0_SMN_C2PMSG_64),
> +			   0x80000000, 0x8000FFFF, false);
> +
> +	return ret;
> +}
> +
>  int psp_v10_0_cmd_submit(struct psp_context *psp,
>  		        struct amdgpu_firmware_info *ucode,
>  		        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> index 2f5a314e..7e9a8cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> @@ -32,6 +32,8 @@ extern int psp_v10_0_prep_cmd_buf(struct
> amdgpu_firmware_info *ucode,
>  				 struct psp_gfx_cmd_resp *cmd);
>  extern int psp_v10_0_ring_init(struct psp_context *psp,
>  			      enum psp_ring_type ring_type);
> +extern int psp_v10_0_ring_create(struct psp_context *psp,
> +				 enum psp_ring_type ring_type);
>  extern int psp_v10_0_cmd_submit(struct psp_context *psp,
>  			       struct amdgpu_firmware_info *ucode,
>  			       uint64_t cmd_buf_mc_addr, uint64_t
> fence_mc_addr,
> --
> 1.9.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 4/4] drm/amdgpu: add ring_destroy for psp v10

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Junwei Zhang
> Sent: Friday, July 14, 2017 6:42 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Jerry
> Subject: [PATCH 4/4] drm/amdgpu: add ring_destroy for psp v10
> 
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  1 +
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 27
> +++++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  |  2 ++
>  3 files changed, 30 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 8f4eafc..644941d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -67,6 +67,7 @@ static int psp_sw_init(void *handle)
>  		psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
>  		psp->ring_init = psp_v10_0_ring_init;
>  		psp->ring_create = psp_v10_0_ring_create;
> +		psp->ring_destroy = psp_v10_0_ring_destroy;
>  		psp->cmd_submit = psp_v10_0_cmd_submit;
>  		psp->compare_sram_data =
> psp_v10_0_compare_sram_data;
>  		break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index fb29cd4..b4af32a3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -210,6 +210,33 @@ int psp_v10_0_ring_create(struct psp_context *psp,
> enum psp_ring_type ring_type)
>  	return ret;
>  }
> 
> +int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type
> ring_type)
> +{
> +	int ret = 0;
> +	struct psp_ring *ring;
> +	unsigned int psp_ring_reg = 0;
> +	struct amdgpu_device *adev = psp->adev;
> +
> +	ring = &psp->km_ring;
> +
> +	/* Write the ring destroy command to C2PMSG_64 */
> +	psp_ring_reg = 3 << 16;
> +	WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
> psp_ring_reg);
> +
> +	/* There might be handshake issue with hardware which needs delay
> */
> +	mdelay(20);
> +
> +	/* Wait for response flag (bit 31) in C2PMSG_64 */
> +	ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
> mmMP0_SMN_C2PMSG_64),
> +			   0x80000000, 0x80000000, false);
> +
> +	if (ring->ring_mem)

You don't have to check if the ring exists.  amdgpu_bo_free_kernel handles NULL bos.
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> +		amdgpu_bo_free_kernel(&adev->firmware.rbuf,
> +				      &ring->ring_mem_mc_addr,
> +				      (void **)&ring->ring_mem);
> +	return ret;
> +}
> +
>  int psp_v10_0_cmd_submit(struct psp_context *psp,
>  		        struct amdgpu_firmware_info *ucode,
>  		        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> index 7e9a8cd..e76cde2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> @@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct psp_context
> *psp,
>  			      enum psp_ring_type ring_type);
>  extern int psp_v10_0_ring_create(struct psp_context *psp,
>  				 enum psp_ring_type ring_type);
> +extern int psp_v10_0_ring_destroy(struct psp_context *psp,
> +				  enum psp_ring_type ring_type);
>  extern int psp_v10_0_cmd_submit(struct psp_context *psp,
>  			       struct amdgpu_firmware_info *ucode,
>  			       uint64_t cmd_buf_mc_addr, uint64_t
> fence_mc_addr,
> --
> 1.9.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 4/4] drm/amdgpu: add ring_destroy for psp v10

[Zhang, Jerry (Junwei)]

On 07/14/2017 10:43 PM, Deucher, Alexander wrote:
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
>> Of Junwei Zhang
>> Sent: Friday, July 14, 2017 6:42 AM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Zhang, Jerry
>> Subject: [PATCH 4/4] drm/amdgpu: add ring_destroy for psp v10
>>
>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c |  1 +
>>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 27
>> +++++++++++++++++++++++++++
>>  drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  |  2 ++
>>  3 files changed, 30 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> index 8f4eafc..644941d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> @@ -67,6 +67,7 @@ static int psp_sw_init(void *handle)
>>                psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
>>                psp->ring_init = psp_v10_0_ring_init;
>>                psp->ring_create = psp_v10_0_ring_create;
>> +             psp->ring_destroy = psp_v10_0_ring_destroy;
>>                psp->cmd_submit = psp_v10_0_cmd_submit;
>>                psp->compare_sram_data =
>> psp_v10_0_compare_sram_data;
>>                break;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> index fb29cd4..b4af32a3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
>> @@ -210,6 +210,33 @@ int psp_v10_0_ring_create(struct psp_context *psp,
>> enum psp_ring_type ring_type)
>>        return ret;
>>  }
>>
>> +int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type
>> ring_type)
>> +{
>> +     int ret = 0;
>> +     struct psp_ring *ring;
>> +     unsigned int psp_ring_reg = 0;
>> +     struct amdgpu_device *adev = psp->adev;
>> +
>> +     ring = &psp->km_ring;
>> +
>> +     /* Write the ring destroy command to C2PMSG_64 */
>> +     psp_ring_reg = 3 << 16;
>> +     WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
>> psp_ring_reg);
>> +
>> +     /* There might be handshake issue with hardware which needs delay
>> */
>> +     mdelay(20);
>> +
>> +     /* Wait for response flag (bit 31) in C2PMSG_64 */
>> +     ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
>> mmMP0_SMN_C2PMSG_64),
>> +                        0x80000000, 0x80000000, false);
>> +
>> +     if (ring->ring_mem)
>
> You don't have to check if the ring exists.  amdgpu_bo_free_kernel handles NULL bos.
> With that fixed:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Yeah, thanks to reminder that.
I will fix it.

Jerry

>
>> +             amdgpu_bo_free_kernel(&adev->firmware.rbuf,
>> +                                   &ring->ring_mem_mc_addr,
>> +                                   (void **)&ring->ring_mem);
>> +     return ret;
>> +}
>> +
>>  int psp_v10_0_cmd_submit(struct psp_context *psp,
>>                        struct amdgpu_firmware_info *ucode,
>>                        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
>> b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
>> index 7e9a8cd..e76cde2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
>> @@ -34,6 +34,8 @@ extern int psp_v10_0_ring_init(struct psp_context
>> *psp,
>>                              enum psp_ring_type ring_type);
>>  extern int psp_v10_0_ring_create(struct psp_context *psp,
>>                                 enum psp_ring_type ring_type);
>> +extern int psp_v10_0_ring_destroy(struct psp_context *psp,
>> +                               enum psp_ring_type ring_type);
>>  extern int psp_v10_0_cmd_submit(struct psp_context *psp,
>>                               struct amdgpu_firmware_info *ucode,
>>                               uint64_t cmd_buf_mc_addr, uint64_t
>> fence_mc_addr,
>> --
>> 1.9.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>>https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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