From: Zhao Qiang <qiang.zhao@nxp.com>
To: <oss@buserror.net>
Cc: <valentin.longchamp@keymile.com>, <linuxppc-dev@lists.ozlabs.org>,
<linux-kernel@vger.kernel.org>, Zhao Qiang <qiang.zhao@nxp.com>
Subject: [PATCH v2] qe: fix compile issue for arm64
Date: Mon, 24 Jul 2017 11:39:15 +0800 [thread overview]
Message-ID: <1500867555-36277-1-git-send-email-qiang.zhao@nxp.com> (raw)
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
Changes for v2:
- include all Errata QE_General4 in #ifdef
drivers/soc/fsl/qe/qe.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 2ef6fc6..4ac9ce8 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -229,9 +229,11 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
that the BRG divisor must be even if you're not using divide-by-16
mode. */
+#ifdef CONFIG_PPC
if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
if (!div16 && (divisor & 1) && (divisor > 3))
divisor++;
+#endif
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;
--
2.1.0.27.g96db324
next reply other threads:[~2017-07-24 3:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-24 3:39 Zhao Qiang [this message]
2017-07-28 6:13 ` [PATCH v2] qe: fix compile issue for arm64 Michael Ellerman
2017-07-28 7:14 ` Qiang Zhao
2017-07-28 7:14 ` Qiang Zhao
2017-07-31 10:37 ` Michael Ellerman
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