* [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
@ 2017-07-17 22:05 Manasi Navare
2017-07-17 22:15 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-07-25 17:38 ` [PATCH] " Paulo Zanoni
0 siblings, 2 replies; 4+ messages in thread
From: Manasi Navare @ 2017-07-17 22:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Rodrigo Vivi
The condition for setting the Loadgen Select bit of
PORT_TX_DW4 register during DDI Vswing Sequence should be
Bit rate <=6 GHz whereas the existing code checks only
Bit Rate < 6GHz. This patch fixes this condition.
While at it also remove the redundant paranthesis.
Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index efb1358..f4fbb39 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2010,8 +2010,8 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
val &= ~LOADGEN_SELECT;
- if (((rate < 600000) && (width == 4) && (ln >= 1)) ||
- ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
+ if ((rate <= 600000 && width == 4 && ln >= 1) ||
+ (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
val |= LOADGEN_SELECT;
}
I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
2017-07-17 22:05 [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence Manasi Navare
@ 2017-07-17 22:15 ` Patchwork
2017-07-25 17:38 ` [PATCH] " Paulo Zanoni
1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2017-07-17 22:15 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
URL : https://patchwork.freedesktop.org/series/27446/
State : success
== Summary ==
Series 27446v1 drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
https://patchwork.freedesktop.org/api/1.0/series/27446/revisions/1/mbox/
Test gem_exec_flush:
Subgroup basic-batch-kernel-default-uc:
fail -> PASS (fi-snb-2600) fdo#100007
Test gem_exec_suspend:
Subgroup basic-s4-devices:
pass -> DMESG-WARN (fi-kbl-7560u) k.org#196399
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
fail -> PASS (fi-snb-2600) fdo#100215
Test kms_flip:
Subgroup basic-flip-vs-modeset:
pass -> SKIP (fi-skl-x1585l) fdo#101781
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> DMESG-WARN (fi-byt-j1900) fdo#101705
fdo#100007 https://bugs.freedesktop.org/show_bug.cgi?id=100007
k.org#196399 https://bugzilla.kernel.org/show_bug.cgi?id=196399
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:442s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:431s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:526s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:508s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:491s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:488s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:593s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:435s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:413s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:418s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:496s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:468s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:469s
fi-kbl-7560u total:279 pass:268 dwarn:1 dfail:0 fail:0 skip:10 time:571s
fi-kbl-r total:279 pass:260 dwarn:1 dfail:0 fail:0 skip:18 time:584s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:562s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:459s
fi-skl-6700hq total:279 pass:262 dwarn:0 dfail:0 fail:0 skip:17 time:583s
fi-skl-6700k total:279 pass:257 dwarn:4 dfail:0 fail:0 skip:18 time:469s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:475s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:435s
fi-skl-x1585l total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:485s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:547s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:407s
3010bfcdfd837d2f7708fc37f1b8de79e8e9362d drm-tip: 2017y-07m-17d-18h-46m-40s UTC integration manifest
ea21419 drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5215/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
2017-07-17 22:05 [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence Manasi Navare
2017-07-17 22:15 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-07-25 17:38 ` Paulo Zanoni
2017-07-25 18:24 ` Navare, Manasi D
1 sibling, 1 reply; 4+ messages in thread
From: Paulo Zanoni @ 2017-07-25 17:38 UTC (permalink / raw)
To: Manasi Navare, intel-gfx; +Cc: Rodrigo Vivi
Em Seg, 2017-07-17 às 15:05 -0700, Manasi Navare escreveu:
> The condition for setting the Loadgen Select bit of
> PORT_TX_DW4 register during DDI Vswing Sequence should be
> Bit rate <=6 GHz whereas the existing code checks only
> Bit Rate < 6GHz. This patch fixes this condition.
> While at it also remove the redundant paranthesis.
>
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing
> sequence.")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index efb1358..f4fbb39 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2010,8 +2010,8 @@ static void cnl_ddi_vswing_sequence(struct
> intel_encoder *encoder, u32 level)
> val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> val &= ~LOADGEN_SELECT;
>
> - if (((rate < 600000) && (width == 4) && (ln >=
> 1)) ||
> - ((rate < 600000) && (width < 4) && ((ln == 1) ||
> (ln == 2)))) {
> + if ((rate <= 600000 && width == 4 && ln >= 1) ||
> + (rate <= 600000 && width < 4 && (ln == 1 || ln
> == 2))) {
> val |= LOADGEN_SELECT;
> }
> I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
2017-07-25 17:38 ` [PATCH] " Paulo Zanoni
@ 2017-07-25 18:24 ` Navare, Manasi D
0 siblings, 0 replies; 4+ messages in thread
From: Navare, Manasi D @ 2017-07-25 18:24 UTC (permalink / raw)
To: Zanoni, Paulo R, intel-gfx; +Cc: Vivi, Rodrigo
Thanks for the review !
Manasi
Em Seg, 2017-07-17 às 15:05 -0700, Manasi Navare escreveu:
> The condition for setting the Loadgen Select bit of
> PORT_TX_DW4 register during DDI Vswing Sequence should be Bit rate <=6
> GHz whereas the existing code checks only Bit Rate < 6GHz. This patch
> fixes this condition.
> While at it also remove the redundant paranthesis.
>
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing
> sequence.")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index efb1358..f4fbb39 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2010,8 +2010,8 @@ static void cnl_ddi_vswing_sequence(struct
> intel_encoder *encoder, u32 level)
> val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
> val &= ~LOADGEN_SELECT;
>
> - if (((rate < 600000) && (width == 4) && (ln >=
> 1)) ||
> - ((rate < 600000) && (width < 4) && ((ln == 1) ||
> (ln == 2)))) {
> + if ((rate <= 600000 && width == 4 && ln >= 1) ||
> + (rate <= 600000 && width < 4 && (ln == 1 || ln
> == 2))) {
> val |= LOADGEN_SELECT;
> }
> I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-07-25 18:24 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-07-17 22:05 [PATCH] drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence Manasi Navare
2017-07-17 22:15 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-07-25 17:38 ` [PATCH] " Paulo Zanoni
2017-07-25 18:24 ` Navare, Manasi D
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.