[U-Boot] [PATCH v2 00/56] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7

[U-Boot] [PATCH v2 00/56] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7

[Philipp Tomsich]

Here's an updated series to enable the RK3368 which addresses the
concerns regarding the prefixing of GRF bit-definitions with a
RK3368-prefix: while I had intended to temporarily pull the GMAC
support to get around the underlying issue, moving the bit-definitions
into the pinctrl-driver's implementation turned out to rather
straightforward (and there's little use in having these definitions
visible outside of the pinctrl driver anyway).

Thanks to everyone, who took the time to comment/discuss the initial
version.

This series (still) has a lot going on, but I didn't want to split it
to allow everyone to understand the motivation between some of the
changes to the SPL/TPL framework.  The short summary of this is
"enablement for DRAM init on the RK3368 with everything else that's
necessary to do it using OF_PLATDATA in TPL".

Enabling the RK3368 created a few more challenges that I'd expected:
 - I needed different stack locations, text addresses and sizes for
   TPL and SPL
 - the TPL stage was to use OF_PLATDATA and SPL was to use full OF_CONTROL
 - with the RK3368 TPL stage, there was a need to extend the back-to-bootrom
   support for Rockchip to AArch64
 - I wanted to start folding some of the Rockchip specific SPL support
   (i.e. back-to-bootrom) back into the general SPL framework to allow
   using it as a general boot method

So I ended up separating quite a bit of features between SPL and TPL
while keeping things transparent to the few other boards using TPL (at
least I hope that things are transparent, as we didn't have any of
those in our lab to test on)...

Tested with: RK3368-uQ7, Debian 9, Linux 4.13-rc1.

Just one final remark: the DMC driver for the RK3368 currently covers
the configuration we use on the RK3368-uQ7 (i.e. 32bit wide, 2 ranks)
and is stress-tested (including 8-way SPEC runs) at all 3 supported
speeds.  I've built a bit of infrastructure (e.g. the way the
memory-schedule is determined) that I hope will be a useful
starting-point in unifying the drivers for the various closely related
DRAM controllers (e.g. for the RK3288) for Rockchip devices in the
future.


Changes in v2:
- dropped the RK3368_ prefix for the GRF constants
- removed the RK3368-prefix on bit-definitions for GMAC pinctrl
- removed the RK3368 prefix on the SD/MMC pin definitions
- added SPI clock setup
- moves the bit-definitions (for GRF registers) specific to the GMAC
  into the GMAC driver: these include interface speed selection and
  configuring the RGMII output mode
- removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi
- copies the enum for the IOMUX config of the debug UART into the TPL
  support code, as the various constants are otherwise private to the
  pinctrl code (and we can't include pinctrl in the TPL stage due to
  size constraints/dependencies)
- added in v2
- reuses the support for configuring the boot order using the
  u-boot,spl-boot-order property
- drops the initialisation of the debug_uart
- adds pinctrl-configuration for the preloader UART
- marks pinctrl-node as 'u-boot,dm-pre-reloc' to ensure MMC2 (eMMC)
  works in the SPL stage
- makes uart0 as 'u-boot,dm-pre-reloc' to allow initialising the
  preloader console (instead of relying solely on the debug UART)
- adds support for SPI1 (and the on-module SPI flash)
- splits the a 'u-boot.dtsi' off the DTS file
- updates the defconfig for SPI and SPI flash support

Klaus Goger (1):
  rockchip: board: puma_rk3399: rename ATF firmware

Philipp Tomsich (55):
  spl: add a 'return to bootrom' boot method
  spl: configure 'return to bootrom' separately for SPL and TPL
  rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64
  rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL
  rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in
    TPL/SPL
  spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and
    SPL_SYSCON
  spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL
  spl: dm: Kconfig: SPL_RAM depends on SPL_DM
  spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
  spl: dm: Kconfig: SPL_CLK depens on SPL_DM
  spl: dm: Kconfig: split CLK support for SPL and TPL
  spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL
  spl: dm: use CONFIG_IS_ENABLED to test for the DM option
  armv8: remove unused low-level modules from TPL
  armv8: spl: Support separate stack for TPL
  spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL
  spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL
  lib: spl: differentiate between TPL and SPL for
    libfdt/of_control/of_platdata
  spl: consistently use $(SPL_TPL_) to select features for SPL and TPL
    builds
  spl: add TPL_DRIVER_MISC_SUPPORT option
  drivers: spl: consistently use the $(SPL_TPL_) macro
  rockchip: Makefile: allow selective inclusion of sdram_common.o from
    TPL/SPL/U-Boot
  rockchip: rk3368: improve Kconfig text for the RK3368
  rockchip: rk3368: mkimage: add support for the RK3368
  rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]
  rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz
  rockchip: rk3368: spl: add memory layout for TPL and SPL
  rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA
  rockchip: rk3368: grf: use shifted-constants
  rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
  rockchip: pinctrl: rk3368: add support for configuring the MMC pins
  rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl
    driver
  rockchip: pinctrl: rk3368: add SPI support
  rockchip: clk: rk3368: implement bandwidth adjust for PLLs
  rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver
  rockchip: clk: rk3368: do not change CPLL/GPLL before returning to
    BROM
  rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
  rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ
  rockchip: clk: rk3368: implement MMC/SD clock reparenting
  rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)
  rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock
  rockchip: clk: rk3368: mark 'priv' __maybe_unused in
    rk3368_clk_set_rate()
  rockchip: clk: rk3368: add support for configuring the SPI clocks
  net: gmac_rockchip: Add support for the RK3368 GMAC
  rockchip: Makefile: streamline SPL/TPL configuration
  rockchip: rk3368: add DRAM controller driver with DRAM initialisation
  rockchip: dts: rk3368: add DMC node in rk3368.dtsi
  rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h
  rockchip: rk3368: spl: add TPL support
  rockchip: spl: make spl-boot-order code reusable (split from rk3399)
  rockchip: rk3368: spl: add SPL support
  rockchip: rk3368: spl: mark SPL and TPL as supported for
    ROCKCHIP_RK3368
  rockchip: spi: enable support for the rk_spi driver for the RK3368
  rockchip: board: lion-rk3368: add support for the RK3368-uQ7
  rockchip: board: puma-rk3399: fix warnings in
    puma_rk3399/fit_spl_atf.its

 Makefile                                           |   2 +-
 arch/arm/cpu/armv8/Makefile                        |   4 +-
 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/rk3368-lion-u-boot.dtsi               |  68 ++
 arch/arm/dts/rk3368-lion.dts                       | 195 ++++
 arch/arm/dts/rk3368.dtsi                           |  25 +-
 arch/arm/include/asm/arch-rockchip/cru_rk3368.h    |  15 +-
 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h    | 187 ++++
 arch/arm/include/asm/arch-rockchip/grf_rk3368.h    | 326 +------
 arch/arm/include/asm/spl.h                         |   1 +
 arch/arm/lib/crt0_64.S                             |   4 +-
 arch/arm/mach-rockchip/Kconfig                     |  37 +-
 arch/arm/mach-rockchip/Makefile                    |  51 +-
 arch/arm/mach-rockchip/bootrom.c                   |   4 +-
 arch/arm/mach-rockchip/rk3188-board-spl.c          |   5 +-
 arch/arm/mach-rockchip/rk3188-board.c              |   2 +-
 arch/arm/mach-rockchip/rk3288-board-spl.c          |   4 +-
 arch/arm/mach-rockchip/rk3288-board.c              |   4 +-
 arch/arm/mach-rockchip/rk3368-board-spl.c          |  98 ++
 arch/arm/mach-rockchip/rk3368-board-tpl.c          | 168 ++++
 arch/arm/mach-rockchip/rk3368/Kconfig              |  21 +
 arch/arm/mach-rockchip/rk3368/Makefile             |   1 -
 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c       |  60 --
 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c      |  35 +
 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds       |  13 +
 arch/arm/mach-rockchip/rk3399-board-spl.c          | 106 +--
 arch/arm/mach-rockchip/save_boot_param.S           |  37 +
 arch/arm/mach-rockchip/spl-boot-order.c            | 108 +++
 board/theobroma-systems/lion_rk3368/Kconfig        |  15 +
 board/theobroma-systems/lion_rk3368/MAINTAINERS    |  10 +
 board/theobroma-systems/lion_rk3368/Makefile       |   7 +
 board/theobroma-systems/lion_rk3368/README         |  60 ++
 .../theobroma-systems/lion_rk3368/fit_spl_atf.its  |  51 ++
 board/theobroma-systems/lion_rk3368/lion_rk3368.c  |  25 +
 board/theobroma-systems/puma_rk3399/README         |   2 +-
 .../theobroma-systems/puma_rk3399/fit_spl_atf.its  |  20 +-
 common/Makefile                                    |   8 +-
 common/spl/Kconfig                                 |  39 +
 common/spl/Makefile                                |  35 +-
 common/spl/spl.c                                   |   5 +-
 common/spl/spl_bootrom.c                           |  27 +
 configs/evb-rk3288_defconfig                       |   2 +-
 configs/fennec-rk3288_defconfig                    |   2 +-
 configs/firefly-rk3288_defconfig                   |   2 +-
 configs/lion-rk3368_defconfig                      |  88 ++
 configs/miqi-rk3288_defconfig                      |   2 +-
 configs/popmetal-rk3288_defconfig                  |   2 +-
 configs/rock2_defconfig                            |   2 +-
 configs/rock_defconfig                             |   2 +-
 configs/tinker-rk3288_defconfig                    |   2 +-
 doc/README.rockchip                                |   2 +-
 .../clock/rockchip,rk3368-dmc.txt                  |  67 ++
 drivers/Makefile                                   |  36 +-
 drivers/clk/Kconfig                                |  12 +-
 drivers/clk/Makefile                               |   2 +-
 drivers/clk/rockchip/clk_rk3368.c                  | 302 ++++++-
 drivers/core/Kconfig                               |  23 +-
 drivers/core/Makefile                              |   4 +-
 drivers/net/gmac_rockchip.c                        |  78 ++
 drivers/pinctrl/rockchip/pinctrl_rk3368.c          | 508 ++++++++++-
 drivers/ram/Kconfig                                |  11 +-
 drivers/ram/Makefile                               |   2 +
 drivers/ram/rockchip/Makefile                      |   7 +
 drivers/ram/rockchip/dmc-rk3368.c                  | 990 +++++++++++++++++++++
 drivers/spi/rk_spi.c                               |   9 +
 dts/Kconfig                                        |  29 +
 include/configs/lion_rk3368.h                      |  19 +
 include/configs/rk3188_common.h                    |   2 +-
 include/configs/rk3288_common.h                    |   2 +-
 include/configs/rk3368_common.h                    |  14 +
 include/configs/rock.h                             |   2 +-
 include/configs/rockchip-common.h                  |   2 +-
 include/dt-bindings/memory/rk3368-dmc.h            |  30 +
 include/linux/kconfig.h                            |  13 +
 include/spl.h                                      |  10 +
 lib/Makefile                                       |  10 +-
 scripts/Makefile.spl                               |  14 +-
 scripts/config_whitelist.txt                       |   4 +
 tools/rkcommon.c                                   |   1 +
 79 files changed, 3538 insertions(+), 657 deletions(-)
 create mode 100644 arch/arm/dts/rk3368-lion-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3368-lion.dts
 create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
 create mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c
 create mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
 create mode 100644 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
 create mode 100644 arch/arm/mach-rockchip/spl-boot-order.c
 create mode 100644 board/theobroma-systems/lion_rk3368/Kconfig
 create mode 100644 board/theobroma-systems/lion_rk3368/MAINTAINERS
 create mode 100644 board/theobroma-systems/lion_rk3368/Makefile
 create mode 100644 board/theobroma-systems/lion_rk3368/README
 create mode 100644 board/theobroma-systems/lion_rk3368/fit_spl_atf.its
 create mode 100644 board/theobroma-systems/lion_rk3368/lion_rk3368.c
 create mode 100644 common/spl/spl_bootrom.c
 create mode 100644 configs/lion-rk3368_defconfig
 create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
 create mode 100644 drivers/ram/rockchip/Makefile
 create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
 create mode 100644 include/configs/lion_rk3368.h
 create mode 100644 include/dt-bindings/memory/rk3368-dmc.h

-- 
2.1.4

[U-Boot] [PATCH v2 01/56] spl: add a 'return to bootrom' boot method

[Philipp Tomsich]

Some devices (e.g. the RK3368) have only limited SRAM, but provide
support for loading the next boot stage after our SPL performs basic
setup (e.g. DRAM).

For target systems like these, we add a boot device BOOTROM that will
invoke a board-specific hook to return to the bootrom (if supported).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/include/asm/spl.h |  1 +
 common/spl/Kconfig         | 11 +++++++++++
 common/spl/Makefile        |  1 +
 common/spl/spl_bootrom.c   | 27 +++++++++++++++++++++++++++
 include/spl.h              | 10 ++++++++++
 5 files changed, 50 insertions(+)
 create mode 100644 common/spl/spl_bootrom.c

diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 0e67470..df45511 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -30,6 +30,7 @@ enum {
 	BOOT_DEVICE_BOARD,
 	BOOT_DEVICE_DFU,
 	BOOT_DEVICE_XIP,
+	BOOT_DEVICE_BOOTROM,
 	BOOT_DEVICE_NONE
 };
 #endif
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 4de8139..ee767b7 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -25,6 +25,17 @@ config SPL_BOARD_INIT
 	  spl_board_init() from board_init_r(). This function should be
 	  provided by the board.
 
+config SPL_BOOTROM_SUPPORT
+        bool "Support returning to the BOOTROM"
+	help
+	  Some platforms (e.g. the Rockchip RK3368) provide support in their
+	  ROM for loading the next boot-stage after performing basic setup
+	  from the SPL stage.
+
+	  Enable this option, to return to the BOOTROM through the
+	  BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
+	  boot device list, if not implemented for a given board)
+
 config SPL_RAW_IMAGE_SUPPORT
 	bool "Support SPL loading and booting of RAW images"
 	default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT))
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 47a64dd..189b272 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,6 +10,7 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
+obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_bootrom.o
 obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o
 obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
 obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o
diff --git a/common/spl/spl_bootrom.c b/common/spl/spl_bootrom.c
new file mode 100644
index 0000000..6804246
--- /dev/null
+++ b/common/spl/spl_bootrom.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+__weak void board_return_to_bootrom(void)
+{
+}
+
+static int spl_return_to_bootrom(struct spl_image_info *spl_image,
+				 struct spl_boot_device *bootdev)
+{
+	/*
+	 * If the board implements a way to return to its ROM (with
+	 * the expectation that the next stage of will be booted by
+	 * the ROM), it will implement board_return_to_bootrom() and
+	 * should not return from it.
+	 */
+	board_return_to_bootrom();
+	return false;
+}
+
+SPL_LOAD_IMAGE_METHOD("BOOTROM", 0, BOOT_DEVICE_BOOTROM, spl_return_to_bootrom);
diff --git a/include/spl.h b/include/spl.h
index ccb1404..b5c2994 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -278,4 +278,14 @@ int spl_mmc_load_image(struct spl_image_info *spl_image,
 		       struct spl_boot_device *bootdev);
 
 void bl31_entry(void);
+
+/**
+ * board_return_to_bootrom - allow for boards to continue with the boot ROM
+ *
+ * If a board (e.g. the Rockchip RK3368 boards) provide some
+ * supporting functionality for SPL in their boot ROM and the SPL
+ * stage wants to return to the ROM code to continue booting, boards
+ * can implement 'board_return_to_bootrom'.
+ */
+void board_return_to_bootrom(void);
 #endif
-- 
2.1.4

[U-Boot] [PATCH v2 02/56] spl: configure 'return to bootrom' separately for SPL and TPL

[Philipp Tomsich]

On the RK3368, we want our TPL to use the 'return to bootrom' boot
method (to have the bootrom load up the SPL stage) and then continue
with different boot methods (MMC, SPI, etc.) from SPL.

This adds the config option needed to control the availabily of the
'return to bootrom' boot-method separately for the TPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 common/spl/Kconfig | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index ee767b7..dd94801 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -698,6 +698,17 @@ config TPL
 
 if TPL
 
+config TPL_BOOTROM_SUPPORT
+        bool "Support returning to the BOOTROM (from TPL)"
+	help
+	  Some platforms (e.g. the Rockchip RK3368) provide support in their
+	  ROM for loading the next boot-stage after performing basic setup
+	  from the TPL stage.
+
+	  Enable this option, to return to the BOOTROM through the
+	  BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
+	  boot device list, if not implemented for a given board)
+
 config TPL_ENV_SUPPORT
 	bool "Support an environment"
 	help
-- 
2.1.4

[U-Boot] [PATCH v2 03/56] rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64

[Philipp Tomsich]

The back-to-bootrom support for Rockchip is equivalent to an
(assembly) implementation of setjmp/longjmp (i.e. it saves the
stack-pointer, link-register and callee-saved registers). Up until
now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
which puts the new ARMv8 devices (which boot in AArch64 mode) at a
slight disadvantage.

To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
RK3368), this commit adds an implementation for AArch64.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/mach-rockchip/save_boot_param.S | 37 ++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S
index 5e6c8db..945a9dd 100644
--- a/arch/arm/mach-rockchip/save_boot_param.S
+++ b/arch/arm/mach-rockchip/save_boot_param.S
@@ -1,11 +1,47 @@
 /*
  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <linux/linkage.h>
 
+#if defined(CONFIG_ARM64)
+.globl	SAVE_SP_ADDR
+SAVE_SP_ADDR:
+	.quad 0
+
+ENTRY(save_boot_params)
+	sub	sp, sp, #0x100
+	stp	x29, x30, [sp, #0x50]
+	stp	x27, x28, [sp, #0x40]
+	stp	x25, x26, [sp, #0x30]
+	stp	x23, x24, [sp, #0x20]
+	stp	x21, x22, [sp, #0x10]
+	stp	x19, x20, [sp, #0]
+	ldr	x8, =SAVE_SP_ADDR
+	mov	x9, sp
+	str	x9, [x8]
+	b	save_boot_params_ret  /* back to my caller */
+ENDPROC(save_boot_params)
+
+.globl _back_to_bootrom_s
+ENTRY(_back_to_bootrom_s)
+	ldr	x0, =SAVE_SP_ADDR
+	ldr	x0, [x0]
+	mov	sp, x0
+	ldp	x29, x30, [sp, #0x50]
+	ldp	x27, x28, [sp, #0x40]
+	ldp	x25, x26, [sp, #0x30]
+	ldp	x23, x24, [sp, #0x20]
+	ldp	x21, x22, [sp, #0x10]
+	ldp	x19, x20, [sp]
+	add	sp, sp, #0x100
+	mov	x0, xzr
+	ret
+ENDPROC(_back_to_bootrom_s)
+#else
 .globl	SAVE_SP_ADDR
 SAVE_SP_ADDR:
 	.word 0
@@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s)
 	mov	r0, #0
 	pop	{r1-r12, pc}
 ENDPROC(_back_to_bootrom_s)
+#endif
-- 
2.1.4

[U-Boot] [PATCH v2 04/56] rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL

[Philipp Tomsich]

The back-to-bootrom option is rather unfortunately named
  CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
instead of
  CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM

To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
we need to rename it.  At the same time, we introduce a TPL_ variant of
the option to give us finer-grained control over when it should be used.

This change is motivated by our RK3368 boot process, which returns to
the boot ROM only from the TPL stage, but not from the SPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/mach-rockchip/Kconfig            | 15 +++++++++++++--
 arch/arm/mach-rockchip/rk3188-board-spl.c |  5 ++---
 arch/arm/mach-rockchip/rk3188-board.c     |  2 +-
 arch/arm/mach-rockchip/rk3288-board-spl.c |  4 ++--
 arch/arm/mach-rockchip/rk3288-board.c     |  4 ++--
 arch/arm/mach-rockchip/rk3399-board-spl.c |  4 ++--
 configs/evb-rk3288_defconfig              |  2 +-
 configs/fennec-rk3288_defconfig           |  2 +-
 configs/firefly-rk3288_defconfig          |  2 +-
 configs/miqi-rk3288_defconfig             |  2 +-
 configs/popmetal-rk3288_defconfig         |  2 +-
 configs/rock2_defconfig                   |  2 +-
 configs/rock_defconfig                    |  2 +-
 configs/tinker-rk3288_defconfig           |  2 +-
 doc/README.rockchip                       |  2 +-
 include/configs/rk3188_common.h           |  2 +-
 include/configs/rk3288_common.h           |  2 +-
 include/configs/rock.h                    |  2 +-
 include/configs/rockchip-common.h         |  2 +-
 19 files changed, 35 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index bb44c61..523bc11 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -99,10 +99,21 @@ config ROCKCHIP_RV1108
 	  The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
 	  and a DSP.
 
-config ROCKCHIP_SPL_BACK_TO_BROM
+config SPL_ROCKCHIP_BACK_TO_BROM
 	bool "SPL returns to bootrom"
 	default y if ROCKCHIP_RK3036
 	select ROCKCHIP_BROM_HELPER
+	depends on SPL
+	help
+	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
+          SPL will return to the boot rom, which will then load the U-Boot
+          binary to keep going on.
+
+config TPL_ROCKCHIP_BACK_TO_BROM
+	bool "TPL returns to bootrom"
+	default y if ROCKCHIP_RK3368
+	select ROCKCHIP_BROM_HELPER
+	depends on TPL
 	help
 	  Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
           SPL will return to the boot rom, which will then load the U-Boot
@@ -120,7 +131,7 @@ config ROCKCHIP_BROM_HELPER
 	bool
 
 config SPL_MMC_SUPPORT
-	default y if !ROCKCHIP_SPL_BACK_TO_BROM
+	default y if !SPL_ROCKCHIP_BACK_TO_BROM
 
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
index c3e174d..d3866bf 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -167,8 +167,7 @@ void board_init_f(ulong dummy)
 	}
 
 	setup_arm_clock();
-
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
 	back_to_bootrom();
 #endif
 }
@@ -229,7 +228,7 @@ void spl_board_init(void)
 	}
 
 	preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	back_to_bootrom();
 #endif
 	return;
diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c
index 3e76100..622e046 100644
--- a/arch/arm/mach-rockchip/rk3188-board.c
+++ b/arch/arm/mach-rockchip/rk3188-board.c
@@ -39,7 +39,7 @@ int board_late_init(void)
 
 int board_init(void)
 {
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	struct udevice *pinctrl;
 	int ret;
 
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 5668fd2..6b7bf85 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -249,7 +249,7 @@ void board_init_f(ulong dummy)
 		debug("DRAM init failed: %d\n", ret);
 		return;
 	}
-#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
 	back_to_bootrom();
 #endif
 }
@@ -316,7 +316,7 @@ void spl_board_init(void)
 	}
 
 	preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	back_to_bootrom();
 #endif
 	return;
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
index 613967c..272f079 100644
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ b/arch/arm/mach-rockchip/rk3288-board.c
@@ -78,7 +78,7 @@ int board_late_init(void)
 	return rk_board_late_init();
 }
 
-#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 static int veyron_init(void)
 {
 	struct udevice *dev;
@@ -115,7 +115,7 @@ static int veyron_init(void)
 
 int board_init(void)
 {
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	struct udevice *pinctrl;
 	int ret;
 
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index e050aff..710f7fe 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -28,7 +28,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL)
+#if CONFIG_IS_ENABLED(OF_CONTROL)
 static int spl_node_to_boot_device(int node)
 {
 	struct udevice *parent;
@@ -263,7 +263,7 @@ void spl_board_init(void)
 	}
 
 	preloader_console_init();
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
 	back_to_bootrom();
 #endif
 
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 0d28311..14345be 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_EVB_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb"
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index 3a51da8..92be959 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_FENNEC_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 6f093f4..7df9d09 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_FIREFLY_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly"
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index c6bfa1e..29bdcdb 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_MIQI_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi"
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 6d02675..1392d6f 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_POPMETAL_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal"
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index eec0613..831d977 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_ROCK2=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square"
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index 5d9b63b..b7fb07f 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -4,7 +4,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3188=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_ROCK=y
 CONFIG_SPL_STACK_R_ADDR=0x60080000
 CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock"
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index c46bacc..b2124b1 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_ROCKCHIP_RK3288=y
-CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_TARGET_TINKER_RK3288=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-tinker"
diff --git a/doc/README.rockchip b/doc/README.rockchip
index dbeb8be..12fec38 100644
--- a/doc/README.rockchip
+++ b/doc/README.rockchip
@@ -130,7 +130,7 @@ load a second-level bootloader(ie. U-BOOT) as soon as it returns to bootrom.
 Therefore RK3288 has another loading sequence like RK3036. The option of
 U-Boot is controlled with this setting in U-Boot:
 
-	#define CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+	#define CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 
 You can create the image via the following operations:
 
diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h
index 3ee9abd..8a01936 100644
--- a/include/configs/rk3188_common.h
+++ b/include/configs/rk3188_common.h
@@ -26,7 +26,7 @@
 
 #define CONFIG_SYS_NS16550_MEM32
 
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
 #define CONFIG_SYS_TEXT_BASE		0x60000000
 #else
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 488d679..ade6caf 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -24,7 +24,7 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SYS_NS16550_MEM32
 
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* Bootrom will load u-boot binary to 0x0 once return from SPL */
 #define CONFIG_SYS_TEXT_BASE		0x00000000
 #else
diff --git a/include/configs/rock.h b/include/configs/rock.h
index de5291c..e76dc73 100644
--- a/include/configs/rock.h
+++ b/include/configs/rock.h
@@ -13,7 +13,7 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV 0
 
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* SPL @ 32k for 34k
  * u-boot directly after @ 68k for 400k or so
  * ENV @ 992k
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h
index 715290d..ce5b1a2 100644
--- a/include/configs/rockchip-common.h
+++ b/include/configs/rockchip-common.h
@@ -41,7 +41,7 @@
 #endif
 
 #if !defined(CONFIG_ENV_OFFSET)
-#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
 /* SPL @ 32k for 34k
  * u-boot directly after @ 68k for 400k or so
  * ENV @ 992k
-- 
2.1.4

[U-Boot] [PATCH v2 05/56] rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL

[Philipp Tomsich]

With the finer-grained control over LIBGENERIC_SUPPORT for TPL/SPL (i.e.
with the newly introduced distinction between TPL_LIBGENERIC_SUPPORT and
SPL_LIBGENERIC_SUPPORT), we can simplify the #ifdef-check to simply use
CONFIG_IS_ENABELD.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/mach-rockchip/bootrom.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
index da36f92..4d38ed6 100644
--- a/arch/arm/mach-rockchip/bootrom.c
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -9,8 +9,8 @@
 
 void back_to_bootrom(void)
 {
-#if defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && !defined(CONFIG_TPL_BUILD)
-	printf("Returning to boot ROM...");
+#if CONFIG_IS_ENABLED(LIBGENERIC_SUPPORT)
+	printf("Returning to boot ROM...\n");
 #endif
 	_back_to_bootrom_s();
 }
-- 
2.1.4

[U-Boot] [PATCH v2 06/56] spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON

[Philipp Tomsich]

SPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a
stricter dependency of SPL_DM was possible.  This commit makes the
prereq more specific.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/core/Kconfig | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index fb5c4e8..01e6d71 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -97,7 +97,7 @@ config REGMAP
 
 config SPL_REGMAP
 	bool "Support register maps in SPL"
-	depends on DM
+	depends on SPL_DM
 	help
 	  Hardware peripherals tend to have one or more sets of registers
 	  which can be accessed to control the hardware. A register map
@@ -116,7 +116,7 @@ config SYSCON
 
 config SPL_SYSCON
 	bool "Support system controllers in SPL"
-	depends on REGMAP
+	depends on SPL_REGMAP
 	help
 	  Many SoCs have a number of system controllers which are dealt with
 	  as a group by a single driver. Some common functionality is provided
-- 
2.1.4

[U-Boot] [PATCH v2 07/56] spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL

[Philipp Tomsich]

This change introduces TPL variants of the REGMAP and SYSCON config
options (i.e. TPL_REGMAP and TPL_SYSCON in analogy to SPL_REGMAP and
SPL_SYSCON) in preparation of a finer-grained feature selection for
building feature-rich TPL variants.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/core/Kconfig  | 19 +++++++++++++++++++
 drivers/core/Makefile |  4 ++--
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 01e6d71..6b5796b 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -105,6 +105,16 @@ config SPL_REGMAP
 	  support any bus type (I2C, SPI) but so far this only supports
 	  direct memory access.
 
+config TPL_REGMAP
+	bool "Support register maps in TPL"
+	depends on TPL_DM
+	help
+	  Hardware peripherals tend to have one or more sets of registers
+	  which can be accessed to control the hardware. A register map
+	  models this with a simple read/write interface. It can in principle
+	  support any bus type (I2C, SPI) but so far this only supports
+	  direct memory access.
+
 config SYSCON
 	bool "Support system controllers"
 	depends on REGMAP
@@ -123,6 +133,15 @@ config SPL_SYSCON
 	  by this uclass, including accessing registers via regmap and
 	  assigning a unique number to each.
 
+config TPL_SYSCON
+	bool "Support system controllers in TPL"
+	depends on TPL_REGMAP
+	help
+	  Many SoCs have a number of system controllers which are dealt with
+	  as a group by a single driver. Some common functionality is provided
+	  by this uclass, including accessing registers via regmap and
+	  assigning a unique number to each.
+
 config DEVRES
 	bool "Managed device resources"
 	depends on DM
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index 435cf98..dcfb1b0 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -9,8 +9,8 @@ obj-$(CONFIG_DEVRES) += devres.o
 obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE)	+= device-remove.o
 obj-$(CONFIG_$(SPL_)SIMPLE_BUS)	+= simple-bus.o
 obj-$(CONFIG_DM)	+= dump.o
-obj-$(CONFIG_$(SPL_)REGMAP)	+= regmap.o
-obj-$(CONFIG_$(SPL_)SYSCON)	+= syscon-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)REGMAP)	+= regmap.o
+obj-$(CONFIG_$(SPL_TPL_)SYSCON)	+= syscon-uclass.o
 obj-$(CONFIG_OF_LIVE) += of_access.o of_addr.o
 ifndef CONFIG_DM_DEV_READ_INLINE
 obj-$(CONFIG_OF_CONTROL) += read.o
-- 
2.1.4

[U-Boot] [PATCH v2 08/56] spl: dm: Kconfig: SPL_RAM depends on SPL_DM

[Philipp Tomsich]

This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/ram/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 61afd7a..e75c23f 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -10,7 +10,7 @@ config RAM
 
 config SPL_RAM
 	bool "Enable RAM support in SPL"
-	depends on RAM
+	depends on RAM && SPL_DM
 	help
 	  The RAM subsystem adds a small amount of overhead to the image.
 	  If this is acceptable and you have a need to use RAM drivers in
-- 
2.1.4

[U-Boot] [PATCH v2 09/56] spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)

[Philipp Tomsich]

To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/ram/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index e75c23f..836be25 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -17,6 +17,15 @@ config SPL_RAM
 	  SPL, enable this option. It might provide a cleaner interface to
 	  setting up RAM (e.g. SDRAM / DDR) within SPL.
 
+config TPL_RAM
+	bool "Enable RAM support in SPL"
+	depends on RAM && TPL_DM
+	help
+	  The RAM subsystem adds a small amount of overhead to the image.
+	  If this is acceptable and you have a need to use RAM drivers in
+	  TPL, enable this option. It might provide a cleaner interface to
+	  setting up RAM (e.g. SDRAM / DDR) within TPL.
+
 config STM32_SDRAM
 	bool "Enable STM32 SDRAM support"
 	depends on RAM
-- 
2.1.4

[U-Boot] [PATCH v2 10/56] spl: dm: Kconfig: SPL_CLK depens on SPL_DM

[Philipp Tomsich]

SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 44da716..9c13587 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,7 +12,7 @@ config CLK
 
 config SPL_CLK
 	bool "Enable clock support in SPL"
-	depends on CLK
+	depends on CLK && SPL_DM
 	help
 	  The clock subsystem adds a small amount of overhead to the image.
 	  If this is acceptable and you have a need to use clock drivers in
-- 
2.1.4

[U-Boot] [PATCH v2 11/56] spl: dm: Kconfig: split CLK support for SPL and TPL

[Philipp Tomsich]

Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/Kconfig  | 10 ++++++++++
 drivers/clk/Makefile |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9c13587..b40bde2 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -20,6 +20,16 @@ config SPL_CLK
 	  setting up clocks within SPL, and allows the same drivers to be
 	  used as U-Boot proper.
 
+config TPL_CLK
+	bool "Enable clock support in TPL"
+	depends on CLK && TPL_DM
+	help
+	  The clock subsystem adds a small amount of overhead to the image.
+	  If this is acceptable and you have a need to use clock drivers in
+	  SPL, enable this option. It might provide a cleaner interface to
+	  setting up clocks within TPL, and allows the same drivers to be
+	  used as U-Boot proper.
+
 config CLK_BCM6345
 	bool "Clock controller driver for BCM6345"
 	depends on CLK && ARCH_BMIPS
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2746a80..844bc4e 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -5,7 +5,7 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
-obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
-- 
2.1.4

[U-Boot] [PATCH v2 12/56] spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL

[Philipp Tomsich]

For the RK3368, we want to use OF_PLATDATA in TPL, but full OF_CONTROL
in SPL: this requires the introduction of a new family of
configuration options to decouple SPL_OF_CONTROL and SPL_OF_PLATDATA
from TPL.

Consequently, Makefile.spl needs to be adjusted to test for these
configuration items through the $(SPL_TPL_) macro instead of
hard-coding the SPL variant.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 Makefile             |  2 +-
 dts/Kconfig          | 29 +++++++++++++++++++++++++++++
 scripts/Makefile.spl |  4 ++--
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 119ad49..d5cdf2a 100644
--- a/Makefile
+++ b/Makefile
@@ -1378,7 +1378,7 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
 spl/u-boot-spl.bin: spl/u-boot-spl
 	@:
 spl/u-boot-spl: tools prepare \
-		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb)
+		$(if $(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),dts/dt.dtb)
 	$(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
 
 spl/sunxi-spl.bin: spl/u-boot-spl
diff --git a/dts/Kconfig b/dts/Kconfig
index b3009af..bbadc32 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -32,6 +32,14 @@ config SPL_OF_CONTROL
 	  which is not enough to support device tree. Enable this option to
 	  allow such boards to be supported by U-Boot SPL.
 
+config TPL_OF_CONTROL
+	bool "Enable run-time configuration via Device Tree in TPL"
+	depends on TPL && OF_CONTROL
+	help
+	  Some boards use device tree in U-Boot but only have 4KB of SRAM
+	  which is not enough to support device tree. Enable this option to
+	  allow such boards to be supported by U-Boot TPL.
+
 config OF_LIVE
 	bool "Enable use of a live tree"
 	depends on OF_CONTROL
@@ -135,4 +143,25 @@ config SPL_OF_PLATDATA
 	  declarations for each node. See README.platdata for more
 	  information.
 
+config TPL_OF_PLATDATA
+	bool "Generate platform data for use in TPL"
+	depends on TPL_OF_CONTROL
+	help
+	  For very constrained SPL environments the overhead of decoding
+	  device tree nodes and converting their contents into platform data
+	  is too large. This overhead includes libfdt code as well as the
+	  device tree contents itself. The latter is fairly compact, but the
+	  former can add 3KB or more to a Thumb 2 Image.
+
+	  This option enables generation of platform data from the device
+	  tree as C code. This code creates devices using U_BOOT_DEVICE()
+	  declarations. The benefit is that it allows driver code to access
+	  the platform data directly in C structures, avoidin the libfdt
+	  overhead.
+
+	  This option works by generating C structure declarations for each
+	  compatible string, then adding platform data and U_BOOT_DEVICE
+	  declarations for each node. See README.platdata for more
+	  information.
+
 endmenu
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ac3c2c7..3e35cd6 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -98,7 +98,7 @@ endif
 
 u-boot-spl-init := $(head-y)
 u-boot-spl-main := $(libs-y)
-ifdef CONFIG_SPL_OF_PLATDATA
+ifdef CONFIG_$(SPL_TPL_)OF_PLATDATA
 u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
 endif
 
@@ -202,7 +202,7 @@ cmd_cat = cat $(filter-out $(PHONY), $^) > $@
 quiet_cmd_copy = COPY    $@
       cmd_copy = cp $< $@
 
-ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy)
+ifeq ($(CONFIG_$(SPL_TPL_)OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
 $(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \
 		$(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \
 		$(obj)/$(SPL_BIN).dtb FORCE
-- 
2.1.4

[U-Boot] [PATCH v2 13/56] spl: dm: use CONFIG_IS_ENABLED to test for the DM option

[Philipp Tomsich]

Even though there's now a TPL_DM configuration option, the spl logic
still checks for SPL_DM and thus does not pick up the proper config
option.

This introduces the use of CONFIG_IS_ENABLED(DM) in spl.c to always
pick up the desired configuration option instead of having a
hard-coded check for the SPL variant.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 common/spl/spl.c        |  5 +++--
 include/linux/kconfig.h | 13 +++++++++++++
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index db55d26..233e4fe 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -6,6 +6,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+
 #include <common.h>
 #include <dm.h>
 #include <spl.h>
@@ -243,7 +244,7 @@ static int spl_common_init(bool setup_malloc)
 			return ret;
 		}
 	}
-	if (IS_ENABLED(CONFIG_SPL_DM)) {
+	if (CONFIG_IS_ENABLED(DM)) {
 		bootstage_start(BOOTSTATE_ID_ACCUM_DM_SPL, "dm_spl");
 		/* With CONFIG_SPL_OF_PLATDATA, bring in all devices */
 		ret = dm_init_and_scan(!CONFIG_IS_ENABLED(OF_PLATDATA));
@@ -425,7 +426,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	      gd->malloc_ptr / 1024);
 #endif
 
-	if (IS_ENABLED(CONFIG_SPL_ATF_SUPPORT)) {
+	if (CONFIG_IS_ENABLED(ATF_SUPPORT)) {
 		debug("loaded - jumping to U-Boot via ATF BL31.\n");
 		bl31_entry();
 	}
diff --git a/include/linux/kconfig.h b/include/linux/kconfig.h
index 486fb94..fbfc718 100644
--- a/include/linux/kconfig.h
+++ b/include/linux/kconfig.h
@@ -51,12 +51,25 @@
 #define _IS_SPL 1
 #endif
 
+#ifdef CONFIG_TPL_BUILD
+#define _IS_TPL 1
+#endif
+
+#if defined(CONFIG_TPL_BUILD)
+#define config_val(cfg) _config_val(_IS_TPL, cfg)
+#define _config_val(x, cfg) __config_val(x, cfg)
+#define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)
+#define ___config_val(arg1_or_junk, cfg)  \
+	____config_val(arg1_or_junk CONFIG_TPL_##cfg, CONFIG_##cfg)
+#define ____config_val(__ignored, val, ...) val
+#else
 #define config_val(cfg) _config_val(_IS_SPL, cfg)
 #define _config_val(x, cfg) __config_val(x, cfg)
 #define __config_val(x, cfg) ___config_val(__ARG_PLACEHOLDER_##x, cfg)
 #define ___config_val(arg1_or_junk, cfg)  \
 	____config_val(arg1_or_junk CONFIG_SPL_##cfg, CONFIG_##cfg)
 #define ____config_val(__ignored, val, ...) val
+#endif
 
 /*
  * CONFIG_VAL(FOO) evaluates to the value of
-- 
2.1.4

[U-Boot] [PATCH v2 14/56] armv8: remove unused low-level modules from TPL

[Philipp Tomsich]

TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option
whether to include this or not), but include the needed support code
for this anyway.

Even for a feature-rich TPL (including DM support as for the RK3368),
this equates to a size difference of approx. 10% in TPL binary size:
- without this change:
   text    data    bss    dec    hex filename
  23635    3112     24  26771   6893 tpl/u-boot-tpl
- with this change:
   text	   data    bss    dec    hex filename
  21583    3112     24  24719   608f tpl/u-boot-tpl

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/cpu/armv8/Makefile | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index c447085..e831471 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -9,12 +9,14 @@ extra-y	:= start.o
 
 obj-y	+= cpu.o
 obj-y	+= generic_timer.o
+ifndef CONFIG_TPL_BUILD
 obj-y	+= cache_v8.o
-obj-y	+= exceptions.o
 obj-y	+= cache.o
 obj-y	+= tlb.o
 obj-y	+= transition.o
 obj-y	+= fwcall.o
+endif
+obj-y	+= exceptions.o
 obj-y	+= cpu-dt.o
 obj-$(CONFIG_ARM_SMCCC)		+= smccc-call.o
 
-- 
2.1.4

[U-Boot] [PATCH v2 15/56] armv8: spl: Support separate stack for TPL

[Philipp Tomsich]

To allow a TPL and SPL to run from different addresses/memories, we
need to split setup of the TPL and SPL stacks.  To do so, we introduce
CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override
the initial stack pointer for TPL.

To provide backward compatibility for existing boards, this is added
as an optional configuration item and the normal search order (i.e.
SPL_STACK, then SYS_STACK) apply if not defined.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/lib/crt0_64.S       | 4 +++-
 scripts/config_whitelist.txt | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 57e728f..177b5bf 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -69,7 +69,9 @@ ENTRY(_main)
 /*
  * Set up initial C runtime environment and call board_init_f(0).
  */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_STACK)
+	ldr	x0, =(CONFIG_TPL_STACK)
+#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
 	ldr	x0, =(CONFIG_SPL_STACK)
 #else
 	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 1ab6101..34aadc5 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4997,6 +4997,7 @@ CONFIG_TI_SPI_MMAP
 CONFIG_TMU_TIMER
 CONFIG_TPL_DRIVERS_MISC_SUPPORT
 CONFIG_TPL_PAD_TO
+CONFIG_TPL_STACK
 CONFIG_TPM_TIS_BASE_ADDRESS
 CONFIG_TPS6586X_POWER
 CONFIG_TQM834X
-- 
2.1.4

[U-Boot] [PATCH v2 16/56] spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL

[Philipp Tomsich]

For the bringup of the RK3368, we need to support TPL and SPL running
from different addresses... which requires both stages to use a
distinct TEXT_BASE.

This commit adds support for having a separate LDSCRIPT for TPL (which
is expected to make use of the TPL_MAX_SIZE define) and for having a
the option of defining TPL_TEXT_BASE and having the TPL stage linked
against this address.

Note that the handling of the TEXT_BASE is designed to not interfere
with the previous assumption that SPL_TEXT_BASE should be used for TPL
as well, unless TPL_TEXT_BASE is defined.  For this reason, the test
in Makefile.spl uses the following (seemingly redundant checks):
 1. looks for $(SPL_TPL_)TEXT_BASE
 2. looks for SPL_TEXT_BASE (even when building in TPL)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 scripts/Makefile.spl         | 10 ++++++++--
 scripts/config_whitelist.txt |  3 +++
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 3e35cd6..4a9a58f 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -103,9 +103,9 @@ u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
 endif
 
 # Linker Script
-ifdef CONFIG_SPL_LDSCRIPT
+ifdef CONFIG_$(SPL_TPL_)LDSCRIPT
 # need to strip off double quotes
-LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%))
+LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(SPL_TPL_)LDSCRIPT:"%"=%))
 endif
 
 ifeq ($(wildcard $(LDSCRIPT)),)
@@ -293,9 +293,15 @@ LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
 # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
 LDFLAGS_$(SPL_BIN) += $(call ld-option, --no-dynamic-linker)
 
+# First try the best-match (i.e. SPL_TEXT_BASE for SPL, TPL_TEXT_BASE for TPL)
+ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),)
+LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(SPL_TPL_)TEXT_BASE)
+else
+# And then fall back to just testing for SPL_TEXT_BASE, even if in TPL mode
 ifneq ($(CONFIG_SPL_TEXT_BASE),)
 LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
 endif
+endif
 
 MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
 $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 34aadc5..d8d00f5 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4996,8 +4996,11 @@ CONFIG_TI_KSNAV
 CONFIG_TI_SPI_MMAP
 CONFIG_TMU_TIMER
 CONFIG_TPL_DRIVERS_MISC_SUPPORT
+CONFIG_TPL_LDSCRIPT
+CONFIG_TPL_MAX_SIZE
 CONFIG_TPL_PAD_TO
 CONFIG_TPL_STACK
+CONFIG_TPL_TEXT_BASE
 CONFIG_TPM_TIS_BASE_ADDRESS
 CONFIG_TPS6586X_POWER
 CONFIG_TQM834X
-- 
2.1.4

[U-Boot] [PATCH v2 17/56] spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL

[Philipp Tomsich]

As include/malloc.h already checks for SYS_MALLOC_SIMPLE using the
CONFIG_IS_ENABLED macro, we need to move to having separate entries
as we switch to fully separate configuration for SPL and TPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 common/spl/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index dd94801..f49b958 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -62,6 +62,15 @@ config SPL_SYS_MALLOC_SIMPLE
 	  this will make the SPL binary smaller at the cost of more heap
 	  usage as the *_simple malloc functions do not re-use free-ed mem.
 
+config TPL_SYS_MALLOC_SIMPLE
+	bool
+	prompt "Only use malloc_simple functions in the TPL"
+	help
+	  Say Y here to only use the *_simple malloc functions from
+	  malloc_simple.c, rather then using the versions from dlmalloc.c;
+	  this will make the TPL binary smaller at the cost of more heap
+	  usage as the *_simple malloc functions do not re-use free-ed mem.
+
 config SPL_STACK_R
 	bool "Enable SDRAM location for SPL stack"
 	help
-- 
2.1.4

[U-Boot] [PATCH v2 18/56] lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata

[Philipp Tomsich]

This splits the compilation of code modules for TPL and SPL for
OF_CONTROL (and related) features between TPL and SPL.  The typical
use-case of this is a TPL stage that uses OF_PLATDATA at TPL and
provides full OF_CONTROL at SPL (e.g. on the RK3368).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 lib/Makefile | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/lib/Makefile b/lib/Makefile
index eacc7d6..2eef1eb 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -49,11 +49,11 @@ obj-$(CONFIG_RSA) += rsa/
 obj-$(CONFIG_SHA1) += sha1.o
 obj-$(CONFIG_SHA256) += sha256.o
 
-obj-$(CONFIG_SPL_SAVEENV) += qsort.o
-obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/
-ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy)
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o
-obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec.o
+obj-$(CONFIG_$(SPL_TPL_)SAVEENV) += qsort.o
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
+ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy)
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec_common.o
+obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-- 
2.1.4

[U-Boot] [PATCH v2 19/56] spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds

[Philipp Tomsich]

To allow for a finer-grained control of features for TPL and SPL
builds all modules/boot-methods/etc. need to be consistently selected
based on the $(SPL_TPL_) macros.

This allows splitting the associated config-options in Kconfig: we
don't split the Kconfig options here and now, as this should happen on
an as-needed basis, whenever someone needs a feature/boot-method/etc.
in their TPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 common/Makefile     |  8 ++++----
 common/spl/Makefile | 36 ++++++++++++++++++------------------
 2 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/common/Makefile b/common/Makefile
index 539cf98..14345de 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -53,7 +53,7 @@ obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
 obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
 
 obj-$(CONFIG_CMD_BEDBUG) += bedbug.o
-obj-$(CONFIG_$(SPL_)OF_LIBFDT) += fdt_support.o
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o
 
 obj-$(CONFIG_MII) += miiphyutil.o
 obj-$(CONFIG_CMD_MII) += miiphyutil.o
@@ -148,9 +148,9 @@ obj-y += malloc_simple.o
 endif
 obj-y += image.o
 obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
-obj-$(CONFIG_$(SPL_)OF_LIBFDT) += image-fdt.o
-obj-$(CONFIG_$(SPL_)FIT) += image-fit.o
-obj-$(CONFIG_$(SPL_)FIT_SIGNATURE) += image-sig.o
+obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
+obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
+obj-$(CONFIG_$(SPL_TPL_)FIT_SIGNATURE) += image-sig.o
 obj-$(CONFIG_IO_TRACE) += iotrace.o
 obj-y += memsize.o
 obj-y += stdio.o
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 189b272..112b3e6 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -10,24 +10,24 @@
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
-obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_bootrom.o
-obj-$(CONFIG_SPL_LOAD_FIT) += spl_fit.o
-obj-$(CONFIG_SPL_NOR_SUPPORT) += spl_nor.o
-obj-$(CONFIG_SPL_XIP_SUPPORT) += spl_xip.o
-obj-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
+obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o
+obj-$(CONFIG_$(SPL_TPL_)SPL_NOR_SUPPORT) += spl_nor.o
+obj-$(CONFIG_$(SPL_TPL_)SPL_XIP_SUPPORT) += spl_xip.o
+obj-$(CONFIG_$(SPL_TPL_)SPL_YMODEM_SUPPORT) += spl_ymodem.o
 ifndef CONFIG_SPL_UBI
-obj-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
-obj-$(CONFIG_SPL_ONENAND_SUPPORT) += spl_onenand.o
+obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += spl_nand.o
+obj-$(CONFIG_$(SPL_TPL_)ONENAND_SUPPORT) += spl_onenand.o
 endif
-obj-$(CONFIG_SPL_UBI) += spl_ubi.o
-obj-$(CONFIG_SPL_NET_SUPPORT) += spl_net.o
-obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc.o
-obj-$(CONFIG_SPL_ATF_SUPPORT) += spl_atf.o
-obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
-obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
-obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o
-obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
-obj-$(CONFIG_SPL_DFU_SUPPORT) += spl_dfu.o
-obj-$(CONFIG_SPL_SPI_LOAD) += spl_spi.o
-obj-$(CONFIG_SPL_RAM_SUPPORT) += spl_ram.o
+obj-$(CONFIG_$(SPL_TPL_)UBI) += spl_ubi.o
+obj-$(CONFIG_$(SPL_TPL_)NET_SUPPORT) += spl_net.o
+obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += spl_mmc.o
+obj-$(CONFIG_$(SPL_TPL_)ATF_SUPPORT) += spl_atf.o
+obj-$(CONFIG_$(SPL_TPL_)USB_SUPPORT) += spl_usb.o
+obj-$(CONFIG_$(SPL_TPL_)FAT_SUPPORT) += spl_fat.o
+obj-$(CONFIG_$(SPL_TPL_)EXT_SUPPORT) += spl_ext.o
+obj-$(CONFIG_$(SPL_TPL_)SATA_SUPPORT) += spl_sata.o
+obj-$(CONFIG_$(SPL_TPL_)DFU_SUPPORT) += spl_dfu.o
+obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
+obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
 endif
-- 
2.1.4

[U-Boot] [PATCH v2 20/56] spl: add TPL_DRIVER_MISC_SUPPORT option

[Philipp Tomsich]

This adds the TPL_DRIVER_MISC_SUPPORT option to allow activation of
DRIVER_MISC_SUPPORT for devices that need it in the TPL stage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 common/spl/Kconfig | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index f49b958..def8107 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -718,6 +718,14 @@ config TPL_BOOTROM_SUPPORT
 	  BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
 	  boot device list, if not implemented for a given board)
 
+config TPL_DRIVERS_MISC_SUPPORT
+	bool "Support misc drivers in TPL"
+	help
+	  Enable miscellaneous drivers in TPL. These drivers perform various
+	  tasks that don't fall nicely into other categories, Enable this
+	  option to build the drivers in drivers/misc as part of an TPL
+	  build, for those that support building in TPL (not all drivers do).
+
 config TPL_ENV_SUPPORT
 	bool "Support an environment"
 	help
-- 
2.1.4

[U-Boot] [PATCH v2 21/56] drivers: spl: consistently use the $(SPL_TPL_) macro

[Philipp Tomsich]

To simplify drivers/Makefile a bit when using TPL/SPL, we consistently
use the $(SPL_TPL_) macro to test for drivers that have separate
configuration symbols for the full U-boot, SPL and TPL stages.
Instead of explicitly repeating them in two separate if-guarded
sections of the Makefile, we can now simply list these options once.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/Makefile | 36 ++++++++++++++++--------------------
 1 file changed, 16 insertions(+), 20 deletions(-)

diff --git a/drivers/Makefile b/drivers/Makefile
index 058bccb..2bd769f 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -2,33 +2,34 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_$(SPL_TPL_)DM)	+= core/
-obj-$(CONFIG_$(SPL_)CLK)	+= clk/
-obj-$(CONFIG_$(SPL_)LED)	+= led/
-obj-$(CONFIG_$(SPL_)PHY)	+= phy/
-obj-$(CONFIG_$(SPL_)PINCTRL)	+= pinctrl/
-obj-$(CONFIG_$(SPL_)RAM)	+= ram/
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/
+obj-$(CONFIG_$(SPL_TPL_)DM) += core/
+obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
+obj-$(CONFIG_$(SPL_TPL_)I2C_SUPPORT) += i2c/
+obj-$(CONFIG_$(SPL_TPL_)LED) += led/
+obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/
+obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/
+obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/
+obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/
+obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/
+obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/
+obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPORT) += mtd/spi/
+obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/
 
+ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
 
 obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
-obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
 obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
-obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc/
 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
 obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
 obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_SPL_SPI_SUPPORT) += spi/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/
 obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/
-obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
 obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/
-obj-$(CONFIG_SPL_NAND_SUPPORT) += mtd/nand/
 obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/
-obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/
 obj-$(CONFIG_SPL_UBI) += mtd/ubispl/
 obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/
 obj-$(CONFIG_SPL_ETH_SUPPORT) += net/
@@ -48,18 +49,13 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+
+endif
 endif
 
 ifdef CONFIG_TPL_BUILD
 
-obj-$(CONFIG_TPL_I2C_SUPPORT) += i2c/
-obj-$(CONFIG_TPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ firmware/
-obj-$(CONFIG_TPL_MMC_SUPPORT) += mmc/
 obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
-obj-$(CONFIG_TPL_NAND_SUPPORT) += mtd/nand/
-obj-$(CONFIG_TPL_SERIAL_SUPPORT) += serial/
-obj-$(CONFIG_TPL_SPI_FLASH_SUPPORT) += mtd/spi/
-obj-$(CONFIG_TPL_SPI_SUPPORT) += spi/
 
 endif
 
-- 
2.1.4

[U-Boot] [PATCH v2 22/56] rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot

[Philipp Tomsich]

The utility functions in sdram_common.c will be useful both for some
SPL implementations (and if unused, the linked will discard these
anyway) and for the full U-Boot stage.

This changes selects sdram_common.o through the $(SPL_TPL_) macro to
allow better control of its inclusion through the CONFIG_ROM,
CONFIG_SPL_RAM or CONFIG_TPL_RAM options.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/mach-rockchip/Makefile | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index cb8d3ef..8a3cb9f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -5,6 +5,7 @@
 #
 
 obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
+obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
 
 ifdef CONFIG_TPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
@@ -21,9 +22,6 @@ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
-ifdef CONFIG_RAM
-obj-y += sdram_common.o
-endif
 endif
 ifndef CONFIG_ARM64
 obj-y += rk_timer.o
-- 
2.1.4

[U-Boot] [PATCH v2 23/56] rockchip: rk3368: improve Kconfig text for the RK3368

[Philipp Tomsich]

The RK3368 option in Kconfig referred to the RK3328 (copy-and-paste)
and had a few typos and unnecessarily used UTF-8 characters.  While
fixing this, I also reformatted and further clarified the text
(e.g. made the grouping into a a big and little cluster of 4 cores
each explicit).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/mach-rockchip/Kconfig | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 523bc11..2ad4943 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -69,12 +69,15 @@ config ROCKCHIP_RK3368
 	select ARM64
 	select SYS_NS16550
 	help
-	  The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53.
-	  including NEON and GPU, 512KB L2 cache for big cluster and 256 KB
-	  L2 cache for little cluser, PowerVR G6110 based graphics, one video
-	  output processor supporting LVDS、HDMI、eDP, several DDR3 options
-	  and video codec support. Peripherals include Gigabit Ethernet,
-	  USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
+	  into a big and little cluster with 4 cores each) Cortex-A53 including
+	  AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
+	  (for the little cluster), PowerVR G6110 based graphics, one video
+	  output processor supporting LVDS/HDMI/eDP, several DDR3 options and
+	  video codec support.
+
+	  On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
+	  I2S, UARTs, SPI, I2C and PWMs.
 
 config ROCKCHIP_RK3399
 	bool "Support Rockchip RK3399"
-- 
2.1.4

[U-Boot] [PATCH v2 24/56] rockchip: rk3368: mkimage: add support for the RK3368

[Philipp Tomsich]

This commit adds support for RK3368 SoC in mkimage.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 tools/rkcommon.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 25b0340..04e8272 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -77,6 +77,7 @@ static struct spl_info spl_infos[] = {
 	{ "rk322x", "RK32", 0x8000 - 0x1000, false, false },
 	{ "rk3288", "RK32", 0x8000, false, false },
 	{ "rk3328", "RK32", 0x8000 - 0x1000, false, false },
+	{ "rk3368", "RK33", 0x8000 - 0x1000, false, true },
 	{ "rk3399", "RK33", 0x30000 - 0x2000, false, true },
 	{ "rv1108", "RK11", 0x1800, false, false},
 };
-- 
2.1.4

[U-Boot] [PATCH v2 25/56] rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]

[Philipp Tomsich]

On the RK3368 we use a TPL-stage similar to Rockchip's DDR init
(i.e. it initialises DRAM, leaves some info for the next stage and
returns to the BootROM).  To allow compatibility with Rockchip's DDR
init code, we use the same register os_reg2 in pmugrf for passing
this info (i.e. DRAM size and configuration) between stages.

This change adds the definitions for os_reg[0] through os_reg[3] to
the pmugrf structure for the RK3368.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index 93c4e7d..a438f5d 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -92,10 +92,11 @@ struct rk3368_pmu_grf {
 	u32 gpio0d_drv;
 	u32 gpio0l_sr;
 	u32 gpio0h_sr;
-	u32 reserved[(0x200 - 0x34) / 4 - 1];
+	u32 reserved[0x72];
 	u32 os_reg[4];
 };
-check_member(rk3368_pmu_grf, os_reg[3], 0x20c);
+check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
+check_member(rk3368_pmu_grf, os_reg[0], 0x200);
 
 /*GRF_GPIO0C_IOMUX*/
 enum {
-- 
2.1.4

[U-Boot] [PATCH v2 26/56] rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz

[Philipp Tomsich]

The BootROM of the RK3368 Boot ROM does not initialise cntfrq_el0.
This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0.

If the counter-frequency is not correctly set up, the calculation of
delays using the ARMv8 generic timer can not work correctly.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 include/configs/rk3368_common.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index b0c858c..ddb7df0 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -21,6 +21,8 @@
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
+#define COUNTER_FREQUENCY               24000000
+
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_TEXT_BASE		0x00200000
-- 
2.1.4

[U-Boot] [PATCH v2 27/56] rockchip: rk3368: spl: add memory layout for TPL and SPL

[Philipp Tomsich]

For the RK3368, we use a multi-stage boot-process consisting of the
following:
  1.  TPL: initalises DRAM, returns to boot-ROM (which then loads
           the next stage and transfers control to it)
  2.  SPL: a full-features SPL stage including OF_CONTROL and FIT
           image loading, which fetches the ATF, DTB and full U-Boot
	   and then transfers control to the ATF (using the BL31
	   parameter block to indicate the location of BL33/U-Boot)
  3.  ATF: sets up the secure world and exits to BL33 (i.e. a full
           U-Boot) in the normal world
  4.  full U-Boot

TPL/SPL and the full U-Boot are built from this tree and need to
run from distinct text addresses and with distinct initial stack
pointer addresses.

This commit sets up the configuration to run:
  -  TPL from the SRAM at 0xff8c0000 (note that the first 0x1000
     	 are reserved for use by the boot-ROM and contain the SP
	 when the TPL is entered)
  -  SPL from DRAM at 0x0
  -  U-Boot from DRAM at 0x200000

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 include/configs/rk3368_common.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index ddb7df0..e35f4c0 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -29,6 +29,17 @@
 #define CONFIG_SYS_INIT_SP_ADDR		0x00300000
 #define CONFIG_SYS_LOAD_ADDR		0x00280000
 
+#define CONFIG_SPL_TEXT_BASE            0x00000000
+#define CONFIG_SPL_MAX_SIZE             0x40000
+#define CONFIG_SPL_BSS_START_ADDR       0x400000
+#define CONFIG_SPL_BSS_MAX_SIZE         0x20000
+
+#define CONFIG_TPL_LDSCRIPT \
+	  "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
+#define CONFIG_TPL_TEXT_BASE		0xff8c1000
+#define CONFIG_TPL_MAX_SIZE		0x7000
+#define CONFIG_TPL_STACK		0xff8cffff
+
 #define CONFIG_BOUNCE_BUFFER
 
 #ifndef CONFIG_SPL_BUILD
-- 
2.1.4

[U-Boot] [PATCH v2 28/56] rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA

[Philipp Tomsich]

The RK3368 has both a limited SPL size (just 0x7000 bytes) and the
added challenge of booting in AArch64, which increases the code size
for SPL (particularily when using the LP64 programming model).  For
this reason we expect the RK3368 to always use OF_PLATDATA for its
SPL stage.

This change adds support for the MSCH, PMUGRF and GRF register regions
in syscon, which are necessary for initialising the RK3368's DRAM
controller.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 35 +++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
index 03e97eb..90a993e 100644
--- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
+++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
@@ -1,6 +1,8 @@
 /*
  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  * Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
@@ -14,6 +16,8 @@ static const struct udevice_id rk3368_syscon_ids[] = {
 	  .data = ROCKCHIP_SYSCON_GRF },
 	{ .compatible = "rockchip,rk3368-pmugrf",
 	  .data = ROCKCHIP_SYSCON_PMUGRF },
+	{ .compatible = "rockchip,rk3368-msch",
+	  .data = ROCKCHIP_SYSCON_MSCH },
 	{ }
 };
 
@@ -22,3 +26,34 @@ U_BOOT_DRIVER(syscon_rk3368) = {
 	.id = UCLASS_SYSCON,
 	.of_match = rk3368_syscon_ids,
 };
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
+{
+	dev->driver_data = dev->driver->of_match->data;
+	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3368_grf) = {
+	.name = "rockchip_rk3368_grf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids,
+	.bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
+	.name = "rockchip_rk3368_pmugrf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids + 1,
+	.bind = rk3368_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3368_msch) = {
+	.name = "rockchip_rk3368_msch",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3368_syscon_ids + 2,
+	.bind = rk3368_syscon_bind_of_platdata,
+};
+#endif
-- 
2.1.4

[U-Boot] [PATCH v2 29/56] rockchip: rk3368: grf: use shifted-constants

[Philipp Tomsich]

The RK3368 GRF header was still defines with a shifted-mask but with
non-shifted function selectors for the IOMUX defines.  As the RK3368
support is still fresh enough to allow a quick change, we do this now
before having more code use this.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- dropped the RK3368_ prefix for the GRF constants

 arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 441 ++++++++++++------------
 drivers/pinctrl/rockchip/pinctrl_rk3368.c       |   9 +-
 2 files changed, 226 insertions(+), 224 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index a438f5d..1966960 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -1,4 +1,6 @@
-/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
@@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
 
 /*GRF_GPIO0C_IOMUX*/
 enum {
-	GPIO0C7_SHIFT		= 14,
-	GPIO0C7_MASK		= 3 << GPIO0C7_SHIFT,
-	GPIO0C7_GPIO		= 0,
-	GPIO0C7_LCDC_D19,
-	GPIO0C7_TRACE_D9,
-	GPIO0C7_UART1_RTSN,
-
-	GPIO0C6_SHIFT           = 12,
-	GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
+	GPIO0C7_MASK	       = GENMASK(15, 14),
+	GPIO0C7_GPIO	       = 0,
+	GPIO0C7_LCDC_D19        = (1 << 14),
+	GPIO0C7_TRACE_D9        = (2 << 14),
+	GPIO0C7_UART1_RTSN      = (3 << 14),
+
+	GPIO0C6_MASK            = GENMASK(13, 12),
 	GPIO0C6_GPIO            = 0,
-	GPIO0C6_LCDC_D18,
-	GPIO0C6_TRACE_D8,
-	GPIO0C6_UART1_CTSN,
+	GPIO0C6_LCDC_D18        = (1 << 12),
+	GPIO0C6_TRACE_D8        = (2 << 12),
+	GPIO0C6_UART1_CTSN      = (3 << 12),
 
-	GPIO0C5_SHIFT           = 10,
-	GPIO0C5_MASK            = 3 << GPIO0C5_SHIFT,
+	GPIO0C5_MASK            = GENMASK(11, 10),
 	GPIO0C5_GPIO            = 0,
-	GPIO0C5_LCDC_D17,
-	GPIO0C5_TRACE_D7,
-	GPIO0C5_UART1_SOUT,
+	GPIO0C5_LCDC_D17        = (1 << 10),
+	GPIO0C5_TRACE_D7        = (2 << 10),
+	GPIO0C5_UART1_SOUT      = (3 << 10),
 
-	GPIO0C4_SHIFT           = 8,
-	GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
+	GPIO0C4_MASK            = GENMASK(9, 8),
 	GPIO0C4_GPIO            = 0,
-	GPIO0C4_LCDC_D16,
-	GPIO0C4_TRACE_D6,
-	GPIO0C4_UART1_SIN,
+	GPIO0C4_LCDC_D16        = (1 << 8),
+	GPIO0C4_TRACE_D6        = (2 << 8),
+	GPIO0C4_UART1_SIN       = (3 << 8),
 
-	GPIO0C3_SHIFT           = 6,
-	GPIO0C3_MASK            = 3 << GPIO0C3_SHIFT,
+	GPIO0C3_MASK            = GENMASK(7, 6),
 	GPIO0C3_GPIO            = 0,
-	GPIO0C3_LCDC_D15,
-	GPIO0C3_TRACE_D5,
-	GPIO0C3_MCU_JTAG_TDO,
+	GPIO0C3_LCDC_D15        = (1 << 6),
+	GPIO0C3_TRACE_D5        = (2 << 6),
+	GPIO0C3_MCU_JTAG_TDO    = (3 << 6),
 
-	GPIO0C2_SHIFT           = 4,
-	GPIO0C2_MASK            = 3 << GPIO0C2_SHIFT,
+	GPIO0C2_MASK            = GENMASK(5, 4),
 	GPIO0C2_GPIO            = 0,
-	GPIO0C2_LCDC_D14,
-	GPIO0C2_TRACE_D4,
-	GPIO0C2_MCU_JTAG_TDI,
+	GPIO0C2_LCDC_D14        = (1 << 4),
+	GPIO0C2_TRACE_D4        = (2 << 4),
+	GPIO0C2_MCU_JTAG_TDI    = (3 << 4),
 
-	GPIO0C1_SHIFT           = 2,
-	GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
+	GPIO0C1_MASK            = GENMASK(3, 2),
 	GPIO0C1_GPIO            = 0,
-	GPIO0C1_LCDC_D13,
-	GPIO0C1_TRACE_D3,
-	GPIO0C1_MCU_JTAG_TRTSN,
+	GPIO0C1_LCDC_D13        = (1 << 2),
+	GPIO0C1_TRACE_D3        = (2 << 2),
+	GPIO0C1_MCU_JTAG_TRTSN  = (3 << 2),
 
-	GPIO0C0_SHIFT           = 0,
-	GPIO0C0_MASK            = 3 << GPIO0C0_SHIFT,
+	GPIO0C0_MASK            = GENMASK(1, 0),
 	GPIO0C0_GPIO            = 0,
-	GPIO0C0_LCDC_D12,
-	GPIO0C0_TRACE_D2,
-	GPIO0C0_MCU_JTAG_TDO,
+	GPIO0C0_LCDC_D12        = (1 << 0),
+	GPIO0C0_TRACE_D2        = (2 << 0),
+	GPIO0C0_MCU_JTAG_TDO    = (3 << 0),
 };
 
 /*GRF_GPIO0D_IOMUX*/
 enum {
-	GPIO0D7_SHIFT           = 14,
-	GPIO0D7_MASK            = 3 << GPIO0D7_SHIFT,
+	GPIO0D7_MASK            = GENMASK(15, 14),
 	GPIO0D7_GPIO            = 0,
-	GPIO0D7_LCDC_DCLK,
-	GPIO0D7_TRACE_CTL,
-	GPIO0D7_PMU_DEBUG5,
+	GPIO0D7_LCDC_DCLK       = (1 << 14),
+	GPIO0D7_TRACE_CTL       = (2 << 14),
+	GPIO0D7_PMU_DEBUG5      = (3 << 14),
 
-	GPIO0D6_SHIFT           = 12,
-	GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
+	GPIO0D6_MASK            = GENMASK(13, 12),
 	GPIO0D6_GPIO            = 0,
-	GPIO0D6_LCDC_DEN,
-	GPIO0D6_TRACE_CLK,
-	GPIO0D6_PMU_DEBUG4,
+	GPIO0D6_LCDC_DEN        = (1 << 12),
+	GPIO0D6_TRACE_CLK       = (2 << 12),
+	GPIO0D6_PMU_DEBUG4      = (3 << 12),
 
-	GPIO0D5_SHIFT           = 10,
-	GPIO0D5_MASK            = 3 << GPIO0D5_SHIFT,
+	GPIO0D5_MASK            = GENMASK(11, 10),
 	GPIO0D5_GPIO            = 0,
-	GPIO0D5_LCDC_VSYNC,
-	GPIO0D5_TRACE_D15,
-	GPIO0D5_PMU_DEBUG3,
+	GPIO0D5_LCDC_VSYNC             = (1 << 10),
+	GPIO0D5_TRACE_D15       = (2 << 10),
+	GPIO0D5_PMU_DEBUG3      = (3 << 10),
 
-	GPIO0D4_SHIFT           = 8,
-	GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
+	GPIO0D4_MASK            = GENMASK(9, 8),
 	GPIO0D4_GPIO            = 0,
-	GPIO0D4_LCDC_HSYNC,
-	GPIO0D4_TRACE_D14,
-	GPIO0D4_PMU_DEBUG2,
+	GPIO0D4_LCDC_HSYNC      = (1 << 8),
+	GPIO0D4_TRACE_D14       = (2 << 8),
+	GPIO0D4_PMU_DEBUG2      = (3 << 8),
 
-	GPIO0D3_SHIFT           = 6,
-	GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
+	GPIO0D3_MASK            = GENMASK(7, 6),
 	GPIO0D3_GPIO            = 0,
-	GPIO0D3_LCDC_D23,
-	GPIO0D3_TRACE_D13,
-	GPIO0D3_UART4_SIN,
+	GPIO0D3_LCDC_D23        = (1 << 6),
+	GPIO0D3_TRACE_D13       = (2 << 6),
+	GPIO0D3_UART4_SIN       = (3 << 6),
 
-	GPIO0D2_SHIFT           = 4,
-	GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
+	GPIO0D2_MASK            = GENMASK(5, 4),
 	GPIO0D2_GPIO            = 0,
-	GPIO0D2_LCDC_D22,
-	GPIO0D2_TRACE_D12,
-	GPIO0D2_UART4_SOUT,
+	GPIO0D2_LCDC_D22        = (1 << 4),
+	GPIO0D2_TRACE_D12       = (2 << 4),
+	GPIO0D2_UART4_SOUT      = (3 << 4),
 
-	GPIO0D1_SHIFT           = 2,
-	GPIO0D1_MASK            = 3 << GPIO0D1_SHIFT,
+	GPIO0D1_MASK            = GENMASK(3, 2),
 	GPIO0D1_GPIO            = 0,
-	GPIO0D1_LCDC_D21,
-	GPIO0D1_TRACE_D11,
-	GPIO0D1_UART4_RTSN,
+	GPIO0D1_LCDC_D21        = (1 << 2),
+	GPIO0D1_TRACE_D11       = (2 << 2),
+	GPIO0D1_UART4_RTSN      = (3 << 2),
 
-	GPIO0D0_SHIFT           = 0,
-	GPIO0D0_MASK            = 3 << GPIO0D0_SHIFT,
+	GPIO0D0_MASK            = GENMASK(1, 0),
 	GPIO0D0_GPIO            = 0,
-	GPIO0D0_LCDC_D20,
-	GPIO0D0_TRACE_D10,
-	GPIO0D0_UART4_CTSN,
+	GPIO0D0_LCDC_D20        = (1 << 0),
+	GPIO0D0_TRACE_D10       = (2 << 0),
+	GPIO0D0_UART4_CTSN      = (3 << 0),
 };
 
 /*GRF_GPIO2A_IOMUX*/
 enum {
-	GPIO2A7_SHIFT           = 14,
-	GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
+	GPIO2A7_MASK            = GENMASK(15, 14),
 	GPIO2A7_GPIO            = 0,
-	GPIO2A7_SDMMC0_D2,
-	GPIO2A7_JTAG_TCK,
+	GPIO2A7_SDMMC0_D2       = (1 << 14),
+	GPIO2A7_JTAG_TCK        = (2 << 14),
 
-	GPIO2A6_SHIFT           = 12,
-	GPIO2A6_MASK            = 3 << GPIO2A6_SHIFT,
+	GPIO2A6_MASK            = GENMASK(13, 12),
 	GPIO2A6_GPIO            = 0,
-	GPIO2A6_SDMMC0_D1,
-	GPIO2A6_UART2_SIN,
+	GPIO2A6_SDMMC0_D1       = (1 << 12),
+	GPIO2A6_UART2_SIN       = (2 << 12),
 
-	GPIO2A5_SHIFT           = 10,
-	GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
+	GPIO2A5_MASK            = GENMASK(11, 10),
 	GPIO2A5_GPIO            = 0,
-	GPIO2A5_SDMMC0_D0,
-	GPIO2A5_UART2_SOUT,
+	GPIO2A5_SDMMC0_D0       = (1 << 10),
+	GPIO2A5_UART2_SOUT      = (2 << 10),
 
-	GPIO2A4_SHIFT           = 8,
-	GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
-	GPIO2A4_GPIO            = 0,
-	GPIO2A4_FLASH_DQS,
-	GPIO2A4_EMMC_CLKO,
+	GPIO2A4_MASK            = GENMASK(9, 8),
+	GPIO2A4_GPIO     = 0,
+	GPIO2A4_FLASH_DQS       = (1 << 8),
+	GPIO2A4_EMMC_CLKOUT     = (2 << 8),
 
-	GPIO2A3_SHIFT           = 6,
-	GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
+	GPIO2A3_MASK            = GENMASK(7, 6),
 	GPIO2A3_GPIO            = 0,
-	GPIO2A3_FLASH_CSN3,
-	GPIO2A3_EMMC_RSTNO,
+	GPIO2A3_FLASH_CSN3      = (1 << 6),
+	GPIO2A3_EMMC_RSTNOUT    = (2 << 6),
 
-	GPIO2A2_SHIFT           = 4,
-	GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
-	GPIO2A2_GPIO           = 0,
-	GPIO2A2_FLASH_CSN2,
+	GPIO2A2_MASK            = GENMASK(5, 4),
+	GPIO2A2_GPIO            = 0,
+	GPIO2A2_FLASH_CSN2      = (1 << 4),
 
-	GPIO2A1_SHIFT           = 2,
-	GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
+	GPIO2A1_MASK            = GENMASK(3, 2),
 	GPIO2A1_GPIO            = 0,
-	GPIO2A1_FLASH_CSN1,
+	GPIO2A1_FLASH_CSN1      = (1 << 2),
 
-	GPIO2A0_SHIFT           = 0,
-	GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
+	GPIO2A0_MASK            = GENMASK(1, 0),
 	GPIO2A0_GPIO            = 0,
-	GPIO2A0_FLASH_CSN0,
+	GPIO2A0_FLASH_CSN0      = (1 << 0),
 };
 
 /*GRF_GPIO2D_IOMUX*/
 enum {
-	GPIO2D7_SHIFT           = 14,
-	GPIO2D7_MASK            = 3 << GPIO2D7_SHIFT,
+	GPIO2D7_MASK            = GENMASK(15, 14),
 	GPIO2D7_GPIO            = 0,
-	GPIO2D7_SDIO0_D3,
+	GPIO2D7_SDIO0_D3        = (1 << 14),
 
-	GPIO2D6_SHIFT           = 12,
-	GPIO2D6_MASK            = 3 << GPIO2D6_SHIFT,
+	GPIO2D6_MASK            = GENMASK(13, 12),
 	GPIO2D6_GPIO            = 0,
-	GPIO2D6_SDIO0_D2,
+	GPIO2D6_SDIO0_D2        = (1 << 12),
 
-	GPIO2D5_SHIFT           = 10,
-	GPIO2D5_MASK            = 3 << GPIO2D5_SHIFT,
+	GPIO2D5_MASK            = GENMASK(11, 10),
 	GPIO2D5_GPIO            = 0,
-	GPIO2D5_SDIO0_D1,
+	GPIO2D5_SDIO0_D1        = (1 << 10),
 
-	GPIO2D4_SHIFT           = 8,
-	GPIO2D4_MASK            = 3 << GPIO2D4_SHIFT,
+	GPIO2D4_MASK            = GENMASK(9, 8),
 	GPIO2D4_GPIO            = 0,
-	GPIO2D4_SDIO0_D0,
+	GPIO2D4_SDIO0_D0        = (1 << 8),
 
-	GPIO2D3_SHIFT           = 6,
-	GPIO2D3_MASK            = 3 << GPIO2D3_SHIFT,
+	GPIO2D3_MASK            = GENMASK(7, 6),
 	GPIO2D3_GPIO            = 0,
-	GPIO2D3_UART0_RTS0,
+	GPIO2D3_UART0_RTS0      = (1 << 6),
 
-	GPIO2D2_SHIFT           = 4,
-	GPIO2D2_MASK            = 3 << GPIO2D2_SHIFT,
+	GPIO2D2_MASK            = GENMASK(5, 4),
 	GPIO2D2_GPIO            = 0,
-	GPIO2D2_UART0_CTS0,
+	GPIO2D2_UART0_CTS0      = (1 << 4),
 
-	GPIO2D1_SHIFT           = 2,
-	GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
+	GPIO2D1_MASK            = GENMASK(3, 2),
 	GPIO2D1_GPIO            = 0,
-	GPIO2D1_UART0_SOUT,
+	GPIO2D1_UART0_SOUT      = (1 << 2),
 
-	GPIO2D0_SHIFT           = 0,
-	GPIO2D0_MASK            = 3 << GPIO2D0_SHIFT,
+	GPIO2D0_MASK            = GENMASK(1, 0),
 	GPIO2D0_GPIO            = 0,
-	GPIO2D0_UART0_SIN,
+	GPIO2D0_UART0_SIN       = (1 << 0),
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+	GPIO1C7_MASK            = GENMASK(15, 14),
+	GPIO1C7_GPIO            = 0,
+	GPIO1C7_EMMC_DATA5      = (2 << 14),
+
+	GPIO1C6_MASK            = GENMASK(13, 12),
+	GPIO1C6_GPIO            = 0,
+	GPIO1C6_EMMC_DATA4      = (2 << 12),
+
+	GPIO1C5_MASK            = GENMASK(11, 10),
+	GPIO1C5_GPIO            = 0,
+	GPIO1C5_EMMC_DATA3      = (2 << 10),
+
+	GPIO1C4_MASK            = GENMASK(9, 8),
+	GPIO1C4_GPIO            = 0,
+	GPIO1C4_EMMC_DATA2      = (2 << 8),
+
+	GPIO1C3_MASK            = GENMASK(7, 6),
+	GPIO1C3_GPIO            = 0,
+	GPIO1C3_EMMC_DATA1      = (2 << 6),
+
+	GPIO1C2_MASK            = GENMASK(5, 4),
+	GPIO1C2_GPIO            = 0,
+	GPIO1C2_EMMC_DATA0      = (2 << 4),
+};
+
+/* GRF_GPIO1D_IOMUX*/
+enum {
+	GPIO1D3_MASK            = GENMASK(7, 6),
+	GPIO1D3_GPIO            = 0,
+	GPIO1D3_EMMC_PWREN      = (2 << 6),
+
+	GPIO1D2_MASK            = GENMASK(5, 4),
+	GPIO1D2_GPIO            = 0,
+	GPIO1D2_EMMC_CMD        = (2 << 4),
+
+	GPIO1D1_MASK            = GENMASK(3, 2),
+	GPIO1D1_GPIO            = 0,
+	GPIO1D1_EMMC_DATA7      = (2 << 2),
+
+	GPIO1D0_MASK            = GENMASK(1, 0),
+	GPIO1D0_GPIO            = 0,
+	GPIO1D0_EMMC_DATA6      = (2 << 0),
+};
+
+
+/*GRF_GPIO3B_IOMUX*/
+enum {
+	GPIO3B7_MASK            = GENMASK(15, 14),
+	GPIO3B7_GPIO            = 0,
+	GPIO3B7_MAC_RXD0        = (1 << 14),
+
+	GPIO3B6_MASK            = GENMASK(13, 12),
+	GPIO3B6_GPIO            = 0,
+	GPIO3B6_MAC_TXD3        = (1 << 12),
+
+	GPIO3B5_MASK            = GENMASK(11, 10),
+	GPIO3B5_GPIO            = 0,
+	GPIO3B5_MAC_TXEN        = (1 << 10),
+
+	GPIO3B4_MASK            = GENMASK(9, 8),
+	GPIO3B4_GPIO            = 0,
+	GPIO3B4_MAC_COL         = (1 << 8),
+
+	GPIO3B3_MASK            = GENMASK(7, 6),
+	GPIO3B3_GPIO            = 0,
+	GPIO3B3_MAC_CRS         = (1 << 6),
+
+	GPIO3B2_MASK            = GENMASK(5, 4),
+	GPIO3B2_GPIO            = 0,
+	GPIO3B2_MAC_TXD2        = (1 << 4),
+
+	GPIO3B1_MASK            = GENMASK(3, 2),
+	GPIO3B1_GPIO            = 0,
+	GPIO3B1_MAC_TXD1        = (1 << 2),
+
+	GPIO3B0_MASK            = GENMASK(1, 0),
+	GPIO3B0_GPIO            = 0,
+	GPIO3B0_MAC_TXD0        = (1 << 0),
+	GPIO3B0_PWM0            = (2 << 0),
 };
 
 /*GRF_GPIO3C_IOMUX*/
 enum {
-	GPIO3C7_SHIFT           = 14,
-	GPIO3C7_MASK            = 3 << GPIO3C7_SHIFT,
-	GPIO3C7_GPIO            = 0,
-	GPIO3C7_EDPHDMI_CECINOUT,
-	GPIO3C7_ISP_FLASHTRIGIN,
-
-	GPIO3C6_SHIFT           = 12,
-	GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
+	GPIO3C6_MASK            = GENMASK(13, 12),
 	GPIO3C6_GPIO            = 0,
-	GPIO3C6_MAC_CLK,
-	GPIO3C6_ISP_SHUTTERTRIG,
+	GPIO3C6_MAC_CLK         = (1 << 12),
 
-	GPIO3C5_SHIFT           = 10,
-	GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
+	GPIO3C5_MASK            = GENMASK(11, 10),
 	GPIO3C5_GPIO            = 0,
-	GPIO3C5_MAC_RXER,
-	GPIO3C5_ISP_PRELIGHTTRIG,
+	GPIO3C5_MAC_RXEN        = (1 << 10),
 
-	GPIO3C4_SHIFT           = 8,
-	GPIO3C4_MASK            = 3 << GPIO3C4_SHIFT,
+	GPIO3C4_MASK            = GENMASK(9, 8),
 	GPIO3C4_GPIO            = 0,
-	GPIO3C4_MAC_RXDV,
-	GPIO3C4_ISP_FLASHTRIGOUT,
+	GPIO3C4_MAC_RXDV        = (1 << 8),
 
-	GPIO3C3_SHIFT           = 6,
-	GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
+	GPIO3C3_MASK            = GENMASK(7, 6),
 	GPIO3C3_GPIO            = 0,
-	GPIO3C3_MAC_RXDV,
-	GPIO3C3_EMMC_RSTNO,
+	GPIO3C3_MAC_MDC         = (1 << 6),
 
-	GPIO3C2_SHIFT           = 4,
-	GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
-	GPIO3C2_MAC_MDC            = 0,
-	GPIO3C2_ISP_SHUTTEREN,
+	GPIO3C2_MASK            = GENMASK(5, 4),
+	GPIO3C2_GPIO            = 0,
+	GPIO3C2_MAC_RXD3        = (1 << 4),
 
-	GPIO3C1_SHIFT           = 2,
-	GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
+	GPIO3C1_MASK            = GENMASK(3, 2),
 	GPIO3C1_GPIO            = 0,
-	GPIO3C1_MAC_RXD2,
-	GPIO3C1_UART3_RTSN,
+	GPIO3C1_MAC_RXD2        = (1 << 2),
 
-	GPIO3C0_SHIFT           = 0,
-	GPIO3C0_MASK            = 3 << GPIO3C0_SHIFT,
+	GPIO3C0_MASK            = GENMASK(1, 0),
 	GPIO3C0_GPIO            = 0,
-	GPIO3C0_MAC_RXD1,
-	GPIO3C0_UART3_CTSN,
-	GPIO3C0_GPS_RFCLK,
+	GPIO3C0_MAC_RXD1        = (1 << 0),
 };
 
 /*GRF_GPIO3D_IOMUX*/
 enum {
-	GPIO3D7_SHIFT           = 14,
-	GPIO3D7_MASK            = 3 << GPIO3D7_SHIFT,
-	GPIO3D7_GPIO            = 0,
-	GPIO3D7_SC_VCC18V,
-	GPIO3D7_I2C2_SDA,
-	GPIO3D7_GPUJTAG_TCK,
-
-	GPIO3D6_SHIFT           = 12,
-	GPIO3D6_MASK            = 3 << GPIO3D6_SHIFT,
-	GPIO3D6_GPIO            = 0,
-	GPIO3D6_IR_TX,
-	GPIO3D6_UART3_SOUT,
-	GPIO3D6_PWM3,
-
-	GPIO3D5_SHIFT           = 10,
-	GPIO3D5_MASK            = 3 << GPIO3D5_SHIFT,
-	GPIO3D5_GPIO            = 0,
-	GPIO3D5_IR_RX,
-	GPIO3D5_UART3_SIN,
-
-	GPIO3D4_SHIFT           = 8,
-	GPIO3D4_MASK            = 3 << GPIO3D4_SHIFT,
+	GPIO3D4_MASK            = GENMASK(9, 8),
 	GPIO3D4_GPIO            = 0,
-	GPIO3D4_MAC_TXCLKOUT,
-	GPIO3D4_SPI1_CSN1,
-
-	GPIO3D3_SHIFT           = 6,
-	GPIO3D3_MASK            = 3 << GPIO3D3_SHIFT,
-	GPIO3D3_GPIO            = 0,
-	GPIO3D3_HDMII2C_SCL,
-	GPIO3D3_I2C5_SCL,
-
-	GPIO3D2_SHIFT           = 4,
-	GPIO3D2_MASK            = 3 << GPIO3D2_SHIFT,
-	GPIO3D2_GPIO            = 0,
-	GPIO3D2_HDMII2C_SDA,
-	GPIO3D2_I2C5_SDA,
-
-	GPIO3D1_SHIFT           = 2,
-	GPIO3D1_MASK            = 3 << GPIO3D1_SHIFT,
+	GPIO3D4_MAC_TXCLK       = (1 << 8),
+
+	GPIO3D1_MASK            = GENMASK(3, 2),
 	GPIO3D1_GPIO            = 0,
-	GPIO3D1_MAC_RXCLKIN,
-	GPIO3D1_I2C4_SCL,
+	GPIO3D1_MAC_RXCLK       = (1 << 2),
 
-	GPIO3D0_SHIFT           = 0,
-	GPIO3D0_MASK            = 3 << GPIO3D0_SHIFT,
+	GPIO3D0_MASK            = GENMASK(1, 0),
 	GPIO3D0_GPIO            = 0,
-	GPIO3D0_MAC_MDIO,
-	GPIO3D0_I2C4_SDA,
+	GPIO3D0_MAC_MDIO        = (1 << 0),
+};
+
+/* GRF_SOC_CON0 */
+enum {
+	NOC_RSP_ERR_STALL = BIT(9),
+	MOBILE_DDR_SEL = BIT(4),
+	DDR0_16BIT_EN = BIT(3),
+	MSCH0_MAINDDR3_DDR3 = BIT(2),
+	MSCH0_MAINPARTIALPOP = BIT(1),
+	UPCTL_C_ACTIVE = BIT(0),
 };
 
 /*GRF_SOC_CON11/12/13*/
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index bdf0758..c96459f 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -31,8 +31,7 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
 	case PERIPH_ID_UART2:
 		rk_clrsetreg(&grf->gpio2a_iomux,
 			     GPIO2A6_MASK | GPIO2A5_MASK,
-			     GPIO2A6_UART2_SIN << GPIO2A6_SHIFT |
-			     GPIO2A5_UART2_SOUT << GPIO2A5_SHIFT);
+			     GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
 		break;
 	case PERIPH_ID_UART0:
 		break;
@@ -44,10 +43,8 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
 		rk_clrsetreg(&pmugrf->gpio0d_iomux,
 			     GPIO0D0_MASK | GPIO0D1_MASK |
 			     GPIO0D2_MASK | GPIO0D3_MASK,
-			     GPIO0D0_GPIO << GPIO0D0_SHIFT |
-			     GPIO0D1_GPIO << GPIO0D1_SHIFT |
-			     GPIO0D2_UART4_SOUT << GPIO0D2_SHIFT |
-			     GPIO0D3_UART4_SIN << GPIO0D3_SHIFT);
+			     GPIO0D0_GPIO | GPIO0D1_GPIO |
+			     GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
 		break;
 	default:
 		debug("uart id = %d iomux error!\n", uart_id);
-- 
2.1.4

[U-Boot] [PATCH v2 30/56] rockchip: pinctrl: rk3368: add GMAC (RGMII only) support

[Philipp Tomsich]

To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
point), we need support for additional pin-configuration.  This commit
adds the pinctrl support for GMAC in RGMII mode:
 * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
 * configures the RGMII pins

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- removed the RK3368-prefix on bit-definitions for GMAC pinctrl

 drivers/pinctrl/rockchip/pinctrl_rk3368.c | 36 +++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index c96459f..22cd593 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -52,6 +52,33 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
 	}
 }
 
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
+{
+	rk_clrsetreg(&grf->gpio3b_iomux,
+		     GPIO3B0_MASK | GPIO3B1_MASK |
+		     GPIO3B2_MASK | GPIO3B5_MASK |
+		     GPIO3B6_MASK | GPIO3B7_MASK,
+		     GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
+		     GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
+		     GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
+	rk_clrsetreg(&grf->gpio3c_iomux,
+		     GPIO3C0_MASK | GPIO3C1_MASK |
+		     GPIO3C2_MASK | GPIO3C3_MASK |
+		     GPIO3C4_MASK | GPIO3C5_MASK |
+		     GPIO3C6_MASK,
+		     GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
+		     GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
+		     GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
+		     GPIO3C6_MAC_CLK);
+	rk_clrsetreg(&grf->gpio3d_iomux,
+		     GPIO3D0_MASK | GPIO3D1_MASK |
+		     GPIO3D4_MASK,
+		     GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
+		     GPIO3D4_MAC_TXCLK);
+}
+#endif
+
 static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
 {
 	struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
@@ -65,6 +92,11 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
 	case PERIPH_ID_UART4:
 		pinctrl_rk3368_uart_config(priv, func);
 		break;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+	case PERIPH_ID_GMAC:
+		pinctrl_rk3368_gmac_config(priv->grf, func);
+		break;
+#endif
 	default:
 		return -EINVAL;
 	}
@@ -94,6 +126,10 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
 		return PERIPH_ID_UART1;
 	case 55:
 		return PERIPH_ID_UART0;
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+	case 27:
+		return PERIPH_ID_GMAC;
+#endif
 	}
 
 	return -ENOENT;
-- 
2.1.4

[U-Boot] [PATCH v2 31/56] rockchip: pinctrl: rk3368: add support for configuring the MMC pins

[Philipp Tomsich]

The RK3368 has two SD/MMC controllers that can be used from U-Boot
both during SPL and for booting an OS from the full bootloader stage.
While both are configured to (mostly) sensible settings from the BROM,
additional configuration for the MMC controller is needed to configure
it to 8bit mode.

This adds pinctrl support for the MMC controller.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- removed the RK3368 prefix on the SD/MMC pin definitions

 drivers/pinctrl/rockchip/pinctrl_rk3368.c | 48 +++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index 22cd593..cf2f834 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -79,6 +79,46 @@ static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
 }
 #endif
 
+static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
+{
+	switch (mmc_id) {
+	case PERIPH_ID_EMMC:
+		debug("mmc id = %d setting registers!\n", mmc_id);
+		rk_clrsetreg(&grf->gpio1c_iomux,
+			     GPIO1C2_MASK | GPIO1C3_MASK |
+			     GPIO1C4_MASK | GPIO1C5_MASK |
+			     GPIO1C6_MASK | GPIO1C7_MASK,
+			     GPIO1C2_EMMC_DATA0 |
+			     GPIO1C3_EMMC_DATA1 |
+			     GPIO1C4_EMMC_DATA2 |
+			     GPIO1C5_EMMC_DATA3 |
+			     GPIO1C6_EMMC_DATA4 |
+			     GPIO1C7_EMMC_DATA5);
+		rk_clrsetreg(&grf->gpio1d_iomux,
+			     GPIO1D0_MASK | GPIO1D1_MASK |
+			     GPIO1D2_MASK | GPIO1D3_MASK,
+			     GPIO1D0_EMMC_DATA6 |
+			     GPIO1D1_EMMC_DATA7 |
+			     GPIO1D2_EMMC_CMD |
+			     GPIO1D3_EMMC_PWREN);
+		rk_clrsetreg(&grf->gpio2a_iomux,
+			     GPIO2A3_MASK | GPIO2A4_MASK,
+			     GPIO2A3_EMMC_RSTNOUT |
+			     GPIO2A4_EMMC_CLKOUT);
+		break;
+	case PERIPH_ID_SDCARD:
+		/*
+		 * We assume that the BROM has already set this up
+		 * correctly for us and that there's nothing to do
+		 * here.
+		 */
+		break;
+	default:
+		debug("mmc id = %d iomux error!\n", mmc_id);
+		break;
+	}
+}
+
 static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
 {
 	struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
@@ -92,6 +132,10 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
 	case PERIPH_ID_UART4:
 		pinctrl_rk3368_uart_config(priv, func);
 		break;
+	case PERIPH_ID_EMMC:
+	case PERIPH_ID_SDCARD:
+		pinctrl_rk3368_sdmmc_config(priv->grf, func);
+		break;
 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 	case PERIPH_ID_GMAC:
 		pinctrl_rk3368_gmac_config(priv->grf, func);
@@ -126,6 +170,10 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
 		return PERIPH_ID_UART1;
 	case 55:
 		return PERIPH_ID_UART0;
+	case 35:
+		return PERIPH_ID_EMMC;
+	case 32:
+		return PERIPH_ID_SDCARD;
 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 	case 27:
 		return PERIPH_ID_GMAC;
-- 
2.1.4

[U-Boot] [PATCH v2 32/56] rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver

[Philipp Tomsich]

There is no real reason to keep the bit-definitions for the IOMUX in
the grf header file (which defines the register layout of the GRF block):
these should only be used by our pinctrl driver (with the possible
exception of early debug-init code in TPL/SPL).

This moves the relevant definitions from the grf_rk3368.h header
into the pinctrl driver pinctrl_rk3368.c.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

- moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX
  definitions) to the rk3368 pinctrl driver implementation

---

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 316 -----------------------
 drivers/pinctrl/rockchip/pinctrl_rk3368.c       | 325 ++++++++++++++++++++++++
 2 files changed, 325 insertions(+), 316 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index 1966960..ec42d7a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -100,322 +100,6 @@ struct rk3368_pmu_grf {
 check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
 check_member(rk3368_pmu_grf, os_reg[0], 0x200);
 
-/*GRF_GPIO0C_IOMUX*/
-enum {
-	GPIO0C7_MASK	       = GENMASK(15, 14),
-	GPIO0C7_GPIO	       = 0,
-	GPIO0C7_LCDC_D19        = (1 << 14),
-	GPIO0C7_TRACE_D9        = (2 << 14),
-	GPIO0C7_UART1_RTSN      = (3 << 14),
-
-	GPIO0C6_MASK            = GENMASK(13, 12),
-	GPIO0C6_GPIO            = 0,
-	GPIO0C6_LCDC_D18        = (1 << 12),
-	GPIO0C6_TRACE_D8        = (2 << 12),
-	GPIO0C6_UART1_CTSN      = (3 << 12),
-
-	GPIO0C5_MASK            = GENMASK(11, 10),
-	GPIO0C5_GPIO            = 0,
-	GPIO0C5_LCDC_D17        = (1 << 10),
-	GPIO0C5_TRACE_D7        = (2 << 10),
-	GPIO0C5_UART1_SOUT      = (3 << 10),
-
-	GPIO0C4_MASK            = GENMASK(9, 8),
-	GPIO0C4_GPIO            = 0,
-	GPIO0C4_LCDC_D16        = (1 << 8),
-	GPIO0C4_TRACE_D6        = (2 << 8),
-	GPIO0C4_UART1_SIN       = (3 << 8),
-
-	GPIO0C3_MASK            = GENMASK(7, 6),
-	GPIO0C3_GPIO            = 0,
-	GPIO0C3_LCDC_D15        = (1 << 6),
-	GPIO0C3_TRACE_D5        = (2 << 6),
-	GPIO0C3_MCU_JTAG_TDO    = (3 << 6),
-
-	GPIO0C2_MASK            = GENMASK(5, 4),
-	GPIO0C2_GPIO            = 0,
-	GPIO0C2_LCDC_D14        = (1 << 4),
-	GPIO0C2_TRACE_D4        = (2 << 4),
-	GPIO0C2_MCU_JTAG_TDI    = (3 << 4),
-
-	GPIO0C1_MASK            = GENMASK(3, 2),
-	GPIO0C1_GPIO            = 0,
-	GPIO0C1_LCDC_D13        = (1 << 2),
-	GPIO0C1_TRACE_D3        = (2 << 2),
-	GPIO0C1_MCU_JTAG_TRTSN  = (3 << 2),
-
-	GPIO0C0_MASK            = GENMASK(1, 0),
-	GPIO0C0_GPIO            = 0,
-	GPIO0C0_LCDC_D12        = (1 << 0),
-	GPIO0C0_TRACE_D2        = (2 << 0),
-	GPIO0C0_MCU_JTAG_TDO    = (3 << 0),
-};
-
-/*GRF_GPIO0D_IOMUX*/
-enum {
-	GPIO0D7_MASK            = GENMASK(15, 14),
-	GPIO0D7_GPIO            = 0,
-	GPIO0D7_LCDC_DCLK       = (1 << 14),
-	GPIO0D7_TRACE_CTL       = (2 << 14),
-	GPIO0D7_PMU_DEBUG5      = (3 << 14),
-
-	GPIO0D6_MASK            = GENMASK(13, 12),
-	GPIO0D6_GPIO            = 0,
-	GPIO0D6_LCDC_DEN        = (1 << 12),
-	GPIO0D6_TRACE_CLK       = (2 << 12),
-	GPIO0D6_PMU_DEBUG4      = (3 << 12),
-
-	GPIO0D5_MASK            = GENMASK(11, 10),
-	GPIO0D5_GPIO            = 0,
-	GPIO0D5_LCDC_VSYNC             = (1 << 10),
-	GPIO0D5_TRACE_D15       = (2 << 10),
-	GPIO0D5_PMU_DEBUG3      = (3 << 10),
-
-	GPIO0D4_MASK            = GENMASK(9, 8),
-	GPIO0D4_GPIO            = 0,
-	GPIO0D4_LCDC_HSYNC      = (1 << 8),
-	GPIO0D4_TRACE_D14       = (2 << 8),
-	GPIO0D4_PMU_DEBUG2      = (3 << 8),
-
-	GPIO0D3_MASK            = GENMASK(7, 6),
-	GPIO0D3_GPIO            = 0,
-	GPIO0D3_LCDC_D23        = (1 << 6),
-	GPIO0D3_TRACE_D13       = (2 << 6),
-	GPIO0D3_UART4_SIN       = (3 << 6),
-
-	GPIO0D2_MASK            = GENMASK(5, 4),
-	GPIO0D2_GPIO            = 0,
-	GPIO0D2_LCDC_D22        = (1 << 4),
-	GPIO0D2_TRACE_D12       = (2 << 4),
-	GPIO0D2_UART4_SOUT      = (3 << 4),
-
-	GPIO0D1_MASK            = GENMASK(3, 2),
-	GPIO0D1_GPIO            = 0,
-	GPIO0D1_LCDC_D21        = (1 << 2),
-	GPIO0D1_TRACE_D11       = (2 << 2),
-	GPIO0D1_UART4_RTSN      = (3 << 2),
-
-	GPIO0D0_MASK            = GENMASK(1, 0),
-	GPIO0D0_GPIO            = 0,
-	GPIO0D0_LCDC_D20        = (1 << 0),
-	GPIO0D0_TRACE_D10       = (2 << 0),
-	GPIO0D0_UART4_CTSN      = (3 << 0),
-};
-
-/*GRF_GPIO2A_IOMUX*/
-enum {
-	GPIO2A7_MASK            = GENMASK(15, 14),
-	GPIO2A7_GPIO            = 0,
-	GPIO2A7_SDMMC0_D2       = (1 << 14),
-	GPIO2A7_JTAG_TCK        = (2 << 14),
-
-	GPIO2A6_MASK            = GENMASK(13, 12),
-	GPIO2A6_GPIO            = 0,
-	GPIO2A6_SDMMC0_D1       = (1 << 12),
-	GPIO2A6_UART2_SIN       = (2 << 12),
-
-	GPIO2A5_MASK            = GENMASK(11, 10),
-	GPIO2A5_GPIO            = 0,
-	GPIO2A5_SDMMC0_D0       = (1 << 10),
-	GPIO2A5_UART2_SOUT      = (2 << 10),
-
-	GPIO2A4_MASK            = GENMASK(9, 8),
-	GPIO2A4_GPIO     = 0,
-	GPIO2A4_FLASH_DQS       = (1 << 8),
-	GPIO2A4_EMMC_CLKOUT     = (2 << 8),
-
-	GPIO2A3_MASK            = GENMASK(7, 6),
-	GPIO2A3_GPIO            = 0,
-	GPIO2A3_FLASH_CSN3      = (1 << 6),
-	GPIO2A3_EMMC_RSTNOUT    = (2 << 6),
-
-	GPIO2A2_MASK            = GENMASK(5, 4),
-	GPIO2A2_GPIO            = 0,
-	GPIO2A2_FLASH_CSN2      = (1 << 4),
-
-	GPIO2A1_MASK            = GENMASK(3, 2),
-	GPIO2A1_GPIO            = 0,
-	GPIO2A1_FLASH_CSN1      = (1 << 2),
-
-	GPIO2A0_MASK            = GENMASK(1, 0),
-	GPIO2A0_GPIO            = 0,
-	GPIO2A0_FLASH_CSN0      = (1 << 0),
-};
-
-/*GRF_GPIO2D_IOMUX*/
-enum {
-	GPIO2D7_MASK            = GENMASK(15, 14),
-	GPIO2D7_GPIO            = 0,
-	GPIO2D7_SDIO0_D3        = (1 << 14),
-
-	GPIO2D6_MASK            = GENMASK(13, 12),
-	GPIO2D6_GPIO            = 0,
-	GPIO2D6_SDIO0_D2        = (1 << 12),
-
-	GPIO2D5_MASK            = GENMASK(11, 10),
-	GPIO2D5_GPIO            = 0,
-	GPIO2D5_SDIO0_D1        = (1 << 10),
-
-	GPIO2D4_MASK            = GENMASK(9, 8),
-	GPIO2D4_GPIO            = 0,
-	GPIO2D4_SDIO0_D0        = (1 << 8),
-
-	GPIO2D3_MASK            = GENMASK(7, 6),
-	GPIO2D3_GPIO            = 0,
-	GPIO2D3_UART0_RTS0      = (1 << 6),
-
-	GPIO2D2_MASK            = GENMASK(5, 4),
-	GPIO2D2_GPIO            = 0,
-	GPIO2D2_UART0_CTS0      = (1 << 4),
-
-	GPIO2D1_MASK            = GENMASK(3, 2),
-	GPIO2D1_GPIO            = 0,
-	GPIO2D1_UART0_SOUT      = (1 << 2),
-
-	GPIO2D0_MASK            = GENMASK(1, 0),
-	GPIO2D0_GPIO            = 0,
-	GPIO2D0_UART0_SIN       = (1 << 0),
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
-	GPIO1C7_MASK            = GENMASK(15, 14),
-	GPIO1C7_GPIO            = 0,
-	GPIO1C7_EMMC_DATA5      = (2 << 14),
-
-	GPIO1C6_MASK            = GENMASK(13, 12),
-	GPIO1C6_GPIO            = 0,
-	GPIO1C6_EMMC_DATA4      = (2 << 12),
-
-	GPIO1C5_MASK            = GENMASK(11, 10),
-	GPIO1C5_GPIO            = 0,
-	GPIO1C5_EMMC_DATA3      = (2 << 10),
-
-	GPIO1C4_MASK            = GENMASK(9, 8),
-	GPIO1C4_GPIO            = 0,
-	GPIO1C4_EMMC_DATA2      = (2 << 8),
-
-	GPIO1C3_MASK            = GENMASK(7, 6),
-	GPIO1C3_GPIO            = 0,
-	GPIO1C3_EMMC_DATA1      = (2 << 6),
-
-	GPIO1C2_MASK            = GENMASK(5, 4),
-	GPIO1C2_GPIO            = 0,
-	GPIO1C2_EMMC_DATA0      = (2 << 4),
-};
-
-/* GRF_GPIO1D_IOMUX*/
-enum {
-	GPIO1D3_MASK            = GENMASK(7, 6),
-	GPIO1D3_GPIO            = 0,
-	GPIO1D3_EMMC_PWREN      = (2 << 6),
-
-	GPIO1D2_MASK            = GENMASK(5, 4),
-	GPIO1D2_GPIO            = 0,
-	GPIO1D2_EMMC_CMD        = (2 << 4),
-
-	GPIO1D1_MASK            = GENMASK(3, 2),
-	GPIO1D1_GPIO            = 0,
-	GPIO1D1_EMMC_DATA7      = (2 << 2),
-
-	GPIO1D0_MASK            = GENMASK(1, 0),
-	GPIO1D0_GPIO            = 0,
-	GPIO1D0_EMMC_DATA6      = (2 << 0),
-};
-
-
-/*GRF_GPIO3B_IOMUX*/
-enum {
-	GPIO3B7_MASK            = GENMASK(15, 14),
-	GPIO3B7_GPIO            = 0,
-	GPIO3B7_MAC_RXD0        = (1 << 14),
-
-	GPIO3B6_MASK            = GENMASK(13, 12),
-	GPIO3B6_GPIO            = 0,
-	GPIO3B6_MAC_TXD3        = (1 << 12),
-
-	GPIO3B5_MASK            = GENMASK(11, 10),
-	GPIO3B5_GPIO            = 0,
-	GPIO3B5_MAC_TXEN        = (1 << 10),
-
-	GPIO3B4_MASK            = GENMASK(9, 8),
-	GPIO3B4_GPIO            = 0,
-	GPIO3B4_MAC_COL         = (1 << 8),
-
-	GPIO3B3_MASK            = GENMASK(7, 6),
-	GPIO3B3_GPIO            = 0,
-	GPIO3B3_MAC_CRS         = (1 << 6),
-
-	GPIO3B2_MASK            = GENMASK(5, 4),
-	GPIO3B2_GPIO            = 0,
-	GPIO3B2_MAC_TXD2        = (1 << 4),
-
-	GPIO3B1_MASK            = GENMASK(3, 2),
-	GPIO3B1_GPIO            = 0,
-	GPIO3B1_MAC_TXD1        = (1 << 2),
-
-	GPIO3B0_MASK            = GENMASK(1, 0),
-	GPIO3B0_GPIO            = 0,
-	GPIO3B0_MAC_TXD0        = (1 << 0),
-	GPIO3B0_PWM0            = (2 << 0),
-};
-
-/*GRF_GPIO3C_IOMUX*/
-enum {
-	GPIO3C6_MASK            = GENMASK(13, 12),
-	GPIO3C6_GPIO            = 0,
-	GPIO3C6_MAC_CLK         = (1 << 12),
-
-	GPIO3C5_MASK            = GENMASK(11, 10),
-	GPIO3C5_GPIO            = 0,
-	GPIO3C5_MAC_RXEN        = (1 << 10),
-
-	GPIO3C4_MASK            = GENMASK(9, 8),
-	GPIO3C4_GPIO            = 0,
-	GPIO3C4_MAC_RXDV        = (1 << 8),
-
-	GPIO3C3_MASK            = GENMASK(7, 6),
-	GPIO3C3_GPIO            = 0,
-	GPIO3C3_MAC_MDC         = (1 << 6),
-
-	GPIO3C2_MASK            = GENMASK(5, 4),
-	GPIO3C2_GPIO            = 0,
-	GPIO3C2_MAC_RXD3        = (1 << 4),
-
-	GPIO3C1_MASK            = GENMASK(3, 2),
-	GPIO3C1_GPIO            = 0,
-	GPIO3C1_MAC_RXD2        = (1 << 2),
-
-	GPIO3C0_MASK            = GENMASK(1, 0),
-	GPIO3C0_GPIO            = 0,
-	GPIO3C0_MAC_RXD1        = (1 << 0),
-};
-
-/*GRF_GPIO3D_IOMUX*/
-enum {
-	GPIO3D4_MASK            = GENMASK(9, 8),
-	GPIO3D4_GPIO            = 0,
-	GPIO3D4_MAC_TXCLK       = (1 << 8),
-
-	GPIO3D1_MASK            = GENMASK(3, 2),
-	GPIO3D1_GPIO            = 0,
-	GPIO3D1_MAC_RXCLK       = (1 << 2),
-
-	GPIO3D0_MASK            = GENMASK(1, 0),
-	GPIO3D0_GPIO            = 0,
-	GPIO3D0_MAC_MDIO        = (1 << 0),
-};
-
-/* GRF_SOC_CON0 */
-enum {
-	NOC_RSP_ERR_STALL = BIT(9),
-	MOBILE_DDR_SEL = BIT(4),
-	DDR0_16BIT_EN = BIT(3),
-	MSCH0_MAINDDR3_DDR3 = BIT(2),
-	MSCH0_MAINPARTIALPOP = BIT(1),
-	UPCTL_C_ACTIVE = BIT(0),
-};
-
 /*GRF_SOC_CON11/12/13*/
 enum {
 	MCU_SRAM_BASE_BIT27_BIT12_SHIFT	= 0,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index cf2f834..67695ab 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -16,6 +16,331 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/*GRF_GPIO0C_IOMUX*/
+enum {
+	GPIO0C7_MASK	       = GENMASK(15, 14),
+	GPIO0C7_GPIO	       = 0,
+	GPIO0C7_LCDC_D19        = (1 << 14),
+	GPIO0C7_TRACE_D9        = (2 << 14),
+	GPIO0C7_UART1_RTSN      = (3 << 14),
+
+	GPIO0C6_MASK            = GENMASK(13, 12),
+	GPIO0C6_GPIO            = 0,
+	GPIO0C6_LCDC_D18        = (1 << 12),
+	GPIO0C6_TRACE_D8        = (2 << 12),
+	GPIO0C6_UART1_CTSN      = (3 << 12),
+
+	GPIO0C5_MASK            = GENMASK(11, 10),
+	GPIO0C5_GPIO            = 0,
+	GPIO0C5_LCDC_D17        = (1 << 10),
+	GPIO0C5_TRACE_D7        = (2 << 10),
+	GPIO0C5_UART1_SOUT      = (3 << 10),
+
+	GPIO0C4_MASK            = GENMASK(9, 8),
+	GPIO0C4_GPIO            = 0,
+	GPIO0C4_LCDC_D16        = (1 << 8),
+	GPIO0C4_TRACE_D6        = (2 << 8),
+	GPIO0C4_UART1_SIN       = (3 << 8),
+
+	GPIO0C3_MASK            = GENMASK(7, 6),
+	GPIO0C3_GPIO            = 0,
+	GPIO0C3_LCDC_D15        = (1 << 6),
+	GPIO0C3_TRACE_D5        = (2 << 6),
+	GPIO0C3_MCU_JTAG_TDO    = (3 << 6),
+
+	GPIO0C2_MASK            = GENMASK(5, 4),
+	GPIO0C2_GPIO            = 0,
+	GPIO0C2_LCDC_D14        = (1 << 4),
+	GPIO0C2_TRACE_D4        = (2 << 4),
+	GPIO0C2_MCU_JTAG_TDI    = (3 << 4),
+
+	GPIO0C1_MASK            = GENMASK(3, 2),
+	GPIO0C1_GPIO            = 0,
+	GPIO0C1_LCDC_D13        = (1 << 2),
+	GPIO0C1_TRACE_D3        = (2 << 2),
+	GPIO0C1_MCU_JTAG_TRTSN  = (3 << 2),
+
+	GPIO0C0_MASK            = GENMASK(1, 0),
+	GPIO0C0_GPIO            = 0,
+	GPIO0C0_LCDC_D12        = (1 << 0),
+	GPIO0C0_TRACE_D2        = (2 << 0),
+	GPIO0C0_MCU_JTAG_TDO    = (3 << 0),
+};
+
+/*GRF_GPIO0D_IOMUX*/
+enum {
+	GPIO0D7_MASK            = GENMASK(15, 14),
+	GPIO0D7_GPIO            = 0,
+	GPIO0D7_LCDC_DCLK       = (1 << 14),
+	GPIO0D7_TRACE_CTL       = (2 << 14),
+	GPIO0D7_PMU_DEBUG5      = (3 << 14),
+
+	GPIO0D6_MASK            = GENMASK(13, 12),
+	GPIO0D6_GPIO            = 0,
+	GPIO0D6_LCDC_DEN        = (1 << 12),
+	GPIO0D6_TRACE_CLK       = (2 << 12),
+	GPIO0D6_PMU_DEBUG4      = (3 << 12),
+
+	GPIO0D5_MASK            = GENMASK(11, 10),
+	GPIO0D5_GPIO            = 0,
+	GPIO0D5_LCDC_VSYNC             = (1 << 10),
+	GPIO0D5_TRACE_D15       = (2 << 10),
+	GPIO0D5_PMU_DEBUG3      = (3 << 10),
+
+	GPIO0D4_MASK            = GENMASK(9, 8),
+	GPIO0D4_GPIO            = 0,
+	GPIO0D4_LCDC_HSYNC      = (1 << 8),
+	GPIO0D4_TRACE_D14       = (2 << 8),
+	GPIO0D4_PMU_DEBUG2      = (3 << 8),
+
+	GPIO0D3_MASK            = GENMASK(7, 6),
+	GPIO0D3_GPIO            = 0,
+	GPIO0D3_LCDC_D23        = (1 << 6),
+	GPIO0D3_TRACE_D13       = (2 << 6),
+	GPIO0D3_UART4_SIN       = (3 << 6),
+
+	GPIO0D2_MASK            = GENMASK(5, 4),
+	GPIO0D2_GPIO            = 0,
+	GPIO0D2_LCDC_D22        = (1 << 4),
+	GPIO0D2_TRACE_D12       = (2 << 4),
+	GPIO0D2_UART4_SOUT      = (3 << 4),
+
+	GPIO0D1_MASK            = GENMASK(3, 2),
+	GPIO0D1_GPIO            = 0,
+	GPIO0D1_LCDC_D21        = (1 << 2),
+	GPIO0D1_TRACE_D11       = (2 << 2),
+	GPIO0D1_UART4_RTSN      = (3 << 2),
+
+	GPIO0D0_MASK            = GENMASK(1, 0),
+	GPIO0D0_GPIO            = 0,
+	GPIO0D0_LCDC_D20        = (1 << 0),
+	GPIO0D0_TRACE_D10       = (2 << 0),
+	GPIO0D0_UART4_CTSN      = (3 << 0),
+};
+
+/*GRF_GPIO2A_IOMUX*/
+enum {
+	GPIO2A7_MASK            = GENMASK(15, 14),
+	GPIO2A7_GPIO            = 0,
+	GPIO2A7_SDMMC0_D2       = (1 << 14),
+	GPIO2A7_JTAG_TCK        = (2 << 14),
+
+	GPIO2A6_MASK            = GENMASK(13, 12),
+	GPIO2A6_GPIO            = 0,
+	GPIO2A6_SDMMC0_D1       = (1 << 12),
+	GPIO2A6_UART2_SIN       = (2 << 12),
+
+	GPIO2A5_MASK            = GENMASK(11, 10),
+	GPIO2A5_GPIO            = 0,
+	GPIO2A5_SDMMC0_D0       = (1 << 10),
+	GPIO2A5_UART2_SOUT      = (2 << 10),
+
+	GPIO2A4_MASK            = GENMASK(9, 8),
+	GPIO2A4_GPIO     = 0,
+	GPIO2A4_FLASH_DQS       = (1 << 8),
+	GPIO2A4_EMMC_CLKOUT     = (2 << 8),
+
+	GPIO2A3_MASK            = GENMASK(7, 6),
+	GPIO2A3_GPIO            = 0,
+	GPIO2A3_FLASH_CSN3      = (1 << 6),
+	GPIO2A3_EMMC_RSTNOUT    = (2 << 6),
+
+	GPIO2A2_MASK            = GENMASK(5, 4),
+	GPIO2A2_GPIO            = 0,
+	GPIO2A2_FLASH_CSN2      = (1 << 4),
+
+	GPIO2A1_MASK            = GENMASK(3, 2),
+	GPIO2A1_GPIO            = 0,
+	GPIO2A1_FLASH_CSN1      = (1 << 2),
+
+	GPIO2A0_MASK            = GENMASK(1, 0),
+	GPIO2A0_GPIO            = 0,
+	GPIO2A0_FLASH_CSN0      = (1 << 0),
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+	GPIO2D7_MASK            = GENMASK(15, 14),
+	GPIO2D7_GPIO            = 0,
+	GPIO2D7_SDIO0_D3        = (1 << 14),
+
+	GPIO2D6_MASK            = GENMASK(13, 12),
+	GPIO2D6_GPIO            = 0,
+	GPIO2D6_SDIO0_D2        = (1 << 12),
+
+	GPIO2D5_MASK            = GENMASK(11, 10),
+	GPIO2D5_GPIO            = 0,
+	GPIO2D5_SDIO0_D1        = (1 << 10),
+
+	GPIO2D4_MASK            = GENMASK(9, 8),
+	GPIO2D4_GPIO            = 0,
+	GPIO2D4_SDIO0_D0        = (1 << 8),
+
+	GPIO2D3_MASK            = GENMASK(7, 6),
+	GPIO2D3_GPIO            = 0,
+	GPIO2D3_UART0_RTS0      = (1 << 6),
+
+	GPIO2D2_MASK            = GENMASK(5, 4),
+	GPIO2D2_GPIO            = 0,
+	GPIO2D2_UART0_CTS0      = (1 << 4),
+
+	GPIO2D1_MASK            = GENMASK(3, 2),
+	GPIO2D1_GPIO            = 0,
+	GPIO2D1_UART0_SOUT      = (1 << 2),
+
+	GPIO2D0_MASK            = GENMASK(1, 0),
+	GPIO2D0_GPIO            = 0,
+	GPIO2D0_UART0_SIN       = (1 << 0),
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+	GPIO1B7_MASK            = GENMASK(15, 14),
+	GPIO1B7_GPIO            = 0,
+	GPIO1B7_SPI1_CSN0       = (2 << 14),
+
+	GPIO1B6_MASK            = GENMASK(13, 12),
+	GPIO1B6_GPIO            = 0,
+	GPIO1B6_SPI1_CLK        = (2 << 12),
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+	GPIO1C7_MASK            = GENMASK(15, 14),
+	GPIO1C7_GPIO            = 0,
+	GPIO1C7_EMMC_DATA5      = (2 << 14),
+
+	GPIO1C6_MASK            = GENMASK(13, 12),
+	GPIO1C6_GPIO            = 0,
+	GPIO1C6_EMMC_DATA4      = (2 << 12),
+
+	GPIO1C5_MASK            = GENMASK(11, 10),
+	GPIO1C5_GPIO            = 0,
+	GPIO1C5_EMMC_DATA3      = (2 << 10),
+
+	GPIO1C4_MASK            = GENMASK(9, 8),
+	GPIO1C4_GPIO            = 0,
+	GPIO1C4_EMMC_DATA2      = (2 << 8),
+
+	GPIO1C3_MASK            = GENMASK(7, 6),
+	GPIO1C3_GPIO            = 0,
+	GPIO1C3_EMMC_DATA1      = (2 << 6),
+
+	GPIO1C2_MASK            = GENMASK(5, 4),
+	GPIO1C2_GPIO            = 0,
+	GPIO1C2_EMMC_DATA0      = (2 << 4),
+
+	GPIO1C1_MASK            = GENMASK(3, 2),
+	GPIO1C1_GPIO            = 0,
+	GPIO1C1_SPI1_RXD        = (2 << 2),
+
+	GPIO1C0_MASK            = GENMASK(1, 0),
+	GPIO1C0_GPIO            = 0,
+	GPIO1C0_SPI1_TXD        = (2 << 0),
+};
+
+/* GRF_GPIO1D_IOMUX*/
+enum {
+	GPIO1D3_MASK            = GENMASK(7, 6),
+	GPIO1D3_GPIO            = 0,
+	GPIO1D3_EMMC_PWREN      = (2 << 6),
+
+	GPIO1D2_MASK            = GENMASK(5, 4),
+	GPIO1D2_GPIO            = 0,
+	GPIO1D2_EMMC_CMD        = (2 << 4),
+
+	GPIO1D1_MASK            = GENMASK(3, 2),
+	GPIO1D1_GPIO            = 0,
+	GPIO1D1_EMMC_DATA7      = (2 << 2),
+
+	GPIO1D0_MASK            = GENMASK(1, 0),
+	GPIO1D0_GPIO            = 0,
+	GPIO1D0_EMMC_DATA6      = (2 << 0),
+};
+
+
+/*GRF_GPIO3B_IOMUX*/
+enum {
+	GPIO3B7_MASK            = GENMASK(15, 14),
+	GPIO3B7_GPIO            = 0,
+	GPIO3B7_MAC_RXD0        = (1 << 14),
+
+	GPIO3B6_MASK            = GENMASK(13, 12),
+	GPIO3B6_GPIO            = 0,
+	GPIO3B6_MAC_TXD3        = (1 << 12),
+
+	GPIO3B5_MASK            = GENMASK(11, 10),
+	GPIO3B5_GPIO            = 0,
+	GPIO3B5_MAC_TXEN        = (1 << 10),
+
+	GPIO3B4_MASK            = GENMASK(9, 8),
+	GPIO3B4_GPIO            = 0,
+	GPIO3B4_MAC_COL         = (1 << 8),
+
+	GPIO3B3_MASK            = GENMASK(7, 6),
+	GPIO3B3_GPIO            = 0,
+	GPIO3B3_MAC_CRS         = (1 << 6),
+
+	GPIO3B2_MASK            = GENMASK(5, 4),
+	GPIO3B2_GPIO            = 0,
+	GPIO3B2_MAC_TXD2        = (1 << 4),
+
+	GPIO3B1_MASK            = GENMASK(3, 2),
+	GPIO3B1_GPIO            = 0,
+	GPIO3B1_MAC_TXD1        = (1 << 2),
+
+	GPIO3B0_MASK            = GENMASK(1, 0),
+	GPIO3B0_GPIO            = 0,
+	GPIO3B0_MAC_TXD0        = (1 << 0),
+	GPIO3B0_PWM0            = (2 << 0),
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+	GPIO3C6_MASK            = GENMASK(13, 12),
+	GPIO3C6_GPIO            = 0,
+	GPIO3C6_MAC_CLK         = (1 << 12),
+
+	GPIO3C5_MASK            = GENMASK(11, 10),
+	GPIO3C5_GPIO            = 0,
+	GPIO3C5_MAC_RXEN        = (1 << 10),
+
+	GPIO3C4_MASK            = GENMASK(9, 8),
+	GPIO3C4_GPIO            = 0,
+	GPIO3C4_MAC_RXDV        = (1 << 8),
+
+	GPIO3C3_MASK            = GENMASK(7, 6),
+	GPIO3C3_GPIO            = 0,
+	GPIO3C3_MAC_MDC         = (1 << 6),
+
+	GPIO3C2_MASK            = GENMASK(5, 4),
+	GPIO3C2_GPIO            = 0,
+	GPIO3C2_MAC_RXD3        = (1 << 4),
+
+	GPIO3C1_MASK            = GENMASK(3, 2),
+	GPIO3C1_GPIO            = 0,
+	GPIO3C1_MAC_RXD2        = (1 << 2),
+
+	GPIO3C0_MASK            = GENMASK(1, 0),
+	GPIO3C0_GPIO            = 0,
+	GPIO3C0_MAC_RXD1        = (1 << 0),
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+	GPIO3D4_MASK            = GENMASK(9, 8),
+	GPIO3D4_GPIO            = 0,
+	GPIO3D4_MAC_TXCLK       = (1 << 8),
+
+	GPIO3D1_MASK            = GENMASK(3, 2),
+	GPIO3D1_GPIO            = 0,
+	GPIO3D1_MAC_RXCLK       = (1 << 2),
+
+	GPIO3D0_MASK            = GENMASK(1, 0),
+	GPIO3D0_GPIO            = 0,
+	GPIO3D0_MAC_MDIO        = (1 << 0),
+};
+
 struct rk3368_pinctrl_priv {
 	struct rk3368_grf *grf;
 	struct rk3368_pmu_grf *pmugrf;
-- 
2.1.4

[U-Boot] [PATCH v2 33/56] rockchip: pinctrl: rk3368: add SPI support

[Philipp Tomsich]

To implement pinctrl support for the RK3368, we need to add the
bit-definitions to configure the IOMUX and tie these into the
pinctrl framework. This also adds the mapping from the IRQ# back
onto the periheral id for the SPI devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/pinctrl/rockchip/pinctrl_rk3368.c | 90 +++++++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
index 67695ab..7a3b7c16 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
@@ -1,8 +1,11 @@
 /*
  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  * Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
+
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
@@ -16,6 +19,25 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* PMUGRF_GPIO0B_IOMUX */
+enum {
+	GPIO0B5_MASK            = GENMASK(11, 10),
+	GPIO0B5_GPIO            = 0,
+	GPIO0B5_SPI2_CSN0       = (2 << 10),
+
+	GPIO0B4_MASK            = GENMASK(9, 8),
+	GPIO0B4_GPIO            = 0,
+	GPIO0B4_SPI2_CLK        = (2 << 8),
+
+	GPIO0B3_MASK            = GENMASK(7, 6),
+	GPIO0B3_GPIO            = 0,
+	GPIO0B3_SPI2_TXD        = (2 << 6),
+
+	GPIO0B2_MASK            = GENMASK(5, 4),
+	GPIO0B2_GPIO            = 0,
+	GPIO0B2_SPI2_RXD        = (2 << 4),
+};
+
 /*GRF_GPIO0C_IOMUX*/
 enum {
 	GPIO0C7_MASK	       = GENMASK(15, 14),
@@ -209,10 +231,12 @@ enum {
 	GPIO1C7_MASK            = GENMASK(15, 14),
 	GPIO1C7_GPIO            = 0,
 	GPIO1C7_EMMC_DATA5      = (2 << 14),
+	GPIO1C7_SPI0_TXD        = (3 << 14),
 
 	GPIO1C6_MASK            = GENMASK(13, 12),
 	GPIO1C6_GPIO            = 0,
 	GPIO1C6_EMMC_DATA4      = (2 << 12),
+	GPIO1C6_SPI0_RXD        = (3 << 12),
 
 	GPIO1C5_MASK            = GENMASK(11, 10),
 	GPIO1C5_GPIO            = 0,
@@ -241,6 +265,10 @@ enum {
 
 /* GRF_GPIO1D_IOMUX*/
 enum {
+	GPIO1D5_MASK            = GENMASK(11, 10),
+	GPIO1D5_GPIO            = 0,
+	GPIO1D5_SPI0_CLK        = (2 << 10),
+
 	GPIO1D3_MASK            = GENMASK(7, 6),
 	GPIO1D3_GPIO            = 0,
 	GPIO1D3_EMMC_PWREN      = (2 << 6),
@@ -252,10 +280,12 @@ enum {
 	GPIO1D1_MASK            = GENMASK(3, 2),
 	GPIO1D1_GPIO            = 0,
 	GPIO1D1_EMMC_DATA7      = (2 << 2),
+	GPIO1D1_SPI0_CSN1       = (3 << 2),
 
 	GPIO1D0_MASK            = GENMASK(1, 0),
 	GPIO1D0_GPIO            = 0,
 	GPIO1D0_EMMC_DATA6      = (2 << 0),
+	GPIO1D0_SPI0_CSN0       = (3 << 0),
 };
 
 
@@ -331,6 +361,7 @@ enum {
 	GPIO3D4_MASK            = GENMASK(9, 8),
 	GPIO3D4_GPIO            = 0,
 	GPIO3D4_MAC_TXCLK       = (1 << 8),
+	GPIO3D4_SPI1_CNS1       = (2 << 8),
 
 	GPIO3D1_MASK            = GENMASK(3, 2),
 	GPIO3D1_GPIO            = 0,
@@ -377,6 +408,54 @@ static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
 	}
 }
 
+static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv,
+				      int spi_id)
+{
+	struct rk3368_grf *grf = priv->grf;
+	struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
+
+	switch (spi_id) {
+	case PERIPH_ID_SPI0:
+		/*
+		 * eMMC can only be connected with 4 bits, when SPI0 is used.
+		 * This is all-or-nothing, so we assume that if someone asks us
+		 * to configure SPI0, that their eMMC interface is unused or
+		 * configured appropriately.
+		 */
+		rk_clrsetreg(&grf->gpio1d_iomux,
+			     GPIO1D0_MASK | GPIO1D1_MASK |
+			     GPIO1D5_MASK,
+			     GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 |
+			     GPIO1D5_SPI0_CLK);
+		rk_clrsetreg(&grf->gpio1c_iomux,
+			     GPIO1C6_MASK | GPIO1C7_MASK,
+			     GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD);
+		break;
+	case PERIPH_ID_SPI1:
+		/*
+		 * We don't implement support for configuring SPI1_CSN#1, as it
+		 * will conflicts with the GMAC (MAC TX clk-out).
+		 */
+		rk_clrsetreg(&grf->gpio1b_iomux,
+			     GPIO1B6_MASK | GPIO1B7_MASK,
+			     GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0);
+		rk_clrsetreg(&grf->gpio1c_iomux,
+			     GPIO1C0_MASK | GPIO1C1_MASK,
+			     GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD);
+		break;
+	case PERIPH_ID_SPI2:
+		rk_clrsetreg(&pmugrf->gpio0b_iomux,
+			     GPIO0B2_MASK | GPIO0B3_MASK |
+			     GPIO0B4_MASK | GPIO0B5_MASK,
+			     GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD |
+			     GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0);
+		break;
+	default:
+		debug("%s: spi id = %d iomux error!\n", __func__, spi_id);
+		break;
+	}
+}
+
 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
 {
@@ -457,6 +536,11 @@ static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
 	case PERIPH_ID_UART4:
 		pinctrl_rk3368_uart_config(priv, func);
 		break;
+	case PERIPH_ID_SPI0:
+	case PERIPH_ID_SPI1:
+	case PERIPH_ID_SPI2:
+		pinctrl_rk3368_spi_config(priv, func);
+		break;
 	case PERIPH_ID_EMMC:
 	case PERIPH_ID_SDCARD:
 		pinctrl_rk3368_sdmmc_config(priv->grf, func);
@@ -495,6 +579,12 @@ static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
 		return PERIPH_ID_UART1;
 	case 55:
 		return PERIPH_ID_UART0;
+	case 44:
+		return PERIPH_ID_SPI0;
+	case 45:
+		return PERIPH_ID_SPI1;
+	case 41:
+		return PERIPH_ID_SPI2;
 	case 35:
 		return PERIPH_ID_EMMC;
 	case 32:
-- 
2.1.4

[U-Boot] [PATCH v2 34/56] rockchip: clk: rk3368: implement bandwidth adjust for PLLs

[Philipp Tomsich]

The RK3368 TRM recommends to configure the bandwith adjustment (CON2)
for PLLs to NF/2.  This implements this for all reconfigurations of
PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the
bandwidth-adjustment feature according to its manual).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk_rk3368.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index e1d9aeb..d8f06d5 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  * Author: Andy Yan <andy.yan@rock-chips.com>
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
  * SPDX-License-Identifier:	GPL-2.0
  */
 
@@ -74,7 +75,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
 }
 
 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
-			 const struct pll_div *div, bool has_bwadj)
+			 const struct pll_div *div)
 {
 	struct rk3368_pll *pll = &cru->pll[pll_id];
 	/* All PLLs have same VCO and output frequency range restrictions*/
@@ -92,6 +93,12 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
 		     ((div->nr - 1) << PLL_NR_SHIFT) |
 		     ((div->no - 1) << PLL_OD_SHIFT));
 	writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
+	/*
+	 * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
+	 * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
+	 */
+	clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
+
 	udelay(10);
 
 	/* return from reset */
@@ -111,10 +118,10 @@ static void rkclk_init(struct rk3368_cru *cru)
 {
 	u32 apllb, aplll, dpll, cpll, gpll;
 
-	rkclk_set_pll(cru, APLLB, &apll_b_init_cfg, false);
-	rkclk_set_pll(cru, APLLL, &apll_l_init_cfg, false);
-	rkclk_set_pll(cru, GPLL, &gpll_init_cfg, false);
-	rkclk_set_pll(cru, CPLL, &cpll_init_cfg, false);
+	rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
+	rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
+	rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
+	rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
 
 	apllb = rkclk_pll_get_rate(cru, APLLB);
 	aplll = rkclk_pll_get_rate(cru, APLLL);
-- 
2.1.4

[U-Boot] [PATCH v2 35/56] rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver

[Philipp Tomsich]

With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for
the SPL stage.  This implements support for OF_PLATDATA in the clock
driver for the RK3368.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk_rk3368.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index d8f06d5..809ad19 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -8,7 +8,9 @@
 #include <common.h>
 #include <clk-uclass.h>
 #include <dm.h>
+#include <dt-structs.h>
 #include <errno.h>
+#include <mapmem.h>
 #include <syscon.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3368.h>
@@ -19,6 +21,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+struct rk3368_clk_plat {
+	struct dtd_rockchip_rk3368_cru dtd;
+};
+#endif
+
 struct pll_div {
 	u32 nr;
 	u32 nf;
@@ -254,7 +262,11 @@ static struct clk_ops rk3368_clk_ops = {
 static int rk3368_clk_probe(struct udevice *dev)
 {
 	struct rk3368_clk_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct rk3368_clk_plat *plat = dev_get_platdata(dev);
 
+	priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
+#endif
 	rkclk_init(priv->cru);
 
 	return 0;
@@ -262,9 +274,11 @@ static int rk3368_clk_probe(struct udevice *dev)
 
 static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
 {
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct rk3368_clk_priv *priv = dev_get_priv(dev);
 
 	priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
+#endif
 
 	return 0;
 }
@@ -291,6 +305,9 @@ U_BOOT_DRIVER(rockchip_rk3368_cru) = {
 	.id		= UCLASS_CLK,
 	.of_match	= rk3368_clk_ids,
 	.priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	.platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
+#endif
 	.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
 	.ops		= &rk3368_clk_ops,
 	.bind		= rk3368_clk_bind,
-- 
2.1.4

[U-Boot] [PATCH v2 36/56] rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM

[Philipp Tomsich]

The RK3368 has a somewhat temperamental BootROM (which I learned the
hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
experiments show that changing the GPLL broke things for me, while
changing the CPLL seems to be more benign).  These should not be
modified by the SPL stage, if we intend to return to the BootROM for
chain booting the next stage.

This commit changes the clock initialisation to not change CPLL/GPLL
before returning to the BootROM (i.e. in TPL).  As it's safe to change
these settings if we no longer intend to return to U-Boot, we'll run
the full PLL setup a little later (i.e. in SPL).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk_rk3368.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 809ad19..d05be72 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -50,10 +50,14 @@ struct pll_div {
 		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
 		       "divisors on line " __stringify(__LINE__));
 
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
+#if !defined(CONFIG_TPL_BUILD)
 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
+#endif
+#endif
 
 /* Get pll rate by id */
 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
@@ -82,6 +86,7 @@ static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
 	}
 }
 
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
 			 const struct pll_div *div)
 {
@@ -121,15 +126,23 @@ static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
 
 	return 0;
 }
+#endif
 
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
 static void rkclk_init(struct rk3368_cru *cru)
 {
 	u32 apllb, aplll, dpll, cpll, gpll;
 
 	rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
 	rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
+#if !defined(CONFIG_TPL_BUILD)
+	/*
+	 * If we plan to return to the boot ROM, we can't increase the
+	 * GPLL rate from the SPL stage.
+	 */
 	rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
 	rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
+#endif
 
 	apllb = rkclk_pll_get_rate(cru, APLLB);
 	aplll = rkclk_pll_get_rate(cru, APLLL);
@@ -140,6 +153,7 @@ static void rkclk_init(struct rk3368_cru *cru)
 	debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
 	       __func__, apllb, aplll, dpll, cpll, gpll);
 }
+#endif
 
 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
 {
@@ -261,13 +275,15 @@ static struct clk_ops rk3368_clk_ops = {
 
 static int rk3368_clk_probe(struct udevice *dev)
 {
-	struct rk3368_clk_priv *priv = dev_get_priv(dev);
+	struct rk3368_clk_priv __maybe_unused *priv = dev_get_priv(dev);
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	struct rk3368_clk_plat *plat = dev_get_platdata(dev);
 
 	priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
 #endif
+#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
 	rkclk_init(priv->cru);
+#endif
 
 	return 0;
 }
-- 
2.1.4

[U-Boot] [PATCH v2 37/56] rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

[Philipp Tomsich]

To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk_rk3368.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index d05be72..33d2946 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -250,6 +250,37 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
 	return rate;
 }
 
+static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
+{
+	const struct pll_div *dpll_cfg = NULL;
+	const ulong MHz = 1000000;
+
+	/* Fout = ((Fin /NR) * NF )/ NO */
+	static const struct pll_div dpll_1200 =
+		PLL_DIVISORS(1200 * MHz, 1, 1);
+	static const struct pll_div dpll_1332 =
+		PLL_DIVISORS(1332 * MHz, 2, 1);
+	static const struct pll_div dpll_1600 =
+		PLL_DIVISORS(1600 * MHz, 3, 2);
+
+	switch (set_rate) {
+	case 1200*MHz:
+		dpll_cfg = &dpll_1200;
+		break;
+	case 1332*MHz:
+		dpll_cfg = &dpll_1332;
+		break;
+	case 1600*MHz:
+		dpll_cfg = &dpll_1600;
+		break;
+	default:
+		error("Unsupported SDRAM frequency!,%ld\n", set_rate);
+	}
+	rkclk_set_pll(cru, DPLL, dpll_cfg);
+
+	return set_rate;
+}
+
 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 {
 	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -257,6 +288,10 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 
 	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
 	switch (clk->id) {
+	case CLK_DDR:
+		ret = rk3368_ddr_set_clk(priv->cru, rate);
+		break;
+
 	case SCLK_SDMMC:
 	case SCLK_EMMC:
 		ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
-- 
2.1.4

[U-Boot] [PATCH v2 38/56] rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ

[Philipp Tomsich]

On he RK3368, we need to temporarily disable security on the DMA
engines during TPL and SPL to allow the MMC host to DMA into DRAM.  To
do so, we need to reset the two DMA engines, which in turn requires
the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the
appropriate bits in the CRU.

As the ATF correctly initialises security (and only leaves EL3 after
doing so), this can not pose a security issue.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 24a9cc0..bf09e2f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -102,6 +102,10 @@ enum {
 	/* SOFTRST1_CON */
 	MCU_PO_SRST_MASK		= BIT(13),
 	MCU_SYS_SRST_MASK		= BIT(12),
+	DMA1_SRST_REQ                   = BIT(2),
+
+	/* SOFTRST4_CON */
+	DMA2_SRST_REQ                   = BIT(0),
 
 	/* GLB_RST_CON */
 	PMU_GLB_SRST_CTRL_SHIFT		= 2,
-- 
2.1.4

[U-Boot] [PATCH v2 39/56] rockchip: clk: rk3368: implement MMC/SD clock reparenting

[Philipp Tomsich]

The original clock support for MMC/SD cards on the RK3368 suffered
from a tendency to select a divider less-or-equal to the the one
giving the requested clock-rate: this can lead to higher-than-expected
(or rather: higher than supported) clock rates for the MMC/SD
communiction.

This change rewrites the MMC/SD clock generation to:
 * always generate a clock less-than-or-equal to the requested clock
 * support reparenting among the CPLL, GPLL and OSC24M parents to
   generate the highest clock that does not exceed the requested rate

In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
always works), we adjust the driver appropriately.

This includes the changes from:
 - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/cru_rk3368.h |   8 +-
 drivers/clk/rockchip/clk_rk3368.c               | 119 ++++++++++++++++++------
 2 files changed, 95 insertions(+), 32 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index bf09e2f..21f11e0 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -92,10 +92,10 @@ enum {
 	/* CLKSEL51_CON */
 	MMC_PLL_SEL_SHIFT		= 8,
 	MMC_PLL_SEL_MASK		= GENMASK(9, 8),
-	MMC_PLL_SEL_CPLL		= 0,
-	MMC_PLL_SEL_GPLL,
-	MMC_PLL_SEL_USBPHY_480M,
-	MMC_PLL_SEL_24M,
+	MMC_PLL_SEL_CPLL		= (0 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_GPLL                = (1 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_USBPHY_480M         = (2 << MMC_PLL_SEL_SHIFT),
+	MMC_PLL_SEL_24M                 = (3 << MMC_PLL_SEL_SHIFT),
 	MMC_CLK_DIV_SHIFT		= 0,
 	MMC_CLK_DIV_MASK		= GENMASK(6, 0),
 
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 33d2946..1327116 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -59,6 +59,8 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
 #endif
 #endif
 
+static ulong rk3368_clk_get_rate(struct clk *clk);
+
 /* Get pll rate by id */
 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
 				   enum rk3368_pll_id pll_id)
@@ -155,16 +157,17 @@ static void rkclk_init(struct rk3368_cru *cru)
 }
 #endif
 
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
 static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
 {
 	u32 div, con, con_id, rate;
 	u32 pll_rate;
 
 	switch (clk_id) {
-	case SCLK_SDMMC:
+	case HCLK_SDMMC:
 		con_id = 50;
 		break;
-	case SCLK_EMMC:
+	case HCLK_EMMC:
 		con_id = 51;
 		break;
 	case SCLK_SDIO0:
@@ -175,7 +178,7 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
 	}
 
 	con = readl(&cru->clksel_con[con_id]);
-	switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
+	switch (con & MMC_PLL_SEL_MASK) {
 	case MMC_PLL_SEL_GPLL:
 		pll_rate = rkclk_pll_get_rate(cru, GPLL);
 		break;
@@ -183,6 +186,8 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
 		pll_rate = OSC_HZ;
 		break;
 	case MMC_PLL_SEL_CPLL:
+		pll_rate = rkclk_pll_get_rate(cru, CPLL);
+		break;
 	case MMC_PLL_SEL_USBPHY_480M:
 	default:
 		return -EINVAL;
@@ -190,23 +195,76 @@ static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
 	div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
 	rate = DIV_TO_RATE(pll_rate, div);
 
+	debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
 	return rate >> 1;
 }
 
-static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
-				ulong clk_id, ulong rate)
+static ulong rk3368_mmc_find_best_rate_and_parent(struct clk *clk,
+						  ulong rate,
+						  u32 *best_mux,
+						  u32 *best_div)
+{
+	int i;
+	ulong best_rate = 0;
+	const ulong MHz = 1000000;
+	const struct {
+		u32 mux;
+		ulong rate;
+	} parents[] = {
+		{ .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
+		{ .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
+		{ .mux = MMC_PLL_SEL_24M,  .rate = 24 * MHz }
+	};
+
+	debug("%s: target rate %ld\n", __func__, rate);
+	for (i = 0; i < ARRAY_SIZE(parents); ++i) {
+		/*
+		 * Find the largest rate no larger than the target-rate for
+		 * the current parent.
+		 */
+		ulong parent_rate = parents[i].rate;
+		u32 div = DIV_ROUND_UP(parent_rate, rate);
+		u32 adj_div = div;
+		ulong new_rate = parent_rate / adj_div;
+
+		debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
+		      __func__, rate, parents[i].mux, parents[i].rate, div);
+
+		/* Skip, if not representable */
+		if ((div - 1) > MMC_CLK_DIV_MASK)
+			continue;
+
+		/* Skip, if we already have a better (or equal) solution */
+		if (new_rate <= best_rate)
+			continue;
+
+		/* This is our new best rate. */
+		best_rate = new_rate;
+		*best_mux = parents[i].mux;
+		*best_div = div - 1;
+	}
+
+	debug("%s: best_mux = %x, best_div = %d, best_rate = %ld\n",
+	      __func__, *best_mux, *best_div, best_rate);
+
+	return best_rate;
+}
+
+static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
 {
-	u32 div;
-	u32 con_id;
-	u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
+	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+	struct rk3368_cru *cru = priv->cru;
+	ulong clk_id = clk->id;
+	u32 con_id, mux = 0, div = 0;
 
-	div = RATE_TO_DIV(gpll_rate, rate << 1);
+	/* Find the best parent and rate */
+	rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
 
 	switch (clk_id) {
-	case SCLK_SDMMC:
+	case HCLK_SDMMC:
 		con_id = 50;
 		break;
-	case SCLK_EMMC:
+	case HCLK_EMMC:
 		con_id = 51;
 		break;
 	case SCLK_SDIO0:
@@ -216,33 +274,33 @@ static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
 		return -EINVAL;
 	}
 
-	if (div > 0x3f) {
-		div = RATE_TO_DIV(OSC_HZ, rate);
-		rk_clrsetreg(&cru->clksel_con[con_id],
-			     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
-			     (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
-			     (div << MMC_CLK_DIV_SHIFT));
-	} else {
-		rk_clrsetreg(&cru->clksel_con[con_id],
-			     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
-			     (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
-			     div << MMC_CLK_DIV_SHIFT);
-	}
+	rk_clrsetreg(&cru->clksel_con[con_id],
+		     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
+		     mux | div);
 
 	return rk3368_mmc_get_clk(cru, clk_id);
 }
+#endif
 
 static ulong rk3368_clk_get_rate(struct clk *clk)
 {
 	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong rate = 0;
 
-	debug("%s id:%ld\n", __func__, clk->id);
+	debug("%s: id %ld\n", __func__, clk->id);
 	switch (clk->id) {
+	case PLL_CPLL:
+		rate = rkclk_pll_get_rate(priv->cru, CPLL);
+		break;
+	case PLL_GPLL:
+		rate = rkclk_pll_get_rate(priv->cru, GPLL);
+		break;
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
 	case HCLK_SDMMC:
 	case HCLK_EMMC:
 		rate = rk3368_mmc_get_clk(priv->cru, clk->id);
 		break;
+#endif
 	default:
 		return -ENOENT;
 	}
@@ -291,10 +349,15 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 	case CLK_DDR:
 		ret = rk3368_ddr_set_clk(priv->cru, rate);
 		break;
-
-	case SCLK_SDMMC:
-	case SCLK_EMMC:
-		ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
+	case HCLK_SDMMC:
+	case HCLK_EMMC:
+		ret = rk3368_mmc_set_clk(clk, rate);
+		break;
+#endif
+	case SCLK_MAC:
+		/* nothing to do, as this is an external clock */
+		ret = rate;
 		break;
 	default:
 		return -ENOENT;
-- 
2.1.4

[U-Boot] [PATCH v2 40/56] rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)

[Philipp Tomsich]

As part of the DRAM initialisation process (running as part of the TPL
stage) on the RK3368, we need to set up the DRAM PLL.

This implements support for configuring the PLL to for 1200, 1332 or
1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk_rk3368.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 1327116..1bed4e2 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -308,18 +308,16 @@ static ulong rk3368_clk_get_rate(struct clk *clk)
 	return rate;
 }
 
+#if IS_ENABLED(CONFIG_TPL_BUILD)
 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
 {
 	const struct pll_div *dpll_cfg = NULL;
 	const ulong MHz = 1000000;
 
 	/* Fout = ((Fin /NR) * NF )/ NO */
-	static const struct pll_div dpll_1200 =
-		PLL_DIVISORS(1200 * MHz, 1, 1);
-	static const struct pll_div dpll_1332 =
-		PLL_DIVISORS(1332 * MHz, 2, 1);
-	static const struct pll_div dpll_1600 =
-		PLL_DIVISORS(1600 * MHz, 3, 2);
+	static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);
+	static const struct pll_div dpll_1332 =	PLL_DIVISORS(1332 * MHz, 2, 1);
+	static const struct pll_div dpll_1600 =	PLL_DIVISORS(1600 * MHz, 3, 2);
 
 	switch (set_rate) {
 	case 1200*MHz:
@@ -338,6 +336,7 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
 
 	return set_rate;
 }
+#endif
 
 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 {
@@ -346,9 +345,11 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 
 	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
 	switch (clk->id) {
+#if IS_ENABLED(CONFIG_TPL_BUILD)
 	case CLK_DDR:
 		ret = rk3368_ddr_set_clk(priv->cru, rate);
 		break;
+#endif
 #if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
 	case HCLK_SDMMC:
 	case HCLK_EMMC:
-- 
2.1.4

[U-Boot] [PATCH v2 41/56] rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock

[Philipp Tomsich]

To enable the GMAC on the RK3368, we need to set up the clocking
appropriately to generate a tx_clk for the MAC.

This adds an implementation that implements the use of the <&ext_gmac>
clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
This is the clock setup used by the boards currently supported by
U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).

This includes the change from commit
 - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  3 +++
 drivers/clk/rockchip/clk_rk3368.c               | 19 +++++++++++++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
index 21f11e0..2b1197f 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h
@@ -89,6 +89,9 @@ enum {
 	MCU_CLK_DIV_SHIFT		= 0,
 	MCU_CLK_DIV_MASK		= GENMASK(4, 0),
 
+	/* CLKSEL43_CON */
+	GMAC_MUX_SEL_EXTCLK             = BIT(8),
+
 	/* CLKSEL51_CON */
 	MMC_PLL_SEL_SHIFT		= 8,
 	MMC_PLL_SEL_MASK		= GENMASK(9, 8),
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 1bed4e2..2b6c8da 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -338,6 +338,19 @@ static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
+static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
+				 ulong clk_id, ulong set_rate)
+{
+	/*
+	 * This models the 'assigned-clock-parents = <&ext_gmac>' from
+	 * the DTS and switches to the 'ext_gmac' clock parent.
+	 */
+	rk_setreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK);
+	return set_rate;
+}
+#endif
+
 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 {
 	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -356,10 +369,12 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 		ret = rk3368_mmc_set_clk(clk, rate);
 		break;
 #endif
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
 	case SCLK_MAC:
-		/* nothing to do, as this is an external clock */
-		ret = rate;
+		/* select the external clock */
+		ret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);
 		break;
+#endif
 	default:
 		return -ENOENT;
 	}
-- 
2.1.4

[U-Boot] [PATCH v2 42/56] rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()

[Philipp Tomsich]

With the clock support in rk3368_clk_set_rate() conditionalized on
various feature definitions, 'priv' can remain unused (e.g. in the
SPL build when only MMC is enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk_rk3368.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 2b6c8da..d3f6c29 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -353,7 +353,7 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
 
 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 {
-	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+	__maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
 	ulong ret = 0;
 
 	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
-- 
2.1.4

[U-Boot] [PATCH v2 43/56] rockchip: clk: rk3368: add support for configuring the SPI clocks

[Philipp Tomsich]

As SPI support may be useful in the boot-flow, this adds support for
configuring the SPI controller's clocks in the RK3368 clock driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2:
- added SPI clock setup

 drivers/clk/rockchip/clk_rk3368.c | 132 ++++++++++++++++++++++++++++++--------
 1 file changed, 106 insertions(+), 26 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index d3f6c29..04f9b80 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -282,32 +282,6 @@ static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
 }
 #endif
 
-static ulong rk3368_clk_get_rate(struct clk *clk)
-{
-	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
-	ulong rate = 0;
-
-	debug("%s: id %ld\n", __func__, clk->id);
-	switch (clk->id) {
-	case PLL_CPLL:
-		rate = rkclk_pll_get_rate(priv->cru, CPLL);
-		break;
-	case PLL_GPLL:
-		rate = rkclk_pll_get_rate(priv->cru, GPLL);
-		break;
-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
-	case HCLK_SDMMC:
-	case HCLK_EMMC:
-		rate = rk3368_mmc_get_clk(priv->cru, clk->id);
-		break;
-#endif
-	default:
-		return -ENOENT;
-	}
-
-	return rate;
-}
-
 #if IS_ENABLED(CONFIG_TPL_BUILD)
 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate)
 {
@@ -351,6 +325,109 @@ static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru,
 }
 #endif
 
+/*
+ * RK3368 SPI clocks have a common divider-width (7 bits) and a single bit
+ * to select either CPLL or GPLL as the clock-parent. The location within
+ * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
+ */
+
+struct spi_clkreg {
+	uint8_t reg;  /* CLKSEL_CON[reg] register in CRU */
+	uint8_t div_shift;
+	uint8_t sel_shift;
+};
+
+/*
+ * The entries are numbered relative to their offset from SCLK_SPI0.
+ */
+static const struct spi_clkreg spi_clkregs[] = {
+	[0] = { .reg = 45, .div_shift = 0, .sel_shift = 7, },
+	[1] = { .reg = 45, .div_shift = 8, .sel_shift = 15, },
+	[2] = { .reg = 46, .div_shift = 8, .sel_shift = 15, },
+};
+
+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
+{
+	return (val >> shift) & ((1 << width) - 1);
+}
+
+static ulong rk3368_spi_get_clk(struct rk3368_cru *cru, ulong clk_id)
+{
+	const struct spi_clkreg *spiclk = NULL;
+	u32 div, val;
+
+	switch (clk_id) {
+	case SCLK_SPI0 ... SCLK_SPI2:
+		spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+		break;
+
+	default:
+		error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+		return -EINVAL;
+	}
+
+	val = readl(&cru->clksel_con[spiclk->reg]);
+	div = extract_bits(val, 7, spiclk->div_shift);
+
+	debug("%s: div 0x%x\n", __func__, div);
+	return DIV_TO_RATE(GPLL_HZ, div);
+}
+
+static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)
+{
+	const struct spi_clkreg *spiclk = NULL;
+	int src_clk_div;
+
+	src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
+	assert(src_clk_div < 127);
+
+	switch (clk_id) {
+	case SCLK_SPI0 ... SCLK_SPI2:
+		spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
+		break;
+
+	default:
+		error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
+		return -EINVAL;
+	}
+
+	rk_clrsetreg(&cru->clksel_con[spiclk->reg],
+		     ((0x7f << spiclk->div_shift) | (0x1 << spiclk->sel_shift)),
+		     ((src_clk_div << spiclk->div_shift) |
+		      (1 /* TODO */ << spiclk->sel_shift)));
+
+	return rk3368_spi_get_clk(cru, clk_id);
+}
+
+static ulong rk3368_clk_get_rate(struct clk *clk)
+{
+	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
+	ulong rate = 0;
+
+	debug("%s: id %ld\n", __func__, clk->id);
+	switch (clk->id) {
+	case PLL_CPLL:
+		rate = rkclk_pll_get_rate(priv->cru, CPLL);
+		break;
+	case PLL_GPLL:
+		rate = rkclk_pll_get_rate(priv->cru, GPLL);
+		break;
+	case SCLK_SPI0 ... SCLK_SPI2:
+		rate = rk3368_spi_get_clk(priv->cru, clk->id);
+		break;
+#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT)
+	case HCLK_SDMMC:
+	case HCLK_EMMC:
+		rate = rk3368_mmc_get_clk(priv->cru, clk->id);
+		break;
+#endif
+	default:
+		return -ENOENT;
+	}
+
+	return rate;
+}
+
 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 {
 	__maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
@@ -358,6 +435,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
 
 	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
 	switch (clk->id) {
+	case SCLK_SPI0 ... SCLK_SPI2:
+		ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
+		break;
 #if IS_ENABLED(CONFIG_TPL_BUILD)
 	case CLK_DDR:
 		ret = rk3368_ddr_set_clk(priv->cru, rate);
-- 
2.1.4

[U-Boot] [PATCH v2 44/56] net: gmac_rockchip: Add support for the RK3368 GMAC

[Philipp Tomsich]

The GMAC in the RK3368 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3368-specific logic necessary to reuse this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- moves the bit-definitions (for GRF registers) specific to the GMAC
  into the GMAC driver: these include interface speed selection and
  configuring the RGMII output mode

 arch/arm/include/asm/arch-rockchip/grf_rk3368.h |  1 +
 drivers/net/gmac_rockchip.c                     | 78 +++++++++++++++++++++++++
 2 files changed, 79 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index ec42d7a..1f84ff9 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -129,4 +129,5 @@ enum {
 	MCU_CODE_BASE_BIT31_BIT28_SHIFT		= 0,
 	MCU_CODE_BASE_BIT31_BIT28_MASK		= GENMASK(3, 0),
 };
+
 #endif
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index c9f9e83..586ccbf 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3368.h>
 #include <asm/arch/grf_rk3399.h>
 #include <dm/pinctrl.h>
 #include <dt-bindings/clock/rk3288-cru.h>
@@ -83,6 +84,38 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 	return 0;
 }
 
+static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk3368_grf *grf;
+	int clk;
+	enum {
+		RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,
+		RK3368_GMAC_CLK_SEL_25M = 3 << 4,
+		RK3368_GMAC_CLK_SEL_125M = 0 << 4,
+		RK3368_GMAC_CLK_SEL_MASK = GENMASK(5, 4),
+	};
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = RK3368_GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = RK3368_GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = RK3368_GMAC_CLK_SEL_125M;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);
+
+	return 0;
+}
+
 static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk3399_grf_regs *grf;
@@ -129,6 +162,44 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk3368_grf *grf;
+	enum {
+		RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,
+		RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),
+		RK3368_RMII_MODE_MASK  = BIT(6),
+		RK3368_RMII_MODE       = BIT(6),
+	};
+	enum {
+		RK3368_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),
+		RK3368_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3368_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),
+		RK3368_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),
+		RK3368_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3368_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),
+		RK3368_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
+		RK3368_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),
+		RK3368_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
+		RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con15,
+		     RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,
+		     RK3368_GMAC_PHY_INTF_SEL_RGMII);
+
+	rk_clrsetreg(&grf->soc_con16,
+		     RK3368_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3368_TXCLK_DLY_ENA_GMAC_MASK |
+		     RK3368_CLK_RX_DL_CFG_GMAC_MASK |
+		     RK3368_CLK_TX_DL_CFG_GMAC_MASK,
+		     RK3368_RXCLK_DLY_ENA_GMAC_ENABLE |
+		     RK3368_TXCLK_DLY_ENA_GMAC_ENABLE |
+		     pdata->rx_delay << RK3368_CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << RK3368_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
 	struct rk3399_grf_regs *grf;
@@ -208,6 +279,11 @@ const struct rk_gmac_ops rk3288_gmac_ops = {
 	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
 
+const struct rk_gmac_ops rk3368_gmac_ops = {
+	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
+	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3399_gmac_ops = {
 	.fix_mac_speed = rk3399_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3399_gmac_set_to_rgmii,
@@ -216,6 +292,8 @@ const struct rk_gmac_ops rk3399_gmac_ops = {
 static const struct udevice_id rockchip_gmac_ids[] = {
 	{ .compatible = "rockchip,rk3288-gmac",
 	  .data = (ulong)&rk3288_gmac_ops },
+	{ .compatible = "rockchip,rk3368-gmac",
+	  .data = (ulong)&rk3368_gmac_ops },
 	{ .compatible = "rockchip,rk3399-gmac",
 	  .data = (ulong)&rk3399_gmac_ops },
 	{ }
-- 
2.1.4

[U-Boot] [PATCH v2 45/56] rockchip: Makefile: streamline SPL/TPL configuration

[Philipp Tomsich]

Handling TPL and SPL in the Makefile for mach-rockchip was based on
nested if checks and/or if-else-if paths.  This can be simplified and
made more readable by using $(SPL_TPL_) and by introducing
intermediate variables for the aggregation of SPL and TPL features.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/mach-rockchip/Makefile | 46 +++++++++++++++++++++++++----------------
 1 file changed, 28 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 8a3cb9f..633c91e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -4,37 +4,47 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+# We don't want the bootrom-helper present in a full U-Boot build, as
+# this may have entered from ATF with the stack-pointer pointing to
+# inaccessible/protected memory (and the bootrom-helper assumes that
+# the stack-pointer is valid before switching to the U-Boot stack).
+obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
+obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
+
+obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
+
+obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
 
-ifdef CONFIG_TPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
-else ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
-obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
-else
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
 endif
+
+obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
+
 ifndef CONFIG_ARM64
 obj-y += rk_timer.o
 endif
-obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
-
-ifndef CONFIG_TPL_BUILD
-obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
-endif
 
+obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
 obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
 obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
 obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
+
+# Clear out SPL objects, in case this is a TPL build
+obj-spl-$(CONFIG_TPL_BUILD) =
+
+# Now add SPL/TPL objects back into the main build
+obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y)
+obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
-- 
2.1.4

[U-Boot] [PATCH v2 46/56] rockchip: rk3368: add DRAM controller driver with DRAM initialisation

[Philipp Tomsich]

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ddr/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
 - DDR3
 - 32-bit configuration (i.e. fully populated)
 - dual-rank (i.e. no auto-detection of ranks)
 - DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM.  It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block.  This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h    | 187 ++++
 arch/arm/include/asm/arch-rockchip/grf_rk3368.h    |   3 +
 arch/arm/mach-rockchip/rk3368/Makefile             |   1 -
 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c       |  60 --
 .../clock/rockchip,rk3368-dmc.txt                  |  67 ++
 drivers/ram/Makefile                               |   2 +
 drivers/ram/rockchip/Makefile                      |   7 +
 drivers/ram/rockchip/dmc-rk3368.c                  | 990 +++++++++++++++++++++
 include/dt-bindings/memory/rk3368-dmc.h            |  30 +
 9 files changed, 1286 insertions(+), 61 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
 delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
 create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
 create mode 100644 drivers/ram/rockchip/Makefile
 create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
 create mode 100644 include/dt-bindings/memory/rk3368-dmc.h

diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
new file mode 100644
index 0000000..4e2b233
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
@@ -0,0 +1,187 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_DDR_RK3368_H__
+#define __ASM_ARCH_DDR_RK3368_H__
+
+/*
+ * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only
+ * in a few details. Most notably, it has an additional field to track
+ * tREFI in controller cycles (i.e. trefi_mem_ddr3).
+ */
+struct rk3368_ddr_pctl {
+	u32 scfg;
+	u32 sctl;
+	u32 stat;
+	u32 intrstat;
+	u32 reserved0[12];
+	u32 mcmd;
+	u32 powctl;
+	u32 powstat;
+	u32 cmdtstat;
+	u32 cmdtstaten;
+	u32 reserved1[3];
+	u32 mrrcfg0;
+	u32 mrrstat0;
+	u32 mrrstat1;
+	u32 reserved2[4];
+	u32 mcfg1;
+	u32 mcfg;
+	u32 ppcfg;
+	u32 mstat;
+	u32 lpddr2zqcfg;
+	u32 reserved3;
+	u32 dtupdes;
+	u32 dtuna;
+	u32 dtune;
+	u32 dtuprd0;
+	u32 dtuprd1;
+	u32 dtuprd2;
+	u32 dtuprd3;
+	u32 dtuawdt;
+	u32 reserved4[3];
+	u32 togcnt1u;
+	u32 tinit;
+	u32 trsth;
+	u32 togcnt100n;
+	u32 trefi;
+	u32 tmrd;
+	u32 trfc;
+	u32 trp;
+	u32 trtw;
+	u32 tal;
+	u32 tcl;
+	u32 tcwl;
+	u32 tras;
+	u32 trc;
+	u32 trcd;
+	u32 trrd;
+	u32 trtp;
+	u32 twr;
+	u32 twtr;
+	u32 texsr;
+	u32 txp;
+	u32 txpdll;
+	u32 tzqcs;
+	u32 tzqcsi;
+	u32 tdqs;
+	u32 tcksre;
+	u32 tcksrx;
+	u32 tcke;
+	u32 tmod;
+	u32 trstl;
+	u32 tzqcl;
+	u32 tmrr;
+	u32 tckesr;
+	u32 tdpd;
+	u32 trefi_mem_ddr3;
+	u32 reserved5[45];
+	u32 dtuwactl;
+	u32 dturactl;
+	u32 dtucfg;
+	u32 dtuectl;
+	u32 dtuwd0;
+	u32 dtuwd1;
+	u32 dtuwd2;
+	u32 dtuwd3;
+	u32 dtuwdm;
+	u32 dturd0;
+	u32 dturd1;
+	u32 dturd2;
+	u32 dturd3;
+	u32 dtulfsrwd;
+	u32 dtulfsrrd;
+	u32 dtueaf;
+	u32 dfitctrldelay;
+	u32 dfiodtcfg;
+	u32 dfiodtcfg1;
+	u32 dfiodtrankmap;
+	u32 dfitphywrdata;
+	u32 dfitphywrlat;
+	u32 reserved7[2];
+	u32 dfitrddataen;
+	u32 dfitphyrdlat;
+	u32 reserved8[2];
+	u32 dfitphyupdtype0;
+	u32 dfitphyupdtype1;
+	u32 dfitphyupdtype2;
+	u32 dfitphyupdtype3;
+	u32 dfitctrlupdmin;
+	u32 dfitctrlupdmax;
+	u32 dfitctrlupddly;
+	u32 reserved9;
+	u32 dfiupdcfg;
+	u32 dfitrefmski;
+	u32 dfitctrlupdi;
+	u32 reserved10[4];
+	u32 dfitrcfg0;
+	u32 dfitrstat0;
+	u32 dfitrwrlvlen;
+	u32 dfitrrdlvlen;
+	u32 dfitrrdlvlgateen;
+	u32 dfiststat0;
+	u32 dfistcfg0;
+	u32 dfistcfg1;
+	u32 reserved11;
+	u32 dfitdramclken;
+	u32 dfitdramclkdis;
+	u32 dfistcfg2;
+	u32 dfistparclr;
+	u32 dfistparlog;
+	u32 reserved12[3];
+	u32 dfilpcfg0;
+	u32 reserved13[3];
+	u32 dfitrwrlvlresp0;
+	u32 dfitrwrlvlresp1;
+	u32 dfitrwrlvlresp2;
+	u32 dfitrrdlvlresp0;
+	u32 dfitrrdlvlresp1;
+	u32 dfitrrdlvlresp2;
+	u32 dfitrwrlvldelay0;
+	u32 dfitrwrlvldelay1;
+	u32 dfitrwrlvldelay2;
+	u32 dfitrrdlvldelay0;
+	u32 dfitrrdlvldelay1;
+	u32 dfitrrdlvldelay2;
+	u32 dfitrrdlvlgatedelay0;
+	u32 dfitrrdlvlgatedelay1;
+	u32 dfitrrdlvlgatedelay2;
+	u32 dfitrcmd;
+	u32 reserved14[46];
+	u32 ipvr;
+	u32 iptr;
+};
+check_member(rk3368_ddr_pctl, iptr, 0x03fc);
+
+struct rk3368_ddrphy {
+	u32 reg[0x100];
+};
+check_member(rk3368_ddrphy, reg[0xff], 0x03fc);
+
+struct rk3368_msch {
+	u32 coreid;
+	u32 revisionid;
+	u32 ddrconf;
+	u32 ddrtiming;
+	u32 ddrmode;
+	u32 readlatency;
+	u32 reserved1[8];
+	u32 activate;
+	u32 devtodev;
+};
+check_member(rk3368_msch, devtodev, 0x003c);
+
+/* GRF_SOC_CON0 */
+enum {
+	NOC_RSP_ERR_STALL = BIT(9),
+	MOBILE_DDR_SEL = BIT(4),
+	DDR0_16BIT_EN = BIT(3),
+	MSCH0_MAINDDR3_DDR3 = BIT(2),
+	MSCH0_MAINPARTIALPOP = BIT(1),
+	UPCTL_C_ACTIVE = BIT(0),
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
index 1f84ff9..6b6651a 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
@@ -76,8 +76,11 @@ struct rk3368_grf {
 	u32 soc_con15;
 	u32 soc_con16;
 	u32 soc_con17;
+	u32 reserved5[0x6e];
+	u32 ddrc0_con0;
 };
 check_member(rk3368_grf, soc_con17, 0x444);
+check_member(rk3368_grf, ddrc0_con0, 0x600);
 
 struct rk3368_pmu_grf {
 	u32 gpio0a_iomux;
diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
index 0390716..46798c2 100644
--- a/arch/arm/mach-rockchip/rk3368/Makefile
+++ b/arch/arm/mach-rockchip/rk3368/Makefile
@@ -5,5 +5,4 @@
 #
 obj-y		+= clk_rk3368.o
 obj-y		+= rk3368.o
-obj-y 		+= sdram_rk3368.o
 obj-y 		+= syscon_rk3368.o
diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
deleted file mode 100644
index d0d0900..0000000
--- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier:     GPL-2.0
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/sdram_common.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-struct dram_info {
-	struct ram_info info;
-	struct rk3368_pmu_grf *pmugrf;
-};
-
-static int rk3368_dmc_probe(struct udevice *dev)
-{
-	struct dram_info *priv = dev_get_priv(dev);
-
-	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-	debug("%s: grf=%p\n", __func__, priv->pmugrf);
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
-	priv->info.size = rockchip_sdram_size(
-			(phys_addr_t)&priv->pmugrf->os_reg[2]);
-
-	return 0;
-}
-
-static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
-{
-	struct dram_info *priv = dev_get_priv(dev);
-
-	*info = priv->info;
-
-	return 0;
-}
-
-static struct ram_ops rk3368_dmc_ops = {
-	.get_info = rk3368_dmc_get_info,
-};
-
-
-static const struct udevice_id rk3368_dmc_ids[] = {
-	{ .compatible = "rockchip,rk3368-dmc" },
-	{ }
-};
-
-U_BOOT_DRIVER(dmc_rk3368) = {
-	.name = "rockchip_rk3368_dmc",
-	.id = UCLASS_RAM,
-	.of_match = rk3368_dmc_ids,
-	.ops = &rk3368_dmc_ops,
-	.probe = rk3368_dmc_probe,
-	.priv_auto_alloc_size = sizeof(struct dram_info),
-};
diff --git a/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
new file mode 100644
index 0000000..8e7357d
--- /dev/null
+++ b/doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
@@ -0,0 +1,67 @@
+RK3368 dynamic memory controller driver
+=======================================
+
+The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
+during TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on
+the following key configuration data:
+  (a) a target-frequency (i.e. operating point) for the memory operation
+  (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware
+  (c) a memory-schedule (i.e. mapping from physical addresses to the address
+      pins of the memory bus)
+
+Required properties
+-------------------
+
+- compatible: "rockchip,rk3368-dmc"
+- reg
+    protocol controller (PCTL) address and PHY controller (DDRPHY) address
+- rockchip,ddr-speed-bin
+    the DDR3 device's speed-bin (as specified according to JESD-79)
+        DDR3_800D (5-5-5)
+        DDR3_800E (6-6-6)
+        DDR3_1066E (6-6-6)
+        DDR3_1066F (7-7-7)
+        DDR3_1066G (8-8-8)
+        DDR3_1333F (7-7-7)
+        DDR3_1333G (8-8-8)
+        DDR3_1333H (9-9-9)
+        DDR3_1333J (10-10-10)
+        DDR3_1600G (8-8-8)
+        DDR3_1600H (9-9-9)
+        DDR3_1600J (10-10-10)
+        DDR3_1600K (11-11-11)
+        DDR3_1866J (10-10-10)
+        DDR3_1866K (11-11-11)
+        DDR3_1866L (12-12-12)
+        DDR3_1866M (13-13-13)
+        DDR3_2133K (11-11-11)
+        DDR3_2133L (12-12-12)
+        DDR3_2133M (13-13-13)
+        DDR3_2133N (14-14-14)
+- rockchip,ddr-frequency:
+    target DDR clock frequency in Hz (not all frequencies may be supported,
+    as there's some cooperation from the clock-driver required)
+- rockchip,memory-schedule:
+    controls the decoding of physical addresses to DRAM addressing (i.e. how
+    the physical address maps onto the address pins/chip-select of the device)
+	DMC_MSCH_CBDR: column -> bank -> device -> row
+	DMC_MSCH_CBRD: column -> band -> row -> device
+	DMC_MSCH_CRBD: column -> row -> band -> device
+
+Example (for DDR3-1600K and 800MHz)
+-----------------------------------
+
+	#include <dt-bindings/memory/rk3368-dmc.h>
+
+	dmc: dmc at ff610000 {
+	        u-boot,dm-pre-reloc;
+		compatible = "rockchip,rk3368-dmc";
+		reg = <0 0xff610000 0 0x400
+		       0 0xff620000 0 0x400>;
+	};
+
+	&dmc {
+		rockchip,ddr-speed-bin = <DDR3_1600K>;
+		rockchip,ddr-frequency = <800000000>;
+		rockchip,memory-schedule = <DMC_MSCH_CBRD>;
+	};
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index c409c48..51ae6be 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -8,3 +8,5 @@ obj-$(CONFIG_RAM) += ram-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_ram.o
 obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o
 obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o
+
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
new file mode 100644
index 0000000..b09d03c
--- /dev/null
+++ b/drivers/ram/rockchip/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c
new file mode 100644
index 0000000..fea96a5
--- /dev/null
+++ b/drivers/ram/rockchip/dmc-rk3368.c
@@ -0,0 +1,990 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-bindings/memory/rk3368-dmc.h>
+#include <dt-structs.h>
+#include <ram.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/ddr_rk3368.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/sdram_common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct dram_info {
+	struct ram_info info;
+	struct clk ddr_clk;
+	struct rk3368_cru *cru;
+	struct rk3368_grf *grf;
+	struct rk3368_ddr_pctl *pctl;
+	struct rk3368_ddrphy *phy;
+	struct rk3368_pmu_grf *pmugrf;
+	struct rk3368_msch *msch;
+};
+
+struct rk3368_sdram_params {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct dtd_rockchip_rk3368_dmc of_plat;
+#endif
+	struct rk3288_sdram_pctl_timing pctl_timing;
+	u32 trefi_mem_ddr3;
+	struct rk3288_sdram_channel chan;
+	struct regmap *map;
+	u32 ddr_freq;
+	u32 memory_schedule;
+	u32 ddr_speed_bin;
+	u32 tfaw_mult;
+};
+
+/* PTCL bits */
+enum {
+	/* PCTL_DFISTCFG0 */
+	DFI_INIT_START = BIT(0),
+	DFI_DATA_BYTE_DISABLE_EN = BIT(2),
+
+	/* PCTL_DFISTCFG1 */
+	DFI_DRAM_CLK_SR_EN = BIT(0),
+	DFI_DRAM_CLK_DPD_EN = BIT(1),
+	ODT_LEN_BL8_W_SHIFT = 16,
+
+	/* PCTL_DFISTCFG2 */
+	DFI_PARITY_INTR_EN = BIT(0),
+	DFI_PARITY_EN = BIT(1),
+
+	/* PCTL_DFILPCFG0 */
+	TLP_RESP_TIME_SHIFT = 16,
+	LP_SR_EN = BIT(8),
+	LP_PD_EN = BIT(0),
+
+	/* PCTL_DFIODTCFG */
+	RANK0_ODT_WRITE_SEL = BIT(3),
+	RANK1_ODT_WRITE_SEL = BIT(11),
+
+	/* PCTL_SCFG */
+	HW_LOW_POWER_EN = BIT(0),
+
+	/* PCTL_MCMD */
+	START_CMD = BIT(31),
+	MCMD_RANK0 = BIT(20),
+	MCMD_RANK1 = BIT(21),
+	DESELECT_CMD = 0,
+	PREA_CMD,
+	REF_CMD,
+	MRS_CMD,
+	ZQCS_CMD,
+	ZQCL_CMD,
+	RSTL_CMD,
+	MRR_CMD	= 8,
+	DPDE_CMD,
+
+	/* PCTL_POWCTL */
+	POWER_UP_START = BIT(0),
+
+	/* PCTL_POWSTAT */
+	POWER_UP_DONE = BIT(0),
+
+	/* PCTL_SCTL */
+	INIT_STATE = 0,
+	CFG_STATE,
+	GO_STATE,
+	SLEEP_STATE,
+	WAKEUP_STATE,
+
+	/* PCTL_STAT */
+	LP_TRIG_SHIFT = 4,
+	LP_TRIG_MASK = 7,
+	PCTL_STAT_MSK = 7,
+	INIT_MEM = 0,
+	CONFIG,
+	CONFIG_REQ,
+	ACCESS,
+	ACCESS_REQ,
+	LOW_POWER,
+	LOW_POWER_ENTRY_REQ,
+	LOW_POWER_EXIT_REQ,
+
+	/* PCTL_MCFG */
+	DDR2_DDR3_BL_8 = BIT(0),
+	DDR3_EN = BIT(5),
+	TFAW_TRRD_MULT4 = (0 << 18),
+	TFAW_TRRD_MULT5 = (1 << 18),
+	TFAW_TRRD_MULT6 = (2 << 18),
+};
+
+#define DDR3_MR0_WR(n) \
+	((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9))
+#define DDR3_MR0_CL(n) \
+	((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2))
+#define DDR3_MR0_BL8 \
+	(0 << 0)
+#define DDR3_MR0_DLL_RESET \
+	(1 << 8)
+#define DDR3_MR1_RTT120OHM \
+	((0 << 9) | (1 << 6) | (0 << 2))
+#define DDR3_MR2_TWL(n) \
+	(((n - 5) & 0x7) << 3)
+
+
+#ifdef CONFIG_TPL_BUILD
+
+static void ddr_set_noc_spr_err_stall(struct rk3368_grf *grf, bool enable)
+{
+	if (enable)
+		rk_setreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
+	else
+		rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL);
+}
+
+static void ddr_set_ddr3_mode(struct rk3368_grf *grf, bool ddr3_mode)
+{
+	if (ddr3_mode)
+		rk_setreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
+	else
+		rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3);
+}
+
+static void ddrphy_config(struct rk3368_ddrphy *phy,
+			  u32 tcl, u32 tal, u32 tcwl)
+{
+	int i;
+
+	/* Set to DDR3 mode */
+	clrsetbits_le32(&phy->reg[1], 0x3, 0x0);
+
+	/* DDRPHY_REGB: CL, AL */
+	clrsetbits_le32(&phy->reg[0xb], 0xff, tcl << 4 | tal);
+	/* DDRPHY_REGC: CWL */
+	clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
+
+	/* Update drive-strength */
+	writel(0xcc, &phy->reg[0x11]);
+	writel(0xaa, &phy->reg[0x16]);
+	/*
+	 * Update NRCOMP/PRCOMP for all 4 channels (for details of all
+	 * affected registers refer to the documentation of DDRPHY_REG20
+	 * and DDRPHY_REG21 in the RK3368 TRM.
+	 */
+	for (i = 0; i < 4; ++i) {
+		writel(0xcc, &phy->reg[0x20 + i * 0x10]);
+		writel(0x44, &phy->reg[0x21 + i * 0x10]);
+	}
+
+	/* Enable write-leveling calibration bypass */
+	setbits_le32(&phy->reg[2], BIT(3));
+}
+
+static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
+{
+	int i;
+
+	for (i = 0; i < n / sizeof(u32); i++)
+		writel(*src++, dest++);
+}
+
+static void send_command(struct rk3368_ddr_pctl *pctl, u32 rank, u32 cmd)
+{
+	u32 mcmd = START_CMD | cmd | rank;
+
+	debug("%s: writing %x to MCMD\n", __func__, mcmd);
+	writel(mcmd, &pctl->mcmd);
+	while (readl(&pctl->mcmd) & START_CMD)
+		/* spin */;
+}
+
+static void send_mrs(struct rk3368_ddr_pctl *pctl,
+			    u32 rank, u32 mr_num, u32 mr_data)
+{
+	u32 mcmd = START_CMD | MRS_CMD | rank | (mr_num << 17) | (mr_data << 4);
+
+	debug("%s: writing %x to MCMD\n", __func__, mcmd);
+	writel(mcmd, &pctl->mcmd);
+	while (readl(&pctl->mcmd) & START_CMD)
+		/* spin */;
+}
+
+static int memory_init(struct rk3368_ddr_pctl *pctl,
+		       struct rk3368_sdram_params *params)
+{
+	u32 mr[4];
+	const ulong timeout_ms = 500;
+	ulong tmp;
+
+	/*
+	 * Power up DRAM by DDR_PCTL_POWCTL[0] register of PCTL and
+	 * wait power up DRAM finish with DDR_PCTL_POWSTAT[0] register
+	 * of PCTL.
+	 */
+	writel(POWER_UP_START, &pctl->powctl);
+
+	tmp = get_timer(0);
+	do {
+		if (get_timer(tmp) > timeout_ms) {
+			error("%s: POWER_UP_START did not complete in %ld ms\n",
+			      __func__, timeout_ms);
+			return -ETIME;
+		}
+	} while (!(readl(&pctl->powstat) & POWER_UP_DONE));
+
+	/* Configure MR0 through MR3 */
+	mr[0] = DDR3_MR0_WR(params->pctl_timing.twr) |
+		DDR3_MR0_CL(params->pctl_timing.tcl) |
+		DDR3_MR0_DLL_RESET;
+	mr[1] = DDR3_MR1_RTT120OHM;
+	mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
+	mr[3] = 0;
+
+	/*
+	 * Also see RK3368 Technical Reference Manual:
+	 *   "16.6.2 Initialization (DDR3 Initialization Sequence)"
+	 */
+	send_command(pctl, MCMD_RANK0 | MCMD_RANK1, DESELECT_CMD);
+	udelay(1);
+	send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
+	send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 2, mr[2]);
+	send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 3, mr[3]);
+	send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 1, mr[1]);
+	send_mrs(pctl, MCMD_RANK0 | MCMD_RANK1, 0, mr[0]);
+	send_command(pctl, MCMD_RANK0 | MCMD_RANK1, ZQCL_CMD);
+
+	return 0;
+}
+
+static void move_to_config_state(struct rk3368_ddr_pctl *pctl)
+{
+	/*
+	 * Also see RK3368 Technical Reference Manual:
+	 *   "16.6.1 State transition of PCTL (Moving to Config State)"
+	 */
+	u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+	switch (state) {
+	case LOW_POWER:
+		writel(WAKEUP_STATE, &pctl->sctl);
+		while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
+			/* spin */;
+
+		/* fall-through */
+	case ACCESS:
+	case INIT_MEM:
+		writel(CFG_STATE, &pctl->sctl);
+		while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+			/* spin */;
+		break;
+
+	case CONFIG:
+		return;
+
+	default:
+		break;
+	}
+}
+
+static void move_to_access_state(struct rk3368_ddr_pctl *pctl)
+{
+	/*
+	 * Also see RK3368 Technical Reference Manual:
+	 *   "16.6.1 State transition of PCTL (Moving to Access State)"
+	 */
+	u32 state = readl(&pctl->stat) & PCTL_STAT_MSK;
+
+	switch (state) {
+	case LOW_POWER:
+		if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
+		     LP_TRIG_MASK) == 1)
+			return;
+
+		writel(WAKEUP_STATE, &pctl->sctl);
+		while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
+			/* spin */;
+
+		/* fall-through */
+	case INIT_MEM:
+		writel(CFG_STATE, &pctl->sctl);
+		while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
+			/* spin */;
+
+		/* fall-through */
+	case CONFIG:
+		writel(GO_STATE, &pctl->sctl);
+		while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
+			/* spin */;
+		break;
+
+	case ACCESS:
+		return;
+
+	default:
+		break;
+	}
+}
+
+static void ddrctl_reset(struct rk3368_cru *cru)
+{
+	const u32 ctl_reset = BIT(3) | BIT(2);
+	const u32 phy_reset = BIT(1) | BIT(0);
+
+	rk_setreg(&cru->softrst_con[10], ctl_reset | phy_reset);
+	udelay(1);
+	rk_clrreg(&cru->softrst_con[10], ctl_reset | phy_reset);
+}
+
+static void ddrphy_reset(struct rk3368_ddrphy *ddrphy)
+{
+	clrbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
+	udelay(1);
+	setbits_le32(&ddrphy->reg[0], BIT(3) | BIT(2));
+}
+
+static void ddrphy_config_delays(struct rk3368_ddrphy *ddrphy, u32 freq)
+{
+	u32 dqs_dll_delay;
+
+	setbits_le32(&ddrphy->reg[0x13], BIT(4));
+	clrbits_le32(&ddrphy->reg[0x14], BIT(3));
+
+	setbits_le32(&ddrphy->reg[0x26], BIT(4));
+	clrbits_le32(&ddrphy->reg[0x27], BIT(3));
+
+	setbits_le32(&ddrphy->reg[0x36], BIT(4));
+	clrbits_le32(&ddrphy->reg[0x37], BIT(3));
+
+	setbits_le32(&ddrphy->reg[0x46], BIT(4));
+	clrbits_le32(&ddrphy->reg[0x47], BIT(3));
+
+	setbits_le32(&ddrphy->reg[0x56], BIT(4));
+	clrbits_le32(&ddrphy->reg[0x57], BIT(3));
+
+	if (freq <= 400000000)
+		setbits_le32(&ddrphy->reg[0xa4], 0x1f);
+	else
+		clrbits_le32(&ddrphy->reg[0xa4], 0x1f);
+
+	if (freq < 681000000)
+		dqs_dll_delay = 3; /* 67.5 degree delay */
+	else
+		dqs_dll_delay = 2; /* 45 degree delay */
+
+	writel(dqs_dll_delay, &ddrphy->reg[0x28]);
+	writel(dqs_dll_delay, &ddrphy->reg[0x38]);
+	writel(dqs_dll_delay, &ddrphy->reg[0x48]);
+	writel(dqs_dll_delay, &ddrphy->reg[0x58]);
+}
+
+static int dfi_cfg(struct rk3368_ddr_pctl *pctl)
+{
+	const ulong timeout_ms = 200;
+	ulong tmp;
+
+	writel(DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
+
+	writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
+	       &pctl->dfistcfg1);
+	writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
+	writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
+	       &pctl->dfilpcfg0);
+
+	writel(1, &pctl->dfitphyupdtype0);
+
+	writel(0x1f, &pctl->dfitphyrdlat);
+	writel(0, &pctl->dfitphywrdata);
+	writel(0, &pctl->dfiupdcfg);  /* phyupd and ctrlupd disabled */
+
+	setbits_le32(&pctl->dfistcfg0, DFI_INIT_START);
+
+	tmp = get_timer(0);
+	do {
+		if (get_timer(tmp) > timeout_ms) {
+			error("%s: DFI init did not complete within %ld ms\n",
+			      __func__, timeout_ms);
+			return -ETIME;
+		}
+	} while ((readl(&pctl->dfiststat0) & 1) == 0);
+
+	return 0;
+}
+
+static inline u32 ps_to_tCK(const u32 ps, const ulong freq)
+{
+	const ulong MHz = 1000000;
+	return DIV_ROUND_UP(ps * freq, 1000000 * MHz);
+}
+
+static inline u32 ns_to_tCK(const u32 ns, const ulong freq)
+{
+	return ps_to_tCK(ns * 1000, freq);
+}
+
+static inline u32 tCK_to_ps(const ulong tCK, const ulong freq)
+{
+	const ulong MHz = 1000000;
+	return DIV_ROUND_UP(tCK * 1000000 * MHz, freq);
+}
+
+static int pctl_calc_timings(struct rk3368_sdram_params *params,
+			      ulong freq)
+{
+	struct rk3288_sdram_pctl_timing *pctl_timing = &params->pctl_timing;
+	const ulong MHz = 1000000;
+	u32 tccd;
+	u32 tfaw_as_ps;
+
+	if (params->ddr_speed_bin != DDR3_1600K) {
+		error("%s: unimplemented DDR3 speed bin %d\n",
+		      __func__, params->ddr_speed_bin);
+		return -1;
+	}
+
+	/* PCTL is clocked at 1/2 the DRAM clock; err on the side of caution */
+	pctl_timing->togcnt1u = DIV_ROUND_UP(freq, 2 * MHz);
+	pctl_timing->togcnt100n = DIV_ROUND_UP(freq / 10, 2 * MHz);
+
+	pctl_timing->tinit = 200;                 /* 200 usec                */
+	pctl_timing->trsth = 500;                 /* 500 usec                */
+	pctl_timing->trefi = 78;                  /* 7.8usec = 78 * 100ns    */
+	params->trefi_mem_ddr3 = ns_to_tCK(pctl_timing->trefi * 100, freq);
+
+	if (freq <= (400 * MHz)) {
+		pctl_timing->tcl = 6;
+		pctl_timing->tcwl = 10;
+	} else if (freq <= (533 * MHz)) {
+		pctl_timing->tcl = 8;
+		pctl_timing->tcwl = 6;
+	} else if (freq <= (666 * MHz)) {
+		pctl_timing->tcl = 10;
+		pctl_timing->tcwl = 7;
+	} else {
+		pctl_timing->tcl = 11;
+		pctl_timing->tcwl = 8;
+	}
+
+	pctl_timing->tmrd = 4;                    /* 4 tCK (all speed bins)  */
+	pctl_timing->trfc = ns_to_tCK(350, freq); /* tRFC: 350 (max) @ 8GBit */
+	pctl_timing->trp = max(4u, ps_to_tCK(13750, freq));
+	/*
+	 * JESD-79:
+	 *   READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
+	 */
+	tccd = 4;
+	pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
+	pctl_timing->tal = 0;
+	pctl_timing->tras = ps_to_tCK(35000, freq);
+	pctl_timing->trc = ps_to_tCK(48750, freq);
+	pctl_timing->trcd = ps_to_tCK(13750, freq);
+	pctl_timing->trrd = max(4u, ps_to_tCK(7500, freq));
+	pctl_timing->trtp = max(4u, ps_to_tCK(7500, freq));
+	pctl_timing->twr = ps_to_tCK(15000, freq);
+	/* The DDR3 mode-register does only support even values for tWR > 8. */
+	if (pctl_timing->twr > 8)
+		pctl_timing->twr = (pctl_timing->twr + 1) & ~1;
+	pctl_timing->twtr = max(4u, ps_to_tCK(7500, freq));
+	pctl_timing->texsr = 512;                 /* tEXSR(max) is tDLLLK    */
+	pctl_timing->txp = max(3u, ps_to_tCK(6000, freq));
+	pctl_timing->txpdll = max(10u, ps_to_tCK(24000, freq));
+	pctl_timing->tzqcs = max(64u, ps_to_tCK(80000, freq));
+	pctl_timing->tzqcsi = 10000;               /* as used by Rockchip    */
+	pctl_timing->tdqs = 1;                     /* fixed for DDR3         */
+	pctl_timing->tcksre = max(5u, ps_to_tCK(10000, freq));
+	pctl_timing->tcksrx = max(5u, ps_to_tCK(10000, freq));
+	pctl_timing->tcke = max(3u, ps_to_tCK(5000, freq));
+	pctl_timing->tmod = max(12u, ps_to_tCK(15000, freq));
+	pctl_timing->trstl = ns_to_tCK(100, freq);
+	pctl_timing->tzqcl = max(256u, ps_to_tCK(320000, freq));   /* tZQoper */
+	pctl_timing->tmrr = 0;
+	pctl_timing->tckesr = pctl_timing->tcke + 1;  /* JESD-79: tCKE + 1tCK */
+	pctl_timing->tdpd = 0;    /* RK3368 TRM: "allowed values for DDR3: 0" */
+
+
+	/*
+	 * The controller can represent tFAW as 4x, 5x or 6x tRRD only.
+	 * We want to use the smallest multiplier that satisfies the tFAW
+	 * requirements of the given speed-bin.  If necessary, we stretch out
+	 * tRRD to allow us to operate on a 6x multiplier for tFAW.
+	 */
+	tfaw_as_ps = 40000;      /* 40ns: tFAW for DDR3-1600K, 2KB page-size */
+	if (tCK_to_ps(pctl_timing->trrd * 6, freq) < tfaw_as_ps) {
+		/* If tFAW is > 6 x tRRD, we need to stretch tRRD */
+		pctl_timing->trrd = ps_to_tCK(DIV_ROUND_UP(40000, 6), freq);
+		params->tfaw_mult = TFAW_TRRD_MULT6;
+	} else if (tCK_to_ps(pctl_timing->trrd * 5, freq) < tfaw_as_ps) {
+		params->tfaw_mult = TFAW_TRRD_MULT6;
+	} else if (tCK_to_ps(pctl_timing->trrd * 4, freq) < tfaw_as_ps) {
+		params->tfaw_mult = TFAW_TRRD_MULT5;
+	} else {
+		params->tfaw_mult = TFAW_TRRD_MULT4;
+	}
+
+	return 0;
+}
+
+static void pctl_cfg(struct rk3368_ddr_pctl *pctl,
+		     struct rk3368_sdram_params *params,
+		     struct rk3368_grf *grf)
+{
+	/* Configure PCTL timing registers */
+	params->pctl_timing.trefi |= BIT(31);   /* see PCTL_TREFI */
+	copy_to_reg(&pctl->togcnt1u, &params->pctl_timing.togcnt1u,
+		    sizeof(params->pctl_timing));
+	writel(params->trefi_mem_ddr3, &pctl->trefi_mem_ddr3);
+
+	/* Set up ODT write selector and ODT write length */
+	writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), &pctl->dfiodtcfg);
+	writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
+
+	/* Set up the CL/CWL-dependent timings of DFI */
+	writel((params->pctl_timing.tcl - 1) / 2 - 1, &pctl->dfitrddataen);
+	writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
+
+	/* DDR3 */
+	writel(params->tfaw_mult | DDR3_EN | DDR2_DDR3_BL_8, &pctl->mcfg);
+	writel(0x001c0004, &grf->ddrc0_con0);
+
+	setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
+}
+
+static int ddrphy_data_training(struct rk3368_ddr_pctl *pctl,
+				struct rk3368_ddrphy *ddrphy)
+{
+	const u32 trefi = readl(&pctl->trefi);
+	const ulong timeout_ms = 500;
+	ulong tmp;
+
+	/* disable auto-refresh */
+	writel(0 | BIT(31), &pctl->trefi);
+
+	clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
+	clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x21);
+
+	tmp = get_timer(0);
+	do {
+		if (get_timer(tmp) > timeout_ms) {
+			error("%s: did not complete within %ld ms\n",
+			      __func__, timeout_ms);
+			return -ETIME;
+		}
+	} while ((readl(&ddrphy->reg[0xff]) & 0xf) != 0xf);
+
+	send_command(pctl, MCMD_RANK0 | MCMD_RANK1, PREA_CMD);
+	clrsetbits_le32(&ddrphy->reg[2], 0x33, 0x20);
+	/* resume auto-refresh */
+	writel(trefi | BIT(31), &pctl->trefi);
+
+	return 0;
+}
+
+static int sdram_col_row_detect(struct udevice *dev)
+{
+	struct dram_info *priv = dev_get_priv(dev);
+	struct rk3368_sdram_params *params = dev_get_platdata(dev);
+	struct rk3368_ddr_pctl *pctl = priv->pctl;
+	struct rk3368_msch *msch = priv->msch;
+	const u32 test_pattern = 0x5aa5f00f;
+	int row, col;
+	uintptr_t addr;
+
+	move_to_config_state(pctl);
+	writel(6, &msch->ddrconf);
+	move_to_access_state(pctl);
+
+	/* Detect col */
+	for (col = 11; col >= 9; col--) {
+		writel(0, CONFIG_SYS_SDRAM_BASE);
+		addr = CONFIG_SYS_SDRAM_BASE +
+			(1 << (col + params->chan.bw - 1));
+		writel(test_pattern, addr);
+		if ((readl(addr) == test_pattern) &&
+		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+			break;
+	}
+
+	if (col == 8) {
+		error("%s: col detect error\n", __func__);
+		return -EINVAL;
+	}
+
+	move_to_config_state(pctl);
+	writel(15, &msch->ddrconf);
+	move_to_access_state(pctl);
+
+	/* Detect row*/
+	for (row = 16; row >= 12; row--) {
+		writel(0, CONFIG_SYS_SDRAM_BASE);
+		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(test_pattern, addr);
+		if ((readl(addr) == test_pattern) &&
+		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+			break;
+	}
+
+	if (row == 11) {
+		error("%s: row detect error\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Record results */
+	debug("%s: col %d, row %d\n", __func__, col, row);
+	params->chan.col = col;
+	params->chan.cs0_row = row;
+	params->chan.cs1_row = row;
+	params->chan.row_3_4 = 0;
+
+	return 0;
+}
+
+static int msch_niu_config(struct rk3368_msch *msch,
+			   struct rk3368_sdram_params *params)
+{
+	int i;
+	const u8 cols =	params->chan.col - ((params->chan.bw == 2) ? 0 : 1);
+	const u8 rows = params->chan.cs0_row;
+
+	/*
+	 * The DDR address-translation table always assumes a 32bit
+	 * bus and the comparison below takes care of adjusting for
+	 * a 16bit bus (i.e. one column-address is consumed).
+	 */
+	const struct {
+		u8 rows;
+		u8 columns;
+		u8 type;
+	} ddrconf_table[] = {
+		/*
+		 * C-B-R-D patterns are first. For these we require an
+		 * exact match for the columns and rows (as there's
+		 * one entry per possible configuration).
+		 */
+		[0] =  { .rows = 13, .columns = 10, .type = DMC_MSCH_CBRD },
+		[1] =  { .rows = 14, .columns = 10, .type = DMC_MSCH_CBRD },
+		[2] =  { .rows = 15, .columns = 10, .type = DMC_MSCH_CBRD },
+		[3] =  { .rows = 16, .columns = 10, .type = DMC_MSCH_CBRD },
+		[4] =  { .rows = 14, .columns = 11, .type = DMC_MSCH_CBRD },
+		[5] =  { .rows = 15, .columns = 11, .type = DMC_MSCH_CBRD },
+		[6] =  { .rows = 16, .columns = 11, .type = DMC_MSCH_CBRD },
+		[7] =  { .rows = 13, .columns = 9, .type = DMC_MSCH_CBRD },
+		[8] =  { .rows = 14, .columns = 9, .type = DMC_MSCH_CBRD },
+		[9] =  { .rows = 15, .columns = 9, .type = DMC_MSCH_CBRD },
+		[10] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBRD },
+		/*
+		 * 11 through 13 are C-R-B-D patterns. These are
+		 * matched for an exact number of columns and to
+		 * ensure that the hardware uses at least as many rows
+		 * as the pattern requires (i.e. we make sure that
+		 * there's no gaps up until we hit the device/chip-select;
+		 * however, these patterns can accept up to 16 rows,
+		 * as the row-address continues right after the CS
+		 * switching)
+		 */
+		[11] = { .rows = 15, .columns = 10, .type = DMC_MSCH_CRBD },
+		[12] = { .rows = 14, .columns = 11, .type = DMC_MSCH_CRBD },
+		[13] = { .rows = 13, .columns = 10, .type = DMC_MSCH_CRBD },
+		/*
+		 * 14 and 15 are catch-all variants using a C-B-D-R
+		 * scheme (i.e. alternating the chip-select every time
+		 * C-B overflows) and stuffing the remaining C-bits
+		 * into the top. Matching needs to make sure that the
+		 * number of columns is either an exact match (i.e. we
+		 * can use less the the maximum number of rows) -or-
+		 * that the columns exceed what is given in this table
+		 * and the rows are an exact match (in which case the
+		 * remaining C-bits will be stuffed onto the top after
+		 * the device/chip-select switches).
+		 */
+		[14] = { .rows = 16, .columns = 10, .type = DMC_MSCH_CBDR },
+		[15] = { .rows = 16, .columns = 9, .type = DMC_MSCH_CBDR },
+	};
+
+	/*
+	 * For C-B-R-D, we need an exact match (i.e. both for the number of
+	 * columns and rows), while for C-B-D-R, only the the number of
+	 * columns needs to match.
+	 */
+	for (i = 0; i < ARRAY_SIZE(ddrconf_table); i++) {
+		bool match = false;
+
+		/* If this entry if for a different matcher, then skip it */
+		if (ddrconf_table[i].type != params->memory_schedule)
+			continue;
+
+		/*
+		 * Match according to the rules (exact/inexact/at-least)
+		 * documented in the ddrconf_table above.
+		 */
+		switch (params->memory_schedule) {
+		case DMC_MSCH_CBRD:
+			match = (ddrconf_table[i].columns == cols) &&
+				(ddrconf_table[i].rows == rows);
+			break;
+
+		case DMC_MSCH_CRBD:
+			match = (ddrconf_table[i].columns == cols) &&
+				(ddrconf_table[i].rows <= rows);
+			break;
+
+		case DMC_MSCH_CBDR:
+			match = (ddrconf_table[i].columns == cols) ||
+				((ddrconf_table[i].columns <= cols) &&
+				 (ddrconf_table[i].rows == rows));
+			break;
+
+		default:
+			break;
+		}
+
+		if (match) {
+			debug("%s: setting ddrconf 0x%x\n", __func__, i);
+			writel(i, &msch->ddrconf);
+			return 0;
+		}
+	}
+
+	error("%s: ddrconf (NIU config) not found\n", __func__);
+	return -EINVAL;
+}
+
+static void dram_all_config(struct udevice *dev)
+{
+	struct dram_info *priv = dev_get_priv(dev);
+	struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
+	struct rk3368_sdram_params *params = dev_get_platdata(dev);
+	const struct rk3288_sdram_channel *info = &params->chan;
+	u32 sys_reg = 0;
+	const int chan = 0;
+
+	sys_reg |= DDR3 << SYS_REG_DDRTYPE_SHIFT;
+	sys_reg |= 0 << SYS_REG_NUM_CH_SHIFT;
+
+	sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
+	sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
+	sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
+	sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
+	sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
+	sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
+	sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
+	sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
+	sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
+
+	writel(sys_reg, &pmugrf->os_reg[2]);
+}
+
+static int setup_sdram(struct udevice *dev)
+{
+	struct dram_info *priv = dev_get_priv(dev);
+	struct rk3368_sdram_params *params = dev_get_platdata(dev);
+
+	struct rk3368_ddr_pctl *pctl = priv->pctl;
+	struct rk3368_ddrphy *ddrphy = priv->phy;
+	struct rk3368_cru *cru = priv->cru;
+	struct rk3368_grf *grf = priv->grf;
+	struct rk3368_msch *msch = priv->msch;
+
+	int ret;
+
+	/* The input clock (i.e. DPLL) needs to be 2x the DRAM frequency */
+	ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq);
+	if (ret < 0) {
+		debug("%s: could not set DDR clock: %d\n", __func__, ret);
+		return ret;
+	}
+
+	/* Update the read-latency for the RK3368 */
+	writel(0x32, &msch->readlatency);
+
+	/* Initialise the DDR PCTL and DDR PHY */
+	ddrctl_reset(cru);
+	ddrphy_reset(ddrphy);
+	ddrphy_config_delays(ddrphy, params->ddr_freq);
+	dfi_cfg(pctl);
+	/* Configure relative system information of grf_ddrc0_con0 register */
+	ddr_set_ddr3_mode(grf, true);
+	ddr_set_noc_spr_err_stall(grf, true);
+	/* Calculate timings */
+	pctl_calc_timings(params, params->ddr_freq);
+	/* Initialise the device timings in protocol controller */
+	pctl_cfg(pctl, params, grf);
+	/* Configure AL, CL ... information of PHY registers */
+	ddrphy_config(ddrphy,
+		      params->pctl_timing.tcl,
+		      params->pctl_timing.tal,
+		      params->pctl_timing.tcwl);
+
+	/* Initialize DRAM and configure with mode-register values */
+	ret = memory_init(pctl, params);
+	if (ret)
+		goto error;
+
+	move_to_config_state(pctl);
+	/* Perform data-training */
+	ddrphy_data_training(pctl, ddrphy);
+	move_to_access_state(pctl);
+
+	/* TODO(prt): could detect rank in training... */
+	params->chan.rank = 2;
+	/* TODO(prt): bus width is not auto-detected (yet)... */
+	params->chan.bw = 2;  /* 32bit wide bus */
+	params->chan.dbw = params->chan.dbw;  /* 32bit wide bus */
+
+	/* DDR3 is always 8 bank */
+	params->chan.bk = 3;
+	/* Detect col and row number */
+	ret = sdram_col_row_detect(dev);
+	if (ret)
+		goto error;
+
+	/* Configure NIU DDR configuration */
+	ret = msch_niu_config(msch, params);
+	if (ret)
+		goto error;
+
+	/* set up OS_REG to communicate w/ next stage and OS */
+	dram_all_config(dev);
+
+	return 0;
+
+error:
+	printf("DRAM init failed!\n");
+	hang();
+}
+#endif
+
+static int rk3368_dmc_ofdata_to_platdata(struct udevice *dev)
+{
+	int ret = 0;
+
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+
+	ret = regmap_init_mem(dev, &plat->map);
+	if (ret)
+		return ret;
+#endif
+
+	return ret;
+}
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int conv_of_platdata(struct udevice *dev)
+{
+	struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+	struct dtd_rockchip_rk3368_dmc *of_plat = &plat->of_plat;
+	int ret;
+
+	plat->ddr_freq = of_plat->rockchip_ddr_frequency;
+	plat->ddr_speed_bin = of_plat->rockchip_ddr_speed_bin;
+	plat->memory_schedule = of_plat->rockchip_memory_schedule;
+
+	ret = regmap_init_mem_platdata(dev, of_plat->reg,
+				       ARRAY_SIZE(of_plat->reg) / 2,
+				       &plat->map);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+#endif
+
+static int rk3368_dmc_probe(struct udevice *dev)
+{
+#ifdef CONFIG_TPL_BUILD
+	struct rk3368_sdram_params *plat = dev_get_platdata(dev);
+	struct rk3368_ddr_pctl *pctl;
+	struct rk3368_ddrphy *ddrphy;
+	struct rk3368_cru *cru;
+	struct rk3368_grf *grf;
+	struct rk3368_msch *msch;
+	int ret;
+	struct udevice *dev_clk;
+#endif
+	struct dram_info *priv = dev_get_priv(dev);
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	ret = conv_of_platdata(dev);
+	if (ret)
+		return ret;
+#endif
+
+	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+	debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
+
+#ifdef CONFIG_TPL_BUILD
+	pctl = regmap_get_range(plat->map, 0);
+	ddrphy = regmap_get_range(plat->map, 1);
+	msch = syscon_get_first_range(ROCKCHIP_SYSCON_MSCH);
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+	priv->pctl = pctl;
+	priv->phy = ddrphy;
+	priv->msch = msch;
+	priv->grf = grf;
+
+	ret = rockchip_get_clk(&dev_clk);
+	if (ret)
+		return ret;
+	priv->ddr_clk.id = CLK_DDR;
+	ret = clk_request(dev_clk, &priv->ddr_clk);
+	if (ret)
+		return ret;
+
+	cru = rockchip_get_cru();
+	priv->cru = cru;
+	if (IS_ERR(priv->cru))
+		return PTR_ERR(priv->cru);
+
+	ret = setup_sdram(dev);
+	if (ret)
+		return ret;
+#endif
+
+	priv->info.base = 0;
+	priv->info.size =
+		rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
+
+	/*
+	* we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff
+	* is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is
+	* inaccessible for some IP controller.
+	*/
+	priv->info.size = min(priv->info.size, (size_t)0xfe000000);
+
+	return 0;
+}
+
+static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+	struct dram_info *priv = dev_get_priv(dev);
+
+	*info = priv->info;
+	return 0;
+}
+
+static struct ram_ops rk3368_dmc_ops = {
+	.get_info = rk3368_dmc_get_info,
+};
+
+
+static const struct udevice_id rk3368_dmc_ids[] = {
+	{ .compatible = "rockchip,rk3368-dmc" },
+	{ }
+};
+
+U_BOOT_DRIVER(dmc_rk3368) = {
+	.name = "rockchip_rk3368_dmc",
+	.id = UCLASS_RAM,
+	.of_match = rk3368_dmc_ids,
+	.ops = &rk3368_dmc_ops,
+	.probe = rk3368_dmc_probe,
+	.priv_auto_alloc_size = sizeof(struct dram_info),
+	.ofdata_to_platdata = rk3368_dmc_ofdata_to_platdata,
+	.probe = rk3368_dmc_probe,
+	.priv_auto_alloc_size = sizeof(struct dram_info),
+	.platdata_auto_alloc_size = sizeof(struct rk3368_sdram_params),
+};
diff --git a/include/dt-bindings/memory/rk3368-dmc.h b/include/dt-bindings/memory/rk3368-dmc.h
new file mode 100644
index 0000000..b06ffde
--- /dev/null
+++ b/include/dt-bindings/memory/rk3368-dmc.h
@@ -0,0 +1,30 @@
+#ifndef DT_BINDINGS_RK3368_DMC_H
+#define DT_BINDINGS_RK3368_DMC_H
+
+#define DMC_MSCH_CBDR       0x0
+#define DMC_MSCH_CBRD       0x1
+#define DMC_MSCH_CRBD       0x2
+
+#define DDR3_800D 0
+#define DDR3_800E 1
+#define DDR3_1066E 2
+#define DDR3_1066F 3
+#define DDR3_1066G 4
+#define DDR3_1333F 5
+#define DDR3_1333G 6
+#define DDR3_1333H 7
+#define DDR3_1333J 8
+#define DDR3_1600G 9
+#define DDR3_1600H 10
+#define DDR3_1600J 11
+#define DDR3_1600K 12
+#define DDR3_1866J 13
+#define DDR3_1866K 14
+#define DDR3_1866L 15
+#define DDR3_1866M 16
+#define DDR3_2133K 17
+#define DDR3_2133L 18
+#define DDR3_2133M 19
+#define DDR3_2133N 20
+
+#endif
-- 
2.1.4

[U-Boot] [PATCH v2 47/56] rockchip: dts: rk3368: add DMC node in rk3368.dtsi

[Philipp Tomsich]

For full SPL support, including DRAM initialisation, we need a few
nodes from the DTS: this commit adds the DMC (DRAM controller) node,
the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
as 'u-boot,dm-pre-reloc'.  In addition to this, we also include the
dt-binding for the DMC to allow DTS files including this DTSI to refer
to the symbolic constants for the DDR3 bin and for the
memory-schedule.

Note that the DMC contains both the memory regions for the
(Designware) protocol controller as well as the DDR PHY.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi

 arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 9daf765..163d9ee 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -46,6 +46,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/memory/rk3368-dmc.h>
 
 / {
 	compatible = "rockchip,rk3368";
@@ -227,6 +228,22 @@
 		#clock-cells = <0>;
 	};
 
+	dmc: dmc at ff610000 {
+		compatible = "rockchip,rk3368-dmc", "syscon";
+		rockchip,cru = <&cru>;
+		rockchip,grf = <&grf>;
+		rockchip,msch = <&service_msch>;
+		reg = <0 0xff610000 0 0x400
+		       0 0xff620000 0 0x400>;
+	};
+
+	service_msch: syscon at ffac0000 {
+		u-boot,dm-pre-reloc;
+		compatible = "rockchip,rk3368-msch", "syscon";
+		reg = <0x0 0xffac0000 0x0 0x2000>;
+		status = "okay";
+	};
+
 	sdmmc: dwmmc at ff0c0000 {
 		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xff0c0000 0x0 0x4000>;
@@ -546,12 +563,6 @@
 		status = "disabled";
 	};
 
-	dmc: dmc at ff610000 {
-		u-boot,dm-pre-reloc;
-		compatible = "rockchip,rk3368-dmc", "syscon";
-		reg = <0x0 0xff610000 0x0 0x1000>;
-	};
-
 	i2c0: i2c at ff650000 {
 		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 		reg = <0x0 0xff650000 0x0 0x1000>;
@@ -653,6 +664,7 @@
 	};
 
 	cru: clock-controller at ff760000 {
+		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3368-cru";
 		reg = <0x0 0xff760000 0x0 0x1000>;
 		rockchip,grf = <&grf>;
@@ -661,6 +673,7 @@
 	};
 
 	grf: syscon at ff770000 {
+		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3368-grf", "syscon";
 		reg = <0x0 0xff770000 0x0 0x1000>;
 	};
-- 
2.1.4

[U-Boot] [PATCH v2 48/56] rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h

[Philipp Tomsich]

To build TPL and SPL stages for the RK3368, we will also need to
enable the SPL_FRAMEWORK.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 2
- dropped duplicate definition (this in fact dropped one of the
  patches in this series) of CONFIG_SYS_SDRAM_BASE from
  rk3368_common.h

---

Changes in v2: None

 include/configs/rk3368_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
index e35f4c0..678f40d 100644
--- a/include/configs/rk3368_common.h
+++ b/include/configs/rk3368_common.h
@@ -23,6 +23,7 @@
 
 #define COUNTER_FREQUENCY               24000000
 
+#define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SYS_NS16550_MEM32
 
 #define CONFIG_SYS_TEXT_BASE		0x00200000
-- 
2.1.4

[U-Boot] [PATCH v2 49/56] rockchip: rk3368: spl: add TPL support

[Philipp Tomsich]

This adds the TPL support for the RK3368, including the u-boot-tpl.lds.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- copies the enum for the IOMUX config of the debug UART into the TPL
  support code, as the various constants are otherwise private to the
  pinctrl code (and we can't include pinctrl in the TPL stage due to
  size constraints/dependencies)

 arch/arm/mach-rockchip/Makefile              |   1 +
 arch/arm/mach-rockchip/rk3368-board-tpl.c    | 168 +++++++++++++++++++++++++++
 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds |  13 +++
 3 files changed, 182 insertions(+)
 create mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c
 create mode 100644 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 633c91e..960f40f 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -12,6 +12,7 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
 obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
 
 obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
+obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
 
 obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c
new file mode 100644
index 0000000..04620e1
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ARMv8 generic timer uses the STIMER1 as its clock-source.
+ * Set up the STIMER1 to free-running (i.e. auto-reload) to start
+ * the generic timer counting (if we don't do this, udelay will not
+ * work and block indefinitively).
+ */
+static void secure_timer_init(void)
+{
+	struct rk_timer * const stimer1 =
+		(struct rk_timer * const)0xff830020;
+	const u32 TIMER_EN = BIT(0);
+
+	writel(~0u, &stimer1->timer_load_count0);
+	writel(~0u, &stimer1->timer_load_count1);
+	writel(TIMER_EN, &stimer1->timer_ctrl_reg);
+}
+
+/*
+ * The SPL (and also the full U-Boot stage on the RK3368) will run in
+ * secure mode (i.e. EL3) and an ATF will eventually be booted before
+ * starting up the operating system... so we can initialize the SGRF
+ * here and rely on the ATF installing the final (secure) policy
+ * later.
+ */
+static inline uintptr_t sgrf_soc_con_addr(unsigned no)
+{
+	const uintptr_t SGRF_BASE = 0xff740000;
+
+	return SGRF_BASE + sizeof(u32) * no;
+}
+
+static inline uintptr_t sgrf_busdmac_addr(unsigned no)
+{
+	const uintptr_t SGRF_BUSDMAC_BASE = 0xff740100;
+
+	return SGRF_BUSDMAC_BASE + sizeof(u32) * no;
+}
+
+static void sgrf_init(void)
+{
+	struct rk3368_cru * const cru =
+		(struct rk3368_cru * const)0xff760000;
+	const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0);
+	const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2);
+	const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12);
+
+	/* Set all configurable IP to 'non secure'-mode */
+	rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC);
+	rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC);
+	rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC);
+
+	/*
+	 * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c
+	 * Original comment: "ddr space set no secure mode"
+	 */
+	rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC);
+	rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC);
+	rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC);
+
+	/* Set 'secure dma' to 'non secure'-mode */
+	rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC);
+	rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC);
+
+	dsb();  /* barrier */
+
+	rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+	rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+
+	dsb();  /* barrier */
+	udelay(10);
+
+	rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ);
+	rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ);
+}
+
+void board_debug_uart_init(void)
+{
+	struct rk3368_grf * const grf =
+		(struct rk3368_grf * const)0xff770000;
+
+	enum {
+		GPIO2D1_MASK            = GENMASK(3, 2),
+		GPIO2D1_GPIO            = 0,
+		GPIO2D1_UART0_SOUT      = (1 << 2),
+
+		GPIO2D0_MASK            = GENMASK(1, 0),
+		GPIO2D0_GPIO            = 0,
+		GPIO2D0_UART0_SIN       = (1 << 0),
+	};
+
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
+	/* Enable early UART0 on the RK3368 */
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D0_MASK, GPIO2D0_UART0_SIN);
+	rk_clrsetreg(&grf->gpio2d_iomux,
+		     GPIO2D1_MASK, GPIO2D1_UART0_SOUT);
+#endif
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *dev;
+	int ret;
+
+#define EARLY_UART
+#ifdef EARLY_UART
+	/*
+	 * Debug UART can be used from here if required:
+	 *
+	 * debug_uart_init();
+	 * printch('a');
+	 * printhex8(0x1234);
+	 * printascii("string");
+	 */
+	debug_uart_init();
+	printascii("U-Boot TPL board init\n");
+#endif
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	/* Make sure the ARMv8 generic timer counts */
+	secure_timer_init();
+	/* Reset security, so we can use DMA in the MMC drivers */
+	sgrf_init();
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return;
+	}
+}
+
+void board_return_to_bootrom(void)
+{
+	back_to_bootrom();
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
diff --git a/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds b/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
new file mode 100644
index 0000000..cc59844
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
@@ -0,0 +1,13 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#undef CONFIG_SPL_TEXT_BASE
+#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE
+
+#undef CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE
+
+#include "../../cpu/armv8/u-boot-spl.lds"
-- 
2.1.4

[U-Boot] [PATCH v2 50/56] rockchip: spl: make spl-boot-order code reusable (split from rk3399)

[Philipp Tomsich]

In order to reuse the support for the u-boot,spl-boot-order property
from the rk3399, we split it into a reusable module that can be
included by the SPL code for any of our boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- added in v2

 arch/arm/mach-rockchip/Makefile           |   2 +-
 arch/arm/mach-rockchip/rk3399-board-spl.c | 104 ----------------------------
 arch/arm/mach-rockchip/spl-boot-order.c   | 108 ++++++++++++++++++++++++++++++
 3 files changed, 109 insertions(+), 105 deletions(-)
 create mode 100644 arch/arm/mach-rockchip/spl-boot-order.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 960f40f..c5d17f9 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -19,7 +19,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
 
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
 obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c
index 710f7fe..a13b717 100644
--- a/arch/arm/mach-rockchip/rk3399-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3399-board-spl.c
@@ -8,9 +8,6 @@
 #include <debug_uart.h>
 #include <dm.h>
 #include <fdtdec.h>
-#include <led.h>
-#include <malloc.h>
-#include <mmc.h>
 #include <ram.h>
 #include <spl.h>
 #include <asm/gpio.h>
@@ -21,111 +18,10 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/timer.h>
 #include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
 #include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static int spl_node_to_boot_device(int node)
-{
-	struct udevice *parent;
-
-	/*
-	 * This should eventually move into the SPL code, once SPL becomes
-	 * aware of the block-device layer.  Until then (and to avoid unneeded
-	 * delays in getting this feature out, it lives at the board-level).
-	 */
-	if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
-		struct udevice *dev;
-		struct blk_desc *desc = NULL;
-
-		for (device_find_first_child(parent, &dev);
-		     dev;
-		     device_find_next_child(&dev)) {
-			if (device_get_uclass_id(dev) == UCLASS_BLK) {
-				desc = dev_get_uclass_platdata(dev);
-				break;
-			}
-		}
-
-		if (!desc)
-			return -ENOENT;
-
-		switch (desc->devnum) {
-		case 0:
-			return BOOT_DEVICE_MMC1;
-		case 1:
-			return BOOT_DEVICE_MMC2;
-		default:
-			return -ENOSYS;
-		}
-	}
-
-	/*
-	 * SPL doesn't differentiate SPI flashes, so we keep the detection
-	 * brief and inaccurate... hopefully, the common SPL layer can be
-	 * extended with awareness of the BLK layer (and matching OF_CONTROL)
-	 * soon.
-	 */
-	if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
-		return BOOT_DEVICE_SPI;
-
-	return -1;
-}
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	const void *blob = gd->fdt_blob;
-	int chosen_node = fdt_path_offset(blob, "/chosen");
-	int idx = 0;
-	int elem;
-	int boot_device;
-	int node;
-	const char *conf;
-
-	if (chosen_node < 0) {
-		debug("%s: /chosen not found, using spl_boot_device()\n",
-		      __func__);
-		spl_boot_list[0] = spl_boot_device();
-		return;
-	}
-
-	for (elem = 0;
-	     (conf = fdt_stringlist_get(blob, chosen_node,
-					"u-boot,spl-boot-order", elem, NULL));
-	     elem++) {
-		/* First check if the list element is an alias */
-		const char *alias = fdt_get_alias(blob, conf);
-		if (alias)
-			conf = alias;
-
-		/* Try to resolve the config item (or alias) as a path */
-		node = fdt_path_offset(blob, conf);
-		if (node < 0) {
-			debug("%s: could not find %s in FDT", __func__, conf);
-			continue;
-		}
-
-		/* Try to map this back onto SPL boot devices */
-		boot_device = spl_node_to_boot_device(node);
-		if (boot_device < 0) {
-			debug("%s: could not map node @%x to a boot-device\n",
-			      __func__, node);
-			continue;
-		}
-
-		spl_boot_list[idx++] = boot_device;
-	}
-
-	/* If we had no matches, fall back to spl_boot_device */
-	if (idx == 0)
-		spl_boot_list[0] = spl_boot_device();
-}
-#endif
-
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_MMC1;
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
new file mode 100644
index 0000000..4f78c72
--- /dev/null
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mmc.h>
+#include <spl.h>
+
+#if CONFIG_IS_ENABLED(OF_CONTROL)
+static int spl_node_to_boot_device(int node)
+{
+	struct udevice *parent;
+
+	/*
+	 * This should eventually move into the SPL code, once SPL becomes
+	 * aware of the block-device layer.  Until then (and to avoid unneeded
+	 * delays in getting this feature out, it lives at the board-level).
+	 */
+	if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
+		struct udevice *dev;
+		struct blk_desc *desc = NULL;
+
+		for (device_find_first_child(parent, &dev);
+		     dev;
+		     device_find_next_child(&dev)) {
+			if (device_get_uclass_id(dev) == UCLASS_BLK) {
+				desc = dev_get_uclass_platdata(dev);
+				break;
+			}
+		}
+
+		if (!desc)
+			return -ENOENT;
+
+		switch (desc->devnum) {
+		case 0:
+			return BOOT_DEVICE_MMC1;
+		case 1:
+			return BOOT_DEVICE_MMC2;
+		default:
+			return -ENOSYS;
+		}
+	}
+
+	/*
+	 * SPL doesn't differentiate SPI flashes, so we keep the detection
+	 * brief and inaccurate... hopefully, the common SPL layer can be
+	 * extended with awareness of the BLK layer (and matching OF_CONTROL)
+	 * soon.
+	 */
+	if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent))
+		return BOOT_DEVICE_SPI;
+
+	return -1;
+}
+
+void board_boot_order(u32 *spl_boot_list)
+{
+	const void *blob = gd->fdt_blob;
+	int chosen_node = fdt_path_offset(blob, "/chosen");
+	int idx = 0;
+	int elem;
+	int boot_device;
+	int node;
+	const char *conf;
+
+	if (chosen_node < 0) {
+		debug("%s: /chosen not found, using spl_boot_device()\n",
+		      __func__);
+		spl_boot_list[0] = spl_boot_device();
+		return;
+	}
+
+	for (elem = 0;
+	     (conf = fdt_stringlist_get(blob, chosen_node,
+					"u-boot,spl-boot-order", elem, NULL));
+	     elem++) {
+		/* First check if the list element is an alias */
+		const char *alias = fdt_get_alias(blob, conf);
+		if (alias)
+			conf = alias;
+
+		/* Try to resolve the config item (or alias) as a path */
+		node = fdt_path_offset(blob, conf);
+		if (node < 0) {
+			debug("%s: could not find %s in FDT", __func__, conf);
+			continue;
+		}
+
+		/* Try to map this back onto SPL boot devices */
+		boot_device = spl_node_to_boot_device(node);
+		if (boot_device < 0) {
+			debug("%s: could not map node @%x to a boot-device\n",
+			      __func__, node);
+			continue;
+		}
+
+		spl_boot_list[idx++] = boot_device;
+	}
+
+	/* If we had no matches, fall back to spl_boot_device */
+	if (idx == 0)
+		spl_boot_list[0] = spl_boot_device();
+}
+#endif
-- 
2.1.4

[U-Boot] [PATCH v2 51/56] rockchip: rk3368: spl: add SPL support

[Philipp Tomsich]

Adds SPL support for the RK3368 (assuming that our TPL stage has
initialised DRAM and set up the memory firewall).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- reuses the support for configuring the boot order using the
  u-boot,spl-boot-order property
- drops the initialisation of the debug_uart
- adds pinctrl-configuration for the preloader UART

 arch/arm/mach-rockchip/Makefile           |  2 +-
 arch/arm/mach-rockchip/rk3368-board-spl.c | 98 +++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index c5d17f9..c3ed862 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -18,7 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
-obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
+obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
 obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
 
 ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c
new file mode 100644
index 0000000..691db41
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3368-board-spl.c
@@ -0,0 +1,98 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/timer.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ARMv8 generic timer uses the STIMER1 as its clock-source.
+ * Set up the STIMER1 to free-running (i.e. auto-reload) to start
+ * the generic timer counting (if we don't do this, udelay will not
+ * work and block indefinitively).
+ */
+static void secure_timer_init(void)
+{
+	struct rk_timer * const stimer1 =
+		(struct rk_timer * const)0xff830020;
+	const u32 TIMER_EN = BIT(0);
+
+	writel(~0u, &stimer1->timer_load_count0);
+	writel(~0u, &stimer1->timer_load_count1);
+	writel(TIMER_EN, &stimer1->timer_ctrl_reg);
+}
+
+void board_debug_uart_init(void)
+{
+}
+
+void board_init_f(ulong dummy)
+{
+	struct udevice *pinctrl;
+	struct udevice *dev;
+	int ret;
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	/* Make sure the ARMv8 generic timer counts */
+	secure_timer_init();
+
+	/* Set up our preloader console */
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		error("%s: pinctrl init failed: %d\n", __func__, ret);
+		hang();
+	}
+
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
+	if (ret) {
+		error("%s: failed to set up console UART\n", __func__);
+		hang();
+	}
+
+	preloader_console_init();
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret) {
+		debug("DRAM init failed: %d\n", ret);
+		return;
+	}
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+	return MMCSD_MODE_RAW;
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_MMC1;
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
-- 
2.1.4

[U-Boot] [PATCH v2 52/56] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368

[Philipp Tomsich]

With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
supported from Kconfig for the RK3368.  As this is primarily tested on
the RK3368-uQ7, we'll leave it to board's individual defconfig to
enable.

Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
during the early boot-up, as we turn on TPL and SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 arch/arm/mach-rockchip/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 2ad4943..fd08897 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -67,6 +67,13 @@ config ROCKCHIP_RK3328
 config ROCKCHIP_RK3368
 	bool "Support Rockchip RK3368"
 	select ARM64
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SPL_SEPARATE_BSS
+	select SPL_SERIAL_SUPPORT
+	select TPL_SERIAL_SUPPORT
+	select ENABLE_ARM_SOC_BOOT0_HOOK
+	select DEBUG_UART_BOARD_INIT
 	select SYS_NS16550
 	help
 	  The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
-- 
2.1.4

[U-Boot] [PATCH v2 53/56] rockchip: spi: enable support for the rk_spi driver for the RK3368

[Philipp Tomsich]

For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.

Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Version-changes: 2
- added in this version

---

Changes in v2: None

 drivers/spi/rk_spi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 7921ea0..c70d636 100644
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -210,6 +210,14 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 
 static int rockchip_spi_calc_modclk(ulong max_freq)
 {
+	/*
+	 * While this is not strictly correct for the RK3368, as the
+	 * GPLL will be 576MHz, things will still work, as the
+	 * clk_set_rate(...) implementation in our clock-driver will
+	 * chose the next closest rate not exceeding what we request
+	 * based on the output of this function.
+	 */
+
 	unsigned div;
 	const unsigned long gpll_hz = 594000000UL;
 
@@ -443,6 +451,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
 
 static const struct udevice_id rockchip_spi_ids[] = {
 	{ .compatible = "rockchip,rk3288-spi" },
+	{ .compatible = "rockchip,rk3368-spi" },
 	{ .compatible = "rockchip,rk3399-spi" },
 	{ }
 };
-- 
2.1.4

[U-Boot] [PATCH v2 54/56] rockchip: board: lion-rk3368: add support for the RK3368-uQ7

[Philipp Tomsich]

The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
MXM-230 edge connector compatible with the Qseven specification)
form-factor system-on-module based on the octo-core Rockchip RK3368.
It is designed, supported and manufactured by Theobroma Systems.

It provides the following features:
 - 8x Cortex-A53 (in 2 clusters of 4 cores each)
 - (on-module) up to 4GB of DDR3 memory
 - (on-module) SPI-NOR flash
 - (on-module) eMMC
 - Gigabit Ethernet (with an on-module KSZ9031 PHY)
 - USB
 - HDMI
 - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
 - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- marks pinctrl-node as 'u-boot,dm-pre-reloc' to ensure MMC2 (eMMC)
  works in the SPL stage
- makes uart0 as 'u-boot,dm-pre-reloc' to allow initialising the
  preloader console (instead of relying solely on the debug UART)
- adds support for SPI1 (and the on-module SPI flash)
- splits the a 'u-boot.dtsi' off the DTS file
- updates the defconfig for SPI and SPI flash support

 arch/arm/dts/Makefile                              |   1 +
 arch/arm/dts/rk3368-lion-u-boot.dtsi               |  68 +++++++
 arch/arm/dts/rk3368-lion.dts                       | 195 +++++++++++++++++++++
 arch/arm/mach-rockchip/rk3368/Kconfig              |  21 +++
 board/theobroma-systems/lion_rk3368/Kconfig        |  15 ++
 board/theobroma-systems/lion_rk3368/MAINTAINERS    |  10 ++
 board/theobroma-systems/lion_rk3368/Makefile       |   7 +
 board/theobroma-systems/lion_rk3368/README         |  60 +++++++
 .../theobroma-systems/lion_rk3368/fit_spl_atf.its  |  51 ++++++
 board/theobroma-systems/lion_rk3368/lion_rk3368.c  |  25 +++
 configs/lion-rk3368_defconfig                      |  88 ++++++++++
 include/configs/lion_rk3368.h                      |  19 ++
 12 files changed, 560 insertions(+)
 create mode 100644 arch/arm/dts/rk3368-lion-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3368-lion.dts
 create mode 100644 board/theobroma-systems/lion_rk3368/Kconfig
 create mode 100644 board/theobroma-systems/lion_rk3368/MAINTAINERS
 create mode 100644 board/theobroma-systems/lion_rk3368/Makefile
 create mode 100644 board/theobroma-systems/lion_rk3368/README
 create mode 100644 board/theobroma-systems/lion_rk3368/fit_spl_atf.its
 create mode 100644 board/theobroma-systems/lion_rk3368/lion_rk3368.c
 create mode 100644 configs/lion-rk3368_defconfig
 create mode 100644 include/configs/lion_rk3368.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index fd28290..5a22bb1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-veyron-mickey.dtb \
 	rk3288-veyron-minnie.dtb \
 	rk3328-evb.dtb \
+	rk3368-lion.dtb \
 	rk3368-sheep.dtb \
 	rk3368-geekbox.dtb \
 	rk3368-px5-evb.dtb \
diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi
new file mode 100644
index 0000000..1f9ade9
--- /dev/null
+++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi
@@ -0,0 +1,68 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+	X11
+ */
+
+/ {
+	config {
+		u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
+		u-boot,mmc-env-offset = <0x4000>;      /* @  16KB */
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		u-boot,spl-boot-order = &emmc, &sdmmc;
+	};
+
+};
+
+&pinctrl {
+	 u-boot,dm-pre-reloc;
+};
+
+&dmc {
+	 u-boot,dm-pre-reloc;
+
+	/*
+	 * Validation of throughput using SPEC2000 shows the following
+	 * relative performance for the different memory schedules:
+	 *  - CBDR: 30.1
+	 *  - CBRD: 29.8
+	 *  - CRBD: 29.9
+	 * Note that the best performance for any given application workload
+	 * may vary from the default configured here (e.g. 164.gzip is fastest
+	 * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
+	 *
+	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
+	 * details on the 'rockchip,memory-schedule' property and how it
+	 * affects the physical-address to device-address mapping.
+	 */
+	rockchip,memory-schedule = <DMC_MSCH_CBDR>;
+	rockchip,ddr-frequency = <800000000>;
+	rockchip,ddr-speed-bin = <DDR3_1600K>;
+
+	status = "okay";
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};
+
+&spi1 {
+	u-boot,dm-pre-reloc;
+
+	spiflash: w25q32dw at 0 {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+
diff --git a/arch/arm/dts/rk3368-lion.dts b/arch/arm/dts/rk3368-lion.dts
new file mode 100644
index 0000000..850db50
--- /dev/null
+++ b/arch/arm/dts/rk3368-lion.dts
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+	X11
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include "rk3368-lion-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Theobroma Systems RK3368-uQ7 SoM";
+	compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
+
+	aliases {
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
+	};
+
+	memory at 0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+
+	ext_gmac: gmac-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "ext_gmac";
+		#clock-cells = <0>;
+	};
+
+	vcc_sys: vcc-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_sys";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&emmc {
+	status = "okay";
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	clock-frequency = <150000000>;
+	disable-wp;
+	keep-power-in-suspend;
+	non-removable;
+	num-slots = <1>;
+	vmmc-supply = <&vcc33_io>;
+	vqmmc-supply = <&vcc18_io>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+};
+
+&sdmmc {
+	status = "okay";
+};
+
+&gmac {
+	status = "okay";
+	phy-supply = <&vcc33_io>;
+	phy-mode = "rgmii";
+	clock_in_out = "input";
+	snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	snps,reset-delays-us = <2 10000 50000>;
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>;
+	tx_delay = <0x10>;
+	rx_delay = <0x10>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	rk808: pmic at 1b {
+		compatible = "rockchip,rk808";
+		reg = <0x1b>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+		rockchip,system-power-controller;
+		vcc1-supply = <&vcc_sys>;
+		vcc2-supply = <&vcc_sys>;
+		vcc3-supply = <&vcc_sys>;
+		vcc4-supply = <&vcc_sys>;
+		vcc6-supply = <&vcc_sys>;
+		vcc7-supply = <&vcc_sys>;
+		vcc8-supply = <&vcc_sys>;
+		vcc9-supply = <&vcc_sys>;
+		vcc10-supply = <&vcc_sys>;
+		vcc11-supply = <&vcc_sys>;
+		vcc12-supply = <&vcc_sys>;
+		clock-output-names = "xin32k", "rk808-clkout2";
+		#clock-cells = <1>;
+
+		regulators {
+			vdd_cpu: DCDC_REG1 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vdd_cpu";
+			};
+
+			vdd_log: DCDC_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1500000>;
+				regulator-name = "vdd_log";
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-name = "vcc_ddr";
+			};
+
+			vcc33_io: DCDC_REG4 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc33_io";
+			};
+
+			vcc33_video: LDO_REG2 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-name = "vcc33_video";
+			};
+
+			vdd10_pll: LDO_REG3 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd10_pll";
+			};
+
+			vcc18_io: LDO_REG4 {
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc18_io";
+			};
+
+			vdd10_video: LDO_REG6 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-name = "vdd10_video";
+			};
+
+			vcc18_video: LDO_REG8 {
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-name = "vcc18_video";
+			};
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi1 {
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	spiflash: w25q32dw at 0 {
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <49500000>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index 6d32068..f8189f1 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -3,6 +3,26 @@ if ROCKCHIP_RK3368
 choice
 	prompt "RK3368 board"
 
+config TARGET_LION_RK3368
+        bool "Theobroma Systems RK3368-uQ7 (Lion) module"
+	help
+	  The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm,
+	  MXM-230 connector) system-on-module designed by Theobroma
+	  Systems for industrial applications.
+
+	  It provides the following features:
+	   - 8x Cortex-A53 (in 2 clusters of 4 cores each)
+	   - (on-module) up to 4GB of DDR3 memory
+	   - (on-module) SPI-NOR flash
+	   - (on-module) eMMC
+	   - Gigabit Ethernet (with an on-module KSZ9031 PHY)
+	   - USB
+	   - HDMI
+	   - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
+	   - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
+	   - on-module STM32 providing CAN, RTC and fan-control
+	   - (optional on-module) EAL4+-certified security module
+
 config TARGET_SHEEP
 	bool "Sheep board"
 	help
@@ -25,6 +45,7 @@ endchoice
 config SYS_SOC
 	default "rockchip"
 
+source "board/theobroma-systems/lion_rk3368/Kconfig"
 source "board/rockchip/sheep_rk3368/Kconfig"
 source "board/geekbuying/geekbox/Kconfig"
 source "board/rockchip/evb_px5/Kconfig"
diff --git a/board/theobroma-systems/lion_rk3368/Kconfig b/board/theobroma-systems/lion_rk3368/Kconfig
new file mode 100644
index 0000000..d7aa487
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LION_RK3368
+
+config SYS_BOARD
+	default "lion_rk3368"
+
+config SYS_VENDOR
+	default "theobroma-systems"
+
+config SYS_CONFIG_NAME
+	default "lion_rk3368"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+
+endif
diff --git a/board/theobroma-systems/lion_rk3368/MAINTAINERS b/board/theobroma-systems/lion_rk3368/MAINTAINERS
new file mode 100644
index 0000000..857f784
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/MAINTAINERS
@@ -0,0 +1,10 @@
+LION-RK3368 (RK3368-uQ7 system-on-module)
+M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M:	Klaus Goger <klaus.goger@theobroma-systems.com>
+S:	Maintained
+F:	board/theobroma-systems/lion_rk3368
+F:	include/configs/lion_rk3368.h
+F:	arch/arm/dts/rk3368-lion.dts
+F:	configs/lion-rk3368_defconfig
+W:	https://www.theobroma-systems.com/rk3368-uq7/tech-specs
+T:	git git://git.theobroma-systems.com/lion-u-boot.git
diff --git a/board/theobroma-systems/lion_rk3368/Makefile b/board/theobroma-systems/lion_rk3368/Makefile
new file mode 100644
index 0000000..f13a20b
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += lion_rk3368.o
diff --git a/board/theobroma-systems/lion_rk3368/README b/board/theobroma-systems/lion_rk3368/README
new file mode 100644
index 0000000..47304fc
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/README
@@ -0,0 +1,60 @@
+Here is the step-by-step to boot to U-Boot on RK3368-uQ7
+
+Get the Source and build ATF
+============================
+
+  > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
+  > cd arm-trusted-firmware
+  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3368 bl31
+  > cp build/rk3368/release/bl31.bin ../u-boot/bl31-rk3368.bin
+
+Configure U-Boot
+================
+
+  > cd ../u-boot
+  > make lion-rk3368_defconfig
+
+Build the TPL/SPL stage
+=======================
+
+  > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm
+  > tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img
+  > cat spl/u-boot-spl-dtb.bin >> spl-3368.img
+
+Build the full U-Boot and a FIT image including the ATF
+=======================================================
+
+  > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm u-boot.itb
+
+Write to a SD-card
+==================
+
+  > dd if=spl-3368.img of=/dev/sdb seek=64
+  > dd if=u-boot.itb of=/dev/sdb seek=512
+
+
+If everything went according to plan, you should see the following
+output on UART0:
+
+<debug_uart> U-Boot TPL board init
+Trying to boot from BOOTROM
+Returning to boot ROM...
+Trying to boot from MMC1
+NOTICE:  BL31: v1.3(release):v1.2-1320-gbf43a443
+NOTICE:  BL31: Built : 18:04:47, Jul  5 2017
+
+
+U-Boot 2017.07-00158-g2395e99858 (Jul 18 2017 - 21:03:31 +0200)
+
+Model: Theobroma Systems RK3368-uQ7 SoM
+DRAM:  2 GiB
+MMC:   dwmmc at ff0c0000: 1, dwmmc at ff0f0000: 0
+Using default environment
+
+In:    serial at ff180000
+Out:   serial at ff180000
+Err:   serial at ff180000
+Net:
+Warning: ethernet at ff290000 (eth0) using random MAC address - d2:69:35:7e:d0:1e
+eth0: ethernet at ff290000
+Hit any key to stop autoboot:  2
diff --git a/board/theobroma-systems/lion_rk3368/fit_spl_atf.its b/board/theobroma-systems/lion_rk3368/fit_spl_atf.its
new file mode 100644
index 0000000..e7d98b9
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/fit_spl_atf.its
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * Minimal dts for a SPL FIT image payload.
+ *
+ * SPDX-License-Identifier: GPL-2.0+  X11
+ */
+
+/dts-v1/;
+
+/ {
+	description = "FIT image with U-Boot proper, ATF bl31, DTB";
+	#address-cells = <1>;
+
+	images {
+		uboot {
+			description = "U-Boot (64-bit)";
+			data = /incbin/("../../../u-boot-nodtb.bin");
+			type = "standalone";
+			arch = "arm64";
+			compression = "none";
+			load = <0x00200000>;
+		};
+		atf {
+			description = "ARM Trusted Firmware";
+			data = /incbin/("../../../bl31-rk3368.bin");
+			type = "firmware";
+			arch = "arm64";
+			compression = "none";
+			load = <0x00010000>;
+			entry = <0x00010000>;
+		};
+
+		fdt {
+			description = "RK3368-uQ7 (Lion) flat device-tree";
+			data = /incbin/("../../../u-boot.dtb");
+			type = "flat_dt";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "conf";
+		conf {
+			description = "Theobroma Systems RK3368-uQ7 (Puma) SoM";
+			firmware = "uboot";
+			loadables = "atf";
+ 			fdt = "fdt";
+		};
+	};
+};
diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
new file mode 100644
index 0000000..73b1488
--- /dev/null
+++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3368.h>
+#include <asm/arch/timer.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int mach_cpu_init(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
new file mode 100644
index 0000000..73671d9
--- /dev/null
+++ b/configs/lion-rk3368_defconfig
@@ -0,0 +1,88 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ROCKCHIP_RK3368=y
+CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
+CONFIG_TPL_LIBCOMMON_SUPPORT=y
+CONFIG_TPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion"
+CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/lion_rk3368/fit_spl_atf.its"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_SPL=y
+CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
+CONFIG_SPL_ATF_SUPPORT=y
+CONFIG_SPL_ATF_TEXT_BASE=0x10000
+CONFIG_TPL=y
+CONFIG_TPL_BOOTROM_SUPPORT=y
+CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_TPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
+CONFIG_TPL_OF_PLATDATA=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TPL_DM=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_TPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_TPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_TPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ9031=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_RGMII=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK3368=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DEBUG_UART_BASE=0xFF180000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_ROCKCHIP_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y
+CONFIG_SMBIOS_MANUFACTURER="rockchip"
diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h
new file mode 100644
index 0000000..1f25b31
--- /dev/null
+++ b/include/configs/lion_rk3368.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIGS_LION_RK3368_H
+#define __CONFIGS_LION_RK3368_H
+
+#include <configs/rk3368_common.h>
+
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define KERNEL_LOAD_ADDR		0x280000
+#define DTB_LOAD_ADDR			0x5600000
+#define INITRD_LOAD_ADDR		0x5bf0000
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x2000
+
+#endif
-- 
2.1.4

[U-Boot] [PATCH v2 55/56] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its

[Philipp Tomsich]

The ITS file generated warnings due to @<num> designations in the naming
which cause DTC to complain as follows:
  Warning (unit_address_vs_reg): Node /images/uboot at 1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/atf at 1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/pmu at 1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /images/fdt at 1 has a unit name, but no reg property
  Warning (unit_address_vs_reg): Node /configurations/conf at 1 has a unit name, but no reg property

This removes the @<num> part from the names, as we only have a single
image for each payload aspect (and only a single configuration) anyway.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
index f93c251..0519fad 100644
--- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
+++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
@@ -13,7 +13,7 @@
 	#address-cells = <1>;
 
 	images {
-		uboot at 1 {
+		uboot {
 			description = "U-Boot (64-bit)";
 			data = /incbin/("../../../u-boot-nodtb.bin");
 			type = "standalone";
@@ -21,7 +21,7 @@
 			compression = "none";
 			load = <0x00200000>;
 		};
-		atf at 1 {
+		atf {
 			description = "ARM Trusted Firmware";
 			data = /incbin/("../../../bl31.bin");
 			type = "firmware";
@@ -30,14 +30,14 @@
 			load = <0x00001000>;
 			entry = <0x00001000>;
 		};
-		pmu at 1 {
+		pmu {
 		        description = "Cortex-M0 firmware";
 			data = /incbin/("../../../rk3399m0.bin");
 			type = "pmu-firmware";
 			compression = "none";
 			load = <0xff8c0000>;
                 };
-		fdt at 1 {
+		fdt {
 			description = "RK3399-Q7 (Puma) flat device-tree";
 			data = /incbin/("../../../u-boot.dtb");
 			type = "flat_dt";
@@ -46,12 +46,12 @@
 	};
 
 	configurations {
-		default = "conf at 1";
-		conf at 1 {
+		default = "conf";
+		conf {
 			description = "Theobroma Systems RK3399-Q7 (Puma) SoM";
-			firmware = "uboot at 1";
-			loadables = "atf at 1";
-			fdt = "fdt at 1";
+			firmware = "uboot";
+			loadables = "atf";
+			fdt = "fdt";
 		};
 	};
 };
-- 
2.1.4

[U-Boot] [PATCH v2 56/56] rockchip: board: puma_rk3399: rename ATF firmware

[Philipp Tomsich]

From: Klaus Goger <klaus.goger@theobroma-systems.com>

prefix the bl31 firmware needed to build uboot.itb so it can coexist in
the build area with ATFs from other boards (i.e. lion_rk3368)

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---

Changes in v2: None

 board/theobroma-systems/puma_rk3399/README          | 2 +-
 board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README
index 250e345..214281a 100644
--- a/board/theobroma-systems/puma_rk3399/README
+++ b/board/theobroma-systems/puma_rk3399/README
@@ -37,7 +37,7 @@ Compile the ATF
 
   > cd arm-trusted-firmware
   > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
-  > cp build/rk3399/release/bl31.bin ../u-boot
+  > cp build/rk3399/release/bl31.bin ../u-boot/bl31-rk3399.bin
 
 Compile the M0 firmware
 =======================
diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
index 0519fad..520f846 100644
--- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
+++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its
@@ -23,7 +23,7 @@
 		};
 		atf {
 			description = "ARM Trusted Firmware";
-			data = /incbin/("../../../bl31.bin");
+			data = /incbin/("../../../bl31-rk3399.bin");
 			type = "firmware";
 			arch = "arm64";
 			compression = "none";
-- 
2.1.4

[U-Boot] [PATCH v2 01/56] spl: add a 'return to bootrom' boot method

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:05PM +0200, Philipp Tomsich wrote:

> Some devices (e.g. the RK3368) have only limited SRAM, but provide
> support for loading the next boot stage after our SPL performs basic
> setup (e.g. DRAM).
> 
> For target systems like these, we add a boot device BOOTROM that will
> invoke a board-specific hook to return to the bootrom (if supported).
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 02/56] spl: configure 'return to bootrom' separately for SPL and TPL

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:06PM +0200, Philipp Tomsich wrote:

> On the RK3368, we want our TPL to use the 'return to bootrom' boot
> method (to have the bootrom load up the SPL stage) and then continue
> with different boot methods (MMC, SPI, etc.) from SPL.
> 
> This adds the config option needed to control the availabily of the
> 'return to bootrom' boot-method separately for the TPL stage.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 09/56] spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:13PM +0200, Philipp Tomsich wrote:

> To allow finer grained selection of features for TPL, we introduce
> TPL_RAM (in analogy to SPL_RAM).
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 06/56] spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:10PM +0200, Philipp Tomsich wrote:

> SPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a
> stricter dependency of SPL_DM was possible.  This commit makes the
> prereq more specific.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 08/56] spl: dm: Kconfig: SPL_RAM depends on SPL_DM

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:12PM +0200, Philipp Tomsich wrote:

> This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 07/56] spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:11PM +0200, Philipp Tomsich wrote:

> This change introduces TPL variants of the REGMAP and SYSCON config
> options (i.e. TPL_REGMAP and TPL_SYSCON in analogy to SPL_REGMAP and
> SPL_SYSCON) in preparation of a finer-grained feature selection for
> building feature-rich TPL variants.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 21/56] drivers: spl: consistently use the $(SPL_TPL_) macro

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:25PM +0200, Philipp Tomsich wrote:

> To simplify drivers/Makefile a bit when using TPL/SPL, we consistently
> use the $(SPL_TPL_) macro to test for drivers that have separate
> configuration symbols for the full U-boot, SPL and TPL stages.
> Instead of explicitly repeating them in two separate if-guarded
> sections of the Makefile, we can now simply list these options once.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 12/56] spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:16PM +0200, Philipp Tomsich wrote:

> For the RK3368, we want to use OF_PLATDATA in TPL, but full OF_CONTROL
> in SPL: this requires the introduction of a new family of
> configuration options to decouple SPL_OF_CONTROL and SPL_OF_PLATDATA
> from TPL.
> 
> Consequently, Makefile.spl needs to be adjusted to test for these
> configuration items through the $(SPL_TPL_) macro instead of
> hard-coding the SPL variant.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 11/56] spl: dm: Kconfig: split CLK support for SPL and TPL

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:15PM +0200, Philipp Tomsich wrote:

> Introduce TPL_CLK to allow finer-grained selection of TPL features
> for feature-rich (i.e. DM-based) TPL stages.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 13/56] spl: dm: use CONFIG_IS_ENABLED to test for the DM option

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:17PM +0200, Philipp Tomsich wrote:

> Even though there's now a TPL_DM configuration option, the spl logic
> still checks for SPL_DM and thus does not pick up the proper config
> option.
> 
> This introduces the use of CONFIG_IS_ENABLED(DM) in spl.c to always
> pick up the desired configuration option instead of having a
> hard-coded check for the SPL variant.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 10/56] spl: dm: Kconfig: SPL_CLK depens on SPL_DM

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:14PM +0200, Philipp Tomsich wrote:

> SPL_CLK should also depend on SPL_DM (and not just on CLK).
> Add the additional dependency.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 15/56] armv8: spl: Support separate stack for TPL

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:19PM +0200, Philipp Tomsich wrote:

> To allow a TPL and SPL to run from different addresses/memories, we
> need to split setup of the TPL and SPL stacks.  To do so, we introduce
> CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override
> the initial stack pointer for TPL.
> 
> To provide backward compatibility for existing boards, this is added
> as an optional configuration item and the normal search order (i.e.
> SPL_STACK, then SYS_STACK) apply if not defined.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 20/56] spl: add TPL_DRIVER_MISC_SUPPORT option

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:24PM +0200, Philipp Tomsich wrote:

> This adds the TPL_DRIVER_MISC_SUPPORT option to allow activation of
> DRIVER_MISC_SUPPORT for devices that need it in the TPL stage.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 19/56] spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:23PM +0200, Philipp Tomsich wrote:

> To allow for a finer-grained control of features for TPL and SPL
> builds all modules/boot-methods/etc. need to be consistently selected
> based on the $(SPL_TPL_) macros.
> 
> This allows splitting the associated config-options in Kconfig: we
> don't split the Kconfig options here and now, as this should happen on
> an as-needed basis, whenever someone needs a feature/boot-method/etc.
> in their TPL.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 14/56] armv8: remove unused low-level modules from TPL

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:18PM +0200, Philipp Tomsich wrote:

> TPL builds today don't need to call into firmware or set up the MMU
> (if this changes, it should be controlled through a config option
> whether to include this or not), but include the needed support code
> for this anyway.
> 
> Even for a feature-rich TPL (including DM support as for the RK3368),
> this equates to a size difference of approx. 10% in TPL binary size:
> - without this change:
>    text    data    bss    dec    hex filename
>   23635    3112     24  26771   6893 tpl/u-boot-tpl
> - with this change:
>    text	   data    bss    dec    hex filename
>   21583    3112     24  24719   608f tpl/u-boot-tpl
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> 
> Changes in v2: None
> 
>  arch/arm/cpu/armv8/Makefile | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
> index c447085..e831471 100644
> --- a/arch/arm/cpu/armv8/Makefile
> +++ b/arch/arm/cpu/armv8/Makefile
> @@ -9,12 +9,14 @@ extra-y	:= start.o
>  
>  obj-y	+= cpu.o
>  obj-y	+= generic_timer.o
> +ifndef CONFIG_TPL_BUILD
>  obj-y	+= cache_v8.o
> -obj-y	+= exceptions.o
>  obj-y	+= cache.o
>  obj-y	+= tlb.o
>  obj-y	+= transition.o
>  obj-y	+= fwcall.o
> +endif
> +obj-y	+= exceptions.o
>  obj-y	+= cpu-dt.o
>  obj-$(CONFIG_ARM_SMCCC)		+= smccc-call.o

We're talking about various asm files above, yes?  Have you looked at
manually adding the section information to these files so they can be
gc'd in all cases?  If it's too complex (for example, some macro-heavy
asm files we borrow from Linux are just too hard to make it work in),
then the above is fine.  Otherwise I'd like to see section naming so
they can be gc'd with the normal flags here.  Thanks!

-- 
Tom
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[U-Boot] [PATCH v2 18/56] lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:22PM +0200, Philipp Tomsich wrote:

> This splits the compilation of code modules for TPL and SPL for
> OF_CONTROL (and related) features between TPL and SPL.  The typical
> use-case of this is a TPL stage that uses OF_PLATDATA at TPL and
> provides full OF_CONTROL at SPL (e.g. on the RK3368).
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 16/56] spl: allow a separate TEXT_BASE, LDSCRIPT and MAX_SIZE for TPL

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:20PM +0200, Philipp Tomsich wrote:

> For the bringup of the RK3368, we need to support TPL and SPL running
> from different addresses... which requires both stages to use a
> distinct TEXT_BASE.
> 
> This commit adds support for having a separate LDSCRIPT for TPL (which
> is expected to make use of the TPL_MAX_SIZE define) and for having a
> the option of defining TPL_TEXT_BASE and having the TPL stage linked
> against this address.
> 
> Note that the handling of the TEXT_BASE is designed to not interfere
> with the previous assumption that SPL_TEXT_BASE should be used for TPL
> as well, unless TPL_TEXT_BASE is defined.  For this reason, the test
> in Makefile.spl uses the following (seemingly redundant checks):
>  1. looks for $(SPL_TPL_)TEXT_BASE
>  2. looks for SPL_TEXT_BASE (even when building in TPL)
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> 
> Changes in v2: None
> 
>  scripts/Makefile.spl         | 10 ++++++++--
>  scripts/config_whitelist.txt |  3 +++
>  2 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
> index 3e35cd6..4a9a58f 100644
> --- a/scripts/Makefile.spl
> +++ b/scripts/Makefile.spl
> @@ -103,9 +103,9 @@ u-boot-spl-platdata := $(obj)/dts/dt-platdata.o
>  endif
>  
>  # Linker Script
> -ifdef CONFIG_SPL_LDSCRIPT
> +ifdef CONFIG_$(SPL_TPL_)LDSCRIPT
>  # need to strip off double quotes
> -LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_SPL_LDSCRIPT:"%"=%))
> +LDSCRIPT := $(addprefix $(srctree)/,$(CONFIG_$(SPL_TPL_)LDSCRIPT:"%"=%))
>  endif
>  
>  ifeq ($(wildcard $(LDSCRIPT)),)
> @@ -293,9 +293,15 @@ LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
>  # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
>  LDFLAGS_$(SPL_BIN) += $(call ld-option, --no-dynamic-linker)
>  
> +# First try the best-match (i.e. SPL_TEXT_BASE for SPL, TPL_TEXT_BASE for TPL)
> +ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),)
> +LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(SPL_TPL_)TEXT_BASE)
> +else
> +# And then fall back to just testing for SPL_TEXT_BASE, even if in TPL mode
>  ifneq ($(CONFIG_SPL_TEXT_BASE),)
>  LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
>  endif
> +endif
>  
>  MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
>  $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index 34aadc5..d8d00f5 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -4996,8 +4996,11 @@ CONFIG_TI_KSNAV
>  CONFIG_TI_SPI_MMAP
>  CONFIG_TMU_TIMER
>  CONFIG_TPL_DRIVERS_MISC_SUPPORT
> +CONFIG_TPL_LDSCRIPT
> +CONFIG_TPL_MAX_SIZE
>  CONFIG_TPL_PAD_TO
>  CONFIG_TPL_STACK
> +CONFIG_TPL_TEXT_BASE
>  CONFIG_TPM_TIS_BASE_ADDRESS
>  CONFIG_TPS6586X_POWER
>  CONFIG_TQM834X

I'm not super happy about adding to the whitelist.  I know some of these
aren't easy to migrate to Kconfig, but can we add the new ones at least
in Kconfig?  Thanks!

-- 
Tom
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[U-Boot] [PATCH v2 17/56] spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:21PM +0200, Philipp Tomsich wrote:

> As include/malloc.h already checks for SYS_MALLOC_SIMPLE using the
> CONFIG_IS_ENABLED macro, we need to move to having separate entries
> as we switch to fully separate configuration for SPL and TPL.
> 
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] [PATCH v2 00/56] Support OF_PLATDATA in TPL, enable RK3368 DRAM init and add RK3368-uQ7

[Tom Rini]

On Wed, Jul 26, 2017 at 12:40:04PM +0200, Philipp Tomsich wrote:

> 
> Here's an updated series to enable the RK3368 which addresses the
> concerns regarding the prefixing of GRF bit-definitions with a
> RK3368-prefix: while I had intended to temporarily pull the GMAC
> support to get around the underlying issue, moving the bit-definitions
> into the pinctrl-driver's implementation turned out to rather
> straightforward (and there's little use in having these definitions
> visible outside of the pinctrl driver anyway).
> 
> Thanks to everyone, who took the time to comment/discuss the initial
> version.
> 
> This series (still) has a lot going on, but I didn't want to split it
> to allow everyone to understand the motivation between some of the
> changes to the SPL/TPL framework.  The short summary of this is
> "enablement for DRAM init on the RK3368 with everything else that's
> necessary to do it using OF_PLATDATA in TPL".

Aside from the few things I commented on that we need to resolve, once
that's all done, go ahead and pick this all up for the rockchip tree,
thanks!

-- 
Tom
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[U-Boot] [PATCH v2 01/56] spl: add a 'return to bootrom' boot method

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Some devices (e.g. the RK3368) have only limited SRAM, but provide
> support for loading the next boot stage after our SPL performs basic
> setup (e.g. DRAM).
>
> For target systems like these, we add a boot device BOOTROM that will
> invoke a board-specific hook to return to the bootrom (if supported).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/spl.h |  1 +
>  common/spl/Kconfig         | 11 +++++++++++
>  common/spl/Makefile        |  1 +
>  common/spl/spl_bootrom.c   | 27 +++++++++++++++++++++++++++
>  include/spl.h              | 10 ++++++++++
>  5 files changed, 50 insertions(+)
>  create mode 100644 common/spl/spl_bootrom.c
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 44/56] net: gmac_rockchip: Add support for the RK3368 GMAC

[Joe Hershberger]

On Wed, Jul 26, 2017 at 5:40 AM, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The GMAC in the RK3368 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
>
> This adds the RK3368-specific logic necessary to reuse this driver.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

[U-Boot] [PATCH v2 02/56] spl: configure 'return to bootrom' separately for SPL and TPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> On the RK3368, we want our TPL to use the 'return to bootrom' boot
> method (to have the bootrom load up the SPL stage) and then continue
> with different boot methods (MMC, SPI, etc.) from SPL.
>
> This adds the config option needed to control the availabily of the
> 'return to bootrom' boot-method separately for the TPL stage.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  common/spl/Kconfig | 11 +++++++++++
>  1 file changed, 11 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 03/56] rockchip: back-to-bootrom: add 'back-to-bootrom' support for AArch64

[Simon Glass]

Hi Philipp,

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The back-to-bootrom support for Rockchip is equivalent to an
> (assembly) implementation of setjmp/longjmp (i.e. it saves the
> stack-pointer, link-register and callee-saved registers). Up until
> now, this had only been implemented for AArch32 (i.e. ARMv7 or older),
> which puts the new ARMv8 devices (which boot in AArch64 mode) at a
> slight disadvantage.
>
> To allow use of the 'back-to-bootrom' feature on new devices (e.g. the
> RK3368), this commit adds an implementation for AArch64.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/save_boot_param.S | 37 ++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

>
> diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S
> index 5e6c8db..945a9dd 100644
> --- a/arch/arm/mach-rockchip/save_boot_param.S
> +++ b/arch/arm/mach-rockchip/save_boot_param.S
> @@ -1,11 +1,47 @@
>  /*
>   * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>   *
>   * SPDX-License-Identifier:     GPL-2.0+
>   */
>
>  #include <linux/linkage.h>
>
> +#if defined(CONFIG_ARM64)
> +.globl SAVE_SP_ADDR
> +SAVE_SP_ADDR:
> +       .quad 0
> +
> +ENTRY(save_boot_params)
> +       sub     sp, sp, #0x100

Can you please add a comment as to why this is 0x100?

> +       stp     x29, x30, [sp, #0x50]
> +       stp     x27, x28, [sp, #0x40]
> +       stp     x25, x26, [sp, #0x30]
> +       stp     x23, x24, [sp, #0x20]
> +       stp     x21, x22, [sp, #0x10]
> +       stp     x19, x20, [sp, #0]
> +       ldr     x8, =SAVE_SP_ADDR
> +       mov     x9, sp
> +       str     x9, [x8]
> +       b       save_boot_params_ret  /* back to my caller */
> +ENDPROC(save_boot_params)
> +
> +.globl _back_to_bootrom_s
> +ENTRY(_back_to_bootrom_s)
> +       ldr     x0, =SAVE_SP_ADDR
> +       ldr     x0, [x0]
> +       mov     sp, x0
> +       ldp     x29, x30, [sp, #0x50]
> +       ldp     x27, x28, [sp, #0x40]
> +       ldp     x25, x26, [sp, #0x30]
> +       ldp     x23, x24, [sp, #0x20]
> +       ldp     x21, x22, [sp, #0x10]
> +       ldp     x19, x20, [sp]
> +       add     sp, sp, #0x100
> +       mov     x0, xzr
> +       ret
> +ENDPROC(_back_to_bootrom_s)
> +#else
>  .globl SAVE_SP_ADDR
>  SAVE_SP_ADDR:
>         .word 0
> @@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s)
>         mov     r0, #0
>         pop     {r1-r12, pc}
>  ENDPROC(_back_to_bootrom_s)
> +#endif
> --
> 2.1.4
>

Regards,
Simon

[U-Boot] [PATCH v2 04/56] rockchip: back-to-bootrom: split BACK_TO_BOOTROM for TPL/SPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The back-to-bootrom option is rather unfortunately named
>   CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM
> instead of
>   CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM
>
> To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM),
> we need to rename it.  At the same time, we introduce a TPL_ variant of
> the option to give us finer-grained control over when it should be used.
>
> This change is motivated by our RK3368 boot process, which returns to
> the boot ROM only from the TPL stage, but not from the SPL stage.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/Kconfig            | 15 +++++++++++++--
>  arch/arm/mach-rockchip/rk3188-board-spl.c |  5 ++---
>  arch/arm/mach-rockchip/rk3188-board.c     |  2 +-
>  arch/arm/mach-rockchip/rk3288-board-spl.c |  4 ++--
>  arch/arm/mach-rockchip/rk3288-board.c     |  4 ++--
>  arch/arm/mach-rockchip/rk3399-board-spl.c |  4 ++--
>  configs/evb-rk3288_defconfig              |  2 +-
>  configs/fennec-rk3288_defconfig           |  2 +-
>  configs/firefly-rk3288_defconfig          |  2 +-
>  configs/miqi-rk3288_defconfig             |  2 +-
>  configs/popmetal-rk3288_defconfig         |  2 +-
>  configs/rock2_defconfig                   |  2 +-
>  configs/rock_defconfig                    |  2 +-
>  configs/tinker-rk3288_defconfig           |  2 +-
>  doc/README.rockchip                       |  2 +-
>  include/configs/rk3188_common.h           |  2 +-
>  include/configs/rk3288_common.h           |  2 +-
>  include/configs/rock.h                    |  2 +-
>  include/configs/rockchip-common.h         |  2 +-
>  19 files changed, 35 insertions(+), 25 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 05/56] rockchip: back-to-bootrom: simplify the #ifdef-check for LIBGENERIC in TPL/SPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> With the finer-grained control over LIBGENERIC_SUPPORT for TPL/SPL (i.e.
> with the newly introduced distinction between TPL_LIBGENERIC_SUPPORT and
> SPL_LIBGENERIC_SUPPORT), we can simplify the #ifdef-check to simply use
> CONFIG_IS_ENABELD.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/bootrom.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 06/56] spl: dm: Kconfig: use more specific prereqs for SPL_REGMAP and SPL_SYSCON

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> SPL_REGMAP and SPL_SYSCON were marked as depending on DM, when a
> stricter dependency of SPL_DM was possible.  This commit makes the
> prereq more specific.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/core/Kconfig | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 07/56] spl: dm: Kconfig: split REGMAP/SYSCON support for TPL from SPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This change introduces TPL variants of the REGMAP and SYSCON config
> options (i.e. TPL_REGMAP and TPL_SYSCON in analogy to SPL_REGMAP and
> SPL_SYSCON) in preparation of a finer-grained feature selection for
> building feature-rich TPL variants.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/core/Kconfig  | 19 +++++++++++++++++++
>  drivers/core/Makefile |  4 ++--
>  2 files changed, 21 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 08/56] spl: dm: Kconfig: SPL_RAM depends on SPL_DM

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This commit models the dependency from SPL_RAM to SPL_DM in Kconfig.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/ram/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 09/56] spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To allow finer grained selection of features for TPL, we introduce
> TPL_RAM (in analogy to SPL_RAM).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/ram/Kconfig | 9 +++++++++
>  1 file changed, 9 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 10/56] spl: dm: Kconfig: SPL_CLK depens on SPL_DM

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> SPL_CLK should also depend on SPL_DM (and not just on CLK).
> Add the additional dependency.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 11/56] spl: dm: Kconfig: split CLK support for SPL and TPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Introduce TPL_CLK to allow finer-grained selection of TPL features
> for feature-rich (i.e. DM-based) TPL stages.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/Kconfig  | 10 ++++++++++
>  drivers/clk/Makefile |  2 +-
>  2 files changed, 11 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 12/56] spl: dm: Kconfig: split OF_CONTROL and OF_PLATDATA between SPL and TPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> For the RK3368, we want to use OF_PLATDATA in TPL, but full OF_CONTROL
> in SPL: this requires the introduction of a new family of
> configuration options to decouple SPL_OF_CONTROL and SPL_OF_PLATDATA
> from TPL.
>
> Consequently, Makefile.spl needs to be adjusted to test for these
> configuration items through the $(SPL_TPL_) macro instead of
> hard-coding the SPL variant.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  Makefile             |  2 +-
>  dts/Kconfig          | 29 +++++++++++++++++++++++++++++
>  scripts/Makefile.spl |  4 ++--
>  3 files changed, 32 insertions(+), 3 deletions(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 13/56] spl: dm: use CONFIG_IS_ENABLED to test for the DM option

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Even though there's now a TPL_DM configuration option, the spl logic
> still checks for SPL_DM and thus does not pick up the proper config
> option.
>
> This introduces the use of CONFIG_IS_ENABLED(DM) in spl.c to always
> pick up the desired configuration option instead of having a
> hard-coded check for the SPL variant.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  common/spl/spl.c        |  5 +++--
>  include/linux/kconfig.h | 13 +++++++++++++
>  2 files changed, 16 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 15/56] armv8: spl: Support separate stack for TPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To allow a TPL and SPL to run from different addresses/memories, we
> need to split setup of the TPL and SPL stacks.  To do so, we introduce
> CONFIG_TPL_STACK (not listed in Kconfig) which can be used to override
> the initial stack pointer for TPL.
>
> To provide backward compatibility for existing boards, this is added
> as an optional configuration item and the normal search order (i.e.
> SPL_STACK, then SYS_STACK) apply if not defined.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/lib/crt0_64.S       | 4 +++-
>  scripts/config_whitelist.txt | 1 +
>  2 files changed, 4 insertions(+), 1 deletion(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 17/56] spl: Kconfig: split SYS_MALLOC_SIMPLE for TPL and SPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> As include/malloc.h already checks for SYS_MALLOC_SIMPLE using the
> CONFIG_IS_ENABLED macro, we need to move to having separate entries
> as we switch to fully separate configuration for SPL and TPL.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  common/spl/Kconfig | 9 +++++++++
>  1 file changed, 9 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 18/56] lib: spl: differentiate between TPL and SPL for libfdt/of_control/of_platdata

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This splits the compilation of code modules for TPL and SPL for
> OF_CONTROL (and related) features between TPL and SPL.  The typical
> use-case of this is a TPL stage that uses OF_PLATDATA at TPL and
> provides full OF_CONTROL at SPL (e.g. on the RK3368).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  lib/Makefile | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 19/56] spl: consistently use $(SPL_TPL_) to select features for SPL and TPL builds

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To allow for a finer-grained control of features for TPL and SPL
> builds all modules/boot-methods/etc. need to be consistently selected
> based on the $(SPL_TPL_) macros.
>
> This allows splitting the associated config-options in Kconfig: we
> don't split the Kconfig options here and now, as this should happen on
> an as-needed basis, whenever someone needs a feature/boot-method/etc.
> in their TPL.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  common/Makefile     |  8 ++++----
>  common/spl/Makefile | 36 ++++++++++++++++++------------------
>  2 files changed, 22 insertions(+), 22 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 20/56] spl: add TPL_DRIVER_MISC_SUPPORT option

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This adds the TPL_DRIVER_MISC_SUPPORT option to allow activation of
> DRIVER_MISC_SUPPORT for devices that need it in the TPL stage.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  common/spl/Kconfig | 8 ++++++++
>  1 file changed, 8 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 21/56] drivers: spl: consistently use the $(SPL_TPL_) macro

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To simplify drivers/Makefile a bit when using TPL/SPL, we consistently
> use the $(SPL_TPL_) macro to test for drivers that have separate
> configuration symbols for the full U-boot, SPL and TPL stages.
> Instead of explicitly repeating them in two separate if-guarded
> sections of the Makefile, we can now simply list these options once.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/Makefile | 36 ++++++++++++++++--------------------
>  1 file changed, 16 insertions(+), 20 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 22/56] rockchip: Makefile: allow selective inclusion of sdram_common.o from TPL/SPL/U-Boot

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The utility functions in sdram_common.c will be useful both for some
> SPL implementations (and if unused, the linked will discard these
> anyway) and for the full U-Boot stage.
>
> This changes selects sdram_common.o through the $(SPL_TPL_) macro to
> allow better control of its inclusion through the CONFIG_ROM,
> CONFIG_SPL_RAM or CONFIG_TPL_RAM options.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/Makefile | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 23/56] rockchip: rk3368: improve Kconfig text for the RK3368

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The RK3368 option in Kconfig referred to the RK3328 (copy-and-paste)
> and had a few typos and unnecessarily used UTF-8 characters.  While
> fixing this, I also reformatted and further clarified the text
> (e.g. made the grouping into a a big and little cluster of 4 cores
> each explicit).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/Kconfig | 15 +++++++++------
>  1 file changed, 9 insertions(+), 6 deletions(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 24/56] rockchip: rk3368: mkimage: add support for the RK3368

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This commit adds support for RK3368 SoC in mkimage.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  tools/rkcommon.c | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 25/56] rockchip: rk3368: pmugrf: add definitions for os_reg[0..3]

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> On the RK3368 we use a TPL-stage similar to Rockchip's DDR init
> (i.e. it initialises DRAM, leaves some info for the next stage and
> returns to the BootROM).  To allow compatibility with Rockchip's DDR
> init code, we use the same register os_reg2 in pmugrf for passing
> this info (i.e. DRAM size and configuration) between stages.
>
> This change adds the definitions for os_reg[0] through os_reg[3] to
> the pmugrf structure for the RK3368.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 26/56] rockchip: rk3368: spl: define COUNTER_FREQUENCY to 24MHz

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The BootROM of the RK3368 Boot ROM does not initialise cntfrq_el0.
> This change defines COUNTER_FREQUENCY, which is used by the AArch64 init
> code in arch/arm/cpu/armv8/start.S to set up cntfrq_el0.
>
> If the counter-frequency is not correctly set up, the calculation of
> delays using the ARMv8 generic timer can not work correctly.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  include/configs/rk3368_common.h | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 27/56] rockchip: rk3368: spl: add memory layout for TPL and SPL

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> For the RK3368, we use a multi-stage boot-process consisting of the
> following:
>   1.  TPL: initalises DRAM, returns to boot-ROM (which then loads
>            the next stage and transfers control to it)
>   2.  SPL: a full-features SPL stage including OF_CONTROL and FIT
>            image loading, which fetches the ATF, DTB and full U-Boot
>            and then transfers control to the ATF (using the BL31
>            parameter block to indicate the location of BL33/U-Boot)
>   3.  ATF: sets up the secure world and exits to BL33 (i.e. a full
>            U-Boot) in the normal world
>   4.  full U-Boot
>
> TPL/SPL and the full U-Boot are built from this tree and need to
> run from distinct text addresses and with distinct initial stack
> pointer addresses.
>
> This commit sets up the configuration to run:
>   -  TPL from the SRAM at 0xff8c0000 (note that the first 0x1000
>          are reserved for use by the boot-ROM and contain the SP
>          when the TPL is entered)
>   -  SPL from DRAM at 0x0
>   -  U-Boot from DRAM at 0x200000
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  include/configs/rk3368_common.h | 11 +++++++++++
>  1 file changed, 11 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 28/56] rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The RK3368 has both a limited SPL size (just 0x7000 bytes) and the
> added challenge of booting in AArch64, which increases the code size
> for SPL (particularily when using the LP64 programming model).  For
> this reason we expect the RK3368 to always use OF_PLATDATA for its
> SPL stage.

But I thought that you had SDRAM ready by the time you boot to SPL? So
why the limit?

>
> This change adds support for the MSCH, PMUGRF and GRF register regions
> in syscon, which are necessary for initialising the RK3368's DRAM
> controller.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 35 +++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)

[U-Boot] [PATCH v2 29/56] rockchip: rk3368: grf: use shifted-constants

[Simon Glass]

Hi Philipp,

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The RK3368 GRF header was still defines with a shifted-mask but with
> non-shifted function selectors for the IOMUX defines.  As the RK3368
> support is still fresh enough to allow a quick change, we do this now
> before having more code use this.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - dropped the RK3368_ prefix for the GRF constants
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 441 ++++++++++++------------
>  drivers/pinctrl/rockchip/pinctrl_rk3368.c       |   9 +-
>  2 files changed, 226 insertions(+), 224 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> index a438f5d..1966960 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> @@ -1,4 +1,6 @@
> -/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
> +/*
> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>   *
>   * SPDX-License-Identifier:     GPL-2.0+
>   */
> @@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
>
>  /*GRF_GPIO0C_IOMUX*/
>  enum {
> -       GPIO0C7_SHIFT           = 14,
> -       GPIO0C7_MASK            = 3 << GPIO0C7_SHIFT,
> -       GPIO0C7_GPIO            = 0,
> -       GPIO0C7_LCDC_D19,
> -       GPIO0C7_TRACE_D9,
> -       GPIO0C7_UART1_RTSN,
> -
> -       GPIO0C6_SHIFT           = 12,
> -       GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
> +       GPIO0C7_MASK           = GENMASK(15, 14),
> +       GPIO0C7_GPIO           = 0,
> +       GPIO0C7_LCDC_D19        = (1 << 14),
> +       GPIO0C7_TRACE_D9        = (2 << 14),
> +       GPIO0C7_UART1_RTSN      = (3 << 14),

Can we keep the SHIFT macros so we(e.g.) don't have to open-code the
'14' each time?

[U-Boot] [PATCH v2 30/56] rockchip: pinctrl: rk3368: add GMAC (RGMII only) support

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this
> point), we need support for additional pin-configuration.  This commit
> adds the pinctrl support for GMAC in RGMII mode:
>  * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
>  * configures the RGMII pins
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - removed the RK3368-prefix on bit-definitions for GMAC pinctrl
>
>  drivers/pinctrl/rockchip/pinctrl_rk3368.c | 36 +++++++++++++++++++++++++++++++
>  1 file changed, 36 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 31/56] rockchip: pinctrl: rk3368: add support for configuring the MMC pins

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The RK3368 has two SD/MMC controllers that can be used from U-Boot
> both during SPL and for booting an OS from the full bootloader stage.
> While both are configured to (mostly) sensible settings from the BROM,
> additional configuration for the MMC controller is needed to configure
> it to 8bit mode.
>
> This adds pinctrl support for the MMC controller.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - removed the RK3368 prefix on the SD/MMC pin definitions
>
>  drivers/pinctrl/rockchip/pinctrl_rk3368.c | 48 +++++++++++++++++++++++++++++++
>  1 file changed, 48 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 32/56] rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> There is no real reason to keep the bit-definitions for the IOMUX in
> the grf header file (which defines the register layout of the GRF block):
> these should only be used by our pinctrl driver (with the possible
> exception of early debug-init code in TPL/SPL).
>
> This moves the relevant definitions from the grf_rk3368.h header
> into the pinctrl driver pinctrl_rk3368.c.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> - moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX
>   definitions) to the rk3368 pinctrl driver implementation
>
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 316 -----------------------
>  drivers/pinctrl/rockchip/pinctrl_rk3368.c       | 325 ++++++++++++++++++++++++
>  2 files changed, 325 insertions(+), 316 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

(although I expect that we will reinstate the SHIFT macros?)

[U-Boot] [PATCH v2 33/56] rockchip: pinctrl: rk3368: add SPI support

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To implement pinctrl support for the RK3368, we need to add the
> bit-definitions to configure the IOMUX and tie these into the
> pinctrl framework. This also adds the mapping from the IRQ# back
> onto the periheral id for the SPI devices.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/pinctrl/rockchip/pinctrl_rk3368.c | 90 +++++++++++++++++++++++++++++++
>  1 file changed, 90 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 34/56] rockchip: clk: rk3368: implement bandwidth adjust for PLLs

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The RK3368 TRM recommends to configure the bandwith adjustment (CON2)
> for PLLs to NF/2.  This implements this for all reconfigurations of
> PLLs and removes the 'has_bwadj' flag (as the RK3368 always has the
> bandwidth-adjustment feature according to its manual).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3368.c | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 35/56] rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> With the RK3368's limited TPL size, we'll want to use OF_PLATFDATA for
> the SPL stage.  This implements support for OF_PLATDATA in the clock
> driver for the RK3368.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3368.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 36/56] rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The RK3368 has a somewhat temperamental BootROM (which I learned the
> hard way) when it comes to reconfiguring the CPLL and GPLL (in fact,
> experiments show that changing the GPLL broke things for me, while
> changing the CPLL seems to be more benign).  These should not be
> modified by the SPL stage, if we intend to return to the BootROM for
> chain booting the next stage.
>
> This commit changes the clock initialisation to not change CPLL/GPLL
> before returning to the BootROM (i.e. in TPL).  As it's safe to change
> these settings if we no longer intend to return to U-Boot, we'll run
> the full PLL setup a little later (i.e. in SPL).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3368.c | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 37/56] rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To implement a TPL stage (incl. its DRAM controller setup) for the
> RK3368, we'll want to configure the DPLL (DRAM PLL).
>
> This commit implements setting the DPLL (CLK_DDR) and provides PLL
> configuration details for the common DRAM operating speeds found on
> RK3368 boards.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3368.c | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 38/56] rockchip: clk: rk3368: define DMA1_SRST_REQ and DMA2_SRST_REQ

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> On he RK3368, we need to temporarily disable security on the DMA
> engines during TPL and SPL to allow the MMC host to DMA into DRAM.  To
> do so, we need to reset the two DMA engines, which in turn requires
> the DMA1_SRST_REQ and DMA2_SRST_REQ constants to refer to the
> appropriate bits in the CRU.
>
> As the ATF correctly initialises security (and only leaves EL3 after
> doing so), this can not pose a security issue.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 4 ++++
>  1 file changed, 4 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 39/56] rockchip: clk: rk3368: implement MMC/SD clock reparenting

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The original clock support for MMC/SD cards on the RK3368 suffered
> from a tendency to select a divider less-or-equal to the the one
> giving the requested clock-rate: this can lead to higher-than-expected
> (or rather: higher than supported) clock rates for the MMC/SD
> communiction.
>
> This change rewrites the MMC/SD clock generation to:
>  * always generate a clock less-than-or-equal to the requested clock
>  * support reparenting among the CPLL, GPLL and OSC24M parents to
>    generate the highest clock that does not exceed the requested rate
>
> In addition to this, the Linux DTS uses HCLK_MMC/HCLK_SDMMC instead of
> SCLK_MMC/SCLK_SDMMC: to match this (and to ensure that clock setup
> always works), we adjust the driver appropriately.
>
> This includes the changes from:
>  - rockchip: clk: rk3368: convert MMC_PLL_SEL_* definitions to shifted-value form
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h |   8 +-
>  drivers/clk/rockchip/clk_rk3368.c               | 119 ++++++++++++++++++------
>  2 files changed, 95 insertions(+), 32 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 40/56] rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> As part of the DRAM initialisation process (running as part of the TPL
> stage) on the RK3368, we need to set up the DRAM PLL.
>
> This implements support for configuring the PLL to for 1200, 1332 or
> 1600 MHz (i.e. for DDR3-1200, DDR3-1333, DDR3-1600 operating modes).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3368.c | 13 +++++++------
>  1 file changed, 7 insertions(+), 6 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 41/56] rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To enable the GMAC on the RK3368, we need to set up the clocking
> appropriately to generate a tx_clk for the MAC.
>
> This adds an implementation that implements the use of the <&ext_gmac>
> clock (i.e. an external 125MHz clock for RGMII provided by the PHY).
> This is the clock setup used by the boards currently supported by
> U-Boot (i.e. Geekbox, Sheep and RK3368-uQ7).
>
> This includes the change from commit
>  - rockchip: clk: rk3368: define GMAC_MUX_SEL_EXTCLK
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3368.h |  3 +++
>  drivers/clk/rockchip/clk_rk3368.c               | 19 +++++++++++++++++--
>  2 files changed, 20 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 42/56] rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> With the clock support in rk3368_clk_set_rate() conditionalized on
> various feature definitions, 'priv' can remain unused (e.g. in the
> SPL build when only MMC is enabled).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3368.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 43/56] rockchip: clk: rk3368: add support for configuring the SPI clocks

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> As SPI support may be useful in the boot-flow, this adds support for
> configuring the SPI controller's clocks in the RK3368 clock driver.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2:
> - added SPI clock setup
>
>  drivers/clk/rockchip/clk_rk3368.c | 132 ++++++++++++++++++++++++++++++--------
>  1 file changed, 106 insertions(+), 26 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 44/56] net: gmac_rockchip: Add support for the RK3368 GMAC

[Simon Glass]

Hi Philipp,

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The GMAC in the RK3368 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
>
> This adds the RK3368-specific logic necessary to reuse this driver.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - moves the bit-definitions (for GRF registers) specific to the GMAC
>   into the GMAC driver: these include interface speed selection and
>   configuring the RGMII output mode
>
>  arch/arm/include/asm/arch-rockchip/grf_rk3368.h |  1 +
>  drivers/net/gmac_rockchip.c                     | 78 +++++++++++++++++++++++++
>  2 files changed, 79 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> index ec42d7a..1f84ff9 100644
> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
> @@ -129,4 +129,5 @@ enum {
>         MCU_CODE_BASE_BIT31_BIT28_SHIFT         = 0,
>         MCU_CODE_BASE_BIT31_BIT28_MASK          = GENMASK(3, 0),
>  };
> +
>  #endif
> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
> index c9f9e83..586ccbf 100644
> --- a/drivers/net/gmac_rockchip.c
> +++ b/drivers/net/gmac_rockchip.c
> @@ -16,6 +16,7 @@
>  #include <asm/arch/clock.h>
>  #include <asm/arch/hardware.h>
>  #include <asm/arch/grf_rk3288.h>
> +#include <asm/arch/grf_rk3368.h>
>  #include <asm/arch/grf_rk3399.h>
>  #include <dm/pinctrl.h>
>  #include <dt-bindings/clock/rk3288-cru.h>
> @@ -83,6 +84,38 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
>         return 0;
>  }
>
> +static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)

What is the plan here? Can we use a ioctl() interface to the grf
syscon perhaps, to remove this SoC-specific code from the driver?

[U-Boot] [PATCH v2 45/56] rockchip: Makefile: streamline SPL/TPL configuration

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Handling TPL and SPL in the Makefile for mach-rockchip was based on
> nested if checks and/or if-else-if paths.  This can be simplified and
> made more readable by using $(SPL_TPL_) and by introducing
> intermediate variables for the aggregation of SPL and TPL features.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/Makefile | 46 +++++++++++++++++++++++++----------------
>  1 file changed, 28 insertions(+), 18 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 46/56] rockchip: rk3368: add DRAM controller driver with DRAM initialisation

[Simon Glass]

Hi Philipp,

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This adds a DRAM controller driver for the RK3368 and places it in
> drivers/ddr/rockchip (where the other DM-enabled DRAM controller
> drivers for rockchip devices should also be moved eventually).

I thought we were actually planning on using drivers/ram ?

>
> At this stage, only the following feature-set is supported:
>  - DDR3
>  - 32-bit configuration (i.e. fully populated)
>  - dual-rank (i.e. no auto-detection of ranks)
>  - DDR3-1600K speed-bin
>
> This driver expects to run from a TPL stage that will later return to
> the RK3368 BROM.  It communicates with later stages through the
> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
> init code).
>
> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
> timings are calculated within the driver based on a target frequency
> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
> time).
>
> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
> register for controlling the operation of its (single-channel) DRAM
> controller in the GRF block.  This provides for selecting DDR3, mobile
> DDR modes, and control low-power operation.
> As part of this change, DDRC0_CON0 is also added to the GRF structure
> definition (at offset 0x600).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/include/asm/arch-rockchip/ddr_rk3368.h    | 187 ++++
>  arch/arm/include/asm/arch-rockchip/grf_rk3368.h    |   3 +
>  arch/arm/mach-rockchip/rk3368/Makefile             |   1 -
>  arch/arm/mach-rockchip/rk3368/sdram_rk3368.c       |  60 --
>  .../clock/rockchip,rk3368-dmc.txt                  |  67 ++
>  drivers/ram/Makefile                               |   2 +
>  drivers/ram/rockchip/Makefile                      |   7 +
>  drivers/ram/rockchip/dmc-rk3368.c                  | 990 +++++++++++++++++++++
>  include/dt-bindings/memory/rk3368-dmc.h            |  30 +
>  9 files changed, 1286 insertions(+), 61 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>  delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>  create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>  create mode 100644 drivers/ram/rockchip/Makefile
>  create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
>  create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>

Apart from that nit:

Reviewed-by: Simon Glass <sjg@chromium.org>

How can we unify these dram drivers?

[U-Boot] [PATCH v2 47/56] rockchip: dts: rk3368: add DMC node in rk3368.dtsi

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> For full SPL support, including DRAM initialisation, we need a few
> nodes from the DTS: this commit adds the DMC (DRAM controller) node,
> the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
> as 'u-boot,dm-pre-reloc'.  In addition to this, we also include the
> dt-binding for the DMC to allow DTS files including this DTSI to refer
> to the symbolic constants for the DDR3 bin and for the
> memory-schedule.
>
> Note that the DMC contains both the memory regions for the
> (Designware) protocol controller as well as the DDR PHY.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi
>
>  arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------
>  1 file changed, 19 insertions(+), 6 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 48/56] rockchip: rk3368: spl: enable SPL_FRAMEWORK in rk3368_common.h

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> To build TPL and SPL stages for the RK3368, we will also need to
> enable the SPL_FRAMEWORK.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Version-changes: 2
> - dropped duplicate definition (this in fact dropped one of the
>   patches in this series) of CONFIG_SYS_SDRAM_BASE from
>   rk3368_common.h
>
> ---
>
> Changes in v2: None
>
>  include/configs/rk3368_common.h | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 49/56] rockchip: rk3368: spl: add TPL support

[Simon Glass]

Hi Philipp,

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This adds the TPL support for the RK3368, including the u-boot-tpl.lds.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - copies the enum for the IOMUX config of the debug UART into the TPL
>   support code, as the various constants are otherwise private to the
>   pinctrl code (and we can't include pinctrl in the TPL stage due to
>   size constraints/dependencies)
>
>  arch/arm/mach-rockchip/Makefile              |   1 +
>  arch/arm/mach-rockchip/rk3368-board-tpl.c    | 168 +++++++++++++++++++++++++++
>  arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds |  13 +++
>  3 files changed, 182 insertions(+)
>  create mode 100644 arch/arm/mach-rockchip/rk3368-board-tpl.c
>  create mode 100644 arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds
>
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 633c91e..960f40f 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -12,6 +12,7 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
>  obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o
>
>  obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o
> +obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o
>
>  obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
>  obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
> diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c
> new file mode 100644
> index 0000000..04620e1
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c
> @@ -0,0 +1,168 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#define DEBUG
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/cru_rk3368.h>
> +#include <asm/arch/grf_rk3368.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/timer.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * The ARMv8 generic timer uses the STIMER1 as its clock-source.
> + * Set up the STIMER1 to free-running (i.e. auto-reload) to start
> + * the generic timer counting (if we don't do this, udelay will not
> + * work and block indefinitively).
> + */
> +static void secure_timer_init(void)
> +{
> +       struct rk_timer * const stimer1 =
> +               (struct rk_timer * const)0xff830020;

Can we not get this and other addresses from DT (or of-platdata)?

[U-Boot] [PATCH v2 50/56] rockchip: spl: make spl-boot-order code reusable (split from rk3399)

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> In order to reuse the support for the u-boot,spl-boot-order property
> from the rk3399, we split it into a reusable module that can be
> included by the SPL code for any of our boards.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - added in v2
>
>  arch/arm/mach-rockchip/Makefile           |   2 +-
>  arch/arm/mach-rockchip/rk3399-board-spl.c | 104 ----------------------------
>  arch/arm/mach-rockchip/spl-boot-order.c   | 108 ++++++++++++++++++++++++++++++
>  3 files changed, 109 insertions(+), 105 deletions(-)
>  create mode 100644 arch/arm/mach-rockchip/spl-boot-order.c

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 51/56] rockchip: rk3368: spl: add SPL support

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> Adds SPL support for the RK3368 (assuming that our TPL stage has
> initialised DRAM and set up the memory firewall).
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - reuses the support for configuring the boot order using the
>   u-boot,spl-boot-order property
> - drops the initialisation of the debug_uart
> - adds pinctrl-configuration for the preloader UART
>
>  arch/arm/mach-rockchip/Makefile           |  2 +-
>  arch/arm/mach-rockchip/rk3368-board-spl.c | 98 +++++++++++++++++++++++++++++++
>  2 files changed, 99 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/mach-rockchip/rk3368-board-spl.c

Reviewed-by: Simon Glass <sjg@chromium.org>

Please see below?

>
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index c5d17f9..c3ed862 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -18,7 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
>  obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
>  obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
>  obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
> -obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o
> +obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o
>  obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o
>
>  ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
> diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c
> new file mode 100644
> index 0000000..691db41
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c
> @@ -0,0 +1,98 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/arch/cru_rk3368.h>
> +#include <asm/arch/grf_rk3368.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/timer.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * The ARMv8 generic timer uses the STIMER1 as its clock-source.
> + * Set up the STIMER1 to free-running (i.e. auto-reload) to start
> + * the generic timer counting (if we don't do this, udelay will not
> + * work and block indefinitively).
> + */
> +static void secure_timer_init(void)
> +{
> +       struct rk_timer * const stimer1 =
> +               (struct rk_timer * const)0xff830020;

Can we use DT for this?

> +       const u32 TIMER_EN = BIT(0);
> +
> +       writel(~0u, &stimer1->timer_load_count0);
> +       writel(~0u, &stimer1->timer_load_count1);
> +       writel(TIMER_EN, &stimer1->timer_ctrl_reg);
> +}
> +
> +void board_debug_uart_init(void)
> +{
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> +       struct udevice *pinctrl;
> +       struct udevice *dev;
> +       int ret;
> +
> +       ret = spl_early_init();
> +       if (ret) {
> +               debug("spl_early_init() failed: %d\n", ret);
> +               hang();
> +       }
> +
> +       /* Make sure the ARMv8 generic timer counts */
> +       secure_timer_init();
> +
> +       /* Set up our preloader console */
> +       ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> +       if (ret) {
> +               error("%s: pinctrl init failed: %d\n", __func__, ret);
> +               hang();
> +       }
> +
> +       ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0);
> +       if (ret) {
> +               error("%s: failed to set up console UART\n", __func__);
> +               hang();
> +       }
> +
> +       preloader_console_init();
> +
> +       ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> +       if (ret) {
> +               debug("DRAM init failed: %d\n", ret);
> +               return;
> +       }
> +}
> +
> +u32 spl_boot_mode(const u32 boot_device)
> +{
> +       return MMCSD_MODE_RAW;
> +}
> +
> +u32 spl_boot_device(void)
> +{
> +       return BOOT_DEVICE_MMC1;
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +       /* Just empty function now - can't decide what to choose */
> +       debug("%s: %s\n", __func__, name);
> +
> +       return 0;
> +}
> +#endif
> --
> 2.1.4
>

Regards,
Simon

[U-Boot] [PATCH v2 52/56] rockchip: rk3368: spl: mark SPL and TPL as supported for ROCKCHIP_RK3368

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> With SPL and TPL support for the RK3368 in place, mark SPL and TPL as
> supported from Kconfig for the RK3368.  As this is primarily tested on
> the RK3368-uQ7, we'll leave it to board's individual defconfig to
> enable.
>
> Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output
> during the early boot-up, as we turn on TPL and SPL.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  arch/arm/mach-rockchip/Kconfig | 7 +++++++
>  1 file changed, 7 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 53/56] rockchip: spi: enable support for the rk_spi driver for the RK3368

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> For the RK3368, we can reuse the SPI driver (although we'll have to
> eventually investigate whether it can be merged with the
> designware_spi.c driver) also used for the RK3288 and RK3399.
> This adds the necessary compatible string to support the RK3368.
>
> Note that the assumption that GPLL will be clocked at 594MHz is not
> true for the RK3368, but this will not lead to incorrect functioning
> (just to a lower-than-expected SPI operating frequency): this has been
> documented in the driver, so it doesn't cause any headaches when
> someone next needs to touch the clock code of this driver.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> Version-changes: 2
> - added in this version
>
> ---
>
> Changes in v2: None
>
>  drivers/spi/rk_spi.c | 9 +++++++++
>  1 file changed, 9 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 54/56] rockchip: board: lion-rk3368: add support for the RK3368-uQ7

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
> MXM-230 edge connector compatible with the Qseven specification)
> form-factor system-on-module based on the octo-core Rockchip RK3368.
> It is designed, supported and manufactured by Theobroma Systems.
>
> It provides the following features:
>  - 8x Cortex-A53 (in 2 clusters of 4 cores each)
>  - (on-module) up to 4GB of DDR3 memory
>  - (on-module) SPI-NOR flash
>  - (on-module) eMMC
>  - Gigabit Ethernet (with an on-module KSZ9031 PHY)
>  - USB
>  - HDMI
>  - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
>  - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - marks pinctrl-node as 'u-boot,dm-pre-reloc' to ensure MMC2 (eMMC)
>   works in the SPL stage
> - makes uart0 as 'u-boot,dm-pre-reloc' to allow initialising the
>   preloader console (instead of relying solely on the debug UART)
> - adds support for SPI1 (and the on-module SPI flash)
> - splits the a 'u-boot.dtsi' off the DTS file
> - updates the defconfig for SPI and SPI flash support
>
>  arch/arm/dts/Makefile                              |   1 +
>  arch/arm/dts/rk3368-lion-u-boot.dtsi               |  68 +++++++
>  arch/arm/dts/rk3368-lion.dts                       | 195 +++++++++++++++++++++
>  arch/arm/mach-rockchip/rk3368/Kconfig              |  21 +++
>  board/theobroma-systems/lion_rk3368/Kconfig        |  15 ++
>  board/theobroma-systems/lion_rk3368/MAINTAINERS    |  10 ++
>  board/theobroma-systems/lion_rk3368/Makefile       |   7 +
>  board/theobroma-systems/lion_rk3368/README         |  60 +++++++
>  .../theobroma-systems/lion_rk3368/fit_spl_atf.its  |  51 ++++++
>  board/theobroma-systems/lion_rk3368/lion_rk3368.c  |  25 +++
>  configs/lion-rk3368_defconfig                      |  88 ++++++++++
>  include/configs/lion_rk3368.h                      |  19 ++
>  12 files changed, 560 insertions(+)
>  create mode 100644 arch/arm/dts/rk3368-lion-u-boot.dtsi
>  create mode 100644 arch/arm/dts/rk3368-lion.dts
>  create mode 100644 board/theobroma-systems/lion_rk3368/Kconfig
>  create mode 100644 board/theobroma-systems/lion_rk3368/MAINTAINERS
>  create mode 100644 board/theobroma-systems/lion_rk3368/Makefile
>  create mode 100644 board/theobroma-systems/lion_rk3368/README
>  create mode 100644 board/theobroma-systems/lion_rk3368/fit_spl_atf.its
>  create mode 100644 board/theobroma-systems/lion_rk3368/lion_rk3368.c
>  create mode 100644 configs/lion-rk3368_defconfig
>  create mode 100644 include/configs/lion_rk3368.h
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 55/56] rockchip: board: puma-rk3399: fix warnings in puma_rk3399/fit_spl_atf.its

[Simon Glass]

On 26 July 2017 at 04:40, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The ITS file generated warnings due to @<num> designations in the naming
> which cause DTC to complain as follows:
>   Warning (unit_address_vs_reg): Node /images/uboot at 1 has a unit name, but no reg property
>   Warning (unit_address_vs_reg): Node /images/atf at 1 has a unit name, but no reg property
>   Warning (unit_address_vs_reg): Node /images/pmu at 1 has a unit name, but no reg property
>   Warning (unit_address_vs_reg): Node /images/fdt at 1 has a unit name, but no reg property
>   Warning (unit_address_vs_reg): Node /configurations/conf at 1 has a unit name, but no reg property
>
> This removes the @<num> part from the names, as we only have a single
> image for each payload aspect (and only a single configuration) anyway.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 56/56] rockchip: board: puma_rk3399: rename ATF firmware

[Simon Glass]

On 26 July 2017 at 04:41, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> From: Klaus Goger <klaus.goger@theobroma-systems.com>
>
> prefix the bl31 firmware needed to build uboot.itb so it can coexist in
> the build area with ATFs from other boards (i.e. lion_rk3368)
>
> Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  board/theobroma-systems/puma_rk3399/README          | 2 +-
>  board/theobroma-systems/puma_rk3399/fit_spl_atf.its | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 47/56] rockchip: dts: rk3368: add DMC node in rk3368.dtsi

[Andy Yan]

Hi Philipp:


On 2017年07月26日 18:40, Philipp Tomsich wrote:
> For full SPL support, including DRAM initialisation, we need a few
> nodes from the DTS: this commit adds the DMC (DRAM controller) node,
> the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
> as 'u-boot,dm-pre-reloc'.  In addition to this, we also include the
> dt-binding for the DMC to allow DTS files including this DTSI to refer
> to the symbolic constants for the DDR3 bin and for the
> memory-schedule.
>
> Note that the DMC contains both the memory regions for the
> (Designware) protocol controller as well as the DDR PHY.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi
>
>   arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------
>   1 file changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
> index 9daf765..163d9ee 100644
> --- a/arch/arm/dts/rk3368.dtsi
> +++ b/arch/arm/dts/rk3368.dtsi
> @@ -46,6 +46,7 @@
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/pinctrl/rockchip.h>
>   #include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/memory/rk3368-dmc.h>
>   
>   / {
>   	compatible = "rockchip,rk3368";
> @@ -227,6 +228,22 @@
>   		#clock-cells = <0>;
>   	};
>   
> +	dmc: dmc at ff610000 {
> +		compatible = "rockchip,rk3368-dmc", "syscon";
> +		rockchip,cru = <&cru>;
> +		rockchip,grf = <&grf>;
> +		rockchip,msch = <&service_msch>;
> +		reg = <0 0xff610000 0 0x400
> +		       0 0xff620000 0 0x400>;
> +	};
> +
> +	service_msch: syscon at ffac0000 {
> +		u-boot,dm-pre-reloc;
> +		compatible = "rockchip,rk3368-msch", "syscon";
> +		reg = <0x0 0xffac0000 0x0 0x2000>;
> +		status = "okay";
> +	};
> +
>   	sdmmc: dwmmc at ff0c0000 {
>   		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
>   		reg = <0x0 0xff0c0000 0x0 0x4000>;
> @@ -546,12 +563,6 @@
>   		status = "disabled";
>   	};
>   
> -	dmc: dmc at ff610000 {
> -		u-boot,dm-pre-reloc;
> -		compatible = "rockchip,rk3368-dmc", "syscon";
> -		reg = <0x0 0xff610000 0x0 0x1000>;
> -	};
> -
>   	i2c0: i2c at ff650000 {
>   		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
>   		reg = <0x0 0xff650000 0x0 0x1000>;
> @@ -653,6 +664,7 @@
>   	};
>   
>   	cru: clock-controller at ff760000 {
> +		u-boot,dm-pre-reloc;

     Can we move these u-boot specific properties to rk3368-uboot.dtsi, 
and keep the core dts/dtsi files
the same as the upstream kernel. It will make things easier if we want 
sync with the upstream kernel someday.
>   		compatible = "rockchip,rk3368-cru";
>   		reg = <0x0 0xff760000 0x0 0x1000>;
>   		rockchip,grf = <&grf>;
> @@ -661,6 +673,7 @@
>   	};
>   
>   	grf: syscon at ff770000 {
> +		u-boot,dm-pre-reloc;
>   		compatible = "rockchip,rk3368-grf", "syscon";
>   		reg = <0x0 0xff770000 0x0 0x1000>;
>   	};

[U-Boot] [PATCH v2 47/56] rockchip: dts: rk3368: add DMC node in rk3368.dtsi

[Dr. Philipp Tomsich]

Andy,

> On 28 Jul 2017, at 10:34, Andy Yan <andy.yan@rock-chips.com> wrote:
> 
> Hi Philipp:
> 
> 
> On 2017年07月26日 18:40, Philipp Tomsich wrote:
>> For full SPL support, including DRAM initialisation, we need a few
>> nodes from the DTS: this commit adds the DMC (DRAM controller) node,
>> the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU
>> as 'u-boot,dm-pre-reloc'.  In addition to this, we also include the
>> dt-binding for the DMC to allow DTS files including this DTSI to refer
>> to the symbolic constants for the DDR3 bin and for the
>> memory-schedule.
>> 
>> Note that the DMC contains both the memory regions for the
>> (Designware) protocol controller as well as the DDR PHY.
>> 
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> 
>> ---
>> 
>> Changes in v2:
>> - removes a 'u-boot,dm-pre-reloc' from dmc-node in rk3368.dtsi
>> 
>>  arch/arm/dts/rk3368.dtsi | 25 +++++++++++++++++++------
>>  1 file changed, 19 insertions(+), 6 deletions(-)
>> 
>> diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
>> index 9daf765..163d9ee 100644
>> --- a/arch/arm/dts/rk3368.dtsi
>> +++ b/arch/arm/dts/rk3368.dtsi
>> @@ -46,6 +46,7 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/pinctrl/rockchip.h>
>>  #include <dt-bindings/thermal/thermal.h>
>> +#include <dt-bindings/memory/rk3368-dmc.h>
>>    / {
>>  	compatible = "rockchip,rk3368";
>> @@ -227,6 +228,22 @@
>>  		#clock-cells = <0>;
>>  	};
>>  +	dmc: dmc at ff610000 {
>> +		compatible = "rockchip,rk3368-dmc", "syscon";
>> +		rockchip,cru = <&cru>;
>> +		rockchip,grf = <&grf>;
>> +		rockchip,msch = <&service_msch>;
>> +		reg = <0 0xff610000 0 0x400
>> +		       0 0xff620000 0 0x400>;
>> +	};
>> +
>> +	service_msch: syscon at ffac0000 {
>> +		u-boot,dm-pre-reloc;
>> +		compatible = "rockchip,rk3368-msch", "syscon";
>> +		reg = <0x0 0xffac0000 0x0 0x2000>;
>> +		status = "okay";
>> +	};
>> +
>>  	sdmmc: dwmmc at ff0c0000 {
>>  		compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
>>  		reg = <0x0 0xff0c0000 0x0 0x4000>;
>> @@ -546,12 +563,6 @@
>>  		status = "disabled";
>>  	};
>>  -	dmc: dmc at ff610000 {
>> -		u-boot,dm-pre-reloc;
>> -		compatible = "rockchip,rk3368-dmc", "syscon";
>> -		reg = <0x0 0xff610000 0x0 0x1000>;
>> -	};
>> -
>>  	i2c0: i2c at ff650000 {
>>  		compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
>>  		reg = <0x0 0xff650000 0x0 0x1000>;
>> @@ -653,6 +664,7 @@
>>  	};
>>    	cru: clock-controller at ff760000 {
>> +		u-boot,dm-pre-reloc;
> 
>    Can we move these u-boot specific properties to rk3368-uboot.dtsi, and keep the core dts/dtsi files
> the same as the upstream kernel. It will make things easier if we want sync with the upstream kernel someday.
>>  		compatible = "rockchip,rk3368-cru";
>>  		reg = <0x0 0xff760000 0x0 0x1000>;
>>  		rockchip,grf = <&grf>;
>> @@ -661,6 +673,7 @@
>>  	};
>>    	grf: syscon at ff770000 {
>> +		u-boot,dm-pre-reloc;
>>  		compatible = "rockchip,rk3368-grf", "syscon";
>>  		reg = <0x0 0xff770000 0x0 0x1000>;
>>  	};

Seems like a missed a couple more of these (as I already started moving these to a
'-u-boot.dtsi’ file.  I’ll try to catch all of these in the next iteration.

Cheers,
Philipp.

[U-Boot] [PATCH v2 46/56] rockchip: rk3368: add DRAM controller driver with DRAM initialisation

[Dr. Philipp Tomsich]

> On 28 Jul 2017, at 05:39, Simon Glass <sjg@chromium.org> wrote:
> 
> Hi Philipp,
> 
> On 26 July 2017 at 04:40, Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>> This adds a DRAM controller driver for the RK3368 and places it in
>> drivers/ddr/rockchip (where the other DM-enabled DRAM controller
>> drivers for rockchip devices should also be moved eventually).
> 
> I thought we were actually planning on using drivers/ram ?

Thanks for catching another one of my out-of-sync commit messages.
The drivers are in fact in drivers/ram (see below for the location of files)
and I just hadn’t updated the message.

Love the fact that someone actually reads these with 

> 
>> 
>> At this stage, only the following feature-set is supported:
>> - DDR3
>> - 32-bit configuration (i.e. fully populated)
>> - dual-rank (i.e. no auto-detection of ranks)
>> - DDR3-1600K speed-bin
>> 
>> This driver expects to run from a TPL stage that will later return to
>> the RK3368 BROM.  It communicates with later stages through the
>> os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
>> init code).
>> 
>> Unlike other DMC drivers for RK32xx and RK33xx parts, the required
>> timings are calculated within the driver based on a target frequency
>> and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
>> time).
>> 
>> The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
>> register for controlling the operation of its (single-channel) DRAM
>> controller in the GRF block.  This provides for selecting DDR3, mobile
>> DDR modes, and control low-power operation.
>> As part of this change, DDRC0_CON0 is also added to the GRF structure
>> definition (at offset 0x600).
>> 
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> ---
>> 
>> Changes in v2: None
>> 
>> arch/arm/include/asm/arch-rockchip/ddr_rk3368.h    | 187 ++++
>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h    |   3 +
>> arch/arm/mach-rockchip/rk3368/Makefile             |   1 -
>> arch/arm/mach-rockchip/rk3368/sdram_rk3368.c       |  60 --
>> .../clock/rockchip,rk3368-dmc.txt                  |  67 ++
>> drivers/ram/Makefile                               |   2 +
>> drivers/ram/rockchip/Makefile                      |   7 +
>> drivers/ram/rockchip/dmc-rk3368.c                  | 990 +++++++++++++++++++++
>> include/dt-bindings/memory/rk3368-dmc.h            |  30 +
>> 9 files changed, 1286 insertions(+), 61 deletions(-)
>> create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3368.h
>> delete mode 100644 arch/arm/mach-rockchip/rk3368/sdram_rk3368.c
>> create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt
>> create mode 100644 drivers/ram/rockchip/Makefile
>> create mode 100644 drivers/ram/rockchip/dmc-rk3368.c
>> create mode 100644 include/dt-bindings/memory/rk3368-dmc.h
>> 
> 
> Apart from that nit:
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> 
> How can we unify these dram drivers?

I already raised the topic with Kever (as the RK322x driver looks identical on
the pctl-side and just has a slightly different PHY): getting these merged is something
I expect to happen for v2017.11 … but will require some effort from Rockchip’s team.

In fact, there’s a couple more drivers and quite a bit of infrastructure code that
requires de-duplication efforts.

Regards,
Philipp.

[U-Boot] [PATCH v2 44/56] net: gmac_rockchip: Add support for the RK3368 GMAC

[Dr. Philipp Tomsich]

> On 28 Jul 2017, at 05:39, Simon Glass <sjg@chromium.org> wrote:
> 
> Hi Philipp,
> 
> On 26 July 2017 at 04:40, Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>> The GMAC in the RK3368 once again is identical to the incarnation in
>> the RK3288 and the RK3399, except for where some of the configuration
>> and control registers are located in the GRF.
>> 
>> This adds the RK3368-specific logic necessary to reuse this driver.
>> 
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> 
>> ---
>> 
>> Changes in v2:
>> - moves the bit-definitions (for GRF registers) specific to the GMAC
>>  into the GMAC driver: these include interface speed selection and
>>  configuring the RGMII output mode
>> 
>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h |  1 +
>> drivers/net/gmac_rockchip.c                     | 78 +++++++++++++++++++++++++
>> 2 files changed, 79 insertions(+)
>> 
>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> index ec42d7a..1f84ff9 100644
>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> @@ -129,4 +129,5 @@ enum {
>>        MCU_CODE_BASE_BIT31_BIT28_SHIFT         = 0,
>>        MCU_CODE_BASE_BIT31_BIT28_MASK          = GENMASK(3, 0),
>> };
>> +
>> #endif
>> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
>> index c9f9e83..586ccbf 100644
>> --- a/drivers/net/gmac_rockchip.c
>> +++ b/drivers/net/gmac_rockchip.c
>> @@ -16,6 +16,7 @@
>> #include <asm/arch/clock.h>
>> #include <asm/arch/hardware.h>
>> #include <asm/arch/grf_rk3288.h>
>> +#include <asm/arch/grf_rk3368.h>
>> #include <asm/arch/grf_rk3399.h>
>> #include <dm/pinctrl.h>
>> #include <dt-bindings/clock/rk3288-cru.h>
>> @@ -83,6 +84,38 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
>>        return 0;
>> }
>> 
>> +static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
> 
> What is the plan here? Can we use a ioctl() interface to the grf
> syscon perhaps, to remove this SoC-specific code from the driver?

Indeed. This is the longer-term plan.

Regards,
Philipp.

[U-Boot] [PATCH v2 32/56] rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver

[Dr. Philipp Tomsich]

> On 28 Jul 2017, at 05:38, Simon Glass <sjg@chromium.org> wrote:
> 
> On 26 July 2017 at 04:40, Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>> There is no real reason to keep the bit-definitions for the IOMUX in
>> the grf header file (which defines the register layout of the GRF block):
>> these should only be used by our pinctrl driver (with the possible
>> exception of early debug-init code in TPL/SPL).
>> 
>> This moves the relevant definitions from the grf_rk3368.h header
>> into the pinctrl driver pinctrl_rk3368.c.
>> 
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> 
>> - moved bit-definitions pertinent to pinctrl (i.e. the various IOMUX
>>  definitions) to the rk3368 pinctrl driver implementation
>> 
>> ---
>> 
>> Changes in v2: None
>> 
>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 316 -----------------------
>> drivers/pinctrl/rockchip/pinctrl_rk3368.c       | 325 ++++++++++++++++++++++++
>> 2 files changed, 325 insertions(+), 316 deletions(-)
> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> 
> (although I expect that we will reinstate the SHIFT macros?)

This is something we’ll need to discuss.

In fact, I was hoping that we could redo the IOMUX support for
the growing number of devices to reduce the amount of code
duplication and to use tables of pin-location/-function.

The current state is untenable for the long run, as we duplicate
not just the GPIO0B1_MASK on every chip, but even have
GPIO0A1_MASK, GPIO0B1_MASK, … all refer to the same
value.

I haven’t fully sketched out how I want this to look, but it’s on my
list for the final release of the year.

—Philipp.

[U-Boot] [PATCH v2 29/56] rockchip: rk3368: grf: use shifted-constants

[Dr. Philipp Tomsich]

> On 28 Jul 2017, at 05:38, Simon Glass <sjg@chromium.org> wrote:
> 
> Hi Philipp,
> 
> On 26 July 2017 at 04:40, Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>> The RK3368 GRF header was still defines with a shifted-mask but with
>> non-shifted function selectors for the IOMUX defines.  As the RK3368
>> support is still fresh enough to allow a quick change, we do this now
>> before having more code use this.
>> 
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> 
>> ---
>> 
>> Changes in v2:
>> - dropped the RK3368_ prefix for the GRF constants
>> 
>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 441 ++++++++++++------------
>> drivers/pinctrl/rockchip/pinctrl_rk3368.c       |   9 +-
>> 2 files changed, 226 insertions(+), 224 deletions(-)
>> 
>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> index a438f5d..1966960 100644
>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>> @@ -1,4 +1,6 @@
>> -/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
>> +/*
>> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>  *
>>  * SPDX-License-Identifier:     GPL-2.0+
>>  */
>> @@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
>> 
>> /*GRF_GPIO0C_IOMUX*/
>> enum {
>> -       GPIO0C7_SHIFT           = 14,
>> -       GPIO0C7_MASK            = 3 << GPIO0C7_SHIFT,
>> -       GPIO0C7_GPIO            = 0,
>> -       GPIO0C7_LCDC_D19,
>> -       GPIO0C7_TRACE_D9,
>> -       GPIO0C7_UART1_RTSN,
>> -
>> -       GPIO0C6_SHIFT           = 12,
>> -       GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
>> +       GPIO0C7_MASK           = GENMASK(15, 14),
>> +       GPIO0C7_GPIO           = 0,
>> +       GPIO0C7_LCDC_D19        = (1 << 14),
>> +       GPIO0C7_TRACE_D9        = (2 << 14),
>> +       GPIO0C7_UART1_RTSN      = (3 << 14),
> 
> Can we keep the SHIFT macros so we(e.g.) don't have to open-code the
> '14' each time?

In fact I wanted this to stick out, so we are motivated to move towards
a model of set_pin_function(BANK_C, PIN_7, UART1) where the
shift-value can then calculated from the pin# within the bank (and the
function id is looked up from a config-table for this pin).

[U-Boot] [PATCH v2 28/56] rockchip: rk3368: syscon: MSCH/PMUGRF/GRF support for OF_PLATDATA

[Dr. Philipp Tomsich]

> On 28 Jul 2017, at 05:38, Simon Glass <sjg@chromium.org> wrote:
> 
> On 26 July 2017 at 04:40, Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>> The RK3368 has both a limited SPL size (just 0x7000 bytes) and the
>> added challenge of booting in AArch64, which increases the code size
>> for SPL (particularily when using the LP64 programming model).  For
>> this reason we expect the RK3368 to always use OF_PLATDATA for its
>> SPL stage.
> 
> But I thought that you had SDRAM ready by the time you boot to SPL? So
> why the limit?

Another commit message from before I moved to having a TPL.
Having another set of eyes look at these is priceless.

> 
>> 
>> This change adds support for the MSCH, PMUGRF and GRF register regions
>> in syscon, which are necessary for initialising the RK3368's DRAM
>> controller.
>> 
>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> ---
>> 
>> Changes in v2: None
>> 
>> arch/arm/mach-rockchip/rk3368/syscon_rk3368.c | 35 +++++++++++++++++++++++++++
>> 1 file changed, 35 insertions(+)

[U-Boot] [PATCH v2 54/56] rockchip: board: lion-rk3368: add support for the RK3368-uQ7

[Andy Yan]

Hi Philipp:


On 2017年07月26日 18:40, Philipp Tomsich wrote:
> The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm,
> MXM-230 edge connector compatible with the Qseven specification)
> form-factor system-on-module based on the octo-core Rockchip RK3368.
> It is designed, supported and manufactured by Theobroma Systems.
>
> It provides the following features:
>   - 8x Cortex-A53 (in 2 clusters of 4 cores each)
>   - (on-module) up to 4GB of DDR3 memory
>   - (on-module) SPI-NOR flash
>   - (on-module) eMMC
>   - Gigabit Ethernet (with an on-module KSZ9031 PHY)
>   - USB
>   - HDMI
>   - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
>   - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - marks pinctrl-node as 'u-boot,dm-pre-reloc' to ensure MMC2 (eMMC)
>    works in the SPL stage
> - makes uart0 as 'u-boot,dm-pre-reloc' to allow initialising the
>    preloader console (instead of relying solely on the debug UART)
> - adds support for SPI1 (and the on-module SPI flash)
> - splits the a 'u-boot.dtsi' off the DTS file
> - updates the defconfig for SPI and SPI flash support
>
>   arch/arm/dts/Makefile                              |   1 +
>   arch/arm/dts/rk3368-lion-u-boot.dtsi               |  68 +++++++
>   arch/arm/dts/rk3368-lion.dts                       | 195 +++++++++++++++++++++
>   arch/arm/mach-rockchip/rk3368/Kconfig              |  21 +++
>   board/theobroma-systems/lion_rk3368/Kconfig        |  15 ++
>   board/theobroma-systems/lion_rk3368/MAINTAINERS    |  10 ++
>   board/theobroma-systems/lion_rk3368/Makefile       |   7 +
>   board/theobroma-systems/lion_rk3368/README         |  60 +++++++
>   .../theobroma-systems/lion_rk3368/fit_spl_atf.its  |  51 ++++++
>   board/theobroma-systems/lion_rk3368/lion_rk3368.c  |  25 +++
>   configs/lion-rk3368_defconfig                      |  88 ++++++++++
>   include/configs/lion_rk3368.h                      |  19 ++
>   12 files changed, 560 insertions(+)
>   create mode 100644 arch/arm/dts/rk3368-lion-u-boot.dtsi
>   create mode 100644 arch/arm/dts/rk3368-lion.dts
>   create mode 100644 board/theobroma-systems/lion_rk3368/Kconfig
>   create mode 100644 board/theobroma-systems/lion_rk3368/MAINTAINERS
>   create mode 100644 board/theobroma-systems/lion_rk3368/Makefile
>   create mode 100644 board/theobroma-systems/lion_rk3368/README
>   create mode 100644 board/theobroma-systems/lion_rk3368/fit_spl_atf.its
>   create mode 100644 board/theobroma-systems/lion_rk3368/lion_rk3368.c
>   create mode 100644 configs/lion-rk3368_defconfig
>   create mode 100644 include/configs/lion_rk3368.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index fd28290..5a22bb1 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>   	rk3288-veyron-mickey.dtb \
>   	rk3288-veyron-minnie.dtb \
>   	rk3328-evb.dtb \
> +	rk3368-lion.dtb \
>   	rk3368-sheep.dtb \
>   	rk3368-geekbox.dtb \
>   	rk3368-px5-evb.dtb \
> diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi
> new file mode 100644
> index 0000000..1f9ade9
> --- /dev/null
> +++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi
> @@ -0,0 +1,68 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier:     GPL-2.0+	X11
> + */
> +
> +/ {
> +	config {
> +		u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
> +		u-boot,mmc-env-offset = <0x4000>;      /* @  16KB */
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +		u-boot,spl-boot-order = &emmc, &sdmmc;
> +	};
> +
> +};
> +
> +&pinctrl {
> +	 u-boot,dm-pre-reloc;
> +};
> +
> +&dmc {
> +	 u-boot,dm-pre-reloc;
> +
> +	/*
> +	 * Validation of throughput using SPEC2000 shows the following
> +	 * relative performance for the different memory schedules:
> +	 *  - CBDR: 30.1
> +	 *  - CBRD: 29.8
> +	 *  - CRBD: 29.9
> +	 * Note that the best performance for any given application workload
> +	 * may vary from the default configured here (e.g. 164.gzip is fastest
> +	 * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
> +	 *
> +	 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
> +	 * details on the 'rockchip,memory-schedule' property and how it
> +	 * affects the physical-address to device-address mapping.
> +	 */
> +	rockchip,memory-schedule = <DMC_MSCH_CBDR>;
> +	rockchip,ddr-frequency = <800000000>;
> +	rockchip,ddr-speed-bin = <DDR3_1600K>;
> +
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&emmc {
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc {
> +	u-boot,dm-pre-reloc;
> +};
> +
> +&spi1 {
> +	u-boot,dm-pre-reloc;
> +
> +	spiflash: w25q32dw at 0 {
> +		u-boot,dm-pre-reloc;
> +	};
> +};
> +
> +
> diff --git a/arch/arm/dts/rk3368-lion.dts b/arch/arm/dts/rk3368-lion.dts
> new file mode 100644
> index 0000000..850db50
> --- /dev/null
> +++ b/arch/arm/dts/rk3368-lion.dts
> @@ -0,0 +1,195 @@
> +/*
> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier:     GPL-2.0+	X11
> + */
> +
> +/dts-v1/;
> +#include "rk3368.dtsi"
> +#include "rk3368-lion-u-boot.dtsi"
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	model = "Theobroma Systems RK3368-uQ7 SoM";
> +	compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
> +
> +	aliases {
> +		mmc0 = &emmc;
> +		mmc1 = &sdmmc;
> +	};
> +
> +	memory at 0 {
> +		device_type = "memory";
> +		reg = <0x0 0x0 0x0 0x80000000>;
> +	};
> +
> +	ext_gmac: gmac-clk {
> +		compatible = "fixed-clock";
> +		clock-frequency = <125000000>;
> +		clock-output-names = "ext_gmac";
> +		#clock-cells = <0>;
> +	};
> +
> +	vcc_sys: vcc-sys-regulator {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vcc_sys";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		regulator-always-on;
> +		regulator-boot-on;
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&emmc {
> +	status = "okay";
> +	bus-width = <8>;
> +	cap-mmc-highspeed;
> +	clock-frequency = <150000000>;
> +	disable-wp;
> +	keep-power-in-suspend;
> +	non-removable;
> +	num-slots = <1>;
> +	vmmc-supply = <&vcc33_io>;
> +	vqmmc-supply = <&vcc18_io>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
> +};
> +
> +&sdmmc {
> +	status = "okay";
> +};
> +
> +&gmac {
> +	status = "okay";
> +	phy-supply = <&vcc33_io>;
> +	phy-mode = "rgmii";
> +	clock_in_out = "input";
> +	snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
> +	snps,reset-active-low;
> +	snps,reset-delays-us = <2 10000 50000>;
> +	assigned-clocks = <&cru SCLK_MAC>;
> +	assigned-clock-parents = <&ext_gmac>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&rgmii_pins>;
> +	tx_delay = <0x10>;
> +	rx_delay = <0x10>;
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +
> +	rk808: pmic at 1b {
> +		compatible = "rockchip,rk808";
> +		reg = <0x1b>;
> +		interrupt-parent = <&gpio0>;
> +		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
> +		rockchip,system-power-controller;
> +		vcc1-supply = <&vcc_sys>;
> +		vcc2-supply = <&vcc_sys>;
> +		vcc3-supply = <&vcc_sys>;
> +		vcc4-supply = <&vcc_sys>;
> +		vcc6-supply = <&vcc_sys>;
> +		vcc7-supply = <&vcc_sys>;
> +		vcc8-supply = <&vcc_sys>;
> +		vcc9-supply = <&vcc_sys>;
> +		vcc10-supply = <&vcc_sys>;
> +		vcc11-supply = <&vcc_sys>;
> +		vcc12-supply = <&vcc_sys>;
> +		clock-output-names = "xin32k", "rk808-clkout2";
> +		#clock-cells = <1>;
> +
> +		regulators {
> +			vdd_cpu: DCDC_REG1 {
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <700000>;
> +				regulator-max-microvolt = <1500000>;
> +				regulator-name = "vdd_cpu";
> +			};
> +
> +			vdd_log: DCDC_REG2 {
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <700000>;
> +				regulator-max-microvolt = <1500000>;
> +				regulator-name = "vdd_log";
> +			};
> +
> +			vcc_ddr: DCDC_REG3 {
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-name = "vcc_ddr";
> +			};
> +
> +			vcc33_io: DCDC_REG4 {
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-name = "vcc33_io";
> +			};
> +
> +			vcc33_video: LDO_REG2 {
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <3300000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-name = "vcc33_video";
> +			};
> +
> +			vdd10_pll: LDO_REG3 {
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <1000000>;
> +				regulator-max-microvolt = <1000000>;
> +				regulator-name = "vdd10_pll";
> +			};
> +
> +			vcc18_io: LDO_REG4 {
> +				regulator-boot-on;
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-name = "vcc18_io";
> +			};
> +
> +			vdd10_video: LDO_REG6 {
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <1000000>;
> +				regulator-max-microvolt = <1000000>;
> +				regulator-name = "vdd10_video";
> +			};
> +
> +			vcc18_video: LDO_REG8 {
> +				regulator-always-on;
> +				regulator-boot-on;
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <1800000>;
> +				regulator-name = "vcc18_video";
> +			};
> +		};
> +	};
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> +
> +&spi1 {
> +	status = "okay";
> +
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	spiflash: w25q32dw at 0 {
> +		compatible = "spi-flash";
> +		reg = <0>;
> +		spi-max-frequency = <49500000>;
> +		spi-cpol;
> +		spi-cpha;
> +	};
> +};
> diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
> index 6d32068..f8189f1 100644
> --- a/arch/arm/mach-rockchip/rk3368/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3368/Kconfig
> @@ -3,6 +3,26 @@ if ROCKCHIP_RK3368
>   choice
>   	prompt "RK3368 board"
>   
> +config TARGET_LION_RK3368
> +        bool "Theobroma Systems RK3368-uQ7 (Lion) module"
> +	help
> +	  The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm,
> +	  MXM-230 connector) system-on-module designed by Theobroma
> +	  Systems for industrial applications.
> +
> +	  It provides the following features:
> +	   - 8x Cortex-A53 (in 2 clusters of 4 cores each)
> +	   - (on-module) up to 4GB of DDR3 memory
> +	   - (on-module) SPI-NOR flash
> +	   - (on-module) eMMC
> +	   - Gigabit Ethernet (with an on-module KSZ9031 PHY)
> +	   - USB
> +	   - HDMI
> +	   - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
> +	   - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
> +	   - on-module STM32 providing CAN, RTC and fan-control
> +	   - (optional on-module) EAL4+-certified security module
> +
>   config TARGET_SHEEP
>   	bool "Sheep board"
>   	help
> @@ -25,6 +45,7 @@ endchoice
>   config SYS_SOC
>   	default "rockchip"
>   
> +source "board/theobroma-systems/lion_rk3368/Kconfig"
>   source "board/rockchip/sheep_rk3368/Kconfig"
>   source "board/geekbuying/geekbox/Kconfig"
>   source "board/rockchip/evb_px5/Kconfig"
> diff --git a/board/theobroma-systems/lion_rk3368/Kconfig b/board/theobroma-systems/lion_rk3368/Kconfig
> new file mode 100644
> index 0000000..d7aa487
> --- /dev/null
> +++ b/board/theobroma-systems/lion_rk3368/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_LION_RK3368
> +
> +config SYS_BOARD
> +	default "lion_rk3368"
> +
> +config SYS_VENDOR
> +	default "theobroma-systems"
> +
> +config SYS_CONFIG_NAME
> +	default "lion_rk3368"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +	def_bool y
> +
> +endif
> diff --git a/board/theobroma-systems/lion_rk3368/MAINTAINERS b/board/theobroma-systems/lion_rk3368/MAINTAINERS
> new file mode 100644
> index 0000000..857f784
> --- /dev/null
> +++ b/board/theobroma-systems/lion_rk3368/MAINTAINERS
> @@ -0,0 +1,10 @@
> +LION-RK3368 (RK3368-uQ7 system-on-module)
> +M:	Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> +M:	Klaus Goger <klaus.goger@theobroma-systems.com>
> +S:	Maintained
> +F:	board/theobroma-systems/lion_rk3368
> +F:	include/configs/lion_rk3368.h
> +F:	arch/arm/dts/rk3368-lion.dts
> +F:	configs/lion-rk3368_defconfig
> +W:	https://www.theobroma-systems.com/rk3368-uq7/tech-specs
> +T:	git git://git.theobroma-systems.com/lion-u-boot.git
> diff --git a/board/theobroma-systems/lion_rk3368/Makefile b/board/theobroma-systems/lion_rk3368/Makefile
> new file mode 100644
> index 0000000..f13a20b
> --- /dev/null
> +++ b/board/theobroma-systems/lion_rk3368/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
> +#
> +# SPDX-License-Identifier:	GPL-2.0+
> +#
> +
> +obj-y += lion_rk3368.o
> diff --git a/board/theobroma-systems/lion_rk3368/README b/board/theobroma-systems/lion_rk3368/README
> new file mode 100644
> index 0000000..47304fc
> --- /dev/null
> +++ b/board/theobroma-systems/lion_rk3368/README
> @@ -0,0 +1,60 @@
> +Here is the step-by-step to boot to U-Boot on RK3368-uQ7
> +
> +Get the Source and build ATF
> +============================
> +
> +  > git clone git://git.theobroma-systems.com/arm-trusted-firmware.git
> +  > cd arm-trusted-firmware
> +  > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3368 bl31
> +  > cp build/rk3368/release/bl31.bin ../u-boot/bl31-rk3368.bin
> +
> +Configure U-Boot
> +================
> +
> +  > cd ../u-boot
> +  > make lion-rk3368_defconfig
> +
> +Build the TPL/SPL stage
> +=======================
> +
> +  > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm
> +  > tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img
> +  > cat spl/u-boot-spl-dtb.bin >> spl-3368.img
> +
> +Build the full U-Boot and a FIT image including the ATF
> +=======================================================
> +
> +  > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm u-boot.itb
> +
> +Write to a SD-card
> +==================
> +
> +  > dd if=spl-3368.img of=/dev/sdb seek=64
> +  > dd if=u-boot.itb of=/dev/sdb seek=512
> +
> +
> +If everything went according to plan, you should see the following
> +output on UART0:
> +
> +<debug_uart> U-Boot TPL board init
> +Trying to boot from BOOTROM
> +Returning to boot ROM...
> +Trying to boot from MMC1
> +NOTICE:  BL31: v1.3(release):v1.2-1320-gbf43a443
> +NOTICE:  BL31: Built : 18:04:47, Jul  5 2017
> +
> +
> +U-Boot 2017.07-00158-g2395e99858 (Jul 18 2017 - 21:03:31 +0200)
> +
> +Model: Theobroma Systems RK3368-uQ7 SoM
> +DRAM:  2 GiB
> +MMC:   dwmmc at ff0c0000: 1, dwmmc at ff0f0000: 0
> +Using default environment
> +
> +In:    serial at ff180000
> +Out:   serial at ff180000
> +Err:   serial at ff180000
> +Net:
> +Warning: ethernet at ff290000 (eth0) using random MAC address - d2:69:35:7e:d0:1e
> +eth0: ethernet at ff290000
> +Hit any key to stop autoboot:  2
> diff --git a/board/theobroma-systems/lion_rk3368/fit_spl_atf.its b/board/theobroma-systems/lion_rk3368/fit_spl_atf.its
> new file mode 100644
> index 0000000..e7d98b9
> --- /dev/null
> +++ b/board/theobroma-systems/lion_rk3368/fit_spl_atf.its
> @@ -0,0 +1,51 @@
> +/*
> + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * Minimal dts for a SPL FIT image payload.
> + *
> + * SPDX-License-Identifier: GPL-2.0+  X11
> + */
> +
> +/dts-v1/;
> +
> +/ {
> +	description = "FIT image with U-Boot proper, ATF bl31, DTB";
> +	#address-cells = <1>;
> +
> +	images {
> +		uboot {
> +			description = "U-Boot (64-bit)";
> +			data = /incbin/("../../../u-boot-nodtb.bin");
> +			type = "standalone";
> +			arch = "arm64";
> +			compression = "none";
> +			load = <0x00200000>;
> +		};
> +		atf {
> +			description = "ARM Trusted Firmware";
> +			data = /incbin/("../../../bl31-rk3368.bin");
> +			type = "firmware";
> +			arch = "arm64";
> +			compression = "none";
> +			load = <0x00010000>;
> +			entry = <0x00010000>;
> +		};
> +
> +		fdt {
> +			description = "RK3368-uQ7 (Lion) flat device-tree";
> +			data = /incbin/("../../../u-boot.dtb");
> +			type = "flat_dt";
> +			compression = "none";
> +		};
> +	};
> +
> +	configurations {
> +		default = "conf";
> +		conf {
> +			description = "Theobroma Systems RK3368-uQ7 (Puma) SoM";
> +			firmware = "uboot";
> +			loadables = "atf";
> + 			fdt = "fdt";

     It seems you use a Space instead of Tab here.
> +		};
> +	};
> +};
> diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
> new file mode 100644
> index 0000000..73b1488
> --- /dev/null
> +++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c
> @@ -0,0 +1,25 @@
> +/*
> + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +#include <common.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3368.h>
> +#include <asm/arch/timer.h>
> +#include <syscon.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int mach_cpu_init(void)
> +{
> +	return 0;
> +}
> +
> +int board_init(void)
> +{
> +	return 0;
> +}
> diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
> new file mode 100644
> index 0000000..73671d9
> --- /dev/null
> +++ b/configs/lion-rk3368_defconfig
> @@ -0,0 +1,88 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_ROCKCHIP_RK3368=y
> +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
> +CONFIG_TPL_LIBCOMMON_SUPPORT=y
> +CONFIG_TPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_SPL_SPI_FLASH_SUPPORT=y
> +CONFIG_SPL_SPI_SUPPORT=y
> +CONFIG_SPL_STACK_R_ADDR=0x600000
> +CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion"
> +CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368"
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/lion_rk3368/fit_spl_atf.its"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_ARCH_EARLY_INIT_R=y
> +CONFIG_SPL=y
> +CONFIG_SPL_BOOTROM_SUPPORT=y
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
> +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
> +CONFIG_SPL_ATF_SUPPORT=y
> +CONFIG_SPL_ATF_TEXT_BASE=0x10000
> +CONFIG_TPL=y
> +CONFIG_TPL_BOOTROM_SUPPORT=y
> +CONFIG_TPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_FASTBOOT=y
> +CONFIG_ANDROID_BOOT_IMAGE=y
> +# CONFIG_CMD_IMLS is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_REGULATOR=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_TPL_OF_CONTROL=y
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
> +CONFIG_TPL_OF_PLATDATA=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_TPL_DM=y
> +CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_TPL_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_TPL_SYSCON=y
> +CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_TPL_CLK=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_PHY_MICREL=y
> +CONFIG_PHY_MICREL_KSZ9031=y
> +CONFIG_DM_ETH=y
> +CONFIG_ETH_DESIGNWARE=y
> +CONFIG_RGMII=y
> +CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PINCTRL_ROCKCHIP_RK3368=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_TPL_RAM=y
> +CONFIG_DEBUG_UART_BASE=0xFF180000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_DEBUG_UART_SKIP_INIT=y
> +CONFIG_ROCKCHIP_SPI=y
> +CONFIG_SYSRESET=y
> +CONFIG_USE_TINY_PRINTF=y
> +CONFIG_SPL_TINY_MEMSET=y
> +CONFIG_ERRNO_STR=y
> +CONFIG_SMBIOS_MANUFACTURER="rockchip"
> diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h
> new file mode 100644
> index 0000000..1f25b31
> --- /dev/null
> +++ b/include/configs/lion_rk3368.h
> @@ -0,0 +1,19 @@
> +/*
> + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#ifndef __CONFIGS_LION_RK3368_H
> +#define __CONFIGS_LION_RK3368_H
> +
> +#include <configs/rk3368_common.h>
> +
> +#define CONFIG_SYS_MMC_ENV_DEV		0
> +#define KERNEL_LOAD_ADDR		0x280000
> +#define DTB_LOAD_ADDR			0x5600000
> +#define INITRD_LOAD_ADDR		0x5bf0000
> +#define CONFIG_ENV_IS_NOWHERE
> +#define CONFIG_ENV_SIZE			0x2000
> +
> +#endif

[U-Boot] [PATCH v2 29/56] rockchip: rk3368: grf: use shifted-constants

[Simon Glass]

On 28 July 2017 at 02:53, Dr. Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
>
>> On 28 Jul 2017, at 05:38, Simon Glass <sjg@chromium.org> wrote:
>>
>> Hi Philipp,
>>
>> On 26 July 2017 at 04:40, Philipp Tomsich
>> <philipp.tomsich@theobroma-systems.com> wrote:
>>> The RK3368 GRF header was still defines with a shifted-mask but with
>>> non-shifted function selectors for the IOMUX defines.  As the RK3368
>>> support is still fresh enough to allow a quick change, we do this now
>>> before having more code use this.
>>>
>>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>>
>>> ---
>>>
>>> Changes in v2:
>>> - dropped the RK3368_ prefix for the GRF constants
>>>
>>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 441 ++++++++++++------------
>>> drivers/pinctrl/rockchip/pinctrl_rk3368.c       |   9 +-
>>> 2 files changed, 226 insertions(+), 224 deletions(-)
>>>
>>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> index a438f5d..1966960 100644
>>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>> @@ -1,4 +1,6 @@
>>> -/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
>>> +/*
>>> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>>  *
>>>  * SPDX-License-Identifier:     GPL-2.0+
>>>  */
>>> @@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
>>>
>>> /*GRF_GPIO0C_IOMUX*/
>>> enum {
>>> -       GPIO0C7_SHIFT           = 14,
>>> -       GPIO0C7_MASK            = 3 << GPIO0C7_SHIFT,
>>> -       GPIO0C7_GPIO            = 0,
>>> -       GPIO0C7_LCDC_D19,
>>> -       GPIO0C7_TRACE_D9,
>>> -       GPIO0C7_UART1_RTSN,
>>> -
>>> -       GPIO0C6_SHIFT           = 12,
>>> -       GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
>>> +       GPIO0C7_MASK           = GENMASK(15, 14),
>>> +       GPIO0C7_GPIO           = 0,
>>> +       GPIO0C7_LCDC_D19        = (1 << 14),
>>> +       GPIO0C7_TRACE_D9        = (2 << 14),
>>> +       GPIO0C7_UART1_RTSN      = (3 << 14),
>>
>> Can we keep the SHIFT macros so we(e.g.) don't have to open-code the
>> '14' each time?
>
> In fact I wanted this to stick out, so we are motivated to move towards
> a model of set_pin_function(BANK_C, PIN_7, UART1) where the
> shift-value can then calculated from the pin# within the bank (and the
> function id is looked up from a config-table for this pin).

That sounds like a separate issue to me. The problem here is that it
it isn't clear where the '14' comes from and what it is common with.
Well, not clear enough to permit using an editor's search/replace
function.

Regards,
Simon

[U-Boot] [PATCH v2 29/56] rockchip: rk3368: grf: use shifted-constants

[Dr. Philipp Tomsich]

> On 01 Aug 2017, at 11:49, Simon Glass <sjg@chromium.org> wrote:
> 
> On 28 July 2017 at 02:53, Dr. Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
>> 
>>> On 28 Jul 2017, at 05:38, Simon Glass <sjg@chromium.org> wrote:
>>> 
>>> Hi Philipp,
>>> 
>>> On 26 July 2017 at 04:40, Philipp Tomsich
>>> <philipp.tomsich@theobroma-systems.com> wrote:
>>>> The RK3368 GRF header was still defines with a shifted-mask but with
>>>> non-shifted function selectors for the IOMUX defines.  As the RK3368
>>>> support is still fresh enough to allow a quick change, we do this now
>>>> before having more code use this.
>>>> 
>>>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>>> 
>>>> ---
>>>> 
>>>> Changes in v2:
>>>> - dropped the RK3368_ prefix for the GRF constants
>>>> 
>>>> arch/arm/include/asm/arch-rockchip/grf_rk3368.h | 441 ++++++++++++------------
>>>> drivers/pinctrl/rockchip/pinctrl_rk3368.c       |   9 +-
>>>> 2 files changed, 226 insertions(+), 224 deletions(-)
>>>> 
>>>> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>>> index a438f5d..1966960 100644
>>>> --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>>> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h
>>>> @@ -1,4 +1,6 @@
>>>> -/* (C) Copyright 2016 Rockchip Electronics Co., Ltd
>>>> +/*
>>>> + * (C) Copyright 2016 Rockchip Electronics Co., Ltd
>>>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
>>>> *
>>>> * SPDX-License-Identifier:     GPL-2.0+
>>>> */
>>>> @@ -100,315 +102,318 @@ check_member(rk3368_pmu_grf, os_reg[0], 0x200);
>>>> 
>>>> /*GRF_GPIO0C_IOMUX*/
>>>> enum {
>>>> -       GPIO0C7_SHIFT           = 14,
>>>> -       GPIO0C7_MASK            = 3 << GPIO0C7_SHIFT,
>>>> -       GPIO0C7_GPIO            = 0,
>>>> -       GPIO0C7_LCDC_D19,
>>>> -       GPIO0C7_TRACE_D9,
>>>> -       GPIO0C7_UART1_RTSN,
>>>> -
>>>> -       GPIO0C6_SHIFT           = 12,
>>>> -       GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
>>>> +       GPIO0C7_MASK           = GENMASK(15, 14),
>>>> +       GPIO0C7_GPIO           = 0,
>>>> +       GPIO0C7_LCDC_D19        = (1 << 14),
>>>> +       GPIO0C7_TRACE_D9        = (2 << 14),
>>>> +       GPIO0C7_UART1_RTSN      = (3 << 14),
>>> 
>>> Can we keep the SHIFT macros so we(e.g.) don't have to open-code the
>>> '14' each time?
>> 
>> In fact I wanted this to stick out, so we are motivated to move towards
>> a model of set_pin_function(BANK_C, PIN_7, UART1) where the
>> shift-value can then calculated from the pin# within the bank (and the
>> function id is looked up from a config-table for this pin).
> 
> That sounds like a separate issue to me. The problem here is that it
> it isn't clear where the '14' comes from and what it is common with.
> Well, not clear enough to permit using an editor's search/replace
> function.

Concern understood. I’ll revise.

Regards,
Philipp.