* [U-Boot] [RESENT PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL
@ 2017-07-27 4:53 Kever Yang
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node Kever Yang
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Kever Yang @ 2017-07-27 4:53 UTC (permalink / raw)
To: u-boot
Disable the ddr secure region setting in SPL and the ddr memory
becomes non-secure, every one can access it. the trust firmware
like OPTEE should have the correct setting for it after SPL if
there is one.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2:
- add comment for the change and update the commit message
arch/arm/mach-rockchip/rk322x-board-spl.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
index 15216c7..4ddb8ba 100644
--- a/arch/arm/mach-rockchip/rk322x-board-spl.c
+++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
@@ -41,6 +41,8 @@ static struct rk322x_grf * const grf = (void *)GRF_BASE;
CON_IOMUX_UART2SEL_MASK,
CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
}
+
+#define SGRF_DDR_CON0 0x10150000
void board_init_f(ulong dummy)
{
struct udevice *dev;
@@ -71,6 +73,8 @@ void board_init_f(ulong dummy)
return;
}
+ /* Disable the ddr secure region setting to make it non-secure */
+ rk_clrreg(SGRF_DDR_CON0, 0x4000);
#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom();
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [RESENT PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node
2017-07-27 4:53 [U-Boot] [RESENT PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Kever Yang
@ 2017-07-27 4:54 ` Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
` (2 more replies)
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 3/4] rockchip: clk: update dwmmc clock div Kever Yang
` (4 subsequent siblings)
5 siblings, 3 replies; 16+ messages in thread
From: Kever Yang @ 2017-07-27 4:54 UTC (permalink / raw)
To: u-boot
mmc using 150000000 as max-frequency like what rk3288 sets.
This can speed up the mmc read/write, the actual mmc clock is:
Before this patch: 37.125M
After this patch: 49.5M
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2:
- remove fifo-mode in patch
- update commit message to explain why this patch needed.
arch/arm/dts/rk3229-evb.dts | 1 -
arch/arm/dts/rk322x.dtsi | 4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index 5042c39..ae0b0a4 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -78,7 +78,6 @@
cap-sd-highspeed;
card-detect-delay = <200>;
disable-wp;
- max-frequency = <50000000>;
num-slots = <1>;
supports-sd;
};
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index ddbe113..22324f9 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -388,6 +388,7 @@
sdmmc: dwmmc at 30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
+ max-frequency = <150000000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
@@ -414,9 +415,8 @@
emmc: dwmmc at 30020000 {
compatible = "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
+ max-frequency = <150000000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <37500000>;
- max-frequency = <37500000>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [RESENT PATCH v2 3/4] rockchip: clk: update dwmmc clock div
2017-07-27 4:53 [U-Boot] [RESENT PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Kever Yang
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node Kever Yang
@ 2017-07-27 4:54 ` Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
` (2 more replies)
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 4/4] rockchip: clk: remove RATE_TO_DIV Kever Yang
` (3 subsequent siblings)
5 siblings, 3 replies; 16+ messages in thread
From: Kever Yang @ 2017-07-27 4:54 UTC (permalink / raw)
To: u-boot
dwmmc controller has default internal divider by 2,
and we always provide double of the clock rate request by
dwmmc controller. Sync code for all Rockchip SoC with:
4055b46 rockchip: clk: rk3288: fix mmc clock setting
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2:
- add comment for mmc clock div 2 internal
- update the commit message
drivers/clk/rockchip/clk_rk3036.c | 6 +++---
drivers/clk/rockchip/clk_rk3188.c | 5 +++--
drivers/clk/rockchip/clk_rk322x.c | 8 ++++----
drivers/clk/rockchip/clk_rk3288.c | 1 +
drivers/clk/rockchip/clk_rk3328.c | 9 +++++----
drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++----
6 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 5ecf512..514ea88 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -235,7 +235,7 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
}
src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
- return DIV_TO_RATE(src_rate, div);
+ return DIV_TO_RATE(src_rate, div) / 2;
}
static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
@@ -247,10 +247,10 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
/* mmc clock auto divide 2 in internal */
- src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+ src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
if (src_clk_div > 0x7f) {
- src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
mux = EMMC_SEL_24M;
} else {
mux = EMMC_SEL_GPLL;
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index 6f30332..cbf31d7 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -287,7 +287,7 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
return -EINVAL;
}
- return DIV_TO_RATE(gclk_rate, div);
+ return DIV_TO_RATE(gclk_rate, div) / 2;
}
static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
@@ -296,7 +296,8 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
int src_clk_div;
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
- src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
assert(src_clk_div <= 0x3f);
switch (periph) {
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index fdeb816..a1a0aff 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -239,7 +239,7 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
}
src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
- return DIV_TO_RATE(src_rate, div);
+ return DIV_TO_RATE(src_rate, div) / 2;
}
static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
@@ -250,11 +250,11 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
- /* mmc clock auto divide 2 in internal */
- src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
if (src_clk_div > 0x7f) {
- src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
mux = EMMC_SEL_24M;
} else {
mux = EMMC_SEL_GPLL;
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index adcc0a6..209075a 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -531,6 +531,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
int mux;
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
if (src_clk_div > 0x3f) {
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 2065a8a..c3a6650 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -412,9 +412,9 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
== CLK_EMMC_PLL_SEL_24M)
- return DIV_TO_RATE(OSC_HZ, div);
+ return DIV_TO_RATE(OSC_HZ, div) / 2;
else
- return DIV_TO_RATE(GPLL_HZ, div);
+ return DIV_TO_RATE(GPLL_HZ, div) / 2;
}
static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
@@ -436,11 +436,12 @@ static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
return -EINVAL;
}
/* Select clk_sdmmc/emmc source from GPLL by default */
- src_clk_div = GPLL_HZ / set_rate;
+ /* mmc clock defaulg div 2 internal, need provide double in cru */
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
if (src_clk_div > 127) {
/* use 24MHz source for 400KHz clock */
- src_clk_div = OSC_HZ / set_rate;
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
rk_clrsetreg(&cru->clksel_con[con_id],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 54079cd..d2abda5 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -750,18 +750,21 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->clksel_con[16]);
+ /* dwmmc controller have internal div 2 */
+ div = 2;
break;
case SCLK_EMMC:
con = readl(&cru->clksel_con[21]);
+ div = 1;
break;
default:
return -EINVAL;
}
- div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
+ div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
== CLK_EMMC_PLL_SEL_24M)
- return DIV_TO_RATE(24*1000*1000, div);
+ return DIV_TO_RATE(OSC_HZ, div);
else
return DIV_TO_RATE(GPLL_HZ, div);
}
@@ -776,11 +779,12 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
case HCLK_SDMMC:
case SCLK_SDMMC:
/* Select clk_sdmmc source from GPLL by default */
- src_clk_div = GPLL_HZ / set_rate;
+ /* mmc clock defaulg div 2 internal, provide double in cru */
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
if (src_clk_div > 127) {
/* use 24MHz source for 400KHz clock */
- src_clk_div = 24*1000*1000 / set_rate;
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
rk_clrsetreg(&cru->clksel_con[16],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [RESENT PATCH v2 4/4] rockchip: clk: remove RATE_TO_DIV
2017-07-27 4:53 [U-Boot] [RESENT PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Kever Yang
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node Kever Yang
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 3/4] rockchip: clk: update dwmmc clock div Kever Yang
@ 2017-07-27 4:54 ` Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
` (2 more replies)
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Philipp Tomsich
` (2 subsequent siblings)
5 siblings, 3 replies; 16+ messages in thread
From: Kever Yang @ 2017-07-27 4:54 UTC (permalink / raw)
To: u-boot
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
Changes in v2:
- add overflow check for div-field
drivers/clk/rockchip/clk_rk3036.c | 3 ++-
drivers/clk/rockchip/clk_rk3188.c | 12 +++++-------
drivers/clk/rockchip/clk_rk322x.c | 6 ++----
drivers/clk/rockchip/clk_rk3288.c | 7 +++----
drivers/clk/rockchip/clk_rk3368.c | 8 +++-----
drivers/clk/rockchip/clk_rk3399.c | 11 ++++++-----
drivers/clk/rockchip/clk_rv1108.c | 3 ---
7 files changed, 21 insertions(+), 29 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 514ea88..83f4ae6 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -249,8 +249,9 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
/* mmc clock auto divide 2 in internal */
src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
- if (src_clk_div > 0x7f) {
+ if (src_clk_div > 128) {
src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ assert(src_clk_div - 1 < 128);
mux = EMMC_SEL_24M;
} else {
mux = EMMC_SEL_GPLL;
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c
index cbf31d7..8c2c9bc 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -71,9 +71,6 @@ enum {
SOCSTS_GPLL_LOCK = 1 << 8,
};
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _nr, _no) {\
@@ -297,7 +294,7 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
/* mmc clock defaulg div 2 internal, need provide double in cru */
- src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
+ src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
assert(src_clk_div <= 0x3f);
switch (periph) {
@@ -351,8 +348,9 @@ static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate,
static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate,
int periph, uint freq)
{
- int src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
+ assert(src_clk_div < 128);
switch (periph) {
case SCLK_SPI0:
assert(src_clk_div <= SPI0_DIV_MASK);
@@ -401,8 +399,8 @@ static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
* reparent aclk_cpu_pre from apll to gpll
* set up dependent divisors for PCLK/HCLK and ACLK clocks.
*/
- aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ);
- assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+ aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1;
+ assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
rk_clrsetreg(&cru->cru_clksel_con[0],
CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT |
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index a1a0aff..d7f6a3c 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -26,9 +26,6 @@ enum {
OUTPUT_MIN_HZ = 24 * 1000000,
};
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
@@ -253,8 +250,9 @@ static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
/* mmc clock defaulg div 2 internal, need provide double in cru */
src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
- if (src_clk_div > 0x7f) {
+ if (src_clk_div > 128) {
src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ assert(src_clk_div - 1 < 128);
mux = EMMC_SEL_24M;
} else {
mux = EMMC_SEL_GPLL;
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 209075a..0490757 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -118,9 +118,6 @@ enum {
SOCSTS_NPLL_LOCK = 1 << 9,
};
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _nr, _no) {\
@@ -536,6 +533,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
if (src_clk_div > 0x3f) {
src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ assert(src_clk_div < 0x40);
mux = EMMC_PLL_SELECT_24MHZ;
assert((int)EMMC_PLL_SELECT_24MHZ ==
(int)MMC0_PLL_SELECT_24MHZ);
@@ -609,7 +607,8 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,
int src_clk_div;
debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
- src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
+ assert(src_clk_div < 128);
switch (periph) {
case SCLK_SPI0:
rk_clrsetreg(&cru->cru_clksel_con[25],
diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c
index 52cad38..22a66c6 100644
--- a/drivers/clk/rockchip/clk_rk3368.c
+++ b/drivers/clk/rockchip/clk_rk3368.c
@@ -30,9 +30,6 @@ struct pll_div {
#define GPLL_HZ (576 * 1000 * 1000)
#define CPLL_HZ (400 * 1000 * 1000)
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _nr, _no) { \
@@ -171,7 +168,7 @@ static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
u32 con_id;
u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
- div = RATE_TO_DIV(gpll_rate, rate << 1);
+ div = DIV_ROUND_UP(gpll_rate, rate << 1) - 1;
switch (clk_id) {
case SCLK_SDMMC:
@@ -188,7 +185,8 @@ static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
}
if (div > 0x3f) {
- div = RATE_TO_DIV(OSC_HZ, rate);
+ div = DIV_ROUND_UP(OSC_HZ, rate) - 1;
+ assert(div < 0x40);
rk_clrsetreg(&cru->clksel_con[con_id],
MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
(MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index d2abda5..e6cb6b4 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -676,8 +676,8 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
const struct spi_clkreg *spiclk = NULL;
int src_clk_div;
- src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
- assert(src_clk_div < 127);
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
+ assert(src_clk_div < 128);
switch (clk_id) {
case SCLK_SPI1 ... SCLK_SPI5:
@@ -782,9 +782,10 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
/* mmc clock defaulg div 2 internal, provide double in cru */
src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
- if (src_clk_div > 127) {
+ if (src_clk_div > 128) {
/* use 24MHz source for 400KHz clock */
src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
+ assert(src_clk_div - 1 < 128);
rk_clrsetreg(&cru->clksel_con[16],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
@@ -799,7 +800,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
case SCLK_EMMC:
/* Select aclk_emmc source from GPLL */
src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
- assert(src_clk_div - 1 < 31);
+ assert(src_clk_div - 1 < 32);
rk_clrsetreg(&cru->clksel_con[21],
ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
@@ -808,7 +809,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
/* Select clk_emmc source from GPLL too */
src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
- assert(src_clk_div - 1 < 127);
+ assert(src_clk_div - 1 < 128);
rk_clrsetreg(&cru->clksel_con[22],
CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c
index 818293d..cf966bb 100644
--- a/drivers/clk/rockchip/clk_rv1108.c
+++ b/drivers/clk/rockchip/clk_rv1108.c
@@ -25,9 +25,6 @@ enum {
OUTPUT_MIN_HZ = 24 * 1000000,
};
-#define RATE_TO_DIV(input_rate, output_rate) \
- ((input_rate) / (output_rate) - 1);
-
#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
--
1.9.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL
2017-07-27 4:53 [U-Boot] [RESENT PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Kever Yang
` (2 preceding siblings ...)
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 4/4] rockchip: clk: remove RATE_TO_DIV Kever Yang
@ 2017-07-27 8:21 ` Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
5 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-07-27 8:21 UTC (permalink / raw)
To: u-boot
> Disable the ddr secure region setting in SPL and the ddr memory
> becomes non-secure, every one can access it. the trust firmware
> like OPTEE should have the correct setting for it after SPL if
> there is one.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - add comment for the change and update the commit message
>
> arch/arm/mach-rockchip/rk322x-board-spl.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 2/4] rockchip: rk322x: update max-frequency for mmc node
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node Kever Yang
@ 2017-07-27 8:21 ` Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-07-27 8:21 UTC (permalink / raw)
To: u-boot
> mmc using 150000000 as max-frequency like what rk3288 sets.
> This can speed up the mmc read/write, the actual mmc clock is:
> Before this patch: 37.125M
> After this patch: 49.5M
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - remove fifo-mode in patch
> - update commit message to explain why this patch needed.
>
> arch/arm/dts/rk3229-evb.dts | 1 -
> arch/arm/dts/rk322x.dtsi | 4 ++--
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 3/4] rockchip: clk: update dwmmc clock div
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 3/4] rockchip: clk: update dwmmc clock div Kever Yang
@ 2017-07-27 8:21 ` Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-07-27 8:21 UTC (permalink / raw)
To: u-boot
> dwmmc controller has default internal divider by 2,
> and we always provide double of the clock rate request by
> dwmmc controller. Sync code for all Rockchip SoC with:
> 4055b46 rockchip: clk: rk3288: fix mmc clock setting
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - add comment for mmc clock div 2 internal
> - update the commit message
>
> drivers/clk/rockchip/clk_rk3036.c | 6 +++---
> drivers/clk/rockchip/clk_rk3188.c | 5 +++--
> drivers/clk/rockchip/clk_rk322x.c | 8 ++++----
> drivers/clk/rockchip/clk_rk3288.c | 1 +
> drivers/clk/rockchip/clk_rk3328.c | 9 +++++----
> drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++----
> 6 files changed, 24 insertions(+), 17 deletions(-)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 4/4] rockchip: clk: remove RATE_TO_DIV
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 4/4] rockchip: clk: remove RATE_TO_DIV Kever Yang
@ 2017-07-27 8:21 ` Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-07-27 8:21 UTC (permalink / raw)
To: u-boot
> Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
> clock driver.
> Add or fix the div-field overflow check at the same time.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - add overflow check for div-field
>
> drivers/clk/rockchip/clk_rk3036.c | 3 ++-
> drivers/clk/rockchip/clk_rk3188.c | 12 +++++-------
> drivers/clk/rockchip/clk_rk322x.c | 6 ++----
> drivers/clk/rockchip/clk_rk3288.c | 7 +++----
> drivers/clk/rockchip/clk_rk3368.c | 8 +++-----
> drivers/clk/rockchip/clk_rk3399.c | 11 ++++++-----
> drivers/clk/rockchip/clk_rv1108.c | 3 ---
> 7 files changed, 21 insertions(+), 29 deletions(-)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL
2017-07-27 4:53 [U-Boot] [RESENT PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Kever Yang
` (3 preceding siblings ...)
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Philipp Tomsich
@ 2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
5 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-07-27 8:22 UTC (permalink / raw)
To: u-boot
> Disable the ddr secure region setting in SPL and the ddr memory
> becomes non-secure, every one can access it. the trust firmware
> like OPTEE should have the correct setting for it after SPL if
> there is one.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - add comment for the change and update the commit message
>
> arch/arm/mach-rockchip/rk322x-board-spl.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 2/4] rockchip: rk322x: update max-frequency for mmc node
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
@ 2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-07-27 8:22 UTC (permalink / raw)
To: u-boot
> mmc using 150000000 as max-frequency like what rk3288 sets.
> This can speed up the mmc read/write, the actual mmc clock is:
> Before this patch: 37.125M
> After this patch: 49.5M
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - remove fifo-mode in patch
> - update commit message to explain why this patch needed.
>
> arch/arm/dts/rk3229-evb.dts | 1 -
> arch/arm/dts/rk322x.dtsi | 4 ++--
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 3/4] rockchip: clk: update dwmmc clock div
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 3/4] rockchip: clk: update dwmmc clock div Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
@ 2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-07-27 8:22 UTC (permalink / raw)
To: u-boot
> dwmmc controller has default internal divider by 2,
> and we always provide double of the clock rate request by
> dwmmc controller. Sync code for all Rockchip SoC with:
> 4055b46 rockchip: clk: rk3288: fix mmc clock setting
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - add comment for mmc clock div 2 internal
> - update the commit message
>
> drivers/clk/rockchip/clk_rk3036.c | 6 +++---
> drivers/clk/rockchip/clk_rk3188.c | 5 +++--
> drivers/clk/rockchip/clk_rk322x.c | 8 ++++----
> drivers/clk/rockchip/clk_rk3288.c | 1 +
> drivers/clk/rockchip/clk_rk3328.c | 9 +++++----
> drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++----
> 6 files changed, 24 insertions(+), 17 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 4/4] rockchip: clk: remove RATE_TO_DIV
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 4/4] rockchip: clk: remove RATE_TO_DIV Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
@ 2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-07-27 8:22 UTC (permalink / raw)
To: u-boot
> Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
> clock driver.
> Add or fix the div-field overflow check at the same time.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> Changes in v2:
> - add overflow check for div-field
>
> drivers/clk/rockchip/clk_rk3036.c | 3 ++-
> drivers/clk/rockchip/clk_rk3188.c | 12 +++++-------
> drivers/clk/rockchip/clk_rk322x.c | 6 ++----
> drivers/clk/rockchip/clk_rk3288.c | 7 +++----
> drivers/clk/rockchip/clk_rk3368.c | 8 +++-----
> drivers/clk/rockchip/clk_rk3399.c | 11 ++++++-----
> drivers/clk/rockchip/clk_rv1108.c | 3 ---
> 7 files changed, 21 insertions(+), 29 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL
2017-07-27 4:53 [U-Boot] [RESENT PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Kever Yang
` (4 preceding siblings ...)
2017-07-27 8:22 ` Philipp Tomsich
@ 2017-08-10 12:50 ` Philipp Tomsich
5 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-08-10 12:50 UTC (permalink / raw)
To: u-boot
> Disable the ddr secure region setting in SPL and the ddr memory
> becomes non-secure, every one can access it. the trust firmware
> like OPTEE should have the correct setting for it after SPL if
> there is one.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2:
> - add comment for the change and update the commit message
>
> arch/arm/mach-rockchip/rk322x-board-spl.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 2/4] rockchip: rk322x: update max-frequency for mmc node
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
@ 2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-08-10 12:50 UTC (permalink / raw)
To: u-boot
> mmc using 150000000 as max-frequency like what rk3288 sets.
> This can speed up the mmc read/write, the actual mmc clock is:
> Before this patch: 37.125M
> After this patch: 49.5M
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2:
> - remove fifo-mode in patch
> - update commit message to explain why this patch needed.
>
> arch/arm/dts/rk3229-evb.dts | 1 -
> arch/arm/dts/rk322x.dtsi | 4 ++--
> 2 files changed, 2 insertions(+), 3 deletions(-)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 3/4] rockchip: clk: update dwmmc clock div
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 3/4] rockchip: clk: update dwmmc clock div Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
@ 2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-08-10 12:50 UTC (permalink / raw)
To: u-boot
> dwmmc controller has default internal divider by 2,
> and we always provide double of the clock rate request by
> dwmmc controller. Sync code for all Rockchip SoC with:
> 4055b46 rockchip: clk: rk3288: fix mmc clock setting
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2:
> - add comment for mmc clock div 2 internal
> - update the commit message
>
> drivers/clk/rockchip/clk_rk3036.c | 6 +++---
> drivers/clk/rockchip/clk_rk3188.c | 5 +++--
> drivers/clk/rockchip/clk_rk322x.c | 8 ++++----
> drivers/clk/rockchip/clk_rk3288.c | 1 +
> drivers/clk/rockchip/clk_rk3328.c | 9 +++++----
> drivers/clk/rockchip/clk_rk3399.c | 12 ++++++++----
> 6 files changed, 24 insertions(+), 17 deletions(-)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 16+ messages in thread
* [U-Boot] [U-Boot, RESENT, v2, 4/4] rockchip: clk: remove RATE_TO_DIV
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 4/4] rockchip: clk: remove RATE_TO_DIV Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
@ 2017-08-10 12:50 ` Philipp Tomsich
2 siblings, 0 replies; 16+ messages in thread
From: Philipp Tomsich @ 2017-08-10 12:50 UTC (permalink / raw)
To: u-boot
> Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
> clock driver.
> Add or fix the div-field overflow check at the same time.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2:
> - add overflow check for div-field
>
> drivers/clk/rockchip/clk_rk3036.c | 3 ++-
> drivers/clk/rockchip/clk_rk3188.c | 12 +++++-------
> drivers/clk/rockchip/clk_rk322x.c | 6 ++----
> drivers/clk/rockchip/clk_rk3288.c | 7 +++----
> drivers/clk/rockchip/clk_rk3368.c | 8 +++-----
> drivers/clk/rockchip/clk_rk3399.c | 11 ++++++-----
> drivers/clk/rockchip/clk_rv1108.c | 3 ---
> 7 files changed, 21 insertions(+), 29 deletions(-)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2017-08-10 12:50 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-07-27 4:53 [U-Boot] [RESENT PATCH v2 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Kever Yang
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 2/4] rockchip: rk322x: update max-frequency for mmc node Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 3/4] rockchip: clk: update dwmmc clock div Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2017-07-27 4:54 ` [U-Boot] [RESENT PATCH v2 4/4] rockchip: clk: remove RATE_TO_DIV Kever Yang
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, " Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
2017-07-27 8:21 ` [U-Boot] [U-Boot, RESENT, v2, 1/4] rockchip: rk322x: set the DDR region as non-secure in SPL Philipp Tomsich
2017-07-27 8:22 ` Philipp Tomsich
2017-08-10 12:50 ` Philipp Tomsich
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