[PATCH 0/3][v3] pinctrl: qcom: add support for sparse GPIOs

[PATCH 0/3][v3] pinctrl: qcom: add support for sparse GPIOs

[Timur Tabi]

First patch update gpiolib so that it requests the GPIO before trying to
initialize it.

Second patch allows for for pinctrl-msm to understand GPIO groups with
no pins.  Such pins are "hidden" and can't be exported or accessed.

Last patch updates the QDF2xxx driver to take advantage of all that.

v3: Add checks in IRQ mask and unmask functions


Timur Tabi (3):
  gliolib: request the gpio before querying its direction
  [v3] pinctrl: qcom: disable GPIO groups with no pins
  [v2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

 drivers/gpio/gpiolib.c                 |  11 +++
 drivers/pinctrl/qcom/pinctrl-msm.c     |  30 +++++--
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 139 ++++++++++++++++++++++++---------
 3 files changed, 139 insertions(+), 41 deletions(-)

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 0/3][v3] pinctrl: qcom: add support for sparse GPIOs

[Timur Tabi]

First patch update gpiolib so that it requests the GPIO before trying to
initialize it.

Second patch allows for for pinctrl-msm to understand GPIO groups with
no pins.  Such pins are "hidden" and can't be exported or accessed.

Last patch updates the QDF2xxx driver to take advantage of all that.

v3: Add checks in IRQ mask and unmask functions


Timur Tabi (3):
  gliolib: request the gpio before querying its direction
  [v3] pinctrl: qcom: disable GPIO groups with no pins
  [v2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

 drivers/gpio/gpiolib.c                 |  11 +++
 drivers/pinctrl/qcom/pinctrl-msm.c     |  30 +++++--
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 139 ++++++++++++++++++++++++---------
 3 files changed, 139 insertions(+), 41 deletions(-)

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/3] gliolib: request the gpio before querying its direction

[Timur Tabi]

Before querying a GPIO to determine its direction, the GPIO should be
formally requested.  This allows the GPIO driver to block access to
unavailable GPIOs, which makes it easier for some drivers to support
sparse GPIO maps.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/gpio/gpiolib.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 9568708..3b4e1e8 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1202,6 +1202,14 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)
 		struct gpio_desc *desc = &gdev->descs[i];
 
 		desc->gdev = gdev;
+
+		if (chip->request) {
+			status = chip->request(chip, i);
+			if (status < 0)
+				/* The GPIO is unavailable, so skip it */
+				continue;
+		}
+
 		/*
 		 * REVISIT: most hardware initializes GPIOs as inputs
 		 * (often with pullups enabled) so power usage is
@@ -1227,6 +1235,9 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)
 			 */
 			set_bit(FLAG_IS_OUT, &desc->flags);
 		}
+
+		if (chip->free)
+			chip->free(chip, i);
 	}
 
 #ifdef CONFIG_PINCTRL
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/3] gliolib: request the gpio before querying its direction

[Timur Tabi]

Before querying a GPIO to determine its direction, the GPIO should be
formally requested.  This allows the GPIO driver to block access to
unavailable GPIOs, which makes it easier for some drivers to support
sparse GPIO maps.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/gpio/gpiolib.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 9568708..3b4e1e8 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1202,6 +1202,14 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)
 		struct gpio_desc *desc = &gdev->descs[i];
 
 		desc->gdev = gdev;
+
+		if (chip->request) {
+			status = chip->request(chip, i);
+			if (status < 0)
+				/* The GPIO is unavailable, so skip it */
+				continue;
+		}
+
 		/*
 		 * REVISIT: most hardware initializes GPIOs as inputs
 		 * (often with pullups enabled) so power usage is
@@ -1227,6 +1235,9 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)
 			 */
 			set_bit(FLAG_IS_OUT, &desc->flags);
 		}
+
+		if (chip->free)
+			chip->free(chip, i);
 	}
 
 #ifdef CONFIG_PINCTRL
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
to disable all IRQs, even those that aren't enabled.  This includes
GPIOs that are unavailable (npins == 0), so add a check to the irq mask
and unmask functions.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..6b4f353 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -494,6 +494,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +508,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,23 +516,30 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
 #define msm_gpio_dbg_show NULL
 #endif
 
+/* If the GPIO has no pins, then treat it as unavailable. */
+static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
+	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static struct gpio_chip msm_gpio_template = {
 	.direction_input  = msm_gpio_direction_input,
 	.direction_output = msm_gpio_direction_output,
 	.get_direction    = msm_gpio_get_direction,
 	.get              = msm_gpio_get,
 	.set              = msm_gpio_set,
-	.request          = gpiochip_generic_request,
+	.request          = msm_gpio_request,
 	.free             = gpiochip_generic_free,
 	.dbg_show         = msm_gpio_dbg_show,
 };
@@ -586,6 +598,10 @@ static void msm_gpio_irq_mask(struct irq_data *d)
 
 	g = &pctrl->soc->groups[d->hwirq];
 
+	/* If there no pins, then this GPIO is unavailable */
+	if (!g->npins)
+		return;
+
 	raw_spin_lock_irqsave(&pctrl->lock, flags);
 
 	val = readl(pctrl->regs + g->intr_cfg_reg);
@@ -607,6 +623,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
 
 	g = &pctrl->soc->groups[d->hwirq];
 
+	/* If there no pins, then this GPIO is unavailable */
+	if (!g->npins)
+		return;
+
 	raw_spin_lock_irqsave(&pctrl->lock, flags);
 
 	val = readl(pctrl->regs + g->intr_cfg_reg);
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

To support sparse GPIO maps, pinctrl-msm client drivers can specify
that a given GPIO has a pin count of zero.  These GPIOs will be
considered "hidden".  Any attempt to claim the GPIO will fail, and they
will not be listed in debugfs.

During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
to disable all IRQs, even those that aren't enabled.  This includes
GPIOs that are unavailable (npins == 0), so add a check to the irq mask
and unmask functions.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 273badd..6b4f353 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -494,6 +494,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -503,7 +508,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -511,23 +516,30 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
 #define msm_gpio_dbg_show NULL
 #endif
 
+/* If the GPIO has no pins, then treat it as unavailable. */
+static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
+	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
+
+	return g->npins ? 0 : -ENODEV;
+}
+
 static struct gpio_chip msm_gpio_template = {
 	.direction_input  = msm_gpio_direction_input,
 	.direction_output = msm_gpio_direction_output,
 	.get_direction    = msm_gpio_get_direction,
 	.get              = msm_gpio_get,
 	.set              = msm_gpio_set,
-	.request          = gpiochip_generic_request,
+	.request          = msm_gpio_request,
 	.free             = gpiochip_generic_free,
 	.dbg_show         = msm_gpio_dbg_show,
 };
@@ -586,6 +598,10 @@ static void msm_gpio_irq_mask(struct irq_data *d)
 
 	g = &pctrl->soc->groups[d->hwirq];
 
+	/* If there no pins, then this GPIO is unavailable */
+	if (!g->npins)
+		return;
+
 	raw_spin_lock_irqsave(&pctrl->lock, flags);
 
 	val = readl(pctrl->regs + g->intr_cfg_reg);
@@ -607,6 +623,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
 
 	g = &pctrl->soc->groups[d->hwirq];
 
+	/* If there no pins, then this GPIO is unavailable */
+	if (!g->npins)
+		return;
+
 	raw_spin_lock_irqsave(&pctrl->lock, flags);
 
 	val = readl(pctrl->regs + g->intr_cfg_reg);
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 3/3] [v2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios".  This property is an array of
specific GPIOs that are accessible.  When an older kernel boots on
newer (restricted) firmware, it will fail to probe.

To implement the sparse GPIO map, we register all of the GPIOs, but set
the pin count for the unavailable GPIOs to zero.  The pinctrl-msm
driver will block those unavailable GPIOs from being accessed.

To allow newer kernels to support older firmware, the driver retains
support for QCOM8001.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 139 ++++++++++++++++++++++++---------
 1 file changed, 103 insertions(+), 36 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c..e3b58c4 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -38,68 +38,141 @@
 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
 #define NAME_SIZE	8
 
+enum {
+	QDF2XXX_V1,
+	QDF2XXX_V2,
+};
+
+static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
+	{"QCOM8001", QDF2XXX_V1},
+	{"QCOM8002", QDF2XXX_V2},
+	{},
+};
+MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
+
 static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 {
+	const struct acpi_device_id *id =
+		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
 	unsigned int i;
 	u32 num_gpios;
+	unsigned int avail_gpios; /* The number of GPIOs we support */
+	u16 *gpios; /* An array of supported GPIOs */
 	int ret;
 
 	/* Query the number of GPIOs from ACPI */
 	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(&pdev->dev, "missing 'num-gpios' property\n");
 		return ret;
 	}
-
 	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
+		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
 		return -ENODEV;
 	}
 
+	/*
+	 * The QCOM8001 HID contains only the number of GPIOs, and assumes
+	 * that all of them are available. avail_gpios is the same as num_gpios.
+	 *
+	 * The QCOM8002 HID introduces the 'gpios' DSD, which lists
+	 * specific GPIOs that the driver is allowed to access.
+	 *
+	 * The make the common code simpler, in both cases we create an
+	 * array of GPIOs that are accessible.  So for QCOM8001, that would
+	 * be all of the GPIOs.
+	 */
+	if (id->driver_data == QDF2XXX_V1) {
+		avail_gpios = num_gpios;
+
+		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
+				     GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		for (i = 0; i < avail_gpios; i++)
+			gpios[i] = i;
+	} else {
+		/* The number of GPIOs in the approved list */
+		ret = device_property_read_u16_array(&pdev->dev, "gpios",
+						     NULL, 0);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing 'num-gpios' property\n");
+			return ret;
+		}
+		if (!ret || ret > MAX_GPIOS) {
+			dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+			return -ENODEV;
+		}
+		avail_gpios = ret;
+
+		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
+				     GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		ret = device_property_read_u16_array(&pdev->dev, "gpios", gpios,
+						     avail_gpios);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "could not read list of GPIOs\n");
+			return ret;
+		}
+	}
+
 	pins = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
 	groups = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
-	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+	names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
 
 	if (!pins || !groups || !names)
 		return -ENOMEM;
 
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number, but nothing else.
+	 */
 	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposes as GPIOs. */
+	for (i = 0; i < avail_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
+	devm_kfree(&pdev->dev, gpios);
+
 	qdf2xxx_pinctrl.pins = pins;
 	qdf2xxx_pinctrl.groups = groups;
 	qdf2xxx_pinctrl.npins = num_gpios;
@@ -109,12 +182,6 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
 }
 
-static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
-	{"QCOM8001"},
-	{},
-};
-MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
-
 static struct platform_driver qdf2xxx_pinctrl_driver = {
 	.driver = {
 		.name = "qdf2xxx-pinctrl",
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 3/3] [v2] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios".  This property is an array of
specific GPIOs that are accessible.  When an older kernel boots on
newer (restricted) firmware, it will fail to probe.

To implement the sparse GPIO map, we register all of the GPIOs, but set
the pin count for the unavailable GPIOs to zero.  The pinctrl-msm
driver will block those unavailable GPIOs from being accessed.

To allow newer kernels to support older firmware, the driver retains
support for QCOM8001.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 139 ++++++++++++++++++++++++---------
 1 file changed, 103 insertions(+), 36 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c..e3b58c4 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -38,68 +38,141 @@
 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
 #define NAME_SIZE	8
 
+enum {
+	QDF2XXX_V1,
+	QDF2XXX_V2,
+};
+
+static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
+	{"QCOM8001", QDF2XXX_V1},
+	{"QCOM8002", QDF2XXX_V2},
+	{},
+};
+MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
+
 static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 {
+	const struct acpi_device_id *id =
+		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
 	unsigned int i;
 	u32 num_gpios;
+	unsigned int avail_gpios; /* The number of GPIOs we support */
+	u16 *gpios; /* An array of supported GPIOs */
 	int ret;
 
 	/* Query the number of GPIOs from ACPI */
 	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(&pdev->dev, "missing 'num-gpios' property\n");
 		return ret;
 	}
-
 	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
+		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
 		return -ENODEV;
 	}
 
+	/*
+	 * The QCOM8001 HID contains only the number of GPIOs, and assumes
+	 * that all of them are available. avail_gpios is the same as num_gpios.
+	 *
+	 * The QCOM8002 HID introduces the 'gpios' DSD, which lists
+	 * specific GPIOs that the driver is allowed to access.
+	 *
+	 * The make the common code simpler, in both cases we create an
+	 * array of GPIOs that are accessible.  So for QCOM8001, that would
+	 * be all of the GPIOs.
+	 */
+	if (id->driver_data == QDF2XXX_V1) {
+		avail_gpios = num_gpios;
+
+		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
+				     GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		for (i = 0; i < avail_gpios; i++)
+			gpios[i] = i;
+	} else {
+		/* The number of GPIOs in the approved list */
+		ret = device_property_read_u16_array(&pdev->dev, "gpios",
+						     NULL, 0);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing 'num-gpios' property\n");
+			return ret;
+		}
+		if (!ret || ret > MAX_GPIOS) {
+			dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+			return -ENODEV;
+		}
+		avail_gpios = ret;
+
+		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
+				     GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		ret = device_property_read_u16_array(&pdev->dev, "gpios", gpios,
+						     avail_gpios);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "could not read list of GPIOs\n");
+			return ret;
+		}
+	}
+
 	pins = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
 	groups = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
-	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+	names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
 
 	if (!pins || !groups || !names)
 		return -ENOMEM;
 
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number, but nothing else.
+	 */
 	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposes as GPIOs. */
+	for (i = 0; i < avail_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
+	devm_kfree(&pdev->dev, gpios);
+
 	qdf2xxx_pinctrl.pins = pins;
 	qdf2xxx_pinctrl.groups = groups;
 	qdf2xxx_pinctrl.npins = num_gpios;
@@ -109,12 +182,6 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
 }
 
-static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
-	{"QCOM8001"},
-	{},
-};
-MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
-
 static struct platform_driver qdf2xxx_pinctrl_driver = {
 	.driver = {
 		.name = "qdf2xxx-pinctrl",
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/3] gliolib: request the gpio before querying its direction

[Linus Walleij]

On Thu, Jul 27, 2017 at 8:19 PM, Timur Tabi <timur@codeaurora.org> wrote:

> Before querying a GPIO to determine its direction, the GPIO should be
> formally requested.  This allows the GPIO driver to block access to
> unavailable GPIOs, which makes it easier for some drivers to support
> sparse GPIO maps.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

This makes all kind of semantic change, so patch applied.

Yours,
Linus Walleij

[PATCH 1/3] gliolib: request the gpio before querying its direction

[Linus Walleij]

On Thu, Jul 27, 2017 at 8:19 PM, Timur Tabi <timur@codeaurora.org> wrote:

> Before querying a GPIO to determine its direction, the GPIO should be
> formally requested.  This allows the GPIO driver to block access to
> unavailable GPIOs, which makes it easier for some drivers to support
> sparse GPIO maps.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

This makes all kind of semantic change, so patch applied.

Yours,
Linus Walleij

Re: [PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Linus Walleij]

On Thu, Jul 27, 2017 at 8:19 PM, Timur Tabi <timur@codeaurora.org> wrote:

> To support sparse GPIO maps, pinctrl-msm client drivers can specify
> that a given GPIO has a pin count of zero.  These GPIOs will be
> considered "hidden".  Any attempt to claim the GPIO will fail, and they
> will not be listed in debugfs.
>
> During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
> to disable all IRQs, even those that aren't enabled.  This includes
> GPIOs that are unavailable (npins == 0), so add a check to the irq mask
> and unmask functions.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

I'm waiting for Björn's review of the two remaining patches.

Yours,
Linus Walleij

[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Linus Walleij]

On Thu, Jul 27, 2017 at 8:19 PM, Timur Tabi <timur@codeaurora.org> wrote:

> To support sparse GPIO maps, pinctrl-msm client drivers can specify
> that a given GPIO has a pin count of zero.  These GPIOs will be
> considered "hidden".  Any attempt to claim the GPIO will fail, and they
> will not be listed in debugfs.
>
> During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
> to disable all IRQs, even those that aren't enabled.  This includes
> GPIOs that are unavailable (npins == 0), so add a check to the irq mask
> and unmask functions.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>

I'm waiting for Bj?rn's review of the two remaining patches.

Yours,
Linus Walleij

Re: [PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/31/2017 08:36 AM, Linus Walleij wrote:
>> To support sparse GPIO maps, pinctrl-msm client drivers can specify
>> that a given GPIO has a pin count of zero.  These GPIOs will be
>> considered "hidden".  Any attempt to claim the GPIO will fail, and they
>> will not be listed in debugfs.
>>
>> During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
>> to disable all IRQs, even those that aren't enabled.  This includes
>> GPIOs that are unavailable (npins == 0), so add a check to the irq mask
>> and unmask functions.
>>
>> Signed-off-by: Timur Tabi<timur@codeaurora.org>

> I'm waiting for Björn's review of the two remaining patches.

Björn, do you have time to review these patches?  I'm hoping to get them 
into 4.14.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

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[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 07/31/2017 08:36 AM, Linus Walleij wrote:
>> To support sparse GPIO maps, pinctrl-msm client drivers can specify
>> that a given GPIO has a pin count of zero.  These GPIOs will be
>> considered "hidden".  Any attempt to claim the GPIO will fail, and they
>> will not be listed in debugfs.
>>
>> During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
>> to disable all IRQs, even those that aren't enabled.  This includes
>> GPIOs that are unavailable (npins == 0), so add a check to the irq mask
>> and unmask functions.
>>
>> Signed-off-by: Timur Tabi<timur@codeaurora.org>

> I'm waiting for Bj?rn's review of the two remaining patches.

Bj?rn, do you have time to review these patches?  I'm hoping to get them 
into 4.14.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Jiandi An]

During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
to disable all IRQs that are registered.  If gpio is not available,
don't register IRQs and it won't be in the irq_desc list it walks through.

If gpio is unavailable, perhaps a more correct fix that covers more is 
to not calling gpiochip_irqchip_add() to register msm_gpio_irq_chip in 
msm_gpio_init().

When registering interrupt for msm_qpio_irq_chip the following are 
registered, not just irq_mask and irq_unmask.

static struct irq_chip msm_gpio_irq_chip = {
	.name           = "msmgpio",
	.irq_mask       = msm_gpio_irq_mask,
	.irq_unmask     = msm_gpio_irq_unmask,
	.irq_ack        = msm_gpio_irq_ack,
	.irq_set_type   = msm_gpio_irq_set_type,
	.irq_set_wake   = msm_gpio_irq_set_wake,
};

Technically the same check added in msm_gpio_irq_mask() and 
msm_gpio_irq_unmask() should be added in msm_gpio_irq_ack(), 
msm_gpio_irq_set_type(), and msm_gpio_irq_set_wake() if it's registered 
with irq domain.

To cover more bases, the more correct way is to not register interrupt 
with irq domain at all if gpio is unavailable.


On 08/09/2017 02:02 PM, Timur Tabi wrote:
> On 07/31/2017 08:36 AM, Linus Walleij wrote:
>>> To support sparse GPIO maps, pinctrl-msm client drivers can specify
>>> that a given GPIO has a pin count of zero.  These GPIOs will be
>>> considered "hidden".  Any attempt to claim the GPIO will fail, and they
>>> will not be listed in debugfs.
>>>
>>> During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
>>> to disable all IRQs, even those that aren't enabled.  This includes
>>> GPIOs that are unavailable (npins == 0), so add a check to the irq mask
>>> and unmask functions.
>>>
>>> Signed-off-by: Timur Tabi<timur@codeaurora.org>
>
>> I'm waiting for Björn's review of the two remaining patches.
>
> Björn, do you have time to review these patches?  I'm hoping to get them
> into 4.14.
>

-- 
Jiandi An
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project.

[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Jiandi An]

During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
to disable all IRQs that are registered.  If gpio is not available,
don't register IRQs and it won't be in the irq_desc list it walks through.

If gpio is unavailable, perhaps a more correct fix that covers more is 
to not calling gpiochip_irqchip_add() to register msm_gpio_irq_chip in 
msm_gpio_init().

When registering interrupt for msm_qpio_irq_chip the following are 
registered, not just irq_mask and irq_unmask.

static struct irq_chip msm_gpio_irq_chip = {
	.name           = "msmgpio",
	.irq_mask       = msm_gpio_irq_mask,
	.irq_unmask     = msm_gpio_irq_unmask,
	.irq_ack        = msm_gpio_irq_ack,
	.irq_set_type   = msm_gpio_irq_set_type,
	.irq_set_wake   = msm_gpio_irq_set_wake,
};

Technically the same check added in msm_gpio_irq_mask() and 
msm_gpio_irq_unmask() should be added in msm_gpio_irq_ack(), 
msm_gpio_irq_set_type(), and msm_gpio_irq_set_wake() if it's registered 
with irq domain.

To cover more bases, the more correct way is to not register interrupt 
with irq domain at all if gpio is unavailable.


On 08/09/2017 02:02 PM, Timur Tabi wrote:
> On 07/31/2017 08:36 AM, Linus Walleij wrote:
>>> To support sparse GPIO maps, pinctrl-msm client drivers can specify
>>> that a given GPIO has a pin count of zero.  These GPIOs will be
>>> considered "hidden".  Any attempt to claim the GPIO will fail, and they
>>> will not be listed in debugfs.
>>>
>>> During a kexec shutdown, machine_kexec_mask_interrupts() will attempt
>>> to disable all IRQs, even those that aren't enabled.  This includes
>>> GPIOs that are unavailable (npins == 0), so add a check to the irq mask
>>> and unmask functions.
>>>
>>> Signed-off-by: Timur Tabi<timur@codeaurora.org>
>
>> I'm waiting for Bj?rn's review of the two remaining patches.
>
> Bj?rn, do you have time to review these patches?  I'm hoping to get them
> into 4.14.
>

-- 
Jiandi An
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project.

Re: [PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 08/16/2017 01:10 PM, Jiandi An wrote:
> 
> Technically the same check added in msm_gpio_irq_mask() and 
> msm_gpio_irq_unmask() should be added in msm_gpio_irq_ack(), 
> msm_gpio_irq_set_type(), and msm_gpio_irq_set_wake() if it's registered 
> with irq domain.

I assume that if the GPIO is never unmasked, then msm_gpio_irq_ack() 
will never be called.

msm_gpio_irq_set_type() and msm_gpio_irq_set_wake() might be called, so 
I can add checks for those functions.  I'm hoping that won't be 
necessary, however.  The GPIO and IRQ code is too entangled for me to 
figure out whether unclaimed GPIOs can still have their interrupts 
programmed.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 08/16/2017 01:10 PM, Jiandi An wrote:
> 
> Technically the same check added in msm_gpio_irq_mask() and 
> msm_gpio_irq_unmask() should be added in msm_gpio_irq_ack(), 
> msm_gpio_irq_set_type(), and msm_gpio_irq_set_wake() if it's registered 
> with irq domain.

I assume that if the GPIO is never unmasked, then msm_gpio_irq_ack() 
will never be called.

msm_gpio_irq_set_type() and msm_gpio_irq_set_wake() might be called, so 
I can add checks for those functions.  I'm hoping that won't be 
necessary, however.  The GPIO and IRQ code is too entangled for me to 
figure out whether unclaimed GPIOs can still have their interrupts 
programmed.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Jiandi An]

On 08/16/2017 01:32 PM, Timur Tabi wrote:
> On 08/16/2017 01:10 PM, Jiandi An wrote:
>>
>> Technically the same check added in msm_gpio_irq_mask() and
>> msm_gpio_irq_unmask() should be added in msm_gpio_irq_ack(),
>> msm_gpio_irq_set_type(), and msm_gpio_irq_set_wake() if it's
>> registered with irq domain.
>
> I assume that if the GPIO is never unmasked, then msm_gpio_irq_ack()
> will never be called.
>
> msm_gpio_irq_set_type() and msm_gpio_irq_set_wake() might be called, so
> I can add checks for those functions.  I'm hoping that won't be
> necessary, however.  The GPIO and IRQ code is too entangled for me to
> figure out whether unclaimed GPIOs can still have their interrupts
> programmed.
>

That is why the suggestion is instead of patching in each of the op
function of registered irq_chip for the unavailable gpio that won't
have use for all that anyways, simply don't register irq for the
unavailable gpio.  What's the use of registering  irq if you know
the gpio is unavailable and not going to use any of the irq_chip
functions.  It's unnecessarily adding an irq_desc in the list.

Technically machine_kexec_mask_interrupts() is not blindly disable
all IRQs.  If you don't register irq, it won't be in the irq_desc
list.

-- 
Jiandi An
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project.

[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Jiandi An]

On 08/16/2017 01:32 PM, Timur Tabi wrote:
> On 08/16/2017 01:10 PM, Jiandi An wrote:
>>
>> Technically the same check added in msm_gpio_irq_mask() and
>> msm_gpio_irq_unmask() should be added in msm_gpio_irq_ack(),
>> msm_gpio_irq_set_type(), and msm_gpio_irq_set_wake() if it's
>> registered with irq domain.
>
> I assume that if the GPIO is never unmasked, then msm_gpio_irq_ack()
> will never be called.
>
> msm_gpio_irq_set_type() and msm_gpio_irq_set_wake() might be called, so
> I can add checks for those functions.  I'm hoping that won't be
> necessary, however.  The GPIO and IRQ code is too entangled for me to
> figure out whether unclaimed GPIOs can still have their interrupts
> programmed.
>

That is why the suggestion is instead of patching in each of the op
function of registered irq_chip for the unavailable gpio that won't
have use for all that anyways, simply don't register irq for the
unavailable gpio.  What's the use of registering  irq if you know
the gpio is unavailable and not going to use any of the irq_chip
functions.  It's unnecessarily adding an irq_desc in the list.

Technically machine_kexec_mask_interrupts() is not blindly disable
all IRQs.  If you don't register irq, it won't be in the irq_desc
list.

-- 
Jiandi An
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project.

Re: [PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Jiandi An]

On 08/16/2017 01:32 PM, Timur Tabi wrote:
> On 08/16/2017 01:10 PM, Jiandi An wrote:
>>
>> Technically the same check added in msm_gpio_irq_mask() and
>> msm_gpio_irq_unmask() should be added in msm_gpio_irq_ack(),
>> msm_gpio_irq_set_type(), and msm_gpio_irq_set_wake() if it's
>> registered with irq domain.
>
> I assume that if the GPIO is never unmasked, then msm_gpio_irq_ack()
> will never be called.
>
> msm_gpio_irq_set_type() and msm_gpio_irq_set_wake() might be called, so
> I can add checks for those functions.  I'm hoping that won't be
> necessary, however.  The GPIO and IRQ code is too entangled for me to
> figure out whether unclaimed GPIOs can still have their interrupts
> programmed.
>

That is why the suggestion is instead of patching in each of the op
function of registered irq_chip for the unavailable gpio that won't
have use for all that anyways, simply don't register irq for the
unavailable gpio.  What's the use of registering  irq if you know
the gpio is unavailable and not going to use any of the irq_chip
functions.  It's unnecessarily adding an irq_desc in the list.

Technically machine_kexec_mask_interrupts() is not blindly disable
all IRQs.  If you don't register irq, it won't be in the irq_desc
list.

-- 
Jiandi An
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project.

[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Jiandi An]

On 08/16/2017 01:32 PM, Timur Tabi wrote:
> On 08/16/2017 01:10 PM, Jiandi An wrote:
>>
>> Technically the same check added in msm_gpio_irq_mask() and
>> msm_gpio_irq_unmask() should be added in msm_gpio_irq_ack(),
>> msm_gpio_irq_set_type(), and msm_gpio_irq_set_wake() if it's
>> registered with irq domain.
>
> I assume that if the GPIO is never unmasked, then msm_gpio_irq_ack()
> will never be called.
>
> msm_gpio_irq_set_type() and msm_gpio_irq_set_wake() might be called, so
> I can add checks for those functions.  I'm hoping that won't be
> necessary, however.  The GPIO and IRQ code is too entangled for me to
> figure out whether unclaimed GPIOs can still have their interrupts
> programmed.
>

That is why the suggestion is instead of patching in each of the op
function of registered irq_chip for the unavailable gpio that won't
have use for all that anyways, simply don't register irq for the
unavailable gpio.  What's the use of registering  irq if you know
the gpio is unavailable and not going to use any of the irq_chip
functions.  It's unnecessarily adding an irq_desc in the list.

Technically machine_kexec_mask_interrupts() is not blindly disable
all IRQs.  If you don't register irq, it won't be in the irq_desc
list.

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Jiandi An
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a 
Linux Foundation Collaborative Project.

Re: [PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 08/16/2017 02:31 PM, Jiandi An wrote:
> That is why the suggestion is instead of patching in each of the op
> function of registered irq_chip for the unavailable gpio that won't
> have use for all that anyways, simply don't register irq for the
> unavailable gpio

Ah, it looks like maybe I can update gpio_chip.irq_valid_mask after 
calling gpiochip_add_data().  I'll try it.

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Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/3] [v3] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 08/16/2017 02:31 PM, Jiandi An wrote:
> That is why the suggestion is instead of patching in each of the op
> function of registered irq_chip for the unavailable gpio that won't
> have use for all that anyways, simply don't register irq for the
> unavailable gpio

Ah, it looks like maybe I can update gpio_chip.irq_valid_mask after 
calling gpiochip_add_data().  I'll try it.

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Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/3] gliolib: request the gpio before querying its direction

[Timur Tabi]

On 07/31/2017 08:35 AM, Linus Walleij wrote:
>> Before querying a GPIO to determine its direction, the GPIO should be
>> formally requested.  This allows the GPIO driver to block access to
>> unavailable GPIOs, which makes it easier for some drivers to support
>> sparse GPIO maps.
>>
>> Signed-off-by: Timur Tabi<timur@codeaurora.org>
> This makes all kind of semantic change, so patch applied.

Have you push it to git.kernel.org?  I don't see it.

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[PATCH 1/3] gliolib: request the gpio before querying its direction

[Timur Tabi]

On 07/31/2017 08:35 AM, Linus Walleij wrote:
>> Before querying a GPIO to determine its direction, the GPIO should be
>> formally requested.  This allows the GPIO driver to block access to
>> unavailable GPIOs, which makes it easier for some drivers to support
>> sparse GPIO maps.
>>
>> Signed-off-by: Timur Tabi<timur@codeaurora.org>
> This makes all kind of semantic change, so patch applied.

Have you push it to git.kernel.org?  I don't see it.

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Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/3] gliolib: request the gpio before querying its direction

[Linus Walleij]

On Mon, Aug 21, 2017 at 11:23 PM, Timur Tabi <timur@codeaurora.org> wrote:
> On 07/31/2017 08:35 AM, Linus Walleij wrote:
>>>
>>> Before querying a GPIO to determine its direction, the GPIO should be
>>> formally requested.  This allows the GPIO driver to block access to
>>> unavailable GPIOs, which makes it easier for some drivers to support
>>> sparse GPIO maps.
>>>
>>> Signed-off-by: Timur Tabi<timur@codeaurora.org>
>>
>> This makes all kind of semantic change, so patch applied.
>
> Have you push it to git.kernel.org?  I don't see it.

It's right there on the "devel" branch from the GPIO git tree.
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/log/?h=devel

Yours,
Linus Walleij

[PATCH 1/3] gliolib: request the gpio before querying its direction

[Linus Walleij]

On Mon, Aug 21, 2017 at 11:23 PM, Timur Tabi <timur@codeaurora.org> wrote:
> On 07/31/2017 08:35 AM, Linus Walleij wrote:
>>>
>>> Before querying a GPIO to determine its direction, the GPIO should be
>>> formally requested.  This allows the GPIO driver to block access to
>>> unavailable GPIOs, which makes it easier for some drivers to support
>>> sparse GPIO maps.
>>>
>>> Signed-off-by: Timur Tabi<timur@codeaurora.org>
>>
>> This makes all kind of semantic change, so patch applied.
>
> Have you push it to git.kernel.org?  I don't see it.

It's right there on the "devel" branch from the GPIO git tree.
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/log/?h=devel

Yours,
Linus Walleij

Re: [PATCH 1/3] gliolib: request the gpio before querying its direction

[Timur Tabi]

On 08/23/2017 03:32 AM, Linus Walleij wrote:
> It's right there on the "devel" branch from the GPIO git tree.
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/log/?h=devel

The devel branch is missing this commit:

https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?id=83cf5faeba37fede8a6274d07f646d1cd1b25d35

which I need to avoid a merge conflict.  I'm going to submit a new 
version of my patches, but they won't apply on top of 'devel' unless you 
pull in that commit from linux-pinctrl.  Or you could copy that my 
gpiolib commit to linux-pinctrl.

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Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/3] gliolib: request the gpio before querying its direction

[Timur Tabi]

On 08/23/2017 03:32 AM, Linus Walleij wrote:
> It's right there on the "devel" branch from the GPIO git tree.
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/log/?h=devel

The devel branch is missing this commit:

https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?id=83cf5faeba37fede8a6274d07f646d1cd1b25d35

which I need to avoid a merge conflict.  I'm going to submit a new 
version of my patches, but they won't apply on top of 'devel' unless you 
pull in that commit from linux-pinctrl.  Or you could copy that my 
gpiolib commit to linux-pinctrl.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Re: [PATCH 1/3] gliolib: request the gpio before querying its direction

[Linus Walleij]

On Thu, Aug 24, 2017 at 1:28 AM, Timur Tabi <timur@codeaurora.org> wrote:
> On 08/23/2017 03:32 AM, Linus Walleij wrote:
>>
>> It's right there on the "devel" branch from the GPIO git tree.
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/log/?h=devel
>
>
> The devel branch is missing this commit:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?id=83cf5faeba37fede8a6274d07f646d1cd1b25d35

Yes I have separate git trees for GPIO and pin control even.

> which I need to avoid a merge conflict.  I'm going to submit a new version
> of my patches, but they won't apply on top of 'devel' unless you pull in
> that commit from linux-pinctrl.  Or you could copy that my gpiolib commit to
> linux-pinctrl.

I don't see how you can have a merge conflict between this
patch that only affects gpiolib.c and something in the pin
control tree?

The merge window is imminent, so if it is not extremely urgent
I would opt to wait until after.

Yours,
Linus Walleij

[PATCH 1/3] gliolib: request the gpio before querying its direction

[Linus Walleij]

On Thu, Aug 24, 2017 at 1:28 AM, Timur Tabi <timur@codeaurora.org> wrote:
> On 08/23/2017 03:32 AM, Linus Walleij wrote:
>>
>> It's right there on the "devel" branch from the GPIO git tree.
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/log/?h=devel
>
>
> The devel branch is missing this commit:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/commit/?id=83cf5faeba37fede8a6274d07f646d1cd1b25d35

Yes I have separate git trees for GPIO and pin control even.

> which I need to avoid a merge conflict.  I'm going to submit a new version
> of my patches, but they won't apply on top of 'devel' unless you pull in
> that commit from linux-pinctrl.  Or you could copy that my gpiolib commit to
> linux-pinctrl.

I don't see how you can have a merge conflict between this
patch that only affects gpiolib.c and something in the pin
control tree?

The merge window is imminent, so if it is not extremely urgent
I would opt to wait until after.

Yours,
Linus Walleij

Re: [PATCH 1/3] gliolib: request the gpio before querying its direction

[Timur Tabi]

On 08/24/2017 04:28 PM, Linus Walleij wrote:
> I don't see how you can have a merge conflict between this
> patch that only affects gpiolib.c and something in the pin
> control tree?

Actually, the merge conflict is because this is missing in the gpio tree:

pinctrl: msm: add support to configure ipq40xx GPIO_PULL bits

> The merge window is imminent, so if it is not extremely urgent
> I would opt to wait until after.

As long as it gets into 4.14-final, I don't care which specific RC it 
appears in.  Thanks.

-- 
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Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/3] gliolib: request the gpio before querying its direction

[Timur Tabi]

On 08/24/2017 04:28 PM, Linus Walleij wrote:
> I don't see how you can have a merge conflict between this
> patch that only affects gpiolib.c and something in the pin
> control tree?

Actually, the merge conflict is because this is missing in the gpio tree:

pinctrl: msm: add support to configure ipq40xx GPIO_PULL bits

> The merge window is imminent, so if it is not extremely urgent
> I would opt to wait until after.

As long as it gets into 4.14-final, I don't care which specific RC it 
appears in.  Thanks.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.