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* [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices
@ 2017-08-04 13:26 ` Simon Horman
  0 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2017-08-04 13:26 UTC (permalink / raw)
  To: linux-renesas-soc; +Cc: linux-arm-kernel, Magnus Damm

From: Dien Pham <dien.pham.ry@rvc.renesas.com>

Current, OPP tables are defined temporary,
they are being evaluated and adjust in future.

Based in part on work by Hien Dang.

Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: consolidated sseveral patches into one]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 309 +++++++++++++++++++++++++++++++
 1 file changed, 309 insertions(+)

I am not aware of any build-time depdendencies of this patch.

This patch has run-time depdnencies on:
* [PATCH] cpufreq: rcar: Add support for R8A7795 SoC
* [PATCH 0/4] r8a7795: Add Z and Z2 clock support

I have provided an integration patch with this patch, those DTS changes,
and Renesas clock updates also depended on by the DTS changes. The result
is working CPUFreq for the r8a7795 (R-Car H3) ES1.0.

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/r8a7795-cpufreq

A description of steps taken to lightly exercise the above can be found here:

http://elinux.org/Tests:R-CAR-GEN3-CPUFreq

If this work is acceptable I plan to follow up with patches to
enable CPUFreq on the r8a7796 (R-Car M3-W).

This patch is based on renesas-arm64-dt-for-v4.14

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index a87ae76880ab..f34da4c9ea52 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -46,6 +46,12 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp_tb0>,
+				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
+				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
+				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
+				<&cluster0_opp_tb7>;
 		};
 
 		a57_1: cpu@1 {
@@ -55,6 +61,11 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp_tb0>,
+				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
+				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
+				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
+				<&cluster0_opp_tb7>;
 		};
 
 		a57_2: cpu@2 {
@@ -64,6 +75,11 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp_tb0>,
+				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
+				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
+				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
+				<&cluster0_opp_tb7>;
 		};
 
 		a57_3: cpu@3 {
@@ -73,6 +89,11 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp_tb0>,
+				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
+				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
+				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
+				<&cluster0_opp_tb7>;
 		};
 
 		a53_0: cpu@100 {
@@ -82,6 +103,8 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+			operating-points-v2 = <&cluster1_opp_tb0>;
 		};
 
 		a53_1: cpu@101 {
@@ -91,6 +114,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp_tb0>;
 		};
 
 		a53_2: cpu@102 {
@@ -100,6 +124,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp_tb0>;
 		};
 
 		a53_3: cpu@103 {
@@ -109,6 +134,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp_tb0>;
 		};
 
 		L2_CA57: cache-controller-0 {
@@ -126,6 +152,289 @@
 		};
 	};
 
+	cluster0_opp_tb0: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <960000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb1: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <890000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <950000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb2: opp_table2 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <810000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <810000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <810000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <880000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <930000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb3: opp_table3 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <870000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <910000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb4: opp_table4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <790000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <790000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <790000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <860000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <890000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb5: opp_table5 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <780000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <780000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <780000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <850000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <880000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb6: opp_table6 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <770000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <770000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <770000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <840000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <870000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb7: opp_table7 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <760000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <760000>;
+			clock-latency-ns = <300000>;
+		};
+		opp@1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <760000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp@1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp@1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <860000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster1_opp_tb0: opp_table10 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+	};
+
 	extal_clk: extal {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-- 
2.1.4

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices
@ 2017-08-04 13:26 ` Simon Horman
  0 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2017-08-04 13:26 UTC (permalink / raw)
  To: linux-arm-kernel

From: Dien Pham <dien.pham.ry@rvc.renesas.com>

Current, OPP tables are defined temporary,
they are being evaluated and adjust in future.

Based in part on work by Hien Dang.

Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: consolidated sseveral patches into one]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 309 +++++++++++++++++++++++++++++++
 1 file changed, 309 insertions(+)

I am not aware of any build-time depdendencies of this patch.

This patch has run-time depdnencies on:
* [PATCH] cpufreq: rcar: Add support for R8A7795 SoC
* [PATCH 0/4] r8a7795: Add Z and Z2 clock support

I have provided an integration patch with this patch, those DTS changes,
and Renesas clock updates also depended on by the DTS changes. The result
is working CPUFreq for the r8a7795 (R-Car H3) ES1.0.

https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/r8a7795-cpufreq

A description of steps taken to lightly exercise the above can be found here:

http://elinux.org/Tests:R-CAR-GEN3-CPUFreq

If this work is acceptable I plan to follow up with patches to
enable CPUFreq on the r8a7796 (R-Car M3-W).

This patch is based on renesas-arm64-dt-for-v4.14

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index a87ae76880ab..f34da4c9ea52 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -46,6 +46,12 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
+			operating-points-v2 = <&cluster0_opp_tb0>,
+				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
+				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
+				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
+				<&cluster0_opp_tb7>;
 		};
 
 		a57_1: cpu at 1 {
@@ -55,6 +61,11 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp_tb0>,
+				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
+				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
+				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
+				<&cluster0_opp_tb7>;
 		};
 
 		a57_2: cpu at 2 {
@@ -64,6 +75,11 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp_tb0>,
+				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
+				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
+				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
+				<&cluster0_opp_tb7>;
 		};
 
 		a57_3: cpu at 3 {
@@ -73,6 +89,11 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster0_opp_tb0>,
+				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
+				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
+				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
+				<&cluster0_opp_tb7>;
 		};
 
 		a53_0: cpu at 100 {
@@ -82,6 +103,8 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
+			operating-points-v2 = <&cluster1_opp_tb0>;
 		};
 
 		a53_1: cpu at 101 {
@@ -91,6 +114,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp_tb0>;
 		};
 
 		a53_2: cpu at 102 {
@@ -100,6 +124,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp_tb0>;
 		};
 
 		a53_3: cpu at 103 {
@@ -109,6 +134,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			operating-points-v2 = <&cluster1_opp_tb0>;
 		};
 
 		L2_CA57: cache-controller-0 {
@@ -126,6 +152,289 @@
 		};
 	};
 
+	cluster0_opp_tb0: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <960000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb1: opp_table1 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <890000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <950000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb2: opp_table2 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <810000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <810000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <810000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <880000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <930000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb3: opp_table3 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <870000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <910000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb4: opp_table4 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <790000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <790000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <790000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <860000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <890000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb5: opp_table5 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <780000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <780000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <780000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <850000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <880000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb6: opp_table6 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <770000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <770000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <770000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <840000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <870000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster0_opp_tb7: opp_table7 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			opp-microvolt = <760000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			opp-microvolt = <760000>;
+			clock-latency-ns = <300000>;
+		};
+		opp at 1500000000 {
+			opp-hz = /bits/ 64 <1500000000>;
+			opp-microvolt = <760000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+		opp at 1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <830000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+		opp at 1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <860000>;
+			clock-latency-ns = <300000>;
+			turbo-mode;
+		};
+	};
+
+	cluster1_opp_tb0: opp_table10 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp at 1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <820000>;
+			clock-latency-ns = <300000>;
+		};
+	};
+
 	extal_clk: extal {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-- 
2.1.4

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices
  2017-08-04 13:26 ` Simon Horman
@ 2017-08-14 12:11   ` Geert Uytterhoeven
  -1 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2017-08-14 12:11 UTC (permalink / raw)
  To: Simon Horman; +Cc: Linux-Renesas, linux-arm-kernel, Magnus Damm

Hi Simon,

2017-08-04 15:26 GMT+02:00 Simon Horman <horms+renesas@verge.net.au>:
> From: Dien Pham <dien.pham.ry@rvc.renesas.com>
>
> Current, OPP tables are defined temporary,
> they are being evaluated and adjust in future.
>
> Based in part on work by Hien Dang.
>
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [simon: consolidated sseveral patches into one]
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 309 +++++++++++++++++++++++++++++++
>  1 file changed, 309 insertions(+)
>
> I am not aware of any build-time depdendencies of this patch.
>
> This patch has run-time depdnencies on:
> * [PATCH] cpufreq: rcar: Add support for R8A7795 SoC
> * [PATCH 0/4] r8a7795: Add Z and Z2 clock support
>
> I have provided an integration patch with this patch, those DTS changes,
> and Renesas clock updates also depended on by the DTS changes. The result
> is working CPUFreq for the r8a7795 (R-Car H3) ES1.0.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/r8a7795-cpufreq
>
> A description of steps taken to lightly exercise the above can be found here:
>
> http://elinux.org/Tests:R-CAR-GEN3-CPUFreq
>
> If this work is acceptable I plan to follow up with patches to
> enable CPUFreq on the r8a7796 (R-Car M3-W).
>
> This patch is based on renesas-arm64-dt-for-v4.14
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index a87ae76880ab..f34da4c9ea52 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi

> @@ -126,6 +152,289 @@
>                 };
>         };
>
> +       cluster0_opp_tb0: opp_table0 {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp@500000000 {

No complaints from "make W=1 dtbs" due to unit-address without reg property?

=> "opp-500000000 { ... };"

> +                       opp-hz = /bits/ 64 <500000000>;
> +                       opp-microvolt = <830000>;
> +                       clock-latency-ns = <300000>;
> +               };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices
@ 2017-08-14 12:11   ` Geert Uytterhoeven
  0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2017-08-14 12:11 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Simon,

2017-08-04 15:26 GMT+02:00 Simon Horman <horms+renesas@verge.net.au>:
> From: Dien Pham <dien.pham.ry@rvc.renesas.com>
>
> Current, OPP tables are defined temporary,
> they are being evaluated and adjust in future.
>
> Based in part on work by Hien Dang.
>
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [simon: consolidated sseveral patches into one]
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 309 +++++++++++++++++++++++++++++++
>  1 file changed, 309 insertions(+)
>
> I am not aware of any build-time depdendencies of this patch.
>
> This patch has run-time depdnencies on:
> * [PATCH] cpufreq: rcar: Add support for R8A7795 SoC
> * [PATCH 0/4] r8a7795: Add Z and Z2 clock support
>
> I have provided an integration patch with this patch, those DTS changes,
> and Renesas clock updates also depended on by the DTS changes. The result
> is working CPUFreq for the r8a7795 (R-Car H3) ES1.0.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/r8a7795-cpufreq
>
> A description of steps taken to lightly exercise the above can be found here:
>
> http://elinux.org/Tests:R-CAR-GEN3-CPUFreq
>
> If this work is acceptable I plan to follow up with patches to
> enable CPUFreq on the r8a7796 (R-Car M3-W).
>
> This patch is based on renesas-arm64-dt-for-v4.14
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index a87ae76880ab..f34da4c9ea52 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi

> @@ -126,6 +152,289 @@
>                 };
>         };
>
> +       cluster0_opp_tb0: opp_table0 {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp at 500000000 {

No complaints from "make W=1 dtbs" due to unit-address without reg property?

=> "opp-500000000 { ... };"

> +                       opp-hz = /bits/ 64 <500000000>;
> +                       opp-microvolt = <830000>;
> +                       clock-latency-ns = <300000>;
> +               };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices
  2017-08-04 13:26 ` Simon Horman
@ 2017-08-29 14:56   ` Niklas Söderlund
  -1 siblings, 0 replies; 8+ messages in thread
From: Niklas Söderlund @ 2017-08-29 14:56 UTC (permalink / raw)
  To: Simon Horman; +Cc: linux-renesas-soc, linux-arm-kernel, Magnus Damm

Hi Simon,

Thanks for your patches and sorry for getting to this a bit late.

On 2017-08-04 15:26:20 +0200, Simon Horman wrote:
> From: Dien Pham <dien.pham.ry@rvc.renesas.com>
> 
> Current, OPP tables are defined temporary,
> they are being evaluated and adjust in future.
> 
> Based in part on work by Hien Dang.
> 
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [simon: consolidated sseveral patches into one]
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 309 +++++++++++++++++++++++++++++++
>  1 file changed, 309 insertions(+)
> 
> I am not aware of any build-time depdendencies of this patch.
> 
> This patch has run-time depdnencies on:
> * [PATCH] cpufreq: rcar: Add support for R8A7795 SoC
> * [PATCH 0/4] r8a7795: Add Z and Z2 clock support
> 
> I have provided an integration patch with this patch, those DTS changes,
> and Renesas clock updates also depended on by the DTS changes. The result
> is working CPUFreq for the r8a7795 (R-Car H3) ES1.0.
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/r8a7795-cpufreq
> 
> A description of steps taken to lightly exercise the above can be found here:
> 
> http://elinux.org/Tests:R-CAR-GEN3-CPUFreq

I tested this it's working, nice!

> 
> If this work is acceptable I plan to follow up with patches to
> enable CPUFreq on the r8a7796 (R-Car M3-W).
> 
> This patch is based on renesas-arm64-dt-for-v4.14
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index a87ae76880ab..f34da4c9ea52 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -46,6 +46,12 @@
>  			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
> +			operating-points-v2 = <&cluster0_opp_tb0>,
> +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> +				<&cluster0_opp_tb7>;

This however leaves me a bit confused. If I understand the bindings 
documentation you should only specify one phandle here. IIUC only the 
first one will be used anyhow, from drivers/base/power/opp/of.c

253 static struct device_node *_opp_of_get_opp_desc_node(struct device_node *np)
254 {
255         /*
256          * There should be only ONE phandle present in "operating-points-v2"
257          * property.
258          */
259 
260         return of_parse_phandle(np, "operating-points-v2", 0);
261 }

I tried to look at other sources and bindings and I can't find anywhere 
where more then one phandle could be useful, but I can have missed 
something? My interest in this is that I wish to hook it up with the 
thermal zones to have it act as passive cooling and implement the part 
of the BSP emergency shutdown driver using already available code and 
having more then one phandle here confuses me how to describe that in DT 
:-)

>  		};
>  
>  		a57_1: cpu@1 {
> @@ -55,6 +61,11 @@
>  			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster0_opp_tb0>,
> +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> +				<&cluster0_opp_tb7>;
>  		};
>  
>  		a57_2: cpu@2 {
> @@ -64,6 +75,11 @@
>  			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster0_opp_tb0>,
> +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> +				<&cluster0_opp_tb7>;
>  		};
>  
>  		a57_3: cpu@3 {
> @@ -73,6 +89,11 @@
>  			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster0_opp_tb0>,
> +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> +				<&cluster0_opp_tb7>;
>  		};
>  
>  		a53_0: cpu@100 {
> @@ -82,6 +103,8 @@
>  			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
> +			operating-points-v2 = <&cluster1_opp_tb0>;
>  		};
>  
>  		a53_1: cpu@101 {
> @@ -91,6 +114,7 @@
>  			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster1_opp_tb0>;
>  		};
>  
>  		a53_2: cpu@102 {
> @@ -100,6 +124,7 @@
>  			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster1_opp_tb0>;
>  		};
>  
>  		a53_3: cpu@103 {
> @@ -109,6 +134,7 @@
>  			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster1_opp_tb0>;
>  		};
>  
>  		L2_CA57: cache-controller-0 {
> @@ -126,6 +152,289 @@
>  		};
>  	};
>  
> +	cluster0_opp_tb0: opp_table0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <830000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <830000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <830000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <960000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb1: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <890000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <950000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb2: opp_table2 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <810000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <810000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <810000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <880000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <930000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb3: opp_table3 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <800000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <800000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <800000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <870000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <910000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb4: opp_table4 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <790000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <790000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <790000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <860000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <890000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb5: opp_table5 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <780000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <780000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <780000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <850000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <880000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb6: opp_table6 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <770000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <770000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <770000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <840000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <870000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb7: opp_table7 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <760000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <760000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp@1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <760000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp@1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <830000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp@1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <860000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster1_opp_tb0: opp_table10 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp@1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +	};
> +
>  	extal_clk: extal {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> -- 
> 2.1.4
> 
> 

-- 
Regards,
Niklas S�derlund

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices
@ 2017-08-29 14:56   ` Niklas Söderlund
  0 siblings, 0 replies; 8+ messages in thread
From: Niklas Söderlund @ 2017-08-29 14:56 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Simon,

Thanks for your patches and sorry for getting to this a bit late.

On 2017-08-04 15:26:20 +0200, Simon Horman wrote:
> From: Dien Pham <dien.pham.ry@rvc.renesas.com>
> 
> Current, OPP tables are defined temporary,
> they are being evaluated and adjust in future.
> 
> Based in part on work by Hien Dang.
> 
> Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [simon: consolidated sseveral patches into one]
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 309 +++++++++++++++++++++++++++++++
>  1 file changed, 309 insertions(+)
> 
> I am not aware of any build-time depdendencies of this patch.
> 
> This patch has run-time depdnencies on:
> * [PATCH] cpufreq: rcar: Add support for R8A7795 SoC
> * [PATCH 0/4] r8a7795: Add Z and Z2 clock support
> 
> I have provided an integration patch with this patch, those DTS changes,
> and Renesas clock updates also depended on by the DTS changes. The result
> is working CPUFreq for the r8a7795 (R-Car H3) ES1.0.
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/r8a7795-cpufreq
> 
> A description of steps taken to lightly exercise the above can be found here:
> 
> http://elinux.org/Tests:R-CAR-GEN3-CPUFreq

I tested this it's working, nice!

> 
> If this work is acceptable I plan to follow up with patches to
> enable CPUFreq on the r8a7796 (R-Car M3-W).
> 
> This patch is based on renesas-arm64-dt-for-v4.14
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> index a87ae76880ab..f34da4c9ea52 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> @@ -46,6 +46,12 @@
>  			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
> +			operating-points-v2 = <&cluster0_opp_tb0>,
> +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> +				<&cluster0_opp_tb7>;

This however leaves me a bit confused. If I understand the bindings 
documentation you should only specify one phandle here. IIUC only the 
first one will be used anyhow, from drivers/base/power/opp/of.c

253 static struct device_node *_opp_of_get_opp_desc_node(struct device_node *np)
254 {
255         /*
256          * There should be only ONE phandle present in "operating-points-v2"
257          * property.
258          */
259 
260         return of_parse_phandle(np, "operating-points-v2", 0);
261 }

I tried to look at other sources and bindings and I can't find anywhere 
where more then one phandle could be useful, but I can have missed 
something? My interest in this is that I wish to hook it up with the 
thermal zones to have it act as passive cooling and implement the part 
of the BSP emergency shutdown driver using already available code and 
having more then one phandle here confuses me how to describe that in DT 
:-)

>  		};
>  
>  		a57_1: cpu at 1 {
> @@ -55,6 +61,11 @@
>  			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster0_opp_tb0>,
> +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> +				<&cluster0_opp_tb7>;
>  		};
>  
>  		a57_2: cpu at 2 {
> @@ -64,6 +75,11 @@
>  			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster0_opp_tb0>,
> +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> +				<&cluster0_opp_tb7>;
>  		};
>  
>  		a57_3: cpu at 3 {
> @@ -73,6 +89,11 @@
>  			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
>  			next-level-cache = <&L2_CA57>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster0_opp_tb0>,
> +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> +				<&cluster0_opp_tb7>;
>  		};
>  
>  		a53_0: cpu at 100 {
> @@ -82,6 +103,8 @@
>  			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;
> +			operating-points-v2 = <&cluster1_opp_tb0>;
>  		};
>  
>  		a53_1: cpu at 101 {
> @@ -91,6 +114,7 @@
>  			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster1_opp_tb0>;
>  		};
>  
>  		a53_2: cpu at 102 {
> @@ -100,6 +124,7 @@
>  			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster1_opp_tb0>;
>  		};
>  
>  		a53_3: cpu at 103 {
> @@ -109,6 +134,7 @@
>  			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
>  			next-level-cache = <&L2_CA53>;
>  			enable-method = "psci";
> +			operating-points-v2 = <&cluster1_opp_tb0>;
>  		};
>  
>  		L2_CA57: cache-controller-0 {
> @@ -126,6 +152,289 @@
>  		};
>  	};
>  
> +	cluster0_opp_tb0: opp_table0 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <830000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <830000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <830000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <900000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <960000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb1: opp_table1 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <890000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <950000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb2: opp_table2 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <810000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <810000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <810000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <880000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <930000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb3: opp_table3 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <800000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <800000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <800000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <870000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <910000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb4: opp_table4 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <790000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <790000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <790000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <860000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <890000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb5: opp_table5 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <780000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <780000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <780000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <850000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <880000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb6: opp_table6 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <770000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <770000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <770000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <840000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <870000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster0_opp_tb7: opp_table7 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			opp-microvolt = <760000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			opp-microvolt = <760000>;
> +			clock-latency-ns = <300000>;
> +		};
> +		opp at 1500000000 {
> +			opp-hz = /bits/ 64 <1500000000>;
> +			opp-microvolt = <760000>;
> +			clock-latency-ns = <300000>;
> +			opp-suspend;
> +		};
> +		opp at 1600000000 {
> +			opp-hz = /bits/ 64 <1600000000>;
> +			opp-microvolt = <830000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +		opp at 1700000000 {
> +			opp-hz = /bits/ 64 <1700000000>;
> +			opp-microvolt = <860000>;
> +			clock-latency-ns = <300000>;
> +			turbo-mode;
> +		};
> +	};
> +
> +	cluster1_opp_tb0: opp_table10 {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp at 1200000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			opp-microvolt = <820000>;
> +			clock-latency-ns = <300000>;
> +		};
> +	};
> +
>  	extal_clk: extal {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> -- 
> 2.1.4
> 
> 

-- 
Regards,
Niklas S?derlund

^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices
  2017-08-29 14:56   ` Niklas Söderlund
@ 2017-09-04  8:35     ` Simon Horman
  -1 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2017-09-04  8:35 UTC (permalink / raw)
  To: Niklas Söderlund; +Cc: linux-renesas-soc, linux-arm-kernel, Magnus Damm

On Tue, Aug 29, 2017 at 04:56:30PM +0200, Niklas Söderlund wrote:
> Hi Simon,
> 
> Thanks for your patches and sorry for getting to this a bit late.
> 
> On 2017-08-04 15:26:20 +0200, Simon Horman wrote:
> > From: Dien Pham <dien.pham.ry@rvc.renesas.com>
> > 
> > Current, OPP tables are defined temporary,
> > they are being evaluated and adjust in future.
> > 
> > Based in part on work by Hien Dang.
> > 
> > Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > [simon: consolidated sseveral patches into one]
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 309 +++++++++++++++++++++++++++++++
> >  1 file changed, 309 insertions(+)
> > 
> > I am not aware of any build-time depdendencies of this patch.
> > 
> > This patch has run-time depdnencies on:
> > * [PATCH] cpufreq: rcar: Add support for R8A7795 SoC
> > * [PATCH 0/4] r8a7795: Add Z and Z2 clock support
> > 
> > I have provided an integration patch with this patch, those DTS changes,
> > and Renesas clock updates also depended on by the DTS changes. The result
> > is working CPUFreq for the r8a7795 (R-Car H3) ES1.0.
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/r8a7795-cpufreq
> > 
> > A description of steps taken to lightly exercise the above can be found here:
> > 
> > http://elinux.org/Tests:R-CAR-GEN3-CPUFreq
> 
> I tested this it's working, nice!

Thanks!

Its seems there are a few rough edges (like the one below).
I'll try and shake those out in the near future.

> > If this work is acceptable I plan to follow up with patches to
> > enable CPUFreq on the r8a7796 (R-Car M3-W).
> > 
> > This patch is based on renesas-arm64-dt-for-v4.14
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > index a87ae76880ab..f34da4c9ea52 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > @@ -46,6 +46,12 @@
> >  			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
> >  			next-level-cache = <&L2_CA57>;
> >  			enable-method = "psci";
> > +			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
> > +			operating-points-v2 = <&cluster0_opp_tb0>,
> > +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> > +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> > +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> > +				<&cluster0_opp_tb7>;
> 
> This however leaves me a bit confused. If I understand the bindings 
> documentation you should only specify one phandle here. IIUC only the 
> first one will be used anyhow, from drivers/base/power/opp/of.c
> 
> 253 static struct device_node *_opp_of_get_opp_desc_node(struct device_node *np)
> 254 {
> 255         /*
> 256          * There should be only ONE phandle present in "operating-points-v2"
> 257          * property.
> 258          */
> 259 
> 260         return of_parse_phandle(np, "operating-points-v2", 0);
> 261 }
> 
> I tried to look at other sources and bindings and I can't find anywhere 
> where more then one phandle could be useful, but I can have missed 
> something? My interest in this is that I wish to hook it up with the 
> thermal zones to have it act as passive cooling and implement the part 
> of the BSP emergency shutdown driver using already available code and 
> having more then one phandle here confuses me how to describe that in DT 
> :-)

Thanks for pointing that out.

I am also unable to find other sources of the bindings
and I now see that having multiple phandles present makes little sense.
I now plan to remove them.

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices
@ 2017-09-04  8:35     ` Simon Horman
  0 siblings, 0 replies; 8+ messages in thread
From: Simon Horman @ 2017-09-04  8:35 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Aug 29, 2017 at 04:56:30PM +0200, Niklas S?derlund wrote:
> Hi Simon,
> 
> Thanks for your patches and sorry for getting to this a bit late.
> 
> On 2017-08-04 15:26:20 +0200, Simon Horman wrote:
> > From: Dien Pham <dien.pham.ry@rvc.renesas.com>
> > 
> > Current, OPP tables are defined temporary,
> > they are being evaluated and adjust in future.
> > 
> > Based in part on work by Hien Dang.
> > 
> > Signed-off-by: Dien Pham <dien.pham.ry@rvc.renesas.com>
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > [simon: consolidated sseveral patches into one]
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a7795.dtsi | 309 +++++++++++++++++++++++++++++++
> >  1 file changed, 309 insertions(+)
> > 
> > I am not aware of any build-time depdendencies of this patch.
> > 
> > This patch has run-time depdnencies on:
> > * [PATCH] cpufreq: rcar: Add support for R8A7795 SoC
> > * [PATCH 0/4] r8a7795: Add Z and Z2 clock support
> > 
> > I have provided an integration patch with this patch, those DTS changes,
> > and Renesas clock updates also depended on by the DTS changes. The result
> > is working CPUFreq for the r8a7795 (R-Car H3) ES1.0.
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git topic/r8a7795-cpufreq
> > 
> > A description of steps taken to lightly exercise the above can be found here:
> > 
> > http://elinux.org/Tests:R-CAR-GEN3-CPUFreq
> 
> I tested this it's working, nice!

Thanks!

Its seems there are a few rough edges (like the one below).
I'll try and shake those out in the near future.

> > If this work is acceptable I plan to follow up with patches to
> > enable CPUFreq on the r8a7796 (R-Car M3-W).
> > 
> > This patch is based on renesas-arm64-dt-for-v4.14
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > index a87ae76880ab..f34da4c9ea52 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
> > @@ -46,6 +46,12 @@
> >  			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
> >  			next-level-cache = <&L2_CA57>;
> >  			enable-method = "psci";
> > +			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;
> > +			operating-points-v2 = <&cluster0_opp_tb0>,
> > +				<&cluster0_opp_tb1>, <&cluster0_opp_tb2>,
> > +				<&cluster0_opp_tb3>, <&cluster0_opp_tb4>,
> > +				<&cluster0_opp_tb5>, <&cluster0_opp_tb6>,
> > +				<&cluster0_opp_tb7>;
> 
> This however leaves me a bit confused. If I understand the bindings 
> documentation you should only specify one phandle here. IIUC only the 
> first one will be used anyhow, from drivers/base/power/opp/of.c
> 
> 253 static struct device_node *_opp_of_get_opp_desc_node(struct device_node *np)
> 254 {
> 255         /*
> 256          * There should be only ONE phandle present in "operating-points-v2"
> 257          * property.
> 258          */
> 259 
> 260         return of_parse_phandle(np, "operating-points-v2", 0);
> 261 }
> 
> I tried to look at other sources and bindings and I can't find anywhere 
> where more then one phandle could be useful, but I can have missed 
> something? My interest in this is that I wish to hook it up with the 
> thermal zones to have it act as passive cooling and implement the part 
> of the BSP emergency shutdown driver using already available code and 
> having more then one phandle here confuses me how to describe that in DT 
> :-)

Thanks for pointing that out.

I am also unable to find other sources of the bindings
and I now see that having multiple phandles present makes little sense.
I now plan to remove them.

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-09-05  7:55 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-04 13:26 [PATCH] arm64: dts: r8a7795: Add OPPs table for cpu devices Simon Horman
2017-08-04 13:26 ` Simon Horman
2017-08-14 12:11 ` Geert Uytterhoeven
2017-08-14 12:11   ` Geert Uytterhoeven
2017-08-29 14:56 ` Niklas Söderlund
2017-08-29 14:56   ` Niklas Söderlund
2017-09-04  8:35   ` Simon Horman
2017-09-04  8:35     ` Simon Horman

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