[cip-dev] [PATCH 00/14] Add Device tree support for iWave G20D-Q7 board

[cip-dev] [PATCH 00/14] Add Device tree support for iWave G20D-Q7 board

[Biju Das]

This patch series aims to add initial SoC DT/Clock and iWave G20D-Q7 
DT.

The clock patch is based on the similar work done on r8a7791(R-Car M2)
SoC.

This series has been tested against linux-cip tag v4.4.y-cip master branch.

Biju Das (8):
  ARM: dts: r8a7743: initial SoC device tree
  ARM: shmobile: r8a7743: Add clock index macros for DT sources
  clk: shmobile: Document r8a7743 CPG clock support
  clk: shmobile: Document r8a7743 CPG DIV6 clock support
  clk: shmobile: Document r8a7743 MSTP clock support
  ARM: dts: r8a7743: Add clocks
  ARM: dts: iwg20m: Add iWave RZG1M Qseven SOM
  ARM: dts: iwg20d-q7: Add support for iWave G20D-Q7 board based on
    RZ/G1M

Sergei Shtylyov (4):
  ARM: dts: r8a7743: add SYS-DMAC support
  ARM: dts: r8a7743: add [H]SCIF{A|B} support
  ARM: dts: r8a7743: add Ether support
  ARM: dts: r8a7743: add IRQC support

Simon Horman (2):
  ARM: shmobile: defconfig: Enable r8a774[35] SoCs
  ARM: multi_v7_defconfig: Enable r8a774[35] SoCs

 .../bindings/clock/renesas,cpg-div6-clocks.txt     |   1 +
 .../bindings/clock/renesas,cpg-mstp-clocks.txt     |   1 +
 .../clock/renesas,rcar-gen2-cpg-clocks.txt         |   1 +
 arch/arm/boot/dts/Makefile                         |   1 +
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts            |  25 +
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi              |  29 +
 arch/arm/boot/dts/r8a7743.dtsi                     | 871 +++++++++++++++++++++
 arch/arm/configs/multi_v7_defconfig                |   2 +
 arch/arm/configs/shmobile_defconfig                |   2 +
 include/dt-bindings/clock/r8a7743-clock.h          | 166 ++++
 10 files changed, 1099 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
 create mode 100644 arch/arm/boot/dts/r8a7743-iwg20m.dtsi
 create mode 100644 arch/arm/boot/dts/r8a7743.dtsi
 create mode 100644 include/dt-bindings/clock/r8a7743-clock.h

-- 
1.9.1

[cip-dev] [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree

[Biju Das]

The  initial r8A7743 SoC device tree including CPU0, GIC and timer.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7743.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7743.dtsi

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
new file mode 100644
index 0000000..8575a2f
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Device Tree Source for the r8a7743 SoC
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "renesas,r8a7743";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a15";
+			reg = <0>;
+			clock-frequency = <1500000000>;
+		};
+	};
+
+	gic: interrupt-controller at f1001000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0 0xf1001000 0 0x1000>,
+		      <0 0xf1002000 0 0x1000>,
+		      <0 0xf1004000 0 0x2000>,
+		      <0 0xf1006000 0 0x2000>;
+		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
+				   IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) |
+				    IRQ_TYPE_LEVEL_LOW)>,
+			     <1 14 (GIC_CPU_MASK_SIMPLE(2) |
+				    IRQ_TYPE_LEVEL_LOW)>,
+			     <1 11 (GIC_CPU_MASK_SIMPLE(2) |
+				    IRQ_TYPE_LEVEL_LOW)>,
+			     <1 10 (GIC_CPU_MASK_SIMPLE(2) |
+				    IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
1.9.1

[cip-dev] [PATCH 02/14] ARM: shmobile: r8a7743: Add clock index macros for DT sources

[Biju Das]

Add macros usable by device tree sources to reference r8a7743 clocks by
index.

This is based on the work done by Laurent Pinchart for the r8a7791 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 include/dt-bindings/clock/r8a7743-clock.h | 166 ++++++++++++++++++++++++++++++
 1 file changed, 166 insertions(+)
 create mode 100644 include/dt-bindings/clock/r8a7743-clock.h

diff --git a/include/dt-bindings/clock/r8a7743-clock.h b/include/dt-bindings/clock/r8a7743-clock.h
new file mode 100644
index 0000000..a5c7e38
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7743-clock.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ * Copyright 2013 Ideas On Board SPRL
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7743_H__
+#define __DT_BINDINGS_CLOCK_R8A7743_H__
+
+/* CPG */
+#define R8A7743_CLK_MAIN		0
+#define R8A7743_CLK_PLL0		1
+#define R8A7743_CLK_PLL1		2
+#define R8A7743_CLK_PLL3		3
+#define R8A7743_CLK_LB			4
+#define R8A7743_CLK_QSPI		5
+#define R8A7743_CLK_SDH			6
+#define R8A7743_CLK_SD0			7
+#define R8A7743_CLK_Z			8
+#define R8A7743_CLK_RCAN		9
+
+/* MSTP0 */
+#define R8A7743_CLK_MSIOF0		0
+
+/* MSTP1 */
+#define R8A7743_CLK_VCP0		1
+#define R8A7743_CLK_VPC0		3
+#define R8A7743_CLK_ADG			6
+#define R8A7743_CLK_TSIF0		8
+#define R8A7743_CLK_TMU1		11
+#define R8A7743_CLK_3DG			12
+#define R8A7743_CLK_2DDMAC		15
+#define R8A7743_CLK_FDP1_1		18
+#define R8A7743_CLK_FDP1_0		19
+#define R8A7743_CLK_TMU3		21
+#define R8A7743_CLK_TMU2		22
+#define R8A7743_CLK_CMT0		24
+#define R8A7743_CLK_TMU0		25
+#define R8A7743_CLK_VSP1_DU1		27
+#define R8A7743_CLK_VSP1_DU0		28
+#define R8A7743_CLK_VSP1_S		31
+
+/* MSTP2 */
+#define R8A7743_CLK_SCIFA2		2
+#define R8A7743_CLK_SCIFA1		3
+#define R8A7743_CLK_SCIFA0		4
+#define R8A7743_CLK_MSIOF2		5
+#define R8A7743_CLK_SCIFB0		6
+#define R8A7743_CLK_SCIFB1		7
+#define R8A7743_CLK_MSIOF1		8
+#define R8A7743_CLK_SCIFB2		16
+#define R8A7743_CLK_SYS_DMAC1		18
+#define R8A7743_CLK_SYS_DMAC0		19
+
+/* MSTP3 */
+#define R8A7743_CLK_TPU0		4
+#define R8A7743_CLK_SDHI3		11
+#define R8A7743_CLK_SDHI2		12
+#define R8A7743_CLK_SDHI0		14
+#define R8A7743_CLK_MMCIF0		15
+#define R8A7743_CLK_IIC0		18
+#define R8A7743_CLK_PCIEC		19
+#define R8A7743_CLK_IIC1		23
+#define R8A7743_CLK_SSUSB		28
+#define R8A7743_CLK_CMT1		29
+#define R8A7743_CLK_USBDMAC0		30
+#define R8A7743_CLK_USBDMAC1		31
+
+/* MSTP4 */
+#define R8A7743_CLK_RWDT		4
+#define R8A7743_CLK_USB_DDM		6
+#define R8A7743_CLK_IRQC		7
+#define R8A7743_CLK_INTC_SYS		8
+
+/* MSTP5 */
+#define R8A7743_CLK_AUDIO_DMAC1		1
+#define R8A7743_CLK_AUDIO_DMAC0		2
+#define R8A7743_CLK_THERMAL		22
+#define R8A7743_CLK_PWM			23
+#define R8A7743_CLK_BOOT_ROM		26
+
+/* MSTP7 */
+#define R8A7743_CLK_USB_EHCI		3
+#define R8A7743_CLK_HSUSB		4
+#define R8A7743_CLK_HSCIF2		13
+#define R8A7743_CLK_SCIF5		14
+#define R8A7743_CLK_SCIF4		15
+#define R8A7743_CLK_HSCIF1		16
+#define R8A7743_CLK_HSCIF0		17
+#define R8A7743_CLK_SCIF3		18
+#define R8A7743_CLK_SCIF2		19
+#define R8A7743_CLK_SCIF1		20
+#define R8A7743_CLK_SCIF0		21
+#define R8A7743_CLK_DU1			23
+#define R8A7743_CLK_DU0			24
+#define R8A7743_CLK_LVDS0		26
+
+/* MSTP8 */
+#define R8A7743_CLK_IPMMU_SGX		0
+#define R8A7743_CLK_VIN2		9
+#define R8A7743_CLK_VIN1		10
+#define R8A7743_CLK_VIN0		11
+#define R8A7743_CLK_ETHERAVB		12
+#define R8A7743_CLK_ETHER		13
+#define R8A7743_CLK_SATA1		14
+#define R8A7743_CLK_SATA0		15
+#define R8A7743_CLK_DCU			30
+
+/* MSTP9 */
+#define R8A7743_CLK_GPIO7		4
+#define R8A7743_CLK_GPIO6		5
+#define R8A7743_CLK_GPIO5		7
+#define R8A7743_CLK_GPIO4		8
+#define R8A7743_CLK_GPIO3		9
+#define R8A7743_CLK_GPIO2		10
+#define R8A7743_CLK_GPIO1		11
+#define R8A7743_CLK_GPIO0		12
+#define R8A7743_CLK_RCAN1		15
+#define R8A7743_CLK_RCAN0		16
+#define R8A7743_CLK_QSPI_MOD		17
+#define R8A7743_CLK_I2C5		25
+#define R8A7743_CLK_IICDVFS		26
+#define R8A7743_CLK_I2C4		27
+#define R8A7743_CLK_I2C3		28
+#define R8A7743_CLK_I2C2		29
+#define R8A7743_CLK_I2C1		30
+#define R8A7743_CLK_I2C0		31
+
+/* MSTP10 */
+#define R8A7743_CLK_SSI_ALL		5
+#define R8A7743_CLK_SSI9		6
+#define R8A7743_CLK_SSI8		7
+#define R8A7743_CLK_SSI7		8
+#define R8A7743_CLK_SSI6		9
+#define R8A7743_CLK_SSI5		10
+#define R8A7743_CLK_SSI4		11
+#define R8A7743_CLK_SSI3		12
+#define R8A7743_CLK_SSI2		13
+#define R8A7743_CLK_SSI1		14
+#define R8A7743_CLK_SSI0		15
+#define R8A7743_CLK_SCU_ALL		17
+#define R8A7743_CLK_SCU_DVC1		18
+#define R8A7743_CLK_SCU_DVC0		19
+#define R8A7743_CLK_SCU_CTU1_MIX1	20
+#define R8A7743_CLK_SCU_CTU0_MIX0	21
+#define R8A7743_CLK_SCU_SRC9		22
+#define R8A7743_CLK_SCU_SRC8		23
+#define R8A7743_CLK_SCU_SRC7		24
+#define R8A7743_CLK_SCU_SRC6		25
+#define R8A7743_CLK_SCU_SRC5		26
+#define R8A7743_CLK_SCU_SRC4		27
+#define R8A7743_CLK_SCU_SRC3		28
+#define R8A7743_CLK_SCU_SRC2		29
+#define R8A7743_CLK_SCU_SRC1		30
+#define R8A7743_CLK_SCU_SRC0		31
+
+/* MSTP11 */
+#define R8A7743_CLK_SCIFA3		6
+#define R8A7743_CLK_SCIFA4		7
+#define R8A7743_CLK_SCIFA5		8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7743_H__ */
-- 
1.9.1

[cip-dev] [PATCH 03/14] clk: shmobile: Document r8a7743 CPG clock support

[Biju Das]

Document r8a7743 CPG clock support.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 2a9a8ed..986b8a1 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -8,6 +8,7 @@ CPG Module Stop (MSTP) Clocks.
 Required Properties:
 
   - compatible: Must be one of
+    - "renesas,r8a7743-cpg-clocks" for the r8a7743 CPG
     - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
     - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
     - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
-- 
1.9.1

[cip-dev] [PATCH 04/14] clk: shmobile: Document r8a7743 CPG DIV6 clock support

[Biju Das]

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 38dcf03..2990615 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -9,6 +9,7 @@ Required Properties:
   - compatible: Must be one of the following
     - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
     - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
+    - "renesas,r8a7743-div6-clock" for R8A7743 (RZ/G1M) DIV6 clocks
     - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
     - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
     - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
-- 
1.9.1

[cip-dev] [PATCH 05/14] clk: shmobile: Document r8a7743 MSTP clock support

[Biju Das]

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index 16ed181..f444798 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -13,6 +13,7 @@ Required Properties:
     - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
     - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
     - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
+    - "renesas,r8a7743-mstp-clocks" for R8A7743 (RZ/G1M) MSTP gate clocks
     - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
     - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
     - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
-- 
1.9.1

[cip-dev] [PATCH 06/14] ARM: dts: r8a7743: Add clocks

[Biju Das]

Declare all core clocks and DIV6 clocks, as well as all MSTP clocks.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/boot/dts/r8a7743.dtsi | 479 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 479 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 8575a2f..ecf5d93 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -8,6 +8,7 @@
  * kind, whether express or implied.
  */
 
+#include <dt-bindings/clock/r8a7743-clock.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
@@ -26,6 +27,7 @@
 			compatible = "arm,cortex-a15";
 			reg = <0>;
 			clock-frequency = <1500000000>;
+			clocks = <&cpg_clocks R8A7743_CLK_Z>;
 		};
 	};
 
@@ -53,4 +55,481 @@
 			     <1 10 (GIC_CPU_MASK_SIMPLE(2) |
 				    IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	clocks {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* External root clock */
+		extal_clk: extal_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+			clock-output-names = "extal";
+		};
+
+		/*
+		 * The external audio clocks are configured as 0 Hz fixed
+		 * frequency clocks by default. Boards that provide audio
+		 * clocks should override them.
+		 */
+		audio_clk_a: audio_clk_a {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "audio_clk_a";
+		};
+		audio_clk_b: audio_clk_b {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "audio_clk_b";
+		};
+		audio_clk_c: audio_clk_c {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <0>;
+			clock-output-names = "audio_clk_c";
+		};
+
+		/* External PCIe clock - can be overridden by the board */
+		pcie_bus_clk: pcie_bus_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "pcie_bus";
+			status = "disabled";
+		};
+
+		/* External USB clock - can be overridden by the board */
+		usb_extal_clk: usb_extal_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <48000000>;
+			clock-output-names = "usb_extal";
+		};
+
+		/* External CAN clock */
+		can_clk: can_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+			clock-output-names = "can_clk";
+			status = "disabled";
+		};
+
+		/* External SCIF clock */
+		scif_clk: scif {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			/* This value must be overridden by the board. */
+			clock-frequency = <0>;
+		};
+
+		/* Special CPG clocks */
+		cpg_clocks: cpg_clocks at e6150000 {
+			compatible = "renesas,r8a7743-cpg-clocks",
+				     "renesas,rcar-gen2-cpg-clocks";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk &usb_extal_clk>;
+			#clock-cells = <1>;
+			clock-output-names = "main", "pll0", "pll1", "pll3",
+					     "lb", "qspi", "sdh", "sd0", "z",
+					     "rcan";
+			#power-domain-cells = <0>;
+		};
+
+		/* Variable factor clocks */
+		sd2_clk: sd2_clk at e6150078 {
+			compatible = "renesas,r8a7743-div6-clock",
+				     "renesas,cpg-div6-clock";
+			reg = <0 0xe6150078 0 4>;
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-output-names = "sd2";
+		};
+		sd3_clk: sd3_clk at e615026c {
+			compatible = "renesas,r8a7743-div6-clock",
+				     "renesas,cpg-div6-clock";
+			reg = <0 0xe615026c 0 4>;
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-output-names = "sd3";
+		};
+		mmc0_clk: mmc0_clk at e6150240 {
+			compatible = "renesas,r8a7743-div6-clock",
+				     "renesas,cpg-div6-clock";
+			reg = <0 0xe6150240 0 4>;
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-output-names = "mmc0";
+		};
+
+		/* Fixed factor clocks */
+		pll1_div2_clk: pll1_div2_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+			clock-output-names = "pll1_div2";
+		};
+		zg_clk: zg_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <3>;
+			clock-mult = <1>;
+			clock-output-names = "zg";
+		};
+		zx_clk: zx_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <3>;
+			clock-mult = <1>;
+			clock-output-names = "zx";
+		};
+		zs_clk: zs_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <6>;
+			clock-mult = <1>;
+			clock-output-names = "zs";
+		};
+		hp_clk: hp_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <12>;
+			clock-mult = <1>;
+			clock-output-names = "hp";
+		};
+		b_clk: b_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <12>;
+			clock-mult = <1>;
+			clock-output-names = "b";
+		};
+		p_clk: p_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <24>;
+			clock-mult = <1>;
+			clock-output-names = "p";
+		};
+		cl_clk: cl_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <48>;
+			clock-mult = <1>;
+			clock-output-names = "cl";
+		};
+		m2_clk: m2_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clock-output-names = "m2";
+		};
+		rclk_clk: rclk_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <(48 * 1024)>;
+			clock-mult = <1>;
+			clock-output-names = "rclk";
+		};
+		oscclk_clk: oscclk_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL1>;
+			#clock-cells = <0>;
+			clock-div = <(12 * 1024)>;
+			clock-mult = <1>;
+			clock-output-names = "oscclk";
+		};
+		zb3_clk: zb3_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL3>;
+			#clock-cells = <0>;
+			clock-div = <4>;
+			clock-mult = <1>;
+			clock-output-names = "zb3";
+		};
+		zb3d2_clk: zb3d2_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL3>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clock-output-names = "zb3d2";
+		};
+		ddr_clk: ddr_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&cpg_clocks R8A7743_CLK_PLL3>;
+			#clock-cells = <0>;
+			clock-div = <8>;
+			clock-mult = <1>;
+			clock-output-names = "ddr";
+		};
+		mp_clk: mp_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&pll1_div2_clk>;
+			#clock-cells = <0>;
+			clock-div = <15>;
+			clock-mult = <1>;
+			clock-output-names = "mp";
+		};
+		cp_clk: cp_clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&extal_clk>;
+			#clock-cells = <0>;
+			clock-div = <2>;
+			clock-mult = <1>;
+			clock-output-names = "cp";
+		};
+
+		/* Gate clocks */
+		mstp0_clks: mstp0_clks at e6150130 {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
+			clocks = <&mp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <R8A7743_CLK_MSIOF0>;
+			clock-output-names = "msiof0";
+		};
+		mstp1_clks: mstp1_clks at e6150134 {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+			clocks = <&zs_clk>, <&zs_clk>, <&p_clk>,
+				 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
+				 <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
+				 <&zs_clk>, <&zs_clk>, <&zs_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_VCP0 R8A7743_CLK_VPC0
+				R8A7743_CLK_TMU1 R8A7743_CLK_3DG
+				R8A7743_CLK_2DDMAC R8A7743_CLK_FDP1_1
+				R8A7743_CLK_FDP1_0 R8A7743_CLK_TMU3
+				R8A7743_CLK_TMU2 R8A7743_CLK_CMT0
+				R8A7743_CLK_TMU0 R8A7743_CLK_VSP1_DU1
+				R8A7743_CLK_VSP1_DU0 R8A7743_CLK_VSP1_S
+			>;
+			clock-output-names =
+				"vcp0", "vpc0", "tmu1", "3dg",
+				"2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2",
+				"cmt0",	"tmu0", "vsp1-du1", "vsp1-du0",
+				"vsp1-sy";
+		};
+		mstp2_clks: mstp2_clks at e6150138 {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
+				 <&zs_clk>, <&zs_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_SCIFA2 R8A7743_CLK_SCIFA1
+				R8A7743_CLK_SCIFA0 R8A7743_CLK_MSIOF2
+				R8A7743_CLK_SCIFB0 R8A7743_CLK_SCIFB1
+				R8A7743_CLK_MSIOF1 R8A7743_CLK_SCIFB2
+				R8A7743_CLK_SYS_DMAC1 R8A7743_CLK_SYS_DMAC0
+			>;
+			clock-output-names =
+				"scifa2", "scifa1", "scifa0", "msiof2",
+				"scifb0", "scifb1", "msiof1", "scifb2",
+				"sys-dmac1", "sys-dmac0";
+		};
+		mstp3_clks: mstp3_clks at e615013c {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
+			clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
+				 <&cpg_clocks R8A7743_CLK_SD0>, <&mmc0_clk>,
+				 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
+				 <&rclk_clk>, <&hp_clk>, <&hp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_TPU0 R8A7743_CLK_SDHI3
+				R8A7743_CLK_SDHI2 R8A7743_CLK_SDHI0
+				R8A7743_CLK_MMCIF0 R8A7743_CLK_IIC0
+				R8A7743_CLK_PCIEC R8A7743_CLK_IIC1
+				R8A7743_CLK_SSUSB R8A7743_CLK_CMT1
+				R8A7743_CLK_USBDMAC0 R8A7743_CLK_USBDMAC1
+			>;
+			clock-output-names =
+				"tpu0", "sdhi3", "sdhi2", "sdhi0", "mmcif0",
+				"i2c7", "pciec", "i2c8", "ssusb", "cmt1",
+				"usbdmac0", "usbdmac1";
+		};
+		mstp4_clks: mstp4_clks at e6150140 {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+			clocks = <&cp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <R8A7743_CLK_IRQC>;
+			clock-output-names = "irqc";
+		};
+		mstp5_clks: mstp5_clks at e6150144 {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
+			clocks = <&hp_clk>, <&hp_clk>,
+				 <&extal_clk>, <&p_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_AUDIO_DMAC0 R8A7743_CLK_AUDIO_DMAC1
+				R8A7743_CLK_THERMAL R8A7743_CLK_PWM
+			>;
+			clock-output-names = "audmac0", "audmac1",
+					     "thermal", "pwm";
+		};
+		mstp7_clks: mstp7_clks at e615014c {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+			clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
+				 <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
+				 <&p_clk>, <&p_clk>, <&p_clk>,<&zx_clk>,
+				 <&zx_clk>, <&zx_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_USB_EHCI R8A7743_CLK_HSUSB
+				R8A7743_CLK_HSCIF2 R8A7743_CLK_SCIF5
+				R8A7743_CLK_SCIF4 R8A7743_CLK_HSCIF1
+				R8A7743_CLK_HSCIF0 R8A7743_CLK_SCIF3
+				R8A7743_CLK_SCIF2 R8A7743_CLK_SCIF1
+				R8A7743_CLK_SCIF0 R8A7743_CLK_DU1
+				R8A7743_CLK_DU0	R8A7743_CLK_LVDS0
+			>;
+			clock-output-names =
+				"ehci", "hsusb", "hscif2", "scif5", "scif4",
+				"hscif1", "hscif0", "scif3", "scif2", "scif1",
+				"scif0", "du1", "du0", "lvds0";
+		};
+		mstp8_clks: mstp8_clks at e6150990 {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
+			clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
+				 <&hp_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_IPMMU_SGX
+				R8A7743_CLK_VIN2 R8A7743_CLK_VIN1
+				R8A7743_CLK_VIN0 R8A7743_CLK_ETHERAVB
+				R8A7743_CLK_ETHER R8A7743_CLK_SATA1
+				R8A7743_CLK_SATA0
+			>;
+			clock-output-names =
+				"ipmmu_sgx", "vin2", "vin1", "vin0",
+				"etheravb", "ether", "sata1", "sata0";
+		};
+		mstp9_clks: mstp9_clks at e6150994 {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
+			clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+				 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
+				 <&p_clk>, <&p_clk>,
+				 <&cpg_clocks R8A7743_CLK_QSPI>, <&hp_clk>,
+				 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+				 <&hp_clk>, <&hp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_GPIO7 R8A7743_CLK_GPIO6
+				R8A7743_CLK_GPIO5 R8A7743_CLK_GPIO4
+				R8A7743_CLK_GPIO3 R8A7743_CLK_GPIO2
+				R8A7743_CLK_GPIO1 R8A7743_CLK_GPIO0
+				R8A7743_CLK_RCAN1 R8A7743_CLK_RCAN0
+				R8A7743_CLK_QSPI_MOD R8A7743_CLK_I2C5
+				R8A7743_CLK_IICDVFS R8A7743_CLK_I2C4
+				R8A7743_CLK_I2C3 R8A7743_CLK_I2C2
+				R8A7743_CLK_I2C1 R8A7743_CLK_I2C0
+			>;
+			clock-output-names =
+				"gpio7", "gpio6", "gpio5", "gpio4", "gpio3",
+				"gpio2", "gpio1", "gpio0", "rcan1", "rcan0",
+				"qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3",
+				"i2c2", "i2c1", "i2c0";
+		};
+		mstp10_clks: mstp10_clks at e6150998 {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
+			clocks = <&p_clk>,
+				 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+				 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+				 <&p_clk>, <&p_clk>,
+				 <&p_clk>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>,
+				 <&mstp10_clks R8A7743_CLK_SCU_ALL>;
+
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_SSI_ALL
+				R8A7743_CLK_SSI9 R8A7743_CLK_SSI8
+				R8A7743_CLK_SSI7 R8A7743_CLK_SSI6
+				R8A7743_CLK_SSI5 R8A7743_CLK_SSI4
+				R8A7743_CLK_SSI3 R8A7743_CLK_SSI2
+				R8A7743_CLK_SSI1 R8A7743_CLK_SSI0
+				R8A7743_CLK_SCU_ALL
+				R8A7743_CLK_SCU_DVC1 R8A7743_CLK_SCU_DVC0
+				R8A7743_CLK_SCU_CTU1_MIX1
+				R8A7743_CLK_SCU_CTU0_MIX0
+				R8A7743_CLK_SCU_SRC9 R8A7743_CLK_SCU_SRC8
+				R8A7743_CLK_SCU_SRC7 R8A7743_CLK_SCU_SRC6
+				R8A7743_CLK_SCU_SRC5 R8A7743_CLK_SCU_SRC4
+				R8A7743_CLK_SCU_SRC3 R8A7743_CLK_SCU_SRC2
+				R8A7743_CLK_SCU_SRC1 R8A7743_CLK_SCU_SRC0
+			>;
+			clock-output-names =
+				"ssi-all",
+				"ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
+				"ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
+				"scu-all",
+				"scu-dvc1", "scu-dvc0",
+				"scu-ctu1-mix1", "scu-ctu0-mix0",
+				"scu-src9", "scu-src8", "scu-src7", "scu-src6",
+				"scu-src5", "scu-src4", "scu-src3", "scu-src2",
+				"scu-src1", "scu-src0";
+		};
+		mstp11_clks: mstp11_clks at e615099c {
+			compatible = "renesas,r8a7743-mstp-clocks",
+				     "renesas,cpg-mstp-clocks";
+			reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
+			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
+			#clock-cells = <1>;
+			clock-indices = <
+				R8A7743_CLK_SCIFA3 R8A7743_CLK_SCIFA4
+				R8A7743_CLK_SCIFA5
+			>;
+			clock-output-names = "scifa3", "scifa4", "scifa5";
+		};
+	};
 };
-- 
1.9.1

[cip-dev] [PATCH 07/14] ARM: dts: r8a7743: add SYS-DMAC support

[Biju Das]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Describe SYS-DMAC0/1 in the R8A7743 device tree.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 6ed5ed500a5c67eed7b76e5353f7bca3b3daae92)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>

Conflicts:
	arch/arm/boot/dts/r8a7743.dtsi
---
 arch/arm/boot/dts/r8a7743.dtsi | 62 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index ecf5d93..1cfee52 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -56,6 +56,68 @@
 				    IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	dmac0: dma-controller at e6700000 {
+		compatible = "renesas,rcar-dmac";
+		reg = <0 0xe6700000 0 0x20000>;
+		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				"ch0", "ch1", "ch2", "ch3",
+				"ch4", "ch5", "ch6", "ch7",
+				"ch8", "ch9", "ch10", "ch11",
+				"ch12", "ch13", "ch14";
+		clocks = <&mstp2_clks R8A7743_CLK_SYS_DMAC0>;
+		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
+		#dma-cells = <1>;
+		dma-channels = <15>;
+	};
+
+	dmac1: dma-controller at e6720000 {
+		compatible = "renesas,rcar-dmac";
+		reg = <0 0xe6720000 0 0x20000>;
+		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+			      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "error",
+				"ch0", "ch1", "ch2", "ch3",
+				"ch4", "ch5", "ch6", "ch7",
+				"ch8", "ch9", "ch10", "ch11",
+				"ch12", "ch13", "ch14";
+		clocks = <&mstp2_clks R8A7743_CLK_SYS_DMAC1>;
+		clock-names = "fck";
+		power-domains = <&cpg_clocks>;
+		#dma-cells = <1>;
+		dma-channels = <15>;
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
-- 
1.9.1

[cip-dev] [PATCH 08/14] ARM: dts: r8a7743: add [H]SCIF{A|B} support

[Biju Das]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Describe [H]SCIF{|A|B} ports in the R8A7743 device tree.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: consistently use tabs for indentation]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

(cherry picked from commit 809c01342691469456489bbe87d2d79ed9638631)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>

Conflicts:
	arch/arm/boot/dts/r8a7743.dtsi
---
 arch/arm/boot/dts/r8a7743.dtsi | 243 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 243 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 1cfee52..d687e47 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -118,6 +118,249 @@
 		dma-channels = <15>;
 	};
 
+	scifa0: serial at e6c40000 {
+		compatible = "renesas,scifa-r8a7743", "renesas,scifa";
+		reg = <0 0xe6c40000 0 0x40>;
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp2_clks R8A7743_CLK_SCIFA0>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+		       <&dmac1 0x21>, <&dmac1 0x22>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scifa1: serial at e6c50000 {
+		compatible = "renesas,scifa-r8a7743", "renesas,scifa";
+		reg = <0 0xe6c50000 0 0x40>;
+		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp2_clks R8A7743_CLK_SCIFA1>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+		       <&dmac1 0x25>, <&dmac1 0x26>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scifa2: serial at e6c60000 {
+		compatible = "renesas,scifa-r8a7743", "renesas,scifa";
+		reg = <0 0xe6c60000 0 0x40>;
+		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp2_clks R8A7743_CLK_SCIFA2>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+		       <&dmac1 0x27>, <&dmac1 0x28>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scifa3: serial at e6c70000 {
+		compatible = "renesas,scifa-r8a7743", "renesas,scifa";
+		reg = <0 0xe6c70000 0 0x40>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp11_clks R8A7743_CLK_SCIFA3>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+		       <&dmac1 0x1b>, <&dmac1 0x1c>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scifa4: serial at e6c78000 {
+		compatible = "renesas,scifa-r8a7743", "renesas,scifa";
+		reg = <0 0xe6c78000 0 0x40>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp11_clks R8A7743_CLK_SCIFA4>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+		       <&dmac1 0x1f>, <&dmac1 0x20>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scifa5: serial at e6c80000 {
+		compatible = "renesas,scifa-r8a7743", "renesas,scifa";
+		reg = <0 0xe6c80000 0 0x40>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp11_clks R8A7743_CLK_SCIFA5>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+		       <&dmac1 0x23>, <&dmac1 0x24>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scifb0: serial at e6c20000 {
+		compatible = "renesas,scifb-r8a7743", "renesas,scifb";
+		reg = <0 0xe6c20000 0 0x100>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp2_clks R8A7743_CLK_SCIFB0>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+		       <&dmac1 0x3d>, <&dmac1 0x3e>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scifb1: serial at e6c30000 {
+		compatible = "renesas,scifb-r8a7743", "renesas,scifb";
+		reg = <0 0xe6c30000 0 0x100>;
+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp2_clks R8A7743_CLK_SCIFB1>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+		       <&dmac1 0x19>, <&dmac1 0x1a>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scifb2: serial at e6ce0000 {
+		compatible = "renesas,scifb-r8a7743", "renesas,scifb";
+		reg = <0 0xe6ce0000 0 0x100>;
+		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp2_clks R8A7743_CLK_SCIFB2>;
+		clock-names = "sci_ick";
+		dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+		       <&dmac1 0x1d>, <&dmac1 0x1e>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scif0: serial at e6e60000 {
+		compatible = "renesas,scif-r8a7743", "renesas,scif";
+		reg = <0 0xe6e60000 0 0x40>;
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_SCIF0>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+		       <&dmac1 0x29>, <&dmac1 0x2a>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scif1: serial at e6e68000 {
+		compatible = "renesas,scif-r8a7743", "renesas,scif";
+		reg = <0 0xe6e68000 0 0x40>;
+		interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_SCIF1>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+		       <&dmac1 0x2d>, <&dmac1 0x2e>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scif2: serial at e6e58000 {
+		compatible = "renesas,scif-r8a7743", "renesas,scif";
+		reg = <0 0xe6e58000 0 0x40>;
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_SCIF2>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+		       <&dmac1 0x2b>, <&dmac1 0x2c>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scif3: serial at e6ea8000 {
+		compatible = "renesas,scif-r8a7743", "renesas,scif";
+		reg = <0 0xe6ea8000 0 0x40>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_SCIF3>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+		       <&dmac1 0x2f>, <&dmac1 0x30>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scif4: serial at e6ee0000 {
+		compatible = "renesas,scif-r8a7743", "renesas,scif";
+		reg = <0 0xe6ee0000 0 0x40>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_SCIF4>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+		       <&dmac1 0xfb>, <&dmac1 0xfc>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	scif5: serial at e6ee8000 {
+		compatible = "renesas,scif-r8a7743", "renesas,scif";
+		reg = <0 0xe6ee8000 0 0x40>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_SCIF5>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+		       <&dmac1 0xfd>, <&dmac1 0xfe>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	hscif0: serial at e62c0000 {
+		compatible = "renesas,hscif-r8a7743", "renesas,hscif";
+		reg = <0 0xe62c0000 0 0x60>;
+		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_HSCIF0>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+		       <&dmac1 0x39>, <&dmac1 0x3a>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	hscif1: serial at e62c8000 {
+		compatible = "renesas,hscif-r8a7743", "renesas,hscif";
+		reg = <0 0xe62c8000 0 0x60>;
+		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_HSCIF1>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+		       <&dmac1 0x4d>, <&dmac1 0x4e>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
+	hscif2: serial at e62d0000 {
+		compatible = "renesas,hscif-r8a7743", "renesas,hscif";
+		reg = <0 0xe62d0000 0 0x60>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp7_clks R8A7743_CLK_HSCIF2>,
+			 <&zs_clk>, <&scif_clk>;
+		clock-names = "sci_ick", "brg_int", "scif_clk";
+		dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+		       <&dmac1 0x3b>, <&dmac1 0x3c>;
+		dma-names = "tx", "rx", "tx", "rx";
+		power-domains = <&cpg_clocks>;
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
-- 
1.9.1

[cip-dev] [PATCH 09/14] ARM: dts: r8a7743: add Ether support

[Biju Das]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Define the generic R8A7743 part of the Ether device node.

Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 75f97fb45e6297e3fbaf837fc30850cf724c8f83)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>

Conflicts:
	arch/arm/boot/dts/r8a7743.dtsi
---
 arch/arm/boot/dts/r8a7743.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index d687e47..88406e32 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -361,6 +361,18 @@
 		status = "disabled";
 	};
 
+	ether: ethernet at ee700000 {
+		compatible = "renesas,ether-r8a7743";
+		reg = <0 0xee700000 0 0x400>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp8_clks R8A7743_CLK_ETHER>;
+		power-domains = <&cpg_clocks>;
+		phy-mode = "rmii";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	clocks {
 		#address-cells = <2>;
 		#size-cells = <2>;
-- 
1.9.1

[cip-dev] [PATCH 10/14] ARM: dts: r8a7743: add IRQC support

[Biju Das]

From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Describe the IRQC interrupt controller in the R8A7743 device tree.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit ef0ca50774495c4ca4d1211252c8ee5af5136187)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>

Conflicts:
	arch/arm/boot/dts/r8a7743.dtsi
---
 arch/arm/boot/dts/r8a7743.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 88406e32..64182bf 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -56,6 +56,25 @@
 				    IRQ_TYPE_LEVEL_LOW)>;
 	};
 
+	irqc: interrupt-controller at e61c0000 {
+		compatible = "renesas,irqc-r8a7743", "renesas,irqc";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0 0xe61c0000 0 0x200>;
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&mstp4_clks R8A7743_CLK_IRQC>;
+		power-domains = <&cpg_clocks>;
+	};
+
 	dmac0: dma-controller at e6700000 {
 		compatible = "renesas,rcar-dmac";
 		reg = <0 0xe6700000 0 0x20000>;
-- 
1.9.1

[cip-dev] [PATCH 11/14] ARM: dts: iwg20m: Add iWave RZG1M Qseven SOM

[Biju Das]

Add support for iWave RZG1M Qseven System On Module.
http://www.iwavesystems.com/rz-g1m-qseven-module.html

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit aabf13bac0046a1add4a3c39881ffb0abe692542)
---
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7743-iwg20m.dtsi

diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
new file mode 100644
index 0000000..001ca91
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Device Tree Source for the iWave-RZG1M-20M Qseven SOM
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include "r8a7743.dtsi"
+
+/ {
+	compatible = "iwave,g20m", "renesas,r8a7743";
+
+	memory at 40000000 {
+		device_type = "memory";
+		reg = <0 0x40000000 0 0x20000000>;
+	};
+
+	memory at 200000000 {
+		device_type = "memory";
+		reg = <2 0x00000000 0 0x20000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <20000000>;
+};
-- 
1.9.1

[cip-dev] [PATCH 12/14] ARM: dts: iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1M

[Biju Das]

Add support for iWave RainboW-G20D-Qseven board based on RZ/G1M.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit ad2c0558d0494b420cadd6e887ddab2cd4e27e48)

Conflicts:
	arch/arm/boot/dts/Makefile
---
 arch/arm/boot/dts/Makefile              |  1 +
 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 25 +++++++++++++++++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 30bbc37..f8fd692 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -544,6 +544,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
 	r7s72100-genmai.dtb \
 	r8a73a4-ape6evm.dtb \
 	r8a7740-armadillo800eva.dtb \
+	r8a7743-iwg20d-q7.dtb \
 	r8a7778-bockw.dtb \
 	r8a7779-marzen.dtb \
 	r8a7790-lager.dtb \
diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
new file mode 100644
index 0000000..9b54783
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for the iWave-RZG1M Qseven carrier board
+ *
+ * Copyright (C) 2017 Renesas Electronics Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7743-iwg20m.dtsi"
+
+/ {
+	model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1M";
+	compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7743";
+
+	aliases {
+		serial0 = &scif0;
+	};
+};
+
+&scif0 {
+	status = "okay";
+};
-- 
1.9.1

[cip-dev] [PATCH 13/14] ARM: shmobile: defconfig: Enable r8a774[35] SoCs

[Biju Das]

From: Simon Horman <horms+renesas@verge.net.au>

Enable recently added r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
(cherry picked from commit d234e29dae04b224a63e39bc29938fa77819b3f1)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/configs/shmobile_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 3aef019..fb8094a 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -14,6 +14,8 @@ CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R7S72100=y
 CONFIG_ARCH_R8A73A4=y
 CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7743=y
+CONFIG_ARCH_R8A7745=y
 CONFIG_ARCH_R8A7778=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_R8A7790=y
-- 
1.9.1

[cip-dev] [PATCH 14/14] ARM: multi_v7_defconfig: Enable r8a774[35] SoCs

[Biju Das]

From: Simon Horman <horms+renesas@verge.net.au>

Enable recently added r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
(cherry picked from commit 0a2cd376019d5bfe8ddcf96a525c8dbd9b295e28)
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 arch/arm/configs/multi_v7_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index cd7b198..f1ba3fb 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -80,6 +80,8 @@ CONFIG_ARCH_EMEV2=y
 CONFIG_ARCH_R7S72100=y
 CONFIG_ARCH_R8A73A4=y
 CONFIG_ARCH_R8A7740=y
+CONFIG_ARCH_R8A7743=y
+CONFIG_ARCH_R8A7745=y
 CONFIG_ARCH_R8A7778=y
 CONFIG_ARCH_R8A7779=y
 CONFIG_ARCH_R8A7790=y
-- 
1.9.1

[cip-dev] [PATCH 00/14] Add Device tree support for iWave G20D-Q7 board

[Chris Paterson]

> From: Biju Das [mailto:biju.das at bp.renesas.com]
> Sent: 08 August 2017 10:50
> 
> This patch series aims to add initial SoC DT/Clock and iWave G20D-Q7 DT.
> 
> The clock patch is based on the similar work done on r8a7791(R-Car M2) SoC.
> 
> This series has been tested against linux-cip tag v4.4.y-cip master branch.

For the series: Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>


> 
> Biju Das (8):
>   ARM: dts: r8a7743: initial SoC device tree
>   ARM: shmobile: r8a7743: Add clock index macros for DT sources
>   clk: shmobile: Document r8a7743 CPG clock support
>   clk: shmobile: Document r8a7743 CPG DIV6 clock support
>   clk: shmobile: Document r8a7743 MSTP clock support
>   ARM: dts: r8a7743: Add clocks
>   ARM: dts: iwg20m: Add iWave RZG1M Qseven SOM
>   ARM: dts: iwg20d-q7: Add support for iWave G20D-Q7 board based on
>     RZ/G1M
> 
> Sergei Shtylyov (4):
>   ARM: dts: r8a7743: add SYS-DMAC support
>   ARM: dts: r8a7743: add [H]SCIF{A|B} support
>   ARM: dts: r8a7743: add Ether support
>   ARM: dts: r8a7743: add IRQC support
> 
> Simon Horman (2):
>   ARM: shmobile: defconfig: Enable r8a774[35] SoCs
>   ARM: multi_v7_defconfig: Enable r8a774[35] SoCs
> 
>  .../bindings/clock/renesas,cpg-div6-clocks.txt     |   1 +
>  .../bindings/clock/renesas,cpg-mstp-clocks.txt     |   1 +
>  .../clock/renesas,rcar-gen2-cpg-clocks.txt         |   1 +
>  arch/arm/boot/dts/Makefile                         |   1 +
>  arch/arm/boot/dts/r8a7743-iwg20d-q7.dts            |  25 +
>  arch/arm/boot/dts/r8a7743-iwg20m.dtsi              |  29 +
>  arch/arm/boot/dts/r8a7743.dtsi                     | 871 +++++++++++++++++++++
>  arch/arm/configs/multi_v7_defconfig                |   2 +
>  arch/arm/configs/shmobile_defconfig                |   2 +
>  include/dt-bindings/clock/r8a7743-clock.h          | 166 ++++
>  10 files changed, 1099 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
>  create mode 100644 arch/arm/boot/dts/r8a7743-iwg20m.dtsi
>  create mode 100644 arch/arm/boot/dts/r8a7743.dtsi  create mode 100644
> include/dt-bindings/clock/r8a7743-clock.h
> 
> --
> 1.9.1

[cip-dev] [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree

[Ben Hutchings]

On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
> The  initial r8A7743 SoC device tree including CPU0, GIC and timer.
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>

I compared this to the upstream version (commit
34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand why
the clocks are described differently, but can you explain why there's no
soc node?

Ben.

> ---
>  arch/arm/boot/dts/r8a7743.dtsi | 56 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 56 insertions(+)
>  create mode 100644 arch/arm/boot/dts/r8a7743.dtsi
> 
> diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
> new file mode 100644
> index 0000000..8575a2f
> --- /dev/null
> +++ b/arch/arm/boot/dts/r8a7743.dtsi
> @@ -0,0 +1,56 @@
> +/*
> + * Device Tree Source for the r8a7743 SoC
> + *
> + * Copyright (C) 2017 Renesas Electronics Corp.
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2.  This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	compatible = "renesas,r8a7743";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a15";
> +			reg = <0>;
> +			clock-frequency = <1500000000>;
> +		};
> +	};
> +
> +	gic: interrupt-controller at f1001000 {
> +		compatible = "arm,gic-400";
> +		#interrupt-cells = <3>;
> +		#address-cells = <0>;
> +		interrupt-controller;
> +		reg = <0 0xf1001000 0 0x1000>,
> +		      <0 0xf1002000 0 0x1000>,
> +		      <0 0xf1004000 0 0x2000>,
> +		      <0 0xf1006000 0 0x2000>;
> +		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
> +				   IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) |
> +				    IRQ_TYPE_LEVEL_LOW)>,
> +			     <1 14 (GIC_CPU_MASK_SIMPLE(2) |
> +				    IRQ_TYPE_LEVEL_LOW)>,
> +			     <1 11 (GIC_CPU_MASK_SIMPLE(2) |
> +				    IRQ_TYPE_LEVEL_LOW)>,
> +			     <1 10 (GIC_CPU_MASK_SIMPLE(2) |
> +				    IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +};

-- 
Ben Hutchings
Software Developer, Codethink Ltd.

[cip-dev] [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree

[Biju Das]

> -----Original Message-----
> From: Ben Hutchings [mailto:ben.hutchings at codethink.co.uk]
> Sent: 22 August 2017 19:08
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Chris Paterson <Chris.Paterson2@renesas.com>; cip-dev at lists.cip-
> project.org
> Subject: Re: [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree
>
> On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
> > The  initial r8A7743 SoC device tree including CPU0, GIC and timer.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> I compared this to the upstream version (commit
> 34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand why
> the clocks are described differently, but can you explain why there's no soc
> node?

Thanks for the comments.

RZ/G1M(r8a7743) and R-Car M2(r8a7791) are almost identical. To make consistant
with other R-Car Gen2 dtsi patches on 4.4 kernel version, I have dropped the soc node.

Do you see any issues with this approach?

> Ben.
>
> > ---
> >  arch/arm/boot/dts/r8a7743.dtsi | 56
> > ++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 56 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/r8a7743.dtsi
> >
> > diff --git a/arch/arm/boot/dts/r8a7743.dtsi
> > b/arch/arm/boot/dts/r8a7743.dtsi new file mode 100644 index
> > 0000000..8575a2f
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/r8a7743.dtsi
> > @@ -0,0 +1,56 @@
> > +/*
> > + * Device Tree Source for the r8a7743 SoC
> > + *
> > + * Copyright (C) 2017 Renesas Electronics Corp.
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > +License
> > + * version 2.  This program is licensed "as is" without any warranty
> > +of any
> > + * kind, whether express or implied.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +compatible = "renesas,r8a7743";
> > +interrupt-parent = <&gic>;
> > +#address-cells = <2>;
> > +#size-cells = <2>;
> > +
> > +cpus {
> > +#address-cells = <1>;
> > +#size-cells = <0>;
> > +
> > +cpu0: cpu at 0 {
> > +device_type = "cpu";
> > +compatible = "arm,cortex-a15";
> > +reg = <0>;
> > +clock-frequency = <1500000000>;
> > +};
> > +};
> > +
> > +gic: interrupt-controller at f1001000 {
> > +compatible = "arm,gic-400";
> > +#interrupt-cells = <3>;
> > +#address-cells = <0>;
> > +interrupt-controller;
> > +reg = <0 0xf1001000 0 0x1000>,
> > +      <0 0xf1002000 0 0x1000>,
> > +      <0 0xf1004000 0 0x2000>,
> > +      <0 0xf1006000 0 0x2000>;
> > +interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) |
> > +   IRQ_TYPE_LEVEL_HIGH)>;
> > +};
> > +
> > +timer {
> > +compatible = "arm,armv7-timer";
> > +interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) |
> > +    IRQ_TYPE_LEVEL_LOW)>,
> > +     <1 14 (GIC_CPU_MASK_SIMPLE(2) |
> > +    IRQ_TYPE_LEVEL_LOW)>,
> > +     <1 11 (GIC_CPU_MASK_SIMPLE(2) |
> > +    IRQ_TYPE_LEVEL_LOW)>,
> > +     <1 10 (GIC_CPU_MASK_SIMPLE(2) |
> > +    IRQ_TYPE_LEVEL_LOW)>;
> > +};
> > +};
>
> --
> Ben Hutchings
> Software Developer, Codethink Ltd.
>




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.

[cip-dev] [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree

[Ben Hutchings]

On Wed, 2017-08-23 at 07:36 +0000, Biju Das wrote:
> 
> 
> > -----Original Message-----
> > From: Ben Hutchings [mailto:ben.hutchings at codethink.co.uk]
> > Sent: 22 August 2017 19:08
> > To: Biju Das <biju.das@bp.renesas.com>
> > Cc: Chris Paterson <Chris.Paterson2@renesas.com>; cip-dev at lists.cip-
> > project.org
> > Subject: Re: [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree
> >
> > On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
> > > The  initial r8A7743 SoC device tree including CPU0, GIC and timer.
> > >
> > > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> >
> > I compared this to the upstream version (commit
> > 34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand why
> > the clocks are described differently, but can you explain why there's no soc
> > node?
> 
> Thanks for the comments.
> 
> RZ/G1M(r8a7743) and R-Car M2(r8a7791) are almost identical. To make consistant
> with other R-Car Gen2 dtsi patches on 4.4 kernel version, I have dropped the soc node.

But in the upstream device tree sources, r8a7743.dtsi has an soc node
and r8a7791.dtsi does not.  If it's OK for the two chips to be described
differently upstream, I don't see why they should be described
consistently here.

> Do you see any issues with this approach?
[...]

I think that consistency with upstream is more important than
consistency within the platform.  (Of course, the kernel and FDT need to
actually *work*, and if introducing the soc node gets in the way of that
then we shouldn't do it.)

Ben.

-- 
Ben Hutchings
Software Developer, Codethink Ltd.

[cip-dev] [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree

[Biju Das]

> -----Original Message-----
> From: Ben Hutchings [mailto:ben.hutchings at codethink.co.uk]
> Sent: 25 August 2017 16:41
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Chris Paterson <Chris.Paterson2@renesas.com>; cip-dev at lists.cip-
> project.org
> Subject: Re: [PATCH 01/14] ARM: dts: r8a7743: initial SoC device tree
>
> On Wed, 2017-08-23 at 07:36 +0000, Biju Das wrote:
> >
> >
> > > -----Original Message-----
> > > From: Ben Hutchings [mailto:ben.hutchings at codethink.co.uk]
> > > Sent: 22 August 2017 19:08
> > > To: Biju Das <biju.das@bp.renesas.com>
> > > Cc: Chris Paterson <Chris.Paterson2@renesas.com>; cip-dev at lists.cip-
> > > project.org
> > > Subject: Re: [PATCH 01/14] ARM: dts: r8a7743: initial SoC device
> > > tree
> > >
> > > On Tue, 2017-08-08 at 10:50 +0100, Biju Das wrote:
> > > > The  initial r8A7743 SoC device tree including CPU0, GIC and timer.
> > > >
> > > > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > >
> > > I compared this to the upstream version (commit
> > > 34e8d993a68ae459ad98c27afc07647e439deacc) and I roughly understand
> > > why the clocks are described differently, but can you explain why
> > > there's no soc node?
> >
> > Thanks for the comments.
> >
> > RZ/G1M(r8a7743) and R-Car M2(r8a7791) are almost identical. To make
> > consistant with other R-Car Gen2 dtsi patches on 4.4 kernel version, I have
> dropped the soc node.
>
> But in the upstream device tree sources, r8a7743.dtsi has an soc node and
> r8a7791.dtsi does not.  If it's OK for the two chips to be described differently
> upstream, I don't see why they should be described consistently here.
>
> > Do you see any issues with this approach?
> [...]
>
> I think that consistency with upstream is more important than consistency
> within the platform.  (Of course, the kernel and FDT need to actually *work*,
> and if introducing the soc node gets in the way of that then we shouldn't do it.)

OK. I will investigate this  and let you know.

> Ben.
>
> --
> Ben Hutchings
> Software Developer, Codethink Ltd.
>




Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.