* [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
@ 2017-08-08 15:51 Jim Bride
2017-08-08 16:12 ` ✓ Fi.CI.BAT: success for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Jim Bride @ 2017-08-08 15:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi
Bit 29 of SRD_CTL needs to have its value preserved, so right before we
write out the register we go ahead and read the register and preserve
the value of that bit before we write out the configured register value.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2546ad..ea8e421 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3872,6 +3872,7 @@ enum {
#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
#define EDP_PSR_ENABLE (1<<31)
#define BDW_PSR_SINGLE_FRAME (1<<30)
+#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX (1<<29) /* SW can't modify */
#define EDP_PSR_LINK_STANDBY (1<<27)
#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..0d08efa 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
+ val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX;
I915_WRITE(EDP_PSR_CTL, val);
}
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
2017-08-08 15:51 [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Jim Bride
@ 2017-08-08 16:12 ` Patchwork
2017-08-08 19:42 ` [PATCH] " Vivi, Rodrigo
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2017-08-08 16:12 UTC (permalink / raw)
To: Jim Bride; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
URL : https://patchwork.freedesktop.org/series/28507/
State : success
== Summary ==
Series 28507v1 drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
https://patchwork.freedesktop.org/api/1.0/series/28507/revisions/1/mbox/
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-atomic:
pass -> FAIL (fi-snb-2600) fdo#100215
fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:440s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:415s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:359s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:496s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:480s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:527s
fi-byt-n2820 total:279 pass:250 dwarn:1 dfail:0 fail:0 skip:28 time:511s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:588s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:430s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:405s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:421s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:505s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:478s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:459s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:563s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:575s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:529s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:443s
fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:651s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:458s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:424s
fi-skl-x1585l total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:486s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:549s
fi-snb-2600 total:279 pass:249 dwarn:0 dfail:0 fail:1 skip:29 time:409s
b7a69d408ccdcc8d4976baa3fc4b6dcdc5c21c8b drm-tip: 2017y-08m-08d-13h-56m-35s UTC integration manifest
d7b727d4219b drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5343/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
2017-08-08 15:51 [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Jim Bride
2017-08-08 16:12 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-08-08 19:42 ` Vivi, Rodrigo
2017-08-08 20:45 ` Jim Bride
2017-08-08 21:51 ` [PATCH v2] " Jim Bride
2017-08-08 22:12 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init (rev2) Patchwork
3 siblings, 1 reply; 8+ messages in thread
From: Vivi, Rodrigo @ 2017-08-08 19:42 UTC (permalink / raw)
To: jim.bride; +Cc: Nikula, Jani, intel-gfx
On Tue, 2017-08-08 at 08:51 -0700, Jim Bride wrote:
> Bit 29 of SRD_CTL needs to have its value preserved,
probably good to kind of quote spec somehow:
"This field is used for hardware communication. Software must not
change this field."
> so right before we
> write out the register we go ahead and read the register and preserve
> the value of that bit before we write out the configured register value.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b2546ad..ea8e421 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3872,6 +3872,7 @@ enum {
> #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
> #define EDP_PSR_ENABLE (1<<31)
> #define BDW_PSR_SINGLE_FRAME (1<<30)
> +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX (1<<29) /* SW can't modify */
- please use real tabs instead of spaces.
- a MASK on the name is better since we are not using this define to set
the bit, but to mask instead.
> #define EDP_PSR_LINK_STANDBY (1<<27)
> #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
> #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 559f1ab..0d08efa 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
> else
> val |= EDP_PSR_TP1_TP2_SEL;
>
I wondered if we should add an extra comment here, but I believe it is
not necessary if we have the "_MASK" on the bit name.
> + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX;
> I915_WRITE(EDP_PSR_CTL, val);
> }
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
2017-08-08 19:42 ` [PATCH] " Vivi, Rodrigo
@ 2017-08-08 20:45 ` Jim Bride
0 siblings, 0 replies; 8+ messages in thread
From: Jim Bride @ 2017-08-08 20:45 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: Nikula, Jani, intel-gfx
On Tue, Aug 08, 2017 at 07:42:50PM +0000, Vivi, Rodrigo wrote:
> On Tue, 2017-08-08 at 08:51 -0700, Jim Bride wrote:
> > Bit 29 of SRD_CTL needs to have its value preserved,
>
> probably good to kind of quote spec somehow:
> "This field is used for hardware communication. Software must not
> change this field."
Added "according to the B-Spec" after the word preserved.
>
> > so right before we
> > write out the register we go ahead and read the register and preserve
> > the value of that bit before we write out the configured register value.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_psr.c | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b2546ad..ea8e421 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3872,6 +3872,7 @@ enum {
> > #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
> > #define EDP_PSR_ENABLE (1<<31)
> > #define BDW_PSR_SINGLE_FRAME (1<<30)
> > +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX (1<<29) /* SW can't modify */
>
> - please use real tabs instead of spaces.
Not sure what happened there, but fixed.
>
> - a MASK on the name is better since we are not using this define to set
> the bit, but to mask instead.
Changed as per suggesation.
> > #define EDP_PSR_LINK_STANDBY (1<<27)
> > #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
> > #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> > index 559f1ab..0d08efa 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
> > else
> > val |= EDP_PSR_TP1_TP2_SEL;
> >
>
> I wondered if we should add an extra comment here, but I believe it is
> not necessary if we have the "_MASK" on the bit name.
I think it would be redundant with the comment in i915_reg.h, which I
believe to be a better place for the note. In any event, a new version
of the patch is coming with the above changes once I smoke-test
everything again.
Jim
> > + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX;
> > I915_WRITE(EDP_PSR_CTL, val);
> > }
> >
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
2017-08-08 15:51 [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Jim Bride
2017-08-08 16:12 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-08 19:42 ` [PATCH] " Vivi, Rodrigo
@ 2017-08-08 21:51 ` Jim Bride
2017-08-09 17:37 ` Rodrigo Vivi
2017-08-08 22:12 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init (rev2) Patchwork
3 siblings, 1 reply; 8+ messages in thread
From: Jim Bride @ 2017-08-08 21:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula, Rodrigo Vivi
Bit 29 of SRD_CTL needs to have its value preserved according to the
B-Spec, so right before we write out the register we go ahead and read
the register and preserve the value of that bit before we write out
the configured register value.
v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_psr.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b2546ad..56df86e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3872,6 +3872,7 @@ enum {
#define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
#define EDP_PSR_ENABLE (1<<31)
#define BDW_PSR_SINGLE_FRAME (1<<30)
+#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
#define EDP_PSR_LINK_STANDBY (1<<27)
#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 559f1ab..1b31ab0 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
else
val |= EDP_PSR_TP1_TP2_SEL;
+ val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
I915_WRITE(EDP_PSR_CTL, val);
}
--
2.7.4
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init (rev2)
2017-08-08 15:51 [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Jim Bride
` (2 preceding siblings ...)
2017-08-08 21:51 ` [PATCH v2] " Jim Bride
@ 2017-08-08 22:12 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2017-08-08 22:12 UTC (permalink / raw)
To: Jim Bride; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init (rev2)
URL : https://patchwork.freedesktop.org/series/28507/
State : success
== Summary ==
Series 28507v2 drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
https://patchwork.freedesktop.org/api/1.0/series/28507/revisions/2/mbox/
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
dmesg-warn -> PASS (fi-byt-n2820) fdo#101705
fdo#101705 https://bugs.freedesktop.org/show_bug.cgi?id=101705
fi-bdw-5557u total:279 pass:268 dwarn:0 dfail:0 fail:0 skip:11 time:436s
fi-bdw-gvtdvm total:279 pass:265 dwarn:0 dfail:0 fail:0 skip:14 time:428s
fi-blb-e6850 total:279 pass:224 dwarn:1 dfail:0 fail:0 skip:54 time:359s
fi-bsw-n3050 total:279 pass:243 dwarn:0 dfail:0 fail:0 skip:36 time:499s
fi-bxt-j4205 total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:498s
fi-byt-j1900 total:279 pass:254 dwarn:1 dfail:0 fail:0 skip:24 time:523s
fi-byt-n2820 total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:508s
fi-glk-2a total:279 pass:260 dwarn:0 dfail:0 fail:0 skip:19 time:588s
fi-hsw-4770 total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:431s
fi-hsw-4770r total:279 pass:263 dwarn:0 dfail:0 fail:0 skip:16 time:404s
fi-ilk-650 total:279 pass:229 dwarn:0 dfail:0 fail:0 skip:50 time:425s
fi-ivb-3520m total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:510s
fi-ivb-3770 total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:484s
fi-kbl-7500u total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:457s
fi-kbl-7560u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:570s
fi-kbl-r total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:578s
fi-pnv-d510 total:279 pass:223 dwarn:1 dfail:0 fail:0 skip:55 time:523s
fi-skl-6260u total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:451s
fi-skl-6700k total:279 pass:261 dwarn:0 dfail:0 fail:0 skip:18 time:643s
fi-skl-6770hq total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:464s
fi-skl-gvtdvm total:279 pass:266 dwarn:0 dfail:0 fail:0 skip:13 time:428s
fi-skl-x1585l total:279 pass:269 dwarn:0 dfail:0 fail:0 skip:10 time:499s
fi-snb-2520m total:279 pass:251 dwarn:0 dfail:0 fail:0 skip:28 time:559s
fi-snb-2600 total:279 pass:250 dwarn:0 dfail:0 fail:0 skip:29 time:405s
e2586470ba9f468a2f72b1619d79aa1d510c45a7 drm-tip: 2017y-08m-08d-20h-39m-09s UTC integration manifest
e08ae0378dfb drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5346/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
2017-08-08 21:51 ` [PATCH v2] " Jim Bride
@ 2017-08-09 17:37 ` Rodrigo Vivi
2017-08-09 17:50 ` Rodrigo Vivi
0 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Vivi @ 2017-08-09 17:37 UTC (permalink / raw)
To: Jim Bride; +Cc: Jani Nikula, intel-gfx, Rodrigo Vivi
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
On Tue, Aug 8, 2017 at 2:51 PM, Jim Bride <jim.bride@linux.intel.com> wrote:
> Bit 29 of SRD_CTL needs to have its value preserved according to the
> B-Spec, so right before we write out the register we go ahead and read
> the register and preserve the value of that bit before we write out
> the configured register value.
>
> v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_psr.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b2546ad..56df86e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3872,6 +3872,7 @@ enum {
> #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
> #define EDP_PSR_ENABLE (1<<31)
> #define BDW_PSR_SINGLE_FRAME (1<<30)
> +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
> #define EDP_PSR_LINK_STANDBY (1<<27)
> #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
> #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 559f1ab..1b31ab0 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
> else
> val |= EDP_PSR_TP1_TP2_SEL;
>
> + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
> I915_WRITE(EDP_PSR_CTL, val);
> }
>
> --
> 2.7.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
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* Re: [PATCH v2] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init
2017-08-09 17:37 ` Rodrigo Vivi
@ 2017-08-09 17:50 ` Rodrigo Vivi
0 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2017-08-09 17:50 UTC (permalink / raw)
To: Jim Bride; +Cc: Jani Nikula, intel-gfx, Rodrigo Vivi
merged to dinq.
Thanks for the patch and reviews
On Wed, Aug 9, 2017 at 10:37 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> On Tue, Aug 8, 2017 at 2:51 PM, Jim Bride <jim.bride@linux.intel.com> wrote:
>> Bit 29 of SRD_CTL needs to have its value preserved according to the
>> B-Spec, so right before we write out the register we go ahead and read
>> the register and preserve the value of that bit before we write out
>> the configured register value.
>>
>> v2: Spaces => tabs, minor name change, and commit message wording (Rodrigo)
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_psr.c | 1 +
>> 2 files changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index b2546ad..56df86e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3872,6 +3872,7 @@ enum {
>> #define EDP_PSR_CTL _MMIO(dev_priv->psr_mmio_base + 0)
>> #define EDP_PSR_ENABLE (1<<31)
>> #define BDW_PSR_SINGLE_FRAME (1<<30)
>> +#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1<<29) /* SW can't modify */
>> #define EDP_PSR_LINK_STANDBY (1<<27)
>> #define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
>> #define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 559f1ab..1b31ab0 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -315,6 +315,7 @@ static void intel_enable_source_psr1(struct intel_dp *intel_dp)
>> else
>> val |= EDP_PSR_TP1_TP2_SEL;
>>
>> + val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
>> I915_WRITE(EDP_PSR_CTL, val);
>> }
>>
>> --
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-08-09 17:50 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-08 15:51 [PATCH] drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init Jim Bride
2017-08-08 16:12 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-08 19:42 ` [PATCH] " Vivi, Rodrigo
2017-08-08 20:45 ` Jim Bride
2017-08-08 21:51 ` [PATCH v2] " Jim Bride
2017-08-09 17:37 ` Rodrigo Vivi
2017-08-09 17:50 ` Rodrigo Vivi
2017-08-08 22:12 ` ✓ Fi.CI.BAT: success for drm/i915/psr: Preserve SRD_CTL bit 29 on PSR init (rev2) Patchwork
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