* [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc
@ 2017-08-09 10:23 Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 2/8] drm/i915/guc: Handle GuC interaction in reset/suspend scenarios Sagar Arun Kamble
` (6 more replies)
0 siblings, 7 replies; 12+ messages in thread
From: Sagar Arun Kamble @ 2017-08-09 10:23 UTC (permalink / raw)
To: intel-gfx
Removed unnecessary intel_uc.h includes as it is present in i915_drv.h.
Created intel_guc.c and intel_guc.h for placing GuC specific code.
Created intel_huc.h to refer to HuC specific functions.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/i915_drv.c | 1 -
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_guc_submission.c | 1 -
drivers/gpu/drm/i915/intel_guc.c | 184 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_guc.h | 203 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_guc_loader.c | 1 -
drivers/gpu/drm/i915/intel_huc.c | 2 -
drivers/gpu/drm/i915/intel_huc.h | 38 ++++++
drivers/gpu/drm/i915/intel_uc.c | 159 +---------------------
drivers/gpu/drm/i915/intel_uc.h | 178 -------------------------
11 files changed, 430 insertions(+), 341 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_guc.c
create mode 100644 drivers/gpu/drm/i915/intel_guc.h
create mode 100644 drivers/gpu/drm/i915/intel_huc.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f822731..efa7605 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -58,6 +58,8 @@ i915-y += i915_cmd_parser.o \
# general-purpose microcontroller (GuC) support
i915-y += intel_uc.o \
+ intel_guc.o \
+ intel_huc.o \
intel_guc_ct.o \
intel_guc_log.o \
intel_guc_loader.o \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 214555e..5512cce 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -50,7 +50,6 @@
#include "i915_trace.h"
#include "i915_vgpu.h"
#include "intel_drv.h"
-#include "intel_uc.h"
static struct drm_driver driver;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2c7456f..085647a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -59,6 +59,8 @@
#include "intel_bios.h"
#include "intel_dpll_mgr.h"
#include "intel_uc.h"
+#include "intel_guc.h"
+#include "intel_huc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 48a1e93..602ae8a 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -23,7 +23,6 @@
*/
#include <linux/circ_buf.h>
#include "i915_drv.h"
-#include "intel_uc.h"
#include <trace/events/dma_fence.h>
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
new file mode 100644
index 0000000..a812d3d
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include "i915_drv.h"
+
+inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
+{
+ GEM_BUG_ON(!guc->send_regs.base);
+ GEM_BUG_ON(!guc->send_regs.count);
+ GEM_BUG_ON(i >= guc->send_regs.count);
+
+ return _MMIO(guc->send_regs.base + 4 * i);
+}
+
+void guc_capture_load_err_log(struct intel_guc *guc)
+{
+ if (!guc->log.vma || i915.guc_log_level < 0)
+ return;
+
+ if (!guc->load_err_log)
+ guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
+}
+
+void guc_free_load_err_log(struct intel_guc *guc)
+{
+ if (guc->load_err_log)
+ i915_gem_object_put(guc->load_err_log);
+}
+
+static void guc_init_send_regs(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ enum forcewake_domains fw_domains = 0;
+ unsigned int i;
+
+ guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
+ guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
+
+ for (i = 0; i < guc->send_regs.count; i++) {
+ fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
+ guc_send_reg(guc, i),
+ FW_REG_READ | FW_REG_WRITE);
+ }
+ guc->send_regs.fw_domains = fw_domains;
+}
+
+int guc_enable_communication(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ guc_init_send_regs(guc);
+
+ if (HAS_GUC_CT(dev_priv))
+ return intel_guc_enable_ct(guc);
+
+ guc->send = intel_guc_send_mmio;
+ return 0;
+}
+
+void guc_disable_communication(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ if (HAS_GUC_CT(dev_priv))
+ intel_guc_disable_ct(guc);
+
+ guc->send = intel_guc_send_nop;
+}
+
+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
+{
+ WARN(1, "Unexpected send: action=%#x\n", *action);
+ return -ENODEV;
+}
+
+/*
+ * This function implements the MMIO based host to GuC interface.
+ */
+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ u32 status;
+ int i;
+ int ret;
+
+ GEM_BUG_ON(!len);
+ GEM_BUG_ON(len > guc->send_regs.count);
+
+ /* If CT is available, we expect to use MMIO only during init/fini */
+ GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
+ *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
+ *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
+
+ mutex_lock(&guc->send_mutex);
+ intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
+
+ for (i = 0; i < len; i++)
+ I915_WRITE(guc_send_reg(guc, i), action[i]);
+
+ POSTING_READ(guc_send_reg(guc, i - 1));
+
+ intel_guc_notify(guc);
+
+ /*
+ * No GuC command should ever take longer than 10ms.
+ * Fast commands should still complete in 10us.
+ */
+ ret = __intel_wait_for_register_fw(dev_priv,
+ guc_send_reg(guc, 0),
+ INTEL_GUC_RECV_MASK,
+ INTEL_GUC_RECV_MASK,
+ 10, 10, &status);
+ if (status != INTEL_GUC_STATUS_SUCCESS) {
+ /*
+ * Either the GuC explicitly returned an error (which
+ * we convert to -EIO here) or no response at all was
+ * received within the timeout limit (-ETIMEDOUT)
+ */
+ if (ret != -ETIMEDOUT)
+ ret = -EIO;
+
+ DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
+ " ret=%d status=0x%08X response=0x%08X\n",
+ action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
+ }
+
+ intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
+ mutex_unlock(&guc->send_mutex);
+
+ return ret;
+}
+
+int intel_guc_sample_forcewake(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ u32 action[2];
+
+ action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
+ /* WaRsDisableCoarsePowerGating:skl,bxt */
+ if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
+ action[1] = 0;
+ else
+ /* bit 0 and 1 are for Render and Media domain separately */
+ action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
+
+ return intel_guc_send(guc, action, ARRAY_SIZE(action));
+}
+
+static void guc_write_irq_trigger(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
+}
+
+void intel_guc_init_early(struct intel_guc *guc)
+{
+ intel_guc_ct_init_early(&guc->ct);
+
+ mutex_init(&guc->send_mutex);
+ guc->send = intel_guc_send_nop;
+ guc->notify = guc_write_irq_trigger;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
new file mode 100644
index 0000000..f29f8ce
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_GUC_H_
+#define _INTEL_GUC_H_
+
+#include "intel_guc_fwif.h"
+#include "i915_guc_reg.h"
+#include "intel_ringbuffer.h"
+#include "intel_guc_ct.h"
+#include "i915_vma.h"
+
+struct drm_i915_gem_request;
+
+/*
+ * This structure primarily describes the GEM object shared with the GuC.
+ * The specs sometimes refer to this object as a "GuC context", but we use
+ * the term "client" to avoid confusion with hardware contexts. This
+ * GEM object is held for the entire lifetime of our interaction with
+ * the GuC, being allocated before the GuC is loaded with its firmware.
+ * Because there's no way to update the address used by the GuC after
+ * initialisation, the shared object must stay pinned into the GGTT as
+ * long as the GuC is in use. We also keep the first page (only) mapped
+ * into kernel address space, as it includes shared data that must be
+ * updated on every request submission.
+ *
+ * The single GEM object described here is actually made up of several
+ * separate areas, as far as the GuC is concerned. The first page (kept
+ * kmap'd) includes the "process descriptor" which holds sequence data for
+ * the doorbell, and one cacheline which actually *is* the doorbell; a
+ * write to this will "ring the doorbell" (i.e. send an interrupt to the
+ * GuC). The subsequent pages of the client object constitute the work
+ * queue (a circular array of work items), again described in the process
+ * descriptor. Work queue pages are mapped momentarily as required.
+ *
+ * We also keep a few statistics on failures. Ideally, these should all
+ * be zero!
+ * no_wq_space: times that the submission pre-check found no space was
+ * available in the work queue (note, the queue is shared,
+ * not per-engine). It is OK for this to be nonzero, but
+ * it should not be huge!
+ * b_fail: failed to ring the doorbell. This should never happen, unless
+ * somehow the hardware misbehaves, or maybe if the GuC firmware
+ * crashes? We probably need to reset the GPU to recover.
+ * retcode: errno from last guc_submit()
+ */
+struct i915_guc_client {
+ struct i915_vma *vma;
+ void *vaddr;
+ struct i915_gem_context *owner;
+ struct intel_guc *guc;
+
+ uint32_t engines; /* bitmap of (host) engine ids */
+ uint32_t priority;
+ u32 stage_id;
+ uint32_t proc_desc_offset;
+
+ u16 doorbell_id;
+ unsigned long doorbell_offset;
+ u32 doorbell_cookie;
+
+ spinlock_t wq_lock;
+ uint32_t wq_offset;
+ uint32_t wq_size;
+ uint32_t wq_tail;
+ uint32_t wq_rsvd;
+ uint32_t no_wq_space;
+
+ /* Per-engine counts of GuC submissions */
+ uint64_t submissions[I915_NUM_ENGINES];
+};
+
+struct intel_guc_log {
+ uint32_t flags;
+ struct i915_vma *vma;
+ /* The runtime stuff gets created only when GuC logging gets enabled */
+ struct {
+ void *buf_addr;
+ struct workqueue_struct *flush_wq;
+ struct work_struct flush_work;
+ struct rchan *relay_chan;
+ } runtime;
+ /* logging related stats */
+ u32 capture_miss_count;
+ u32 flush_interrupt_count;
+ u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
+ u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
+ u32 flush_count[GUC_MAX_LOG_BUFFER];
+};
+
+struct intel_guc {
+ struct intel_uc_fw fw;
+ struct intel_guc_log log;
+ struct intel_guc_ct ct;
+
+ /* Log snapshot if GuC errors during load */
+ struct drm_i915_gem_object *load_err_log;
+
+ /* intel_guc_recv interrupt related state */
+ bool interrupts_enabled;
+
+ struct i915_vma *ads_vma;
+ struct i915_vma *stage_desc_pool;
+ void *stage_desc_pool_vaddr;
+ struct ida stage_ids;
+
+ struct i915_guc_client *execbuf_client;
+
+ DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
+ uint32_t db_cacheline; /* Cyclic counter mod pagesize */
+
+ /* GuC's FW specific registers used in MMIO send */
+ struct {
+ u32 base;
+ unsigned int count;
+ enum forcewake_domains fw_domains;
+ } send_regs;
+
+ /* To serialize the intel_guc_send actions */
+ struct mutex send_mutex;
+
+ /* GuC's FW specific send function */
+ int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
+
+ /* GuC's FW specific notify function */
+ void (*notify)(struct intel_guc *guc);
+};
+
+/* intel_guc.c */
+inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i);
+void guc_capture_load_err_log(struct intel_guc *guc);
+void guc_free_load_err_log(struct intel_guc *guc);
+int guc_enable_communication(struct intel_guc *guc);
+void guc_disable_communication(struct intel_guc *guc);
+void intel_guc_init_early(struct intel_guc *guc);
+int intel_guc_sample_forcewake(struct intel_guc *guc);
+int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
+int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
+
+static inline int intel_guc_send(struct intel_guc *guc, const u32 *action,
+ u32 len)
+{
+ return guc->send(guc, action, len);
+}
+
+static inline void intel_guc_notify(struct intel_guc *guc)
+{
+ guc->notify(guc);
+}
+
+/* intel_guc_loader.c */
+int intel_guc_select_fw(struct intel_guc *guc);
+int intel_guc_init_hw(struct intel_guc *guc);
+int intel_guc_suspend(struct drm_i915_private *dev_priv);
+int intel_guc_resume(struct drm_i915_private *dev_priv);
+u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
+
+/* i915_guc_submission.c */
+int i915_guc_submission_init(struct drm_i915_private *dev_priv);
+int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
+int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
+void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
+void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
+void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
+struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
+
+/* intel_guc_log.c */
+int intel_guc_log_create(struct intel_guc *guc);
+void intel_guc_log_destroy(struct intel_guc *guc);
+int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
+void i915_guc_log_register(struct drm_i915_private *dev_priv);
+void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
+
+static inline u32 guc_ggtt_offset(struct i915_vma *vma)
+{
+ u32 offset = i915_ggtt_offset(vma);
+
+ GEM_BUG_ON(offset < GUC_WOPCM_TOP);
+ GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
+ return offset;
+}
+
+#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8b0ae7f..81e03a6 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -27,7 +27,6 @@
* Alex Dai <yu.dai@intel.com>
*/
#include "i915_drv.h"
-#include "intel_uc.h"
/**
* DOC: GuC-specific firmware loader
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 6145fa0..8db3d5a 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -21,9 +21,7 @@
* IN THE SOFTWARE.
*
*/
-#include <linux/firmware.h>
#include "i915_drv.h"
-#include "intel_uc.h"
/**
* DOC: HuC Firmware
diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
new file mode 100644
index 0000000..4c46857
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_huc.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#ifndef _INTEL_HUC_H_
+#define _INTEL_HUC_H_
+
+struct intel_huc {
+ /* Generic uC firmware management */
+ struct intel_uc_fw fw;
+
+ /* HuC-specific additions */
+};
+
+/* intel_huc.c */
+void intel_huc_select_fw(struct intel_huc *huc);
+void intel_huc_init_hw(struct intel_huc *huc);
+void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
+#endif
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 27e072c..95af45f 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -23,7 +23,6 @@
*/
#include "i915_drv.h"
-#include "intel_uc.h"
#include <linux/firmware.h>
/* Cleans up uC firmware by releasing the firmware GEM obj.
@@ -94,22 +93,11 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
}
-static void guc_write_irq_trigger(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
-
- I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
-}
-
void intel_uc_init_early(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
- intel_guc_ct_init_early(&guc->ct);
-
- mutex_init(&guc->send_mutex);
- guc->send = intel_guc_send_nop;
- guc->notify = guc_write_irq_trigger;
+ intel_guc_init_early(guc);
}
static void fetch_uc_fw(struct drm_i915_private *dev_priv,
@@ -262,72 +250,6 @@ void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
__intel_uc_fw_fini(&dev_priv->huc.fw);
}
-static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
-{
- GEM_BUG_ON(!guc->send_regs.base);
- GEM_BUG_ON(!guc->send_regs.count);
- GEM_BUG_ON(i >= guc->send_regs.count);
-
- return _MMIO(guc->send_regs.base + 4 * i);
-}
-
-static void guc_init_send_regs(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- enum forcewake_domains fw_domains = 0;
- unsigned int i;
-
- guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
- guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
-
- for (i = 0; i < guc->send_regs.count; i++) {
- fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
- guc_send_reg(guc, i),
- FW_REG_READ | FW_REG_WRITE);
- }
- guc->send_regs.fw_domains = fw_domains;
-}
-
-static void guc_capture_load_err_log(struct intel_guc *guc)
-{
- if (!guc->log.vma || i915.guc_log_level < 0)
- return;
-
- if (!guc->load_err_log)
- guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
-
- return;
-}
-
-static void guc_free_load_err_log(struct intel_guc *guc)
-{
- if (guc->load_err_log)
- i915_gem_object_put(guc->load_err_log);
-}
-
-static int guc_enable_communication(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
-
- guc_init_send_regs(guc);
-
- if (HAS_GUC_CT(dev_priv))
- return intel_guc_enable_ct(guc);
-
- guc->send = intel_guc_send_mmio;
- return 0;
-}
-
-static void guc_disable_communication(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
-
- if (HAS_GUC_CT(dev_priv))
- intel_guc_disable_ct(guc);
-
- guc->send = intel_guc_send_nop;
-}
-
int intel_uc_init_hw(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
@@ -458,82 +380,3 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
i915_ggtt_disable_guc(dev_priv);
}
-
-int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
-{
- WARN(1, "Unexpected send: action=%#x\n", *action);
- return -ENODEV;
-}
-
-/*
- * This function implements the MMIO based host to GuC interface.
- */
-int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- u32 status;
- int i;
- int ret;
-
- GEM_BUG_ON(!len);
- GEM_BUG_ON(len > guc->send_regs.count);
-
- /* If CT is available, we expect to use MMIO only during init/fini */
- GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
- *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
- *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
-
- mutex_lock(&guc->send_mutex);
- intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
-
- for (i = 0; i < len; i++)
- I915_WRITE(guc_send_reg(guc, i), action[i]);
-
- POSTING_READ(guc_send_reg(guc, i - 1));
-
- intel_guc_notify(guc);
-
- /*
- * No GuC command should ever take longer than 10ms.
- * Fast commands should still complete in 10us.
- */
- ret = __intel_wait_for_register_fw(dev_priv,
- guc_send_reg(guc, 0),
- INTEL_GUC_RECV_MASK,
- INTEL_GUC_RECV_MASK,
- 10, 10, &status);
- if (status != INTEL_GUC_STATUS_SUCCESS) {
- /*
- * Either the GuC explicitly returned an error (which
- * we convert to -EIO here) or no response at all was
- * received within the timeout limit (-ETIMEDOUT)
- */
- if (ret != -ETIMEDOUT)
- ret = -EIO;
-
- DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
- " ret=%d status=0x%08X response=0x%08X\n",
- action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
- }
-
- intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
- mutex_unlock(&guc->send_mutex);
-
- return ret;
-}
-
-int intel_guc_sample_forcewake(struct intel_guc *guc)
-{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
- u32 action[2];
-
- action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
- /* WaRsDisableCoarsePowerGating:skl,bxt */
- if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
- action[1] = 0;
- else
- /* bit 0 and 1 are for Render and Media domain separately */
- action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
-
- return intel_guc_send(guc, action, ARRAY_SIZE(action));
-}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 22ae52b..13460f8 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -24,72 +24,6 @@
#ifndef _INTEL_UC_H_
#define _INTEL_UC_H_
-#include "intel_guc_fwif.h"
-#include "i915_guc_reg.h"
-#include "intel_ringbuffer.h"
-#include "intel_guc_ct.h"
-#include "i915_vma.h"
-
-struct drm_i915_gem_request;
-
-/*
- * This structure primarily describes the GEM object shared with the GuC.
- * The specs sometimes refer to this object as a "GuC context", but we use
- * the term "client" to avoid confusion with hardware contexts. This
- * GEM object is held for the entire lifetime of our interaction with
- * the GuC, being allocated before the GuC is loaded with its firmware.
- * Because there's no way to update the address used by the GuC after
- * initialisation, the shared object must stay pinned into the GGTT as
- * long as the GuC is in use. We also keep the first page (only) mapped
- * into kernel address space, as it includes shared data that must be
- * updated on every request submission.
- *
- * The single GEM object described here is actually made up of several
- * separate areas, as far as the GuC is concerned. The first page (kept
- * kmap'd) includes the "process descriptor" which holds sequence data for
- * the doorbell, and one cacheline which actually *is* the doorbell; a
- * write to this will "ring the doorbell" (i.e. send an interrupt to the
- * GuC). The subsequent pages of the client object constitute the work
- * queue (a circular array of work items), again described in the process
- * descriptor. Work queue pages are mapped momentarily as required.
- *
- * We also keep a few statistics on failures. Ideally, these should all
- * be zero!
- * no_wq_space: times that the submission pre-check found no space was
- * available in the work queue (note, the queue is shared,
- * not per-engine). It is OK for this to be nonzero, but
- * it should not be huge!
- * b_fail: failed to ring the doorbell. This should never happen, unless
- * somehow the hardware misbehaves, or maybe if the GuC firmware
- * crashes? We probably need to reset the GPU to recover.
- * retcode: errno from last guc_submit()
- */
-struct i915_guc_client {
- struct i915_vma *vma;
- void *vaddr;
- struct i915_gem_context *owner;
- struct intel_guc *guc;
-
- uint32_t engines; /* bitmap of (host) engine ids */
- uint32_t priority;
- u32 stage_id;
- uint32_t proc_desc_offset;
-
- u16 doorbell_id;
- unsigned long doorbell_offset;
- u32 doorbell_cookie;
-
- spinlock_t wq_lock;
- uint32_t wq_offset;
- uint32_t wq_size;
- uint32_t wq_tail;
- uint32_t wq_rsvd;
- uint32_t no_wq_space;
-
- /* Per-engine counts of GuC submissions */
- uint64_t submissions[I915_NUM_ENGINES];
-};
-
enum intel_uc_fw_status {
INTEL_UC_FIRMWARE_FAIL = -1,
INTEL_UC_FIRMWARE_NONE = 0,
@@ -156,69 +90,6 @@ struct intel_uc_fw {
uint32_t ucode_offset;
};
-struct intel_guc_log {
- uint32_t flags;
- struct i915_vma *vma;
- /* The runtime stuff gets created only when GuC logging gets enabled */
- struct {
- void *buf_addr;
- struct workqueue_struct *flush_wq;
- struct work_struct flush_work;
- struct rchan *relay_chan;
- } runtime;
- /* logging related stats */
- u32 capture_miss_count;
- u32 flush_interrupt_count;
- u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
- u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
- u32 flush_count[GUC_MAX_LOG_BUFFER];
-};
-
-struct intel_guc {
- struct intel_uc_fw fw;
- struct intel_guc_log log;
- struct intel_guc_ct ct;
-
- /* Log snapshot if GuC errors during load */
- struct drm_i915_gem_object *load_err_log;
-
- /* intel_guc_recv interrupt related state */
- bool interrupts_enabled;
-
- struct i915_vma *ads_vma;
- struct i915_vma *stage_desc_pool;
- void *stage_desc_pool_vaddr;
- struct ida stage_ids;
-
- struct i915_guc_client *execbuf_client;
-
- DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
- uint32_t db_cacheline; /* Cyclic counter mod pagesize */
-
- /* GuC's FW specific registers used in MMIO send */
- struct {
- u32 base;
- unsigned int count;
- enum forcewake_domains fw_domains;
- } send_regs;
-
- /* To serialize the intel_guc_send actions */
- struct mutex send_mutex;
-
- /* GuC's FW specific send function */
- int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
-
- /* GuC's FW specific notify function */
- void (*notify)(struct intel_guc *guc);
-};
-
-struct intel_huc {
- /* Generic uC firmware management */
- struct intel_uc_fw fw;
-
- /* HuC-specific additions */
-};
-
/* intel_uc.c */
void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
void intel_uc_init_early(struct drm_i915_private *dev_priv);
@@ -226,54 +97,5 @@ struct intel_huc {
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
-int intel_guc_sample_forcewake(struct intel_guc *guc);
-int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
-int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
-
-static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
-{
- return guc->send(guc, action, len);
-}
-
-static inline void intel_guc_notify(struct intel_guc *guc)
-{
- guc->notify(guc);
-}
-
-/* intel_guc_loader.c */
-int intel_guc_select_fw(struct intel_guc *guc);
-int intel_guc_init_hw(struct intel_guc *guc);
-int intel_guc_suspend(struct drm_i915_private *dev_priv);
-int intel_guc_resume(struct drm_i915_private *dev_priv);
-u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
-
-/* i915_guc_submission.c */
-int i915_guc_submission_init(struct drm_i915_private *dev_priv);
-int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
-int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
-void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
-void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
-void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
-struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
-
-/* intel_guc_log.c */
-int intel_guc_log_create(struct intel_guc *guc);
-void intel_guc_log_destroy(struct intel_guc *guc);
-int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
-void i915_guc_log_register(struct drm_i915_private *dev_priv);
-void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
-
-static inline u32 guc_ggtt_offset(struct i915_vma *vma)
-{
- u32 offset = i915_ggtt_offset(vma);
- GEM_BUG_ON(offset < GUC_WOPCM_TOP);
- GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
- return offset;
-}
-
-/* intel_huc.c */
-void intel_huc_select_fw(struct intel_huc *huc);
-void intel_huc_init_hw(struct intel_huc *huc);
-void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
#endif
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/8] drm/i915/guc: Handle GuC interaction in reset/suspend scenarios
2017-08-09 10:23 [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Sagar Arun Kamble
@ 2017-08-09 10:23 ` Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 3/8] drm/i915/guc: Handle GuC HW/SW state cleanup in unload path Sagar Arun Kamble
` (5 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Sagar Arun Kamble @ 2017-08-09 10:23 UTC (permalink / raw)
To: intel-gfx
Tearing down of guc_ggtt_invalidate/guc_interrupts/guc_communication
setup should happen towards end of reset/suspend as these are
setup back again during recovery/resume.
Prepared helpers intel_guc_pause and intel_guc_unpause that will do
teardown/bringup of this setup along with suspension/resumption of GuC if
loaded. Moved intel_guc_suspend, intel_guc_resume to intel_guc.c.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 6 +-
drivers/gpu/drm/i915/i915_gem.c | 6 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 52 ------------
drivers/gpu/drm/i915/intel_guc.c | 131 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_guc.h | 7 +-
5 files changed, 142 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5512cce..218a8e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1688,8 +1688,6 @@ static int i915_drm_resume(struct drm_device *dev)
}
mutex_unlock(&dev->struct_mutex);
- intel_guc_resume(dev_priv);
-
intel_modeset_init_hw(dev);
spin_lock_irq(&dev_priv->irq_lock);
@@ -2484,7 +2482,7 @@ static int intel_runtime_suspend(struct device *kdev)
*/
i915_gem_runtime_suspend(dev_priv);
- intel_guc_suspend(dev_priv);
+ intel_guc_runtime_suspend(&dev_priv->guc);
intel_runtime_pm_disable_interrupts(dev_priv);
@@ -2569,7 +2567,7 @@ static int intel_runtime_resume(struct device *kdev)
if (intel_uncore_unclaimed_mmio(dev_priv))
DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
- intel_guc_resume(dev_priv);
+ intel_guc_runtime_resume(&dev_priv->guc);
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 000a764..e118b9a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2840,6 +2840,8 @@ int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
i915_gem_revoke_fences(dev_priv);
+ intel_guc_reset_prepare(&dev_priv->guc);
+
return err;
}
@@ -4555,8 +4557,6 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
i915_gem_contexts_lost(dev_priv);
mutex_unlock(&dev->struct_mutex);
- intel_guc_suspend(dev_priv);
-
cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
cancel_delayed_work_sync(&dev_priv->gt.retire_work);
@@ -4572,6 +4572,8 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
WARN_ON(dev_priv->gt.awake);
WARN_ON(!intel_engines_are_idle(dev_priv));
+ intel_guc_system_suspend(&dev_priv->guc);
+
/*
* Neither the BIOS, ourselves or any other kernel
* expects the system to be in execlists mode on startup,
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index 602ae8a..2f977ab 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -1287,55 +1287,3 @@ void i915_guc_submission_disable(struct drm_i915_private *dev_priv)
guc_client_free(guc->execbuf_client);
guc->execbuf_client = NULL;
}
-
-/**
- * intel_guc_suspend() - notify GuC entering suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_suspend(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- gen9_disable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
- /* any value greater than GUC_POWER_D0 */
- data[1] = GUC_POWER_D1;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
-
-/**
- * intel_guc_resume() - notify GuC resuming from suspend state
- * @dev_priv: i915 device private
- */
-int intel_guc_resume(struct drm_i915_private *dev_priv)
-{
- struct intel_guc *guc = &dev_priv->guc;
- struct i915_gem_context *ctx;
- u32 data[3];
-
- if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
- return 0;
-
- if (i915.guc_log_level >= 0)
- gen9_enable_guc_interrupts(dev_priv);
-
- ctx = dev_priv->kernel_context;
-
- data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
- data[1] = GUC_POWER_D0;
- /* first page is shared data with GuC */
- data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
-
- return intel_guc_send(guc, data, ARRAY_SIZE(data));
-}
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index a812d3d..3777659 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -182,3 +182,134 @@ void intel_guc_init_early(struct intel_guc *guc)
guc->send = intel_guc_send_nop;
guc->notify = guc_write_irq_trigger;
}
+
+/**
+ * intel_guc_suspend() - notify GuC entering suspend state
+ */
+static int intel_guc_suspend(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct i915_gem_context *ctx;
+ u32 data[3];
+
+ if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ return 0;
+
+ ctx = dev_priv->kernel_context;
+
+ data[0] = INTEL_GUC_ACTION_ENTER_S_STATE;
+ /* any value greater than GUC_POWER_D0 */
+ data[1] = GUC_POWER_D1;
+ /* first page is shared data with GuC */
+ data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
+
+ return intel_guc_send(guc, data, ARRAY_SIZE(data));
+}
+
+/**
+ * intel_guc_resume() - notify GuC resuming from suspend state
+ */
+static int intel_guc_resume(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct i915_gem_context *ctx;
+ u32 data[3];
+
+ if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
+ return 0;
+
+ ctx = dev_priv->kernel_context;
+
+ data[0] = INTEL_GUC_ACTION_EXIT_S_STATE;
+ data[1] = GUC_POWER_D0;
+ /* first page is shared data with GuC */
+ data[2] = guc_ggtt_offset(ctx->engine[RCS].state);
+
+ return intel_guc_send(guc, data, ARRAY_SIZE(data));
+}
+
+static void intel_guc_sanitize(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+
+ i915_ggtt_disable_guc(dev_priv);
+ guc_disable_communication(guc);
+ gen9_disable_guc_interrupts(dev_priv);
+}
+
+void intel_guc_reset_prepare(struct intel_guc *guc)
+{
+ if (!i915.enable_guc_loading)
+ return;
+
+ intel_guc_sanitize(guc);
+ guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;
+}
+
+static int intel_guc_pause(struct intel_guc *guc)
+{
+ int ret = 0;
+
+ ret = intel_guc_suspend(guc);
+ intel_guc_sanitize(guc);
+
+ return ret;
+}
+
+static int intel_guc_unpause(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ int ret = 0;
+
+ if (i915.guc_log_level >= 0)
+ gen9_enable_guc_interrupts(dev_priv);
+ guc_enable_communication(guc);
+ i915_ggtt_enable_guc(dev_priv);
+ ret = intel_guc_resume(guc);
+
+ return ret;
+}
+
+int intel_guc_runtime_suspend(struct intel_guc *guc)
+{
+ if (!i915.enable_guc_loading)
+ return 0;
+
+ return intel_guc_pause(guc);
+}
+
+int intel_guc_runtime_resume(struct intel_guc *guc)
+{
+ if (!i915.enable_guc_loading)
+ return 0;
+
+ return intel_guc_unpause(guc);
+}
+
+int intel_guc_system_suspend(struct intel_guc *guc)
+{
+ int ret = 0;
+
+ if (!i915.enable_guc_loading)
+ return ret;
+
+ ret = intel_guc_pause(guc);
+ guc->fw.load_status = INTEL_UC_FIRMWARE_PENDING;
+
+ return ret;
+}
+
+int intel_guc_system_resume(struct intel_guc *guc)
+{
+ int ret = 0;
+
+ if (!i915.enable_guc_loading)
+ return ret;
+
+ /*
+ * Placeholder for GuC resume from system suspend/freeze states.
+ * Currently full reinitialization of GEM and GuC happens along
+ * these paths, Hence this function is doing nothing.
+ */
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index f29f8ce..e9664bf 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -156,6 +156,11 @@ struct intel_guc {
int intel_guc_sample_forcewake(struct intel_guc *guc);
int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
+void intel_guc_reset_prepare(struct intel_guc *guc);
+int intel_guc_runtime_suspend(struct intel_guc *guc);
+int intel_guc_runtime_resume(struct intel_guc *guc);
+int intel_guc_system_suspend(struct intel_guc *guc);
+int intel_guc_system_resume(struct intel_guc *guc);
static inline int intel_guc_send(struct intel_guc *guc, const u32 *action,
u32 len)
@@ -171,8 +176,6 @@ static inline void intel_guc_notify(struct intel_guc *guc)
/* intel_guc_loader.c */
int intel_guc_select_fw(struct intel_guc *guc);
int intel_guc_init_hw(struct intel_guc *guc);
-int intel_guc_suspend(struct drm_i915_private *dev_priv);
-int intel_guc_resume(struct drm_i915_private *dev_priv);
u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
/* i915_guc_submission.c */
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/8] drm/i915/guc: Handle GuC HW/SW state cleanup in unload path
2017-08-09 10:23 [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 2/8] drm/i915/guc: Handle GuC interaction in reset/suspend scenarios Sagar Arun Kamble
@ 2017-08-09 10:23 ` Sagar Arun Kamble
2017-08-09 14:36 ` Michal Wajdeczko
2017-08-09 10:23 ` [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9 Sagar Arun Kamble
` (4 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Sagar Arun Kamble @ 2017-08-09 10:23 UTC (permalink / raw)
To: intel-gfx
Teardown of GuC HW/SW state was not properly done in unload path.
During unload, we can rely on intel_guc_reset_prepare being done
as part of i915_gem_suspend for disabling GuC interfaces.
We will have to disable GuC submission prior to suspend as that involves
communication with GuC to destroy doorbell. So intel_uc_fini_hw has to
be called as part of i915_gem_suspend during unload as that really
takes care of finishing the GuC operations. Created new parameter for
i915_gem_suspend to handle unload/suspend path w.r.t gem and GuC suspend.
GuC related allocations are cleaned up as part of intel_uc_cleanup_hw.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 8 ++++++--
drivers/gpu/drm/i915/intel_guc.c | 13 +++++++++++++
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_uc.c | 14 +++++---------
drivers/gpu/drm/i915/intel_uc.h | 1 +
7 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 218a8e1..c3fb73f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -599,7 +599,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
i915_gem_drain_workqueue(dev_priv);
mutex_lock(&dev_priv->drm.struct_mutex);
- intel_uc_fini_hw(dev_priv);
+ intel_uc_cleanup_hw(dev_priv);
i915_gem_cleanup_engines(dev_priv);
i915_gem_contexts_fini(dev_priv);
i915_gem_cleanup_userptr(dev_priv);
@@ -680,7 +680,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
return 0;
cleanup_gem:
- if (i915_gem_suspend(dev_priv))
+ if (i915_gem_suspend(dev_priv, true))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
i915_gem_fini(dev_priv);
cleanup_uc:
@@ -1373,7 +1373,7 @@ void i915_driver_unload(struct drm_device *dev)
i915_driver_unregister(dev_priv);
- if (i915_gem_suspend(dev_priv))
+ if (i915_gem_suspend(dev_priv, true))
DRM_ERROR("failed to idle hardware; continuing to unload!\n");
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
@@ -1518,7 +1518,7 @@ static int i915_drm_suspend(struct drm_device *dev)
pci_save_state(pdev);
- error = i915_gem_suspend(dev_priv);
+ error = i915_gem_suspend(dev_priv, false);
if (error) {
dev_err(&pdev->dev,
"GEM idle failed, resume might fail\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 085647a..dd6a3ff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3547,7 +3547,8 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
unsigned int flags);
-int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
+int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv,
+ bool unload);
void i915_gem_resume(struct drm_i915_private *dev_priv);
int i915_gem_fault(struct vm_fault *vmf);
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e118b9a..1b1b9c7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4525,7 +4525,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
}
}
-int i915_gem_suspend(struct drm_i915_private *dev_priv)
+int i915_gem_suspend(struct drm_i915_private *dev_priv, bool unload)
{
struct drm_device *dev = &dev_priv->drm;
int ret;
@@ -4572,7 +4572,11 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
WARN_ON(dev_priv->gt.awake);
WARN_ON(!intel_engines_are_idle(dev_priv));
- intel_guc_system_suspend(&dev_priv->guc);
+ /* Handle GuC suspension in case of unloading/system suspend */
+ if (unload)
+ intel_uc_fini_hw(dev_priv);
+ else
+ intel_guc_system_suspend(&dev_priv->guc);
/*
* Neither the BIOS, ourselves or any other kernel
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 3777659..f4ddfbb 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -313,3 +313,16 @@ int intel_guc_system_resume(struct intel_guc *guc)
*/
return ret;
}
+
+void intel_guc_fini(struct intel_guc *guc)
+{
+ struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_device *dev = &dev_priv->drm;
+
+ if (i915.enable_guc_submission) {
+ mutex_lock(&dev->struct_mutex);
+ i915_guc_submission_disable(dev_priv);
+ mutex_unlock(&dev->struct_mutex);
+ intel_guc_reset_prepare(&dev_priv->guc);
+ }
+}
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index e9664bf..ed3d202 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -161,6 +161,7 @@ struct intel_guc {
int intel_guc_runtime_resume(struct intel_guc *guc);
int intel_guc_system_suspend(struct intel_guc *guc);
int intel_guc_system_resume(struct intel_guc *guc);
+void intel_guc_fini(struct intel_guc *guc);
static inline int intel_guc_send(struct intel_guc *guc, const u32 *action,
u32 len)
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 95af45f..e6b9330 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -363,20 +363,16 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
{
+ intel_guc_fini(&dev_priv->guc);
+}
+
+void intel_uc_cleanup_hw(struct drm_i915_private *dev_priv)
+{
guc_free_load_err_log(&dev_priv->guc);
if (!i915.enable_guc_loading)
return;
if (i915.enable_guc_submission)
- i915_guc_submission_disable(dev_priv);
-
- guc_disable_communication(&dev_priv->guc);
-
- if (i915.enable_guc_submission) {
- gen9_disable_guc_interrupts(dev_priv);
i915_guc_submission_fini(dev_priv);
- }
-
- i915_ggtt_disable_guc(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 13460f8..bfe5639 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -97,5 +97,6 @@ struct intel_uc_fw {
void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
int intel_uc_init_hw(struct drm_i915_private *dev_priv);
void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
+void intel_uc_cleanup_hw(struct drm_i915_private *dev_priv);
#endif
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9
2017-08-09 10:23 [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 2/8] drm/i915/guc: Handle GuC interaction in reset/suspend scenarios Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 3/8] drm/i915/guc: Handle GuC HW/SW state cleanup in unload path Sagar Arun Kamble
@ 2017-08-09 10:23 ` Sagar Arun Kamble
2017-08-09 10:49 ` Chris Wilson
2017-08-09 10:23 ` [PATCH 5/8] drm/i915/guc: Change default GuC FW for SKL to v9.33 Sagar Arun Kamble
` (3 subsequent siblings)
6 siblings, 1 reply; 12+ messages in thread
From: Sagar Arun Kamble @ 2017-08-09 10:23 UTC (permalink / raw)
To: intel-gfx
From GuC v9 firmware (for KBL v9.39+), separate control is added to enable
critical logging in GuC to enable capturing minimal important logs in
production systems.
i915.guc_log_level controls the verbosity and logging in GuC for logs other
than critical logs. By default, logging in GuC is disabled through
i915.guc_log_level.
This patch introduces new kernel param i915.enable_guc_critical_logging.
For Linux release builds, if needed critical GuC logs can be enabled
separately through this parameter. GuC log snapshot captured in error state
will have these minimal critical events logged.
Default value for this parameter is currently set to false.
This patch updates the initialization parameter sent during GuC load to
disable critical logging unless i915.guc_log_level is set to enable logging
and ensures it is enabled/disabling while enabling/disabling through
debugfs based on i915.enable_guc_critical_logging.
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Spotswood John A <john.a.spotswood@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_params.c | 5 +++++
drivers/gpu/drm/i915/i915_params.h | 3 ++-
drivers/gpu/drm/i915/intel_guc_fwif.h | 14 +++++++++++++-
drivers/gpu/drm/i915/intel_guc_loader.c | 21 ++++++++++++++++++++-
drivers/gpu/drm/i915/intel_guc_log.c | 9 ++++++++-
5 files changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 14e2c2e..902bf2c 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -59,6 +59,7 @@ struct i915_params i915 __read_mostly = {
.enable_guc_loading = 0,
.enable_guc_submission = 0,
.guc_log_level = -1,
+ .enable_guc_critical_logging = false,
.guc_firmware_path = NULL,
.huc_firmware_path = NULL,
.enable_dp_mst = true,
@@ -232,6 +233,10 @@ struct i915_params i915 __read_mostly = {
MODULE_PARM_DESC(guc_log_level,
"GuC firmware logging level (-1:disabled (default), 0-3:enabled)");
+module_param_named(enable_guc_critical_logging, i915.enable_guc_critical_logging, bool, 0400);
+MODULE_PARM_DESC(enable_guc_critical_logging,
+ "Enable GuC firmware critical logging (default: false)");
+
module_param_named_unsafe(guc_firmware_path, i915.guc_firmware_path, charp, 0400);
MODULE_PARM_DESC(guc_firmware_path,
"GuC firmware path to use instead of the default one");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index febbfdb..7c208f0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -67,7 +67,8 @@
func(bool, nuclear_pageflip); \
func(bool, enable_dp_mst); \
func(bool, enable_dpcd_backlight); \
- func(bool, enable_gvt)
+ func(bool, enable_gvt); \
+ func(bool, enable_guc_critical_logging)
#define MEMBER(T, member) T member
struct i915_params {
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 5fa2860..353b081 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -132,6 +132,7 @@
#define GUC_WQ_TRACK_ENABLED (1 << 8)
#define GUC_ADS_ENABLED (1 << 9)
#define GUC_DEBUG_RESERVED (1 << 10)
+#define GUC_V9_CRITICAL_LOGGING_DISABLED (1 << 10)
#define GUC_ADS_ADDR_SHIFT 11
#define GUC_ADS_ADDR_MASK 0xfffff800
@@ -139,6 +140,16 @@
#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
+/*
+ * Critical logging in GuC is to be enabled always from GuC v9+.
+ * (for KBL - v9.39+)
+ */
+#define NEEDS_GUC_CRITICAL_LOGGING(dev_priv, guc_fw) \
+ (((IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) && \
+ guc_fw->major_ver_found >= 9) || \
+ (IS_KABYLAKE(dev_priv) && guc_fw->major_ver_found >= 9 && \
+ guc_fw->minor_ver_found >= 39))
+
/**
* DOC: GuC Firmware Layout
*
@@ -539,7 +550,8 @@ struct guc_log_buffer_state {
u32 logging_enabled:1;
u32 reserved1:3;
u32 verbosity:4;
- u32 reserved2:24;
+ u32 critical_logging_enabled:1;
+ u32 reserved2:23;
};
u32 value;
} __packed;
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 81e03a6..535c665 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -106,8 +106,10 @@ static u32 get_core_family(struct drm_i915_private *dev_priv)
static void guc_params_init(struct drm_i915_private *dev_priv)
{
struct intel_guc *guc = &dev_priv->guc;
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
u32 params[GUC_CTL_MAX_DWORDS];
int i;
+ bool enable_critical_logging = false;
memset(¶ms, 0, sizeof(params));
@@ -130,11 +132,28 @@ static void guc_params_init(struct drm_i915_private *dev_priv)
params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
+ /*
+ * Enable critical logging in GuC based on i915.guc_log_level and
+ * i915.enable_guc_critical_logging.
+ */
if (i915.guc_log_level >= 0) {
params[GUC_CTL_DEBUG] =
i915.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
- } else
+ enable_critical_logging = true;
+ } else {
params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
+ if (i915.enable_guc_critical_logging)
+ enable_critical_logging = true;
+ }
+
+ if (NEEDS_GUC_CRITICAL_LOGGING(dev_priv, guc_fw)) {
+ if (enable_critical_logging)
+ params[GUC_CTL_DEBUG] &=
+ ~GUC_V9_CRITICAL_LOGGING_DISABLED;
+ else
+ params[GUC_CTL_DEBUG] |=
+ GUC_V9_CRITICAL_LOGGING_DISABLED;
+ }
/* If GuC submission is enabled, set up additional parameters here */
if (i915.enable_guc_submission) {
diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
index 16d3b87..2f9bf79 100644
--- a/drivers/gpu/drm/i915/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/intel_guc_log.c
@@ -589,7 +589,7 @@ void intel_guc_log_destroy(struct intel_guc *guc)
int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
{
struct intel_guc *guc = &dev_priv->guc;
-
+ struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
union guc_log_control log_param;
int ret;
@@ -603,6 +603,13 @@ int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val)
if (!log_param.logging_enabled && (i915.guc_log_level < 0))
return 0;
+ if (NEEDS_GUC_CRITICAL_LOGGING(dev_priv, guc_fw)) {
+ log_param.critical_logging_enabled = 1;
+ if (!log_param.logging_enabled &&
+ !i915.enable_guc_critical_logging)
+ log_param.critical_logging_enabled = 0;
+ }
+
ret = guc_log_control(guc, log_param.value);
if (ret < 0) {
DRM_DEBUG_DRIVER("guc_logging_control action failed %d\n", ret);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/8] drm/i915/guc: Change default GuC FW for SKL to v9.33
2017-08-09 10:23 [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Sagar Arun Kamble
` (2 preceding siblings ...)
2017-08-09 10:23 ` [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9 Sagar Arun Kamble
@ 2017-08-09 10:23 ` Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 6/8] drm/i915/guc: Change default GuC FW for BXT to v9.29 Sagar Arun Kamble
` (2 subsequent siblings)
6 siblings, 0 replies; 12+ messages in thread
From: Sagar Arun Kamble @ 2017-08-09 10:23 UTC (permalink / raw)
To: intel-gfx
This patch makes v9.33 firmware as default firmware for SKL.
This update includes (since v6.1):
- HuC RSA Keys updated.
- Adding per engine preemption support in GuC scheduler
- Minor bug fixes.
- Added support to log media reset count for host to read it
- Sub-feature level control for power management features.
- Minor clean-up for power management interface.
- Unified power management interface and scheduler interface into
1 file using same version.
- Bug Fix for multi context scheduler flag.
- DCC spec changes for BXT + DCT enabling
- SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC
- Moving GuC non_critical r/w data to lower SRAM 64KB
- Media engine Reset fix. Correctly marking context for resubmission in
Media Reset case.
- ABT Disable bug fix. Disabled Evaluation mode on context change.
- Async FW in Engine Schedule feature (not enabled from KMD)
- GuC clean up to align developer build in line to production build.
- DCC consistency fix for SKL
- Disable ARAT interrupt before programming ARAT delta.
- Memory range check in Parse to avoid failure due to overflow.
- Enabled WA for MSGCH hang issue
- Clear forcewake in CSB when SQ is empty.
- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder.
- This is file location change.No functional change done as part of this
check in.
- Enable decoupled freq for SKL GT4
- 3 tries of wake request needed from GuC2CSME for ME to wake up. Request
has come from ME spec
- During reset one parameter was not getting accounted
- Enabling Guc Log changes for ultra low logging for OCA
- Enabling build failure check to catch critical section overflow.
- Disable build.bat redundant prints.
- Move few least used functions to non-critical section.
- Rearrange GuC documentation folder structure.
- Synchronize SLPC internal debug interface with other branches.
- Fixing Issue with Default Guc Log changes for OCA using special Control
Bit
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Spotswood John A <john.a.spotswood@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 535c665..b704193 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -51,8 +51,8 @@
*
*/
-#define SKL_FW_MAJOR 6
-#define SKL_FW_MINOR 1
+#define SKL_FW_MAJOR 9
+#define SKL_FW_MINOR 33
#define BXT_FW_MAJOR 8
#define BXT_FW_MINOR 7
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/8] drm/i915/guc: Change default GuC FW for BXT to v9.29
2017-08-09 10:23 [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Sagar Arun Kamble
` (3 preceding siblings ...)
2017-08-09 10:23 ` [PATCH 5/8] drm/i915/guc: Change default GuC FW for SKL to v9.33 Sagar Arun Kamble
@ 2017-08-09 10:23 ` Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 7/8] drm/i915/guc: Change default GuC FW for KBL to v9.39 Sagar Arun Kamble
2017-08-09 13:58 ` [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Michal Wajdeczko
6 siblings, 0 replies; 12+ messages in thread
From: Sagar Arun Kamble @ 2017-08-09 10:23 UTC (permalink / raw)
To: intel-gfx
This patch makes v9.29 firmware as default firmware for BXT.
This update includes (since v8.7):
- Added support to log media reset count for host to read it
- BXT WA for fixing MTP hangs. WaDisableDOPRenderClkGatingAtSubmit
- Sub-feature level control for power management features.
- Minor clean-up for power management interface.
- Unified power management interface and scheduler interface into
1 file using same version.
- Bug Fix for multi context scheduler flag.
- DCC spec changes for BXT + DCT enabling
- Springboard based Pre-ETM/ETM flow enabling for debug signed GuC/HuC
- Moving GuC non_critical r/w data to lower SRAM 64KB
- Enabled IBC for BXT
- Media engine Reset fix. Correctly marking context for resubmission in
Media Reset case.
- SLPC Dynamic RPe fix to resolve issues where incorrect frequency was set.
- ABT Disable bug fix. Disabled Evaluation mode on context change.
- GuC clean up to align developer build in line to production build.
- Disable ARAT interrupt before programming ARAT delta.
- Memory range check in Parse to avoid failure due to overflow.
- Clear forcewake in CSB when SQ is empty.
- SLPC IBC 1.6 for APL to ensure multiplier does not cap IA below Pe.
- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder.
- This is file location change. No functional change done as part of this
check in.
- 3 tries of wake request needed from GuC2CSME for ME to wake up. Request
has come from ME spec
- During reset one parameter was not getting accounted
- Enabling Guc Log changes for ultra low logging for OCA
- Disable build.bat redundant prints.
- Move few least used functions to non-critical section.
- Rearrange GuC documentation folder structure.
- Fixing Issue with Default Guc Log changes for OCA using special Control
Bit
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Spotswood John A <john.a.spotswood@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_guc_loader.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index b704193..9a41386 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -54,8 +54,8 @@
#define SKL_FW_MAJOR 9
#define SKL_FW_MINOR 33
-#define BXT_FW_MAJOR 8
-#define BXT_FW_MINOR 7
+#define BXT_FW_MAJOR 9
+#define BXT_FW_MINOR 29
#define KBL_FW_MAJOR 9
#define KBL_FW_MINOR 14
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 7/8] drm/i915/guc: Change default GuC FW for KBL to v9.39
2017-08-09 10:23 [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Sagar Arun Kamble
` (4 preceding siblings ...)
2017-08-09 10:23 ` [PATCH 6/8] drm/i915/guc: Change default GuC FW for BXT to v9.29 Sagar Arun Kamble
@ 2017-08-09 10:23 ` Sagar Arun Kamble
2017-08-09 13:58 ` [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Michal Wajdeczko
6 siblings, 0 replies; 12+ messages in thread
From: Sagar Arun Kamble @ 2017-08-09 10:23 UTC (permalink / raw)
To: intel-gfx
This patch makes v9.39 firmware as default firmware for KBL.
This update includes (since v9.14):
- DCC spec changes for BXT + DCT enabling
- Bug Fix for power conservation feature SLPC_DCC
- Scheduler 1-element submission during DCC cycles.
- SB based Pre-ETM/ETM flow enabling for debug signed GuC/HuC
- Moving GuC non_critical r/w data to lower SRAM 64KB
- Media engine Reset fix. Correctly marking context for resubmission in
Media Reset case.
- ABT Disable bug fix. Disabled Evaluation mode on context change.
- Async FW in Engine Schedule feature (not enabled from KMD)
- GuC clean up to align developer build in line to production build.
- Disable ARAT interrupt before programming ARAT delta.
- Memory range check in Parse to avoid failure due to overflow.
- GuC Msg Channel Hang WA - Stall GUC for mmio access when IDI is low
during CPD flow.
- Fix for submit queue over flow issue
- Enabling IBC on KBL GT3 15W, GT4 45W
- Disabling wrong device ID WA in production signed kernel
- Enabling WA for MSGCH hang issue upto required KBL stepping
- Clear forcewake in CSB when SQ is empty.
- 3Tries of GuC2CSME wake request
- During reset one parameter was not getting accounted
- Disable DCC 1-elem mode submission
- Move UkGuckmdInterface.h file from 2016 folders to common 2016 folder.
- This is file location change.No functional change done as part of this
check in.
- Enabling Guc Log changes for ultra low logging for OCA
- Enabling Dynamic Render Power Well Hysteresis Programming for Compute
Worklaods
- Enabling build failure check to catch critical section overflow.
- Disable build.bat redundant prints.
- Move few least used functions to non-critical section.
- Rearrange GuC documentation folder structure.
- Synchronize SLPC internal debug interface with other branches.
- Fixing Issue with Default Guc Log changes for OCA using special Control
Bit
- Aggressive DCC implementation for supported platforms.
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Spotswood John A <john.a.spotswood@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/intel_guc_loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 9a41386..05696f2 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -58,7 +58,7 @@
#define BXT_FW_MINOR 29
#define KBL_FW_MAJOR 9
-#define KBL_FW_MINOR 14
+#define KBL_FW_MINOR 39
#define GLK_FW_MAJOR 10
#define GLK_FW_MINOR 56
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9
2017-08-09 10:23 ` [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9 Sagar Arun Kamble
@ 2017-08-09 10:49 ` Chris Wilson
2017-08-14 10:45 ` Kamble, Sagar A
0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2017-08-09 10:49 UTC (permalink / raw)
To: Sagar Arun Kamble, intel-gfx
Quoting Sagar Arun Kamble (2017-08-09 11:23:48)
> From GuC v9 firmware (for KBL v9.39+), separate control is added to enable
> critical logging in GuC to enable capturing minimal important logs in
> production systems.
> i915.guc_log_level controls the verbosity and logging in GuC for logs other
> than critical logs. By default, logging in GuC is disabled through
> i915.guc_log_level.
> This patch introduces new kernel param i915.enable_guc_critical_logging.
> For Linux release builds, if needed critical GuC logs can be enabled
> separately through this parameter. GuC log snapshot captured in error state
> will have these minimal critical events logged.
> Default value for this parameter is currently set to false.
> This patch updates the initialization parameter sent during GuC load to
> disable critical logging unless i915.guc_log_level is set to enable logging
> and ensures it is enabled/disabling while enabling/disabling through
> debugfs based on i915.enable_guc_critical_logging.
>
> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Spotswood John A <john.a.spotswood@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 +++++
> drivers/gpu/drm/i915/i915_params.h | 3 ++-
> drivers/gpu/drm/i915/intel_guc_fwif.h | 14 +++++++++++++-
> drivers/gpu/drm/i915/intel_guc_loader.c | 21 ++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_guc_log.c | 9 ++++++++-
> 5 files changed, 48 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 14e2c2e..902bf2c 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -59,6 +59,7 @@ struct i915_params i915 __read_mostly = {
> .enable_guc_loading = 0,
> .enable_guc_submission = 0,
> .guc_log_level = -1,
> + .enable_guc_critical_logging = false,
What's the point in having a log level if LOG_LEVEL_CRITICAL is not part
of it? Please do explain why the current parameter does not cover this.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc
2017-08-09 10:23 [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Sagar Arun Kamble
` (5 preceding siblings ...)
2017-08-09 10:23 ` [PATCH 7/8] drm/i915/guc: Change default GuC FW for KBL to v9.39 Sagar Arun Kamble
@ 2017-08-09 13:58 ` Michal Wajdeczko
6 siblings, 0 replies; 12+ messages in thread
From: Michal Wajdeczko @ 2017-08-09 13:58 UTC (permalink / raw)
To: Sagar Arun Kamble; +Cc: intel-gfx
On Wed, Aug 09, 2017 at 03:53:45PM +0530, Sagar Arun Kamble wrote:
> Removed unnecessary intel_uc.h includes as it is present in i915_drv.h.
> Created intel_guc.c and intel_guc.h for placing GuC specific code.
> Created intel_huc.h to refer to HuC specific functions.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 2 +
> drivers/gpu/drm/i915/i915_drv.c | 1 -
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/i915_guc_submission.c | 1 -
> drivers/gpu/drm/i915/intel_guc.c | 184 ++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_guc.h | 203 +++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_guc_loader.c | 1 -
> drivers/gpu/drm/i915/intel_huc.c | 2 -
> drivers/gpu/drm/i915/intel_huc.h | 38 ++++++
> drivers/gpu/drm/i915/intel_uc.c | 159 +---------------------
> drivers/gpu/drm/i915/intel_uc.h | 178 -------------------------
> 11 files changed, 430 insertions(+), 341 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_guc.c
> create mode 100644 drivers/gpu/drm/i915/intel_guc.h
> create mode 100644 drivers/gpu/drm/i915/intel_huc.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index f822731..efa7605 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -58,6 +58,8 @@ i915-y += i915_cmd_parser.o \
>
> # general-purpose microcontroller (GuC) support
> i915-y += intel_uc.o \
> + intel_guc.o \
> + intel_huc.o \
Please leave intel_huc.o below, *after* all intel_guc... files
> intel_guc_ct.o \
> intel_guc_log.o \
> intel_guc_loader.o \
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 214555e..5512cce 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -50,7 +50,6 @@
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> #include "intel_drv.h"
> -#include "intel_uc.h"
>
> static struct drm_driver driver;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2c7456f..085647a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -59,6 +59,8 @@
> #include "intel_bios.h"
> #include "intel_dpll_mgr.h"
> #include "intel_uc.h"
> +#include "intel_guc.h"
> +#include "intel_huc.h"
Hmm, I'm not sure this is right direction.
We should use intel_uc.h as super set of all our [gh]uc components.
> #include "intel_lrc.h"
> #include "intel_ringbuffer.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 48a1e93..602ae8a 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -23,7 +23,6 @@
> */
> #include <linux/circ_buf.h>
> #include "i915_drv.h"
> -#include "intel_uc.h"
>
> #include <trace/events/dma_fence.h>
>
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> new file mode 100644
> index 0000000..a812d3d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -0,0 +1,184 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +
> +#include "i915_drv.h"
> +
> +inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
Why "static" was dropped ?
Also, please keep this function near other "send" functions
> +{
> + GEM_BUG_ON(!guc->send_regs.base);
> + GEM_BUG_ON(!guc->send_regs.count);
> + GEM_BUG_ON(i >= guc->send_regs.count);
> +
> + return _MMIO(guc->send_regs.base + 4 * i);
> +}
> +
> +void guc_capture_load_err_log(struct intel_guc *guc)
> +{
> + if (!guc->log.vma || i915.guc_log_level < 0)
> + return;
> +
> + if (!guc->load_err_log)
> + guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
> +}
> +
> +void guc_free_load_err_log(struct intel_guc *guc)
> +{
> + if (guc->load_err_log)
> + i915_gem_object_put(guc->load_err_log);
> +}
I guess above two functions can be treated as releated to "uc" activity and
as such can stay in intel_uc.c
> +
> +static void guc_init_send_regs(struct intel_guc *guc)
Maybe this function shall be named as "intel_guc_init()" and called only
once directly from intel_uc_init_hw() ?
> +{
> + struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + enum forcewake_domains fw_domains = 0;
> + unsigned int i;
> +
> + guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> + guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
> +
> + for (i = 0; i < guc->send_regs.count; i++) {
> + fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
> + guc_send_reg(guc, i),
> + FW_REG_READ | FW_REG_WRITE);
> + }
> + guc->send_regs.fw_domains = fw_domains;
> +}
> +
> +int guc_enable_communication(struct intel_guc *guc)
> +{
> + struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> + guc_init_send_regs(guc);
> +
> + if (HAS_GUC_CT(dev_priv))
> + return intel_guc_enable_ct(guc);
> +
> + guc->send = intel_guc_send_mmio;
> + return 0;
> +}
> +
> +void guc_disable_communication(struct intel_guc *guc)
> +{
> + struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> + if (HAS_GUC_CT(dev_priv))
> + intel_guc_disable_ct(guc);
> +
> + guc->send = intel_guc_send_nop;
> +}
I've mixed feelings about moving [enable|disable] functions here...
> +
> +int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
> +{
> + WARN(1, "Unexpected send: action=%#x\n", *action);
> + return -ENODEV;
> +}
> +
> +/*
> + * This function implements the MMIO based host to GuC interface.
> + */
> +int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
> +{
> + struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + u32 status;
> + int i;
> + int ret;
> +
> + GEM_BUG_ON(!len);
> + GEM_BUG_ON(len > guc->send_regs.count);
> +
> + /* If CT is available, we expect to use MMIO only during init/fini */
> + GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
> + *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
> + *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
> +
> + mutex_lock(&guc->send_mutex);
> + intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
> +
> + for (i = 0; i < len; i++)
> + I915_WRITE(guc_send_reg(guc, i), action[i]);
> +
> + POSTING_READ(guc_send_reg(guc, i - 1));
> +
> + intel_guc_notify(guc);
> +
> + /*
> + * No GuC command should ever take longer than 10ms.
> + * Fast commands should still complete in 10us.
> + */
> + ret = __intel_wait_for_register_fw(dev_priv,
> + guc_send_reg(guc, 0),
> + INTEL_GUC_RECV_MASK,
> + INTEL_GUC_RECV_MASK,
> + 10, 10, &status);
> + if (status != INTEL_GUC_STATUS_SUCCESS) {
> + /*
> + * Either the GuC explicitly returned an error (which
> + * we convert to -EIO here) or no response at all was
> + * received within the timeout limit (-ETIMEDOUT)
> + */
> + if (ret != -ETIMEDOUT)
> + ret = -EIO;
> +
> + DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
> + " ret=%d status=0x%08X response=0x%08X\n",
> + action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
> + }
> +
> + intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
> + mutex_unlock(&guc->send_mutex);
> +
> + return ret;
> +}
> +
> +int intel_guc_sample_forcewake(struct intel_guc *guc)
This function can be moved to the end.
> +{
> + struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + u32 action[2];
> +
> + action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
> + /* WaRsDisableCoarsePowerGating:skl,bxt */
> + if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
> + action[1] = 0;
> + else
> + /* bit 0 and 1 are for Render and Media domain separately */
> + action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
> +
> + return intel_guc_send(guc, action, ARRAY_SIZE(action));
> +}
> +
> +static void guc_write_irq_trigger(struct intel_guc *guc)
> +{
> + struct drm_i915_private *dev_priv = guc_to_i915(guc);
> +
> + I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
> +}
> +
> +void intel_guc_init_early(struct intel_guc *guc)
Please move this function as far to the top as possible.
> +{
> + intel_guc_ct_init_early(&guc->ct);
> +
> + mutex_init(&guc->send_mutex);
> + guc->send = intel_guc_send_nop;
> + guc->notify = guc_write_irq_trigger;
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> new file mode 100644
> index 0000000..f29f8ce
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -0,0 +1,203 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#ifndef _INTEL_GUC_H_
> +#define _INTEL_GUC_H_
> +
> +#include "intel_guc_fwif.h"
> +#include "i915_guc_reg.h"
> +#include "intel_ringbuffer.h"
> +#include "intel_guc_ct.h"
> +#include "i915_vma.h"
> +
> +struct drm_i915_gem_request;
> +
> +/*
> + * This structure primarily describes the GEM object shared with the GuC.
> + * The specs sometimes refer to this object as a "GuC context", but we use
> + * the term "client" to avoid confusion with hardware contexts. This
> + * GEM object is held for the entire lifetime of our interaction with
> + * the GuC, being allocated before the GuC is loaded with its firmware.
> + * Because there's no way to update the address used by the GuC after
> + * initialisation, the shared object must stay pinned into the GGTT as
> + * long as the GuC is in use. We also keep the first page (only) mapped
> + * into kernel address space, as it includes shared data that must be
> + * updated on every request submission.
> + *
> + * The single GEM object described here is actually made up of several
> + * separate areas, as far as the GuC is concerned. The first page (kept
> + * kmap'd) includes the "process descriptor" which holds sequence data for
> + * the doorbell, and one cacheline which actually *is* the doorbell; a
> + * write to this will "ring the doorbell" (i.e. send an interrupt to the
> + * GuC). The subsequent pages of the client object constitute the work
> + * queue (a circular array of work items), again described in the process
> + * descriptor. Work queue pages are mapped momentarily as required.
> + *
> + * We also keep a few statistics on failures. Ideally, these should all
> + * be zero!
> + * no_wq_space: times that the submission pre-check found no space was
> + * available in the work queue (note, the queue is shared,
> + * not per-engine). It is OK for this to be nonzero, but
> + * it should not be huge!
> + * b_fail: failed to ring the doorbell. This should never happen, unless
> + * somehow the hardware misbehaves, or maybe if the GuC firmware
> + * crashes? We probably need to reset the GPU to recover.
> + * retcode: errno from last guc_submit()
> + */
> +struct i915_guc_client {
> + struct i915_vma *vma;
> + void *vaddr;
> + struct i915_gem_context *owner;
> + struct intel_guc *guc;
> +
> + uint32_t engines; /* bitmap of (host) engine ids */
> + uint32_t priority;
> + u32 stage_id;
> + uint32_t proc_desc_offset;
> +
> + u16 doorbell_id;
> + unsigned long doorbell_offset;
> + u32 doorbell_cookie;
> +
> + spinlock_t wq_lock;
> + uint32_t wq_offset;
> + uint32_t wq_size;
> + uint32_t wq_tail;
> + uint32_t wq_rsvd;
> + uint32_t no_wq_space;
> +
> + /* Per-engine counts of GuC submissions */
> + uint64_t submissions[I915_NUM_ENGINES];
> +};
> +
> +struct intel_guc_log {
> + uint32_t flags;
> + struct i915_vma *vma;
> + /* The runtime stuff gets created only when GuC logging gets enabled */
> + struct {
> + void *buf_addr;
> + struct workqueue_struct *flush_wq;
> + struct work_struct flush_work;
> + struct rchan *relay_chan;
> + } runtime;
> + /* logging related stats */
> + u32 capture_miss_count;
> + u32 flush_interrupt_count;
> + u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
> + u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
> + u32 flush_count[GUC_MAX_LOG_BUFFER];
> +};
> +
> +struct intel_guc {
> + struct intel_uc_fw fw;
> + struct intel_guc_log log;
> + struct intel_guc_ct ct;
> +
> + /* Log snapshot if GuC errors during load */
> + struct drm_i915_gem_object *load_err_log;
> +
> + /* intel_guc_recv interrupt related state */
> + bool interrupts_enabled;
> +
> + struct i915_vma *ads_vma;
> + struct i915_vma *stage_desc_pool;
> + void *stage_desc_pool_vaddr;
> + struct ida stage_ids;
> +
> + struct i915_guc_client *execbuf_client;
> +
> + DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
> + uint32_t db_cacheline; /* Cyclic counter mod pagesize */
> +
> + /* GuC's FW specific registers used in MMIO send */
> + struct {
> + u32 base;
> + unsigned int count;
> + enum forcewake_domains fw_domains;
> + } send_regs;
> +
> + /* To serialize the intel_guc_send actions */
> + struct mutex send_mutex;
> +
> + /* GuC's FW specific send function */
> + int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
> +
> + /* GuC's FW specific notify function */
> + void (*notify)(struct intel_guc *guc);
> +};
> +
> +/* intel_guc.c */
> +inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i);
Why?
> +void guc_capture_load_err_log(struct intel_guc *guc);
> +void guc_free_load_err_log(struct intel_guc *guc);
> +int guc_enable_communication(struct intel_guc *guc);
> +void guc_disable_communication(struct intel_guc *guc);
Likely also not needed.
Btw, public functions shall start with "intel_guc_" prefix.
> +void intel_guc_init_early(struct intel_guc *guc);
> +int intel_guc_sample_forcewake(struct intel_guc *guc);
> +int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
> +int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
> +
> +static inline int intel_guc_send(struct intel_guc *guc, const u32 *action,
> + u32 len)
> +{
> + return guc->send(guc, action, len);
> +}
> +
> +static inline void intel_guc_notify(struct intel_guc *guc)
> +{
> + guc->notify(guc);
> +}
> +
> +/* intel_guc_loader.c */
> +int intel_guc_select_fw(struct intel_guc *guc);
> +int intel_guc_init_hw(struct intel_guc *guc);
> +int intel_guc_suspend(struct drm_i915_private *dev_priv);
> +int intel_guc_resume(struct drm_i915_private *dev_priv);
> +u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
> +
> +/* i915_guc_submission.c */
> +int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> +int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
> +int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
> +void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
> +void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
> +void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
> +struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
> +
> +/* intel_guc_log.c */
> +int intel_guc_log_create(struct intel_guc *guc);
> +void intel_guc_log_destroy(struct intel_guc *guc);
> +int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
> +void i915_guc_log_register(struct drm_i915_private *dev_priv);
> +void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
> +
> +static inline u32 guc_ggtt_offset(struct i915_vma *vma)
Placement of this function here, suggests that it is related to guc_log.h
Maybe moving it right after struct intel_guc definition will be better ?
> +{
> + u32 offset = i915_ggtt_offset(vma);
> +
> + GEM_BUG_ON(offset < GUC_WOPCM_TOP);
> + GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
> + return offset;
> +}
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index 8b0ae7f..81e03a6 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -27,7 +27,6 @@
> * Alex Dai <yu.dai@intel.com>
> */
> #include "i915_drv.h"
> -#include "intel_uc.h"
>
> /**
> * DOC: GuC-specific firmware loader
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index 6145fa0..8db3d5a 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -21,9 +21,7 @@
> * IN THE SOFTWARE.
> *
> */
> -#include <linux/firmware.h>
> #include "i915_drv.h"
> -#include "intel_uc.h"
>
> /**
> * DOC: HuC Firmware
> diff --git a/drivers/gpu/drm/i915/intel_huc.h b/drivers/gpu/drm/i915/intel_huc.h
> new file mode 100644
> index 0000000..4c46857
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_huc.h
> @@ -0,0 +1,38 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */
> +#ifndef _INTEL_HUC_H_
> +#define _INTEL_HUC_H_
> +
> +struct intel_huc {
> + /* Generic uC firmware management */
> + struct intel_uc_fw fw;
> +
> + /* HuC-specific additions */
> +};
> +
> +/* intel_huc.c */
> +void intel_huc_select_fw(struct intel_huc *huc);
> +void intel_huc_init_hw(struct intel_huc *huc);
> +void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
Hmm, I'm still having a problem with function...
Maybe we should convert it into
void intel_guc_auth_huc(struct intel_guc *guc,
struct intel_uc_fw *fw)
{
}
and move to intel_guc.c, or rename into
void intel_huc_auth(struct intel_huc *huc)
{
}
and use intel_guc_auth_huc() only to wrap send() code ?
> +#endif
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 27e072c..95af45f 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -23,7 +23,6 @@
> */
>
> #include "i915_drv.h"
> -#include "intel_uc.h"
> #include <linux/firmware.h>
>
> /* Cleans up uC firmware by releasing the firmware GEM obj.
> @@ -94,22 +93,11 @@ void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
> i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
> }
>
> -static void guc_write_irq_trigger(struct intel_guc *guc)
> -{
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -
> - I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
> -}
> -
> void intel_uc_init_early(struct drm_i915_private *dev_priv)
> {
> struct intel_guc *guc = &dev_priv->guc;
>
> - intel_guc_ct_init_early(&guc->ct);
> -
> - mutex_init(&guc->send_mutex);
> - guc->send = intel_guc_send_nop;
> - guc->notify = guc_write_irq_trigger;
> + intel_guc_init_early(guc);
> }
>
> static void fetch_uc_fw(struct drm_i915_private *dev_priv,
> @@ -262,72 +250,6 @@ void intel_uc_fini_fw(struct drm_i915_private *dev_priv)
> __intel_uc_fw_fini(&dev_priv->huc.fw);
> }
>
> -static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
> -{
> - GEM_BUG_ON(!guc->send_regs.base);
> - GEM_BUG_ON(!guc->send_regs.count);
> - GEM_BUG_ON(i >= guc->send_regs.count);
> -
> - return _MMIO(guc->send_regs.base + 4 * i);
> -}
> -
> -static void guc_init_send_regs(struct intel_guc *guc)
> -{
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - enum forcewake_domains fw_domains = 0;
> - unsigned int i;
> -
> - guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> - guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
> -
> - for (i = 0; i < guc->send_regs.count; i++) {
> - fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
> - guc_send_reg(guc, i),
> - FW_REG_READ | FW_REG_WRITE);
> - }
> - guc->send_regs.fw_domains = fw_domains;
> -}
> -
> -static void guc_capture_load_err_log(struct intel_guc *guc)
> -{
> - if (!guc->log.vma || i915.guc_log_level < 0)
> - return;
> -
> - if (!guc->load_err_log)
> - guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
> -
> - return;
> -}
> -
> -static void guc_free_load_err_log(struct intel_guc *guc)
> -{
> - if (guc->load_err_log)
> - i915_gem_object_put(guc->load_err_log);
> -}
> -
> -static int guc_enable_communication(struct intel_guc *guc)
> -{
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -
> - guc_init_send_regs(guc);
> -
> - if (HAS_GUC_CT(dev_priv))
> - return intel_guc_enable_ct(guc);
> -
> - guc->send = intel_guc_send_mmio;
> - return 0;
> -}
> -
> -static void guc_disable_communication(struct intel_guc *guc)
> -{
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> -
> - if (HAS_GUC_CT(dev_priv))
> - intel_guc_disable_ct(guc);
> -
> - guc->send = intel_guc_send_nop;
> -}
> -
> int intel_uc_init_hw(struct drm_i915_private *dev_priv)
> {
> struct intel_guc *guc = &dev_priv->guc;
> @@ -458,82 +380,3 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
>
> i915_ggtt_disable_guc(dev_priv);
> }
> -
> -int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len)
> -{
> - WARN(1, "Unexpected send: action=%#x\n", *action);
> - return -ENODEV;
> -}
> -
> -/*
> - * This function implements the MMIO based host to GuC interface.
> - */
> -int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len)
> -{
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - u32 status;
> - int i;
> - int ret;
> -
> - GEM_BUG_ON(!len);
> - GEM_BUG_ON(len > guc->send_regs.count);
> -
> - /* If CT is available, we expect to use MMIO only during init/fini */
> - GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
> - *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
> - *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
> -
> - mutex_lock(&guc->send_mutex);
> - intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
> -
> - for (i = 0; i < len; i++)
> - I915_WRITE(guc_send_reg(guc, i), action[i]);
> -
> - POSTING_READ(guc_send_reg(guc, i - 1));
> -
> - intel_guc_notify(guc);
> -
> - /*
> - * No GuC command should ever take longer than 10ms.
> - * Fast commands should still complete in 10us.
> - */
> - ret = __intel_wait_for_register_fw(dev_priv,
> - guc_send_reg(guc, 0),
> - INTEL_GUC_RECV_MASK,
> - INTEL_GUC_RECV_MASK,
> - 10, 10, &status);
> - if (status != INTEL_GUC_STATUS_SUCCESS) {
> - /*
> - * Either the GuC explicitly returned an error (which
> - * we convert to -EIO here) or no response at all was
> - * received within the timeout limit (-ETIMEDOUT)
> - */
> - if (ret != -ETIMEDOUT)
> - ret = -EIO;
> -
> - DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
> - " ret=%d status=0x%08X response=0x%08X\n",
> - action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
> - }
> -
> - intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
> - mutex_unlock(&guc->send_mutex);
> -
> - return ret;
> -}
> -
> -int intel_guc_sample_forcewake(struct intel_guc *guc)
> -{
> - struct drm_i915_private *dev_priv = guc_to_i915(guc);
> - u32 action[2];
> -
> - action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
> - /* WaRsDisableCoarsePowerGating:skl,bxt */
> - if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
> - action[1] = 0;
> - else
> - /* bit 0 and 1 are for Render and Media domain separately */
> - action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
> -
> - return intel_guc_send(guc, action, ARRAY_SIZE(action));
> -}
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 22ae52b..13460f8 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -24,72 +24,6 @@
> #ifndef _INTEL_UC_H_
> #define _INTEL_UC_H_
>
> -#include "intel_guc_fwif.h"
> -#include "i915_guc_reg.h"
> -#include "intel_ringbuffer.h"
> -#include "intel_guc_ct.h"
> -#include "i915_vma.h"
> -
> -struct drm_i915_gem_request;
> -
> -/*
> - * This structure primarily describes the GEM object shared with the GuC.
> - * The specs sometimes refer to this object as a "GuC context", but we use
> - * the term "client" to avoid confusion with hardware contexts. This
> - * GEM object is held for the entire lifetime of our interaction with
> - * the GuC, being allocated before the GuC is loaded with its firmware.
> - * Because there's no way to update the address used by the GuC after
> - * initialisation, the shared object must stay pinned into the GGTT as
> - * long as the GuC is in use. We also keep the first page (only) mapped
> - * into kernel address space, as it includes shared data that must be
> - * updated on every request submission.
> - *
> - * The single GEM object described here is actually made up of several
> - * separate areas, as far as the GuC is concerned. The first page (kept
> - * kmap'd) includes the "process descriptor" which holds sequence data for
> - * the doorbell, and one cacheline which actually *is* the doorbell; a
> - * write to this will "ring the doorbell" (i.e. send an interrupt to the
> - * GuC). The subsequent pages of the client object constitute the work
> - * queue (a circular array of work items), again described in the process
> - * descriptor. Work queue pages are mapped momentarily as required.
> - *
> - * We also keep a few statistics on failures. Ideally, these should all
> - * be zero!
> - * no_wq_space: times that the submission pre-check found no space was
> - * available in the work queue (note, the queue is shared,
> - * not per-engine). It is OK for this to be nonzero, but
> - * it should not be huge!
> - * b_fail: failed to ring the doorbell. This should never happen, unless
> - * somehow the hardware misbehaves, or maybe if the GuC firmware
> - * crashes? We probably need to reset the GPU to recover.
> - * retcode: errno from last guc_submit()
> - */
> -struct i915_guc_client {
> - struct i915_vma *vma;
> - void *vaddr;
> - struct i915_gem_context *owner;
> - struct intel_guc *guc;
> -
> - uint32_t engines; /* bitmap of (host) engine ids */
> - uint32_t priority;
> - u32 stage_id;
> - uint32_t proc_desc_offset;
> -
> - u16 doorbell_id;
> - unsigned long doorbell_offset;
> - u32 doorbell_cookie;
> -
> - spinlock_t wq_lock;
> - uint32_t wq_offset;
> - uint32_t wq_size;
> - uint32_t wq_tail;
> - uint32_t wq_rsvd;
> - uint32_t no_wq_space;
> -
> - /* Per-engine counts of GuC submissions */
> - uint64_t submissions[I915_NUM_ENGINES];
> -};
> -
> enum intel_uc_fw_status {
> INTEL_UC_FIRMWARE_FAIL = -1,
> INTEL_UC_FIRMWARE_NONE = 0,
> @@ -156,69 +90,6 @@ struct intel_uc_fw {
> uint32_t ucode_offset;
> };
>
> -struct intel_guc_log {
> - uint32_t flags;
> - struct i915_vma *vma;
> - /* The runtime stuff gets created only when GuC logging gets enabled */
> - struct {
> - void *buf_addr;
> - struct workqueue_struct *flush_wq;
> - struct work_struct flush_work;
> - struct rchan *relay_chan;
> - } runtime;
> - /* logging related stats */
> - u32 capture_miss_count;
> - u32 flush_interrupt_count;
> - u32 prev_overflow_count[GUC_MAX_LOG_BUFFER];
> - u32 total_overflow_count[GUC_MAX_LOG_BUFFER];
> - u32 flush_count[GUC_MAX_LOG_BUFFER];
> -};
> -
> -struct intel_guc {
> - struct intel_uc_fw fw;
> - struct intel_guc_log log;
> - struct intel_guc_ct ct;
> -
> - /* Log snapshot if GuC errors during load */
> - struct drm_i915_gem_object *load_err_log;
> -
> - /* intel_guc_recv interrupt related state */
> - bool interrupts_enabled;
> -
> - struct i915_vma *ads_vma;
> - struct i915_vma *stage_desc_pool;
> - void *stage_desc_pool_vaddr;
> - struct ida stage_ids;
> -
> - struct i915_guc_client *execbuf_client;
> -
> - DECLARE_BITMAP(doorbell_bitmap, GUC_NUM_DOORBELLS);
> - uint32_t db_cacheline; /* Cyclic counter mod pagesize */
> -
> - /* GuC's FW specific registers used in MMIO send */
> - struct {
> - u32 base;
> - unsigned int count;
> - enum forcewake_domains fw_domains;
> - } send_regs;
> -
> - /* To serialize the intel_guc_send actions */
> - struct mutex send_mutex;
> -
> - /* GuC's FW specific send function */
> - int (*send)(struct intel_guc *guc, const u32 *data, u32 len);
> -
> - /* GuC's FW specific notify function */
> - void (*notify)(struct intel_guc *guc);
> -};
> -
> -struct intel_huc {
> - /* Generic uC firmware management */
> - struct intel_uc_fw fw;
> -
> - /* HuC-specific additions */
> -};
> -
> /* intel_uc.c */
> void intel_uc_sanitize_options(struct drm_i915_private *dev_priv);
> void intel_uc_init_early(struct drm_i915_private *dev_priv);
> @@ -226,54 +97,5 @@ struct intel_huc {
> void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
> int intel_uc_init_hw(struct drm_i915_private *dev_priv);
> void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
> -int intel_guc_sample_forcewake(struct intel_guc *guc);
> -int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len);
> -int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len);
> -
> -static inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
> -{
> - return guc->send(guc, action, len);
> -}
> -
> -static inline void intel_guc_notify(struct intel_guc *guc)
> -{
> - guc->notify(guc);
> -}
> -
> -/* intel_guc_loader.c */
> -int intel_guc_select_fw(struct intel_guc *guc);
> -int intel_guc_init_hw(struct intel_guc *guc);
> -int intel_guc_suspend(struct drm_i915_private *dev_priv);
> -int intel_guc_resume(struct drm_i915_private *dev_priv);
> -u32 intel_guc_wopcm_size(struct drm_i915_private *dev_priv);
> -
> -/* i915_guc_submission.c */
> -int i915_guc_submission_init(struct drm_i915_private *dev_priv);
> -int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
> -int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
> -void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
> -void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
> -void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
> -struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
> -
> -/* intel_guc_log.c */
> -int intel_guc_log_create(struct intel_guc *guc);
> -void intel_guc_log_destroy(struct intel_guc *guc);
> -int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val);
> -void i915_guc_log_register(struct drm_i915_private *dev_priv);
> -void i915_guc_log_unregister(struct drm_i915_private *dev_priv);
> -
> -static inline u32 guc_ggtt_offset(struct i915_vma *vma)
> -{
> - u32 offset = i915_ggtt_offset(vma);
> - GEM_BUG_ON(offset < GUC_WOPCM_TOP);
> - GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
> - return offset;
> -}
> -
> -/* intel_huc.c */
> -void intel_huc_select_fw(struct intel_huc *huc);
> -void intel_huc_init_hw(struct intel_huc *huc);
> -void intel_guc_auth_huc(struct drm_i915_private *dev_priv);
>
> #endif
> --
> 1.9.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/8] drm/i915/guc: Handle GuC HW/SW state cleanup in unload path
2017-08-09 10:23 ` [PATCH 3/8] drm/i915/guc: Handle GuC HW/SW state cleanup in unload path Sagar Arun Kamble
@ 2017-08-09 14:36 ` Michal Wajdeczko
0 siblings, 0 replies; 12+ messages in thread
From: Michal Wajdeczko @ 2017-08-09 14:36 UTC (permalink / raw)
To: Sagar Arun Kamble; +Cc: intel-gfx
On Wed, Aug 09, 2017 at 03:53:47PM +0530, Sagar Arun Kamble wrote:
> Teardown of GuC HW/SW state was not properly done in unload path.
> During unload, we can rely on intel_guc_reset_prepare being done
> as part of i915_gem_suspend for disabling GuC interfaces.
> We will have to disable GuC submission prior to suspend as that involves
> communication with GuC to destroy doorbell. So intel_uc_fini_hw has to
> be called as part of i915_gem_suspend during unload as that really
> takes care of finishing the GuC operations. Created new parameter for
> i915_gem_suspend to handle unload/suspend path w.r.t gem and GuC suspend.
> GuC related allocations are cleaned up as part of intel_uc_cleanup_hw.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> drivers/gpu/drm/i915/i915_gem.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_guc.c | 13 +++++++++++++
> drivers/gpu/drm/i915/intel_guc.h | 1 +
> drivers/gpu/drm/i915/intel_uc.c | 14 +++++---------
> drivers/gpu/drm/i915/intel_uc.h | 1 +
> 7 files changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 218a8e1..c3fb73f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -599,7 +599,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv)
> i915_gem_drain_workqueue(dev_priv);
>
> mutex_lock(&dev_priv->drm.struct_mutex);
> - intel_uc_fini_hw(dev_priv);
> + intel_uc_cleanup_hw(dev_priv);
> i915_gem_cleanup_engines(dev_priv);
> i915_gem_contexts_fini(dev_priv);
> i915_gem_cleanup_userptr(dev_priv);
> @@ -680,7 +680,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> return 0;
>
> cleanup_gem:
> - if (i915_gem_suspend(dev_priv))
> + if (i915_gem_suspend(dev_priv, true))
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
> i915_gem_fini(dev_priv);
> cleanup_uc:
> @@ -1373,7 +1373,7 @@ void i915_driver_unload(struct drm_device *dev)
>
> i915_driver_unregister(dev_priv);
>
> - if (i915_gem_suspend(dev_priv))
> + if (i915_gem_suspend(dev_priv, true))
> DRM_ERROR("failed to idle hardware; continuing to unload!\n");
>
> intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> @@ -1518,7 +1518,7 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> pci_save_state(pdev);
>
> - error = i915_gem_suspend(dev_priv);
> + error = i915_gem_suspend(dev_priv, false);
> if (error) {
> dev_err(&pdev->dev,
> "GEM idle failed, resume might fail\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 085647a..dd6a3ff 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3547,7 +3547,8 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
> void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
> int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
> unsigned int flags);
> -int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
> +int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv,
> + bool unload);
> void i915_gem_resume(struct drm_i915_private *dev_priv);
> int i915_gem_fault(struct vm_fault *vmf);
> int i915_gem_object_wait(struct drm_i915_gem_object *obj,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e118b9a..1b1b9c7 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4525,7 +4525,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915)
> }
> }
>
> -int i915_gem_suspend(struct drm_i915_private *dev_priv)
> +int i915_gem_suspend(struct drm_i915_private *dev_priv, bool unload)
This extra param is not very intuitive.
Can we have two public functions:
int i915_gem_suspend(struct drm_i915_private *dev_priv)
int i915_gem_unload(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = &dev_priv->drm;
> int ret;
> @@ -4572,7 +4572,11 @@ int i915_gem_suspend(struct drm_i915_private *dev_priv)
> WARN_ON(dev_priv->gt.awake);
> WARN_ON(!intel_engines_are_idle(dev_priv));
>
> - intel_guc_system_suspend(&dev_priv->guc);
> + /* Handle GuC suspension in case of unloading/system suspend */
> + if (unload)
> + intel_uc_fini_hw(dev_priv);
> + else
> + intel_guc_system_suspend(&dev_priv->guc);
>
> /*
> * Neither the BIOS, ourselves or any other kernel
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 3777659..f4ddfbb 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -313,3 +313,16 @@ int intel_guc_system_resume(struct intel_guc *guc)
> */
> return ret;
> }
> +
> +void intel_guc_fini(struct intel_guc *guc)
> +{
> + struct drm_i915_private *dev_priv = guc_to_i915(guc);
> + struct drm_device *dev = &dev_priv->drm;
> +
> + if (i915.enable_guc_submission) {
> + mutex_lock(&dev->struct_mutex);
> + i915_guc_submission_disable(dev_priv);
> + mutex_unlock(&dev->struct_mutex);
> + intel_guc_reset_prepare(&dev_priv->guc);
You can use "guc" param here.
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
> index e9664bf..ed3d202 100644
> --- a/drivers/gpu/drm/i915/intel_guc.h
> +++ b/drivers/gpu/drm/i915/intel_guc.h
> @@ -161,6 +161,7 @@ struct intel_guc {
> int intel_guc_runtime_resume(struct intel_guc *guc);
> int intel_guc_system_suspend(struct intel_guc *guc);
> int intel_guc_system_resume(struct intel_guc *guc);
> +void intel_guc_fini(struct intel_guc *guc);
>
> static inline int intel_guc_send(struct intel_guc *guc, const u32 *action,
> u32 len)
> diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
> index 95af45f..e6b9330 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -363,20 +363,16 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
>
> void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
> {
> + intel_guc_fini(&dev_priv->guc);
> +}
> +
> +void intel_uc_cleanup_hw(struct drm_i915_private *dev_priv)
I'm little confused with above names.
Is there matching "prepare" function ?
What is the expected order of calls ?
early_init/init/prepare/cleanup/fini ?
> +{
> guc_free_load_err_log(&dev_priv->guc);
>
> if (!i915.enable_guc_loading)
> return;
>
> if (i915.enable_guc_submission)
> - i915_guc_submission_disable(dev_priv);
> -
> - guc_disable_communication(&dev_priv->guc);
> -
> - if (i915.enable_guc_submission) {
> - gen9_disable_guc_interrupts(dev_priv);
> i915_guc_submission_fini(dev_priv);
> - }
> -
> - i915_ggtt_disable_guc(dev_priv);
> }
> diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
> index 13460f8..bfe5639 100644
> --- a/drivers/gpu/drm/i915/intel_uc.h
> +++ b/drivers/gpu/drm/i915/intel_uc.h
> @@ -97,5 +97,6 @@ struct intel_uc_fw {
> void intel_uc_fini_fw(struct drm_i915_private *dev_priv);
> int intel_uc_init_hw(struct drm_i915_private *dev_priv);
> void intel_uc_fini_hw(struct drm_i915_private *dev_priv);
> +void intel_uc_cleanup_hw(struct drm_i915_private *dev_priv);
>
> #endif
> --
> 1.9.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9
2017-08-09 10:49 ` Chris Wilson
@ 2017-08-14 10:45 ` Kamble, Sagar A
2017-08-17 5:07 ` Srivatsa, Anusha
0 siblings, 1 reply; 12+ messages in thread
From: Kamble, Sagar A @ 2017-08-14 10:45 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
-----Original Message-----
From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
Sent: Wednesday, August 9, 2017 4:20 PM
To: Kamble, Sagar A <sagar.a.kamble@intel.com>; intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9
Quoting Sagar Arun Kamble (2017-08-09 11:23:48)
> From GuC v9 firmware (for KBL v9.39+), separate control is added to
> enable critical logging in GuC to enable capturing minimal important
> logs in production systems.
> i915.guc_log_level controls the verbosity and logging in GuC for logs
> other than critical logs. By default, logging in GuC is disabled
> through i915.guc_log_level.
> This patch introduces new kernel param i915.enable_guc_critical_logging.
> For Linux release builds, if needed critical GuC logs can be enabled
> separately through this parameter. GuC log snapshot captured in error
> state will have these minimal critical events logged.
> Default value for this parameter is currently set to false.
> This patch updates the initialization parameter sent during GuC load
> to disable critical logging unless i915.guc_log_level is set to enable
> logging and ensures it is enabled/disabling while enabling/disabling
> through debugfs based on i915.enable_guc_critical_logging.
>
> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Spotswood John A <john.a.spotswood@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> ---
> drivers/gpu/drm/i915/i915_params.c | 5 +++++
> drivers/gpu/drm/i915/i915_params.h | 3 ++-
> drivers/gpu/drm/i915/intel_guc_fwif.h | 14 +++++++++++++-
> drivers/gpu/drm/i915/intel_guc_loader.c | 21 ++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_guc_log.c | 9 ++++++++-
> 5 files changed, 48 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_params.c
> b/drivers/gpu/drm/i915/i915_params.c
> index 14e2c2e..902bf2c 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -59,6 +59,7 @@ struct i915_params i915 __read_mostly = {
> .enable_guc_loading = 0,
> .enable_guc_submission = 0,
> .guc_log_level = -1,
> + .enable_guc_critical_logging = false,
What's the point in having a log level if LOG_LEVEL_CRITICAL is not part of it? Please do explain why the current parameter does not cover this.
-Chris
<Sagar> Agree that this could have been enumerated as another log level. Having it as log level simplifies other capture code too which
I am seeing needs fix with current change. Will check if this can be changed in upcoming releases.
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9
2017-08-14 10:45 ` Kamble, Sagar A
@ 2017-08-17 5:07 ` Srivatsa, Anusha
0 siblings, 0 replies; 12+ messages in thread
From: Srivatsa, Anusha @ 2017-08-17 5:07 UTC (permalink / raw)
To: Kamble, Sagar A, Chris Wilson, intel-gfx
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Kamble, Sagar A
>Sent: Monday, August 14, 2017 3:45 AM
>To: Chris Wilson <chris@chris-wilson.co.uk>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC
>by default from GuC v9
>
>
>
>-----Original Message-----
>From: Chris Wilson [mailto:chris@chris-wilson.co.uk]
>Sent: Wednesday, August 9, 2017 4:20 PM
>To: Kamble, Sagar A <sagar.a.kamble@intel.com>; intel-
>gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC
>by default from GuC v9
>
>Quoting Sagar Arun Kamble (2017-08-09 11:23:48)
>> From GuC v9 firmware (for KBL v9.39+), separate control is added to
>> enable critical logging in GuC to enable capturing minimal important
>> logs in production systems.
>> i915.guc_log_level controls the verbosity and logging in GuC for logs
>> other than critical logs. By default, logging in GuC is disabled
>> through i915.guc_log_level.
>> This patch introduces new kernel param i915.enable_guc_critical_logging.
>> For Linux release builds, if needed critical GuC logs can be enabled
>> separately through this parameter. GuC log snapshot captured in error
>> state will have these minimal critical events logged.
>> Default value for this parameter is currently set to false.
>> This patch updates the initialization parameter sent during GuC load
>> to disable critical logging unless i915.guc_log_level is set to enable
>> logging and ensures it is enabled/disabling while enabling/disabling
>> through debugfs based on i915.enable_guc_critical_logging.
>>
>> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
>> Cc: Spotswood John A <john.a.spotswood@intel.com>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_params.c | 5 +++++
>> drivers/gpu/drm/i915/i915_params.h | 3 ++-
>> drivers/gpu/drm/i915/intel_guc_fwif.h | 14 +++++++++++++-
>> drivers/gpu/drm/i915/intel_guc_loader.c | 21 ++++++++++++++++++++-
>> drivers/gpu/drm/i915/intel_guc_log.c | 9 ++++++++-
>> 5 files changed, 48 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_params.c
>> b/drivers/gpu/drm/i915/i915_params.c
>> index 14e2c2e..902bf2c 100644
>> --- a/drivers/gpu/drm/i915/i915_params.c
>> +++ b/drivers/gpu/drm/i915/i915_params.c
>> @@ -59,6 +59,7 @@ struct i915_params i915 __read_mostly = {
>> .enable_guc_loading = 0,
>> .enable_guc_submission = 0,
>> .guc_log_level = -1,
>> + .enable_guc_critical_logging = false,
>
>What's the point in having a log level if LOG_LEVEL_CRITICAL is not part of it?
>Please do explain why the current parameter does not cover this.
>-Chris
I agree with Chris. Apart from introducing a new parameter, this is also introducing the dependency on an existing one - guc_log_level.
Anusha
><Sagar> Agree that this could have been enumerated as another log level. Having
>it as log level simplifies other capture code too which I am seeing needs fix with
>current change. Will check if this can be changed in upcoming releases.
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2017-08-17 5:07 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-09 10:23 [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 2/8] drm/i915/guc: Handle GuC interaction in reset/suspend scenarios Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 3/8] drm/i915/guc: Handle GuC HW/SW state cleanup in unload path Sagar Arun Kamble
2017-08-09 14:36 ` Michal Wajdeczko
2017-08-09 10:23 ` [PATCH 4/8] drm/i915/guc: Disable critical logging in GuC by default from GuC v9 Sagar Arun Kamble
2017-08-09 10:49 ` Chris Wilson
2017-08-14 10:45 ` Kamble, Sagar A
2017-08-17 5:07 ` Srivatsa, Anusha
2017-08-09 10:23 ` [PATCH 5/8] drm/i915/guc: Change default GuC FW for SKL to v9.33 Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 6/8] drm/i915/guc: Change default GuC FW for BXT to v9.29 Sagar Arun Kamble
2017-08-09 10:23 ` [PATCH 7/8] drm/i915/guc: Change default GuC FW for KBL to v9.39 Sagar Arun Kamble
2017-08-09 13:58 ` [PATCH 1/8] drm/i915: Separate GuC/HuC specific functionality from intel_uc Michal Wajdeczko
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