* [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT
@ 2017-08-09 12:51 Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 01/13] scripts: spl: fix typo Peng Fan
` (12 more replies)
0 siblings, 13 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:51 UTC (permalink / raw)
To: u-boot
This patch set is to support SPL FIT for mx6sabresd board.
Patchset tested on 6qsabresd and 6qpsabresd board, works well.
The mkimage_fit.sh is modified from sunxi code to generate u-boot.its.
V2:
Rebased to latest master branch
Include patch https://patchwork.ozlabs.org/patch/798992/ to make this
patchset could be applied together.
Peng Fan (13):
scripts: spl: fix typo
arm: dts: include dts for imx6sabresd
power: pmic/regulator allow dm be omited by SPL
Makefile: build FIT image if CONFIG_SPL_FIT_GENERATOR defined
imx: introduce mkimage_fit.sh
imx: mx6sabresd: implement board_fit_config_name_match
imx: mx6sabresd: enable SPL FIT
scripts: spl: Disable DM MMC when SPL DM not enabled
mmc: fsl_esdhc: switch to use CONFIG_IS_ENABLED
power: pmic.h: include dm/ofnode.h
board: freescale: common: add pfuze dm code
imx: mx6sabresd: enable dm drivers
imx: mx6sabresd: update README
Makefile | 4 +
arch/arm/dts/Makefile | 3 +
arch/arm/dts/imx6dl-sabresd.dts | 22 +
arch/arm/dts/imx6dl.dtsi | 242 +++++++++++
arch/arm/dts/imx6q-sabresd.dts | 30 ++
arch/arm/dts/imx6q.dtsi | 164 ++++++-
arch/arm/dts/imx6qdl-sabresd.dtsi | 738 ++++++++++++++++++++++++++++++++
arch/arm/dts/imx6qdl.dtsi | 100 +++--
arch/arm/dts/imx6qp-sabresd.dts | 93 ++++
arch/arm/dts/imx6qp.dtsi | 153 +++++++
arch/arm/mach-imx/mkimage_fit.sh | 63 +++
board/freescale/common/Makefile | 1 +
board/freescale/common/pfuze.h | 5 +
board/freescale/common/pfuze_dm.c | 89 ++++
board/freescale/mx6sabresd/README | 18 +-
board/freescale/mx6sabresd/mx6sabresd.c | 339 ++++++---------
configs/mx6sabresd_defconfig | 22 +-
drivers/mmc/fsl_esdhc.c | 14 +-
drivers/power/pmic/Makefile | 4 +-
drivers/power/regulator/Makefile | 2 +-
include/configs/mx6sabresd.h | 15 +-
include/power/pmic.h | 1 +
scripts/Makefile.uncmd_spl | 3 +-
23 files changed, 1869 insertions(+), 256 deletions(-)
create mode 100644 arch/arm/dts/imx6dl-sabresd.dts
create mode 100644 arch/arm/dts/imx6q-sabresd.dts
create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi
create mode 100644 arch/arm/dts/imx6qp-sabresd.dts
create mode 100644 arch/arm/dts/imx6qp.dtsi
create mode 100755 arch/arm/mach-imx/mkimage_fit.sh
create mode 100644 board/freescale/common/pfuze_dm.c
--
2.6.2
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 01/13] scripts: spl: fix typo
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
@ 2017-08-09 12:51 ` Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 02/13] arm: dts: include dts for imx6sabresd Peng Fan
` (11 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:51 UTC (permalink / raw)
To: u-boot
Typo fix: CONIFG->CONFIG
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Tom Rini <trini@konsulko.com>
---
scripts/Makefile.uncmd_spl | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl
index 15d0836..b399411 100644
--- a/scripts/Makefile.uncmd_spl
+++ b/scripts/Makefile.uncmd_spl
@@ -9,7 +9,7 @@ ifdef CONFIG_SPL_BUILD
ifndef CONFIG_SPL_DM
CONFIG_DM_SERIAL=
CONFIG_DM_GPIO=
-CONIFG_DM_I2C=
+CONFIG_DM_I2C=
CONFIG_DM_SPI=
CONFIG_DM_SPI_FLASH=
endif
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 02/13] arm: dts: include dts for imx6sabresd
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 01/13] scripts: spl: fix typo Peng Fan
@ 2017-08-09 12:51 ` Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 03/13] power: pmic/regulator allow dm be omited by SPL Peng Fan
` (10 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:51 UTC (permalink / raw)
To: u-boot
Import dts from commit aae4e7a8bc("Linux 4.13-rc4") for imx6sabresd board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/imx6dl-sabresd.dts | 22 ++
arch/arm/dts/imx6dl.dtsi | 242 +++++++++++++
arch/arm/dts/imx6q-sabresd.dts | 30 ++
arch/arm/dts/imx6q.dtsi | 164 ++++++++-
arch/arm/dts/imx6qdl-sabresd.dtsi | 738 ++++++++++++++++++++++++++++++++++++++
arch/arm/dts/imx6qdl.dtsi | 100 ++++--
arch/arm/dts/imx6qp-sabresd.dts | 93 +++++
arch/arm/dts/imx6qp.dtsi | 153 ++++++++
9 files changed, 1520 insertions(+), 25 deletions(-)
create mode 100644 arch/arm/dts/imx6dl-sabresd.dts
create mode 100644 arch/arm/dts/imx6q-sabresd.dts
create mode 100644 arch/arm/dts/imx6qdl-sabresd.dtsi
create mode 100644 arch/arm/dts/imx6qp-sabresd.dts
create mode 100644 arch/arm/dts/imx6qp.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c2dc240..a700864 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -356,6 +356,9 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
imx6sll-evk.dtb \
imx6dl-icore.dtb \
imx6dl-icore-rqs.dtb \
+ imx6dl-sabresd.dtb \
+ imx6q-sabresd.dtb \
+ imx6qp-sabresd.dtb \
imx6q-icore.dtb \
imx6q-icore-rqs.dtb \
imx6q-logicpd.dtb \
diff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts
new file mode 100644
index 0000000..9607afe
--- /dev/null
+++ b/arch/arm/dts/imx6dl-sabresd.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+ model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
+ compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi
index 9a4c22c..8475e6c 100644
--- a/arch/arm/dts/imx6dl.dtsi
+++ b/arch/arm/dts/imx6dl.dtsi
@@ -100,6 +100,11 @@
};
};
+ capture-subsystem {
+ compatible = "fsl,imx-capture-subsystem";
+ ports = <&ipu1_csi0>, <&ipu1_csi1>;
+ };
+
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>;
@@ -111,6 +116,169 @@
};
};
+&gpio1 {
+ gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
+ <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
+ <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
+ <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
+ <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
+ <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
+ <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
+};
+
+&gpio2 {
+ gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
+ <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
+ <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
+ <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
+ <&iomuxc 28 113 4>;
+};
+
+&gpio3 {
+ gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
+ <&iomuxc 16 81 16>;
+};
+
+&gpio4 {
+ gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
+ <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
+ <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
+ <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
+ <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
+};
+
+&gpio5 {
+ gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
+ <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
+ <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
+ <&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
+};
+
+&gpio6 {
+ gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
+ <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
+ <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
+ <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
+ <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
+ <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
+};
+
+&gpio7 {
+ gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
+ <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
+ <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
+};
+
+&gpr {
+ ipu1_csi0_mux: ipu1_csi0_mux at 34 {
+ compatible = "video-mux";
+ mux-controls = <&mux 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ipu1_csi0_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 5 {
+ reg = <5>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu1_csi1_mux: ipu1_csi1_mux at 34 {
+ compatible = "video-mux";
+ mux-controls = <&mux 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi1_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi1_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi1_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ ipu1_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ ipu1_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 5 {
+ reg = <5>;
+
+ ipu1_csi1_mux_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
+ };
+ };
+ };
+};
+
&gpt {
compatible = "fsl,imx6dl-gpt";
};
@@ -119,6 +287,12 @@
compatible = "fsl,imx6dl-hdmi";
};
+&ipu1_csi1 {
+ ipu1_csi1_from_ipu1_csi1_mux: endpoint {
+ remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
+ };
+};
+
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -128,6 +302,74 @@
"di0", "di1";
};
+&mipi_csi {
+ port at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+
+ mipi_vc0_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc1_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
+ };
+
+ mipi_vc1_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc2_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
+ };
+
+ mipi_vc2_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc3_to_ipu1_csi0_mux: endpoint at 0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
+ };
+
+ mipi_vc3_to_ipu1_csi1_mux: endpoint at 1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
+
+&mux {
+ mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
+ <0x34 0x00000038>, /* IPU_CSI1_MUX */
+ <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+ <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+ <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+ <0x28 0x00000003>, /* DCIC1_MUX_CTL */
+ <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};
diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts
new file mode 100644
index 0000000..527772b
--- /dev/null
+++ b/arch/arm/dts/imx6q-sabresd.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+ model = "Freescale i.MX6 Quad SABRE Smart Device Board";
+ compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+};
+
+&sata {
+ status = "okay";
+};
+
+&ipu1_csi1_from_mipi_vc1 {
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+};
diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi
index c30c836..90a74173 100644
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@@ -125,7 +125,7 @@
clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
- power-domains = <&gpc 1>;
+ power-domains = <&pd_pu>;
};
ipu2: ipu at 02800000 {
@@ -143,10 +143,18 @@
ipu2_csi0: port at 0 {
reg = <0>;
+
+ ipu2_csi0_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
+ };
};
ipu2_csi1: port at 1 {
reg = <1>;
+
+ ipu2_csi1_from_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
+ };
};
ipu2_di0: port at 2 {
@@ -198,6 +206,11 @@
};
};
+ capture-subsystem {
+ compatible = "fsl,imx-capture-subsystem";
+ ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
+ };
+
display-subsystem {
compatible = "fsl,imx-display-subsystem";
ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
@@ -209,6 +222,105 @@
};
};
+&gpio1 {
+ gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
+ <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
+ <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
+ <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
+ <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
+ <&iomuxc 22 116 10>;
+};
+
+&gpio2 {
+ gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
+ <&iomuxc 31 44 1>;
+};
+
+&gpio3 {
+ gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
+};
+
+&gpio4 {
+ gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
+};
+
+&gpio5 {
+ gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
+ <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
+};
+
+&gpio6 {
+ gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
+ <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
+ <&iomuxc 31 86 1>;
+};
+
+&gpio7 {
+ gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
+};
+
+&gpr {
+ ipu1_csi0_mux {
+ compatible = "video-mux";
+ mux-controls = <&mux 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu2_csi1_mux {
+ compatible = "video-mux";
+ mux-controls = <&mux 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ ipu2_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+
+ ipu2_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ ipu2_csi1_mux_to_ipu2_csi1: endpoint {
+ remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
+ };
+ };
+ };
+};
+
&hdmi {
compatible = "fsl,imx6q-hdmi";
@@ -229,6 +341,12 @@
};
};
+&ipu1_csi1 {
+ ipu1_csi1_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
+ };
+};
+
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -275,6 +393,40 @@
};
};
+&mipi_csi {
+ port at 1 {
+ reg = <1>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+ };
+
+ port at 2 {
+ reg = <2>;
+
+ mipi_vc1_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
+ };
+ };
+
+ port at 3 {
+ reg = <3>;
+
+ mipi_vc2_to_ipu2_csi0: endpoint {
+ remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
+ };
+ };
+
+ port at 4 {
+ reg = <4>;
+
+ mipi_vc3_to_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
+
&mipi_dsi {
ports {
port at 2 {
@@ -295,6 +447,16 @@
};
};
+&mux {
+ mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
+ <0x04 0x00100000>, /* MIPI_IPU2_MUX */
+ <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
+ <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
+ <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
+ <0x28 0x00000003>, /* DCIC1_MUX_CTL */
+ <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
+};
+
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};
diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi
new file mode 100644
index 0000000..b72b6fa
--- /dev/null
+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
@@ -0,0 +1,738 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg_vbus: regulator at 0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 22 0>;
+ enable-active-high;
+ vin-supply = <&swbst_reg>;
+ };
+
+ reg_usb_h1_vbus: regulator at 1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 29 0>;
+ enable-active-high;
+ vin-supply = <&swbst_reg>;
+ };
+
+ reg_audio: regulator at 2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "wm8962-supply";
+ gpio = <&gpio4 10 0>;
+ enable-active-high;
+ };
+
+ reg_pcie: regulator at 3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie_reg>;
+ regulator-name = "MPCIE_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 19 0>;
+ regulator-always-on;
+ enable-active-high;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ label = "Power Button";
+ gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ linux,code = <KEY_POWER>;
+ };
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+ gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx6q-sabresd-wm8962",
+ "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+ ssi-controller = <&ssi2>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "Ext Spk", "SPKOUTL",
+ "Ext Spk", "SPKOUTR",
+ "AMIC", "MICBIAS",
+ "IN3R", "AMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <3>;
+ };
+
+ backlight_lvds: backlight-lvds {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ red {
+ gpios = <&gpio1 2 0>;
+ default-state = "on";
+ };
+ };
+
+ panel {
+ compatible = "hannstar,hsd100pxn1";
+ backlight = <&backlight_lvds>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
+&mipi_csi {
+ status = "okay";
+
+ port at 0 {
+ reg = <0>;
+
+ mipi_csi2_in: endpoint {
+ remote-endpoint = <&ov5640_to_mipi_csi2>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 9 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p32", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: wm8962 at 1a {
+ compatible = "wlf,wm8962";
+ reg = <0x1a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ DCVDD-supply = <®_audio>;
+ DBVDD-supply = <®_audio>;
+ AVDD-supply = <®_audio>;
+ CPVDD-supply = <®_audio>;
+ MICVDD-supply = <®_audio>;
+ PLLVDD-supply = <®_audio>;
+ SPKVDD1-supply = <®_audio>;
+ SPKVDD2-supply = <®_audio>;
+ gpio-cfg = <
+ 0x0000 /* 0:Default */
+ 0x0000 /* 1:Default */
+ 0x0013 /* 2:FN_DMICCLK */
+ 0x0000 /* 3:Default */
+ 0x8014 /* 4:FN_DMICCDAT */
+ 0x0000 /* 5:Default */
+ >;
+ };
+
+ ov5642: camera at 3c {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ reg = <0x3c>;
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
+ status = "disabled";
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ ov5640: camera at 3c {
+ compatible = "ovti,ov5640";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ reg = <0x3c>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+
+ pmic: pfuze100 at 08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ egalax_ts at 04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <7 2>;
+ wakeup-gpios = <&gpio6 7 0>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ imx6qdl-sabresd {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
+ >;
+ };
+
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ >;
+ };
+
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
+ >;
+ };
+
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
+ >;
+ };
+
+ pinctrl_pcie_reg: pciereggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
+ >;
+ };
+ };
+
+ gpio_leds {
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
+ >;
+ };
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds-channel at 1 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+
+ port at 4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie>;
+ reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+
+®_arm {
+ vin-supply = <&sw1a_reg>;
+};
+
+®_pu {
+ vin-supply = <&sw1c_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1c_reg>;
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&ssi2 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ status = "disabled";
+};
+
+&wdog2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index b13b0b2..a9723b9 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -13,9 +13,18 @@
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /*
+ * The decompressor and also some bootloaders rely on a
+ * pre-existing /chosen node to be available to insert the
+ * command line and merge other ATAGS info.
+ * Also for U-Boot there must be a pre-existing /memory node.
+ */
+ chosen {};
+ memory { device_type = "memory"; reg = <0 0>; };
+
aliases {
ethernet0 = &fec;
can0 = &can1;
@@ -147,7 +156,7 @@
<&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>;
clock-names = "bus", "core", "shader";
- power-domains = <&gpc 1>;
+ power-domains = <&pd_pu>;
};
gpu_2d: gpu at 00134000 {
@@ -157,7 +166,7 @@
clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
- power-domains = <&gpc 1>;
+ power-domains = <&pd_pu>;
};
timer at 00a00600 {
@@ -188,7 +197,7 @@
arm,shared-override;
};
- pcie: pcie at 0x01000000 {
+ pcie: pcie at 1ffc000 {
compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
reg = <0x01ffc000 0x04000>,
<0x01f00000 0x80000>;
@@ -196,6 +205,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+ bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
@@ -204,9 +214,9 @@
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
<&clks IMX6QDL_CLK_LVDS1_GATE>,
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
@@ -424,7 +434,7 @@
clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
clock-names = "per", "ahb";
- power-domains = <&gpc 1>;
+ power-domains = <&pd_pu>;
resets = <&src 1>;
iram = <&ocram>;
};
@@ -625,8 +635,8 @@
regulator-1p1 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
- regulator-min-microvolt = <800000>;
- regulator-max-microvolt = <1375000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
@@ -634,6 +644,7 @@
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
+ anatop-enable-bit = <0>;
};
regulator-3p0 {
@@ -648,20 +659,22 @@
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
+ anatop-enable-bit = <0>;
};
regulator-2p5 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
- regulator-min-microvolt = <2000000>;
+ regulator-min-microvolt = <2250000>;
regulator-max-microvolt = <2750000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
- anatop-min-voltage = <2000000>;
- anatop-max-voltage = <2750000>;
+ anatop-min-voltage = <2100000>;
+ anatop-max-voltage = <2875000>;
+ anatop-enable-bit = <0>;
};
reg_arm: regulator-vddcore {
@@ -787,19 +800,39 @@
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
- pu-supply = <®_pu>;
- clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
- <&clks IMX6QDL_CLK_GPU3D_SHADER>,
- <&clks IMX6QDL_CLK_GPU2D_CORE>,
- <&clks IMX6QDL_CLK_GPU2D_AXI>,
- <&clks IMX6QDL_CLK_OPENVG_AXI>,
- <&clks IMX6QDL_CLK_VPU_AXI>;
- #power-domain-cells = <1>;
+ clocks = <&clks IMX6QDL_CLK_IPG>;
+ clock-names = "ipg";
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain at 0 {
+ reg = <0>;
+ #power-domain-cells = <0>;
+ };
+ pd_pu: power-domain at 1 {
+ reg = <1>;
+ #power-domain-cells = <0>;
+ power-supply = <®_pu>;
+ clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
+ <&clks IMX6QDL_CLK_GPU3D_SHADER>,
+ <&clks IMX6QDL_CLK_GPU2D_CORE>,
+ <&clks IMX6QDL_CLK_GPU2D_AXI>,
+ <&clks IMX6QDL_CLK_OPENVG_AXI>,
+ <&clks IMX6QDL_CLK_VPU_AXI>;
+ };
+ };
};
gpr: iomuxc-gpr at 020e0000 {
- compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
reg = <0x020e0000 0x38>;
+
+ mux: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ };
};
iomuxc: iomuxc at 020e0000 {
@@ -807,7 +840,7 @@
reg = <0x020e0000 0x4000>;
};
- ldb: ldb at 020e0008 {
+ ldb: ldb {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
@@ -1092,10 +1125,14 @@
};
weim: weim at 021b8000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+ fsl,weim-cs-gpr = <&gpr>;
+ status = "disabled";
};
ocotp: ocotp at 021bc000 {
@@ -1121,7 +1158,16 @@
};
mipi_csi: mipi at 021dc000 {
+ compatible = "fsl,imx6-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 100 0x04>, <0 101 0x04>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>,
+ <&clks IMX6QDL_CLK_VIDEO_27M>,
+ <&clks IMX6QDL_CLK_EIM_PODF>;
+ clock-names = "dphy", "ref", "pix";
+ status = "disabled";
};
mipi_dsi: mipi at 021e0000 {
@@ -1153,8 +1199,10 @@
};
vdoa at 021e4000 {
+ compatible = "fsl,imx6q-vdoa";
reg = <0x021e4000 0x4000>;
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6QDL_CLK_VDOA>;
};
uart2: serial at 021e8000 {
@@ -1221,6 +1269,10 @@
ipu1_csi0: port at 0 {
reg = <0>;
+
+ ipu1_csi0_from_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
+ };
};
ipu1_csi1: port at 1 {
diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts
new file mode 100644
index 0000000..a8a5004
--- /dev/null
+++ b/arch/arm/dts/imx6qp-sabresd.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6qp.dtsi"
+#include "imx6qdl-sabresd.dtsi"
+
+/ {
+ model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
+ compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
+};
+
+®_arm {
+ vin-supply = <&sw2_reg>;
+};
+
+&iomuxc {
+ imx6qdl-sabresd {
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+ };
+};
+
+&pcie {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi
new file mode 100644
index 0000000..299d863
--- /dev/null
+++ b/arch/arm/dts/imx6qp.dtsi
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6q.dtsi"
+
+/ {
+ soc {
+ ocram2: sram at 00940000 {
+ compatible = "mmio-sram";
+ reg = <0x00940000 0x20000>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+ ocram3: sram at 00960000 {
+ compatible = "mmio-sram";
+ reg = <0x00960000 0x20000>;
+ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+ aips-bus at 02100000 {
+ pre1: pre at 21c8000 {
+ compatible = "fsl,imx6qp-pre";
+ reg = <0x021c8000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clks IMX6QDL_CLK_PRE0>;
+ clock-names = "axi";
+ fsl,iram = <&ocram2>;
+ };
+
+ pre2: pre at 21c9000 {
+ compatible = "fsl,imx6qp-pre";
+ reg = <0x021c9000 0x1000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clks IMX6QDL_CLK_PRE1>;
+ clock-names = "axi";
+ fsl,iram = <&ocram2>;
+ };
+
+ pre3: pre at 21ca000 {
+ compatible = "fsl,imx6qp-pre";
+ reg = <0x021ca000 0x1000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clks IMX6QDL_CLK_PRE2>;
+ clock-names = "axi";
+ fsl,iram = <&ocram3>;
+ };
+
+ pre4: pre at 21cb000 {
+ compatible = "fsl,imx6qp-pre";
+ reg = <0x021cb000 0x1000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clks IMX6QDL_CLK_PRE3>;
+ clock-names = "axi";
+ fsl,iram = <&ocram3>;
+ };
+
+ prg1: prg at 21cc000 {
+ compatible = "fsl,imx6qp-prg";
+ reg = <0x021cc000 0x1000>;
+ clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
+ <&clks IMX6QDL_CLK_PRG0_AXI>;
+ clock-names = "ipg", "axi";
+ fsl,pres = <&pre1>, <&pre2>, <&pre3>;
+ };
+
+ prg2: prg at 21cd000 {
+ compatible = "fsl,imx6qp-prg";
+ reg = <0x021cd000 0x1000>;
+ clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
+ <&clks IMX6QDL_CLK_PRG1_AXI>;
+ clock-names = "ipg", "axi";
+ fsl,pres = <&pre4>, <&pre2>, <&pre3>;
+ };
+ };
+ };
+};
+
+&fec {
+ /delete-property/interrupts-extended;
+ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
+ <0 119 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpc {
+ compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
+};
+
+&ipu1 {
+ compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+ fsl,prg = <&prg1>;
+};
+
+&ipu2 {
+ compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
+ fsl,prg = <&prg2>;
+};
+
+&ldb {
+ clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
+ clock-names = "di0_pll", "di1_pll",
+ "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+ "di0", "di1";
+};
+
+&mmdc0 {
+ compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
+};
+
+&pcie {
+ compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";
+};
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 03/13] power: pmic/regulator allow dm be omited by SPL
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 01/13] scripts: spl: fix typo Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 02/13] arm: dts: include dts for imx6sabresd Peng Fan
@ 2017-08-09 12:51 ` Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 04/13] Makefile: build FIT image if CONFIG_SPL_FIT_GENERATOR defined Peng Fan
` (9 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:51 UTC (permalink / raw)
To: u-boot
Allow the dm driver be omited by SPL.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Keerthy <j-keerthy@ti.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Cc: Jacob Chen <jacob-chen@iotwrt.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/power/pmic/Makefile | 4 ++--
drivers/power/regulator/Makefile | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index f7bdfa5..4abdaf6 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -5,10 +5,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
+obj-$(CONFIG_$(SPL_)DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
-obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
obj-$(CONFIG_PMIC_S2MPS11) += s2mps11.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
obj-$(CONFIG_PMIC_ACT8846) += act8846.o
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 18fb870..ec1b1e0 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR) += regulator-uclass.o
obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
-obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
+obj-$(CONFIG_$(SPL_)DM_REGULATOR_PFUZE100) += pfuze100.o
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 04/13] Makefile: build FIT image if CONFIG_SPL_FIT_GENERATOR defined
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (2 preceding siblings ...)
2017-08-09 12:51 ` [U-Boot] [patch v2 03/13] power: pmic/regulator allow dm be omited by SPL Peng Fan
@ 2017-08-09 12:51 ` Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 05/13] imx: introduce mkimage_fit.sh Peng Fan
` (8 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:51 UTC (permalink / raw)
To: u-boot
Build FIT image if CONFIG_SPL_FIT_GENERATOR defined.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: "Cooper Jr., Franklin" <fcooper@ti.com>
Cc: "Álvaro Fernández Rojas" <noltari@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
---
Makefile | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Makefile b/Makefile
index 50a002e..fbe7714 100644
--- a/Makefile
+++ b/Makefile
@@ -804,6 +804,10 @@ ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin
endif
+ifneq ($(CONFIG_SPL_FIT_GENERATOR),)
+ALL-y += u-boot.itb
+endif
+
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 05/13] imx: introduce mkimage_fit.sh
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (3 preceding siblings ...)
2017-08-09 12:51 ` [U-Boot] [patch v2 04/13] Makefile: build FIT image if CONFIG_SPL_FIT_GENERATOR defined Peng Fan
@ 2017-08-09 12:51 ` Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 06/13] imx: mx6sabresd: implement board_fit_config_name_match Peng Fan
` (7 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:51 UTC (permalink / raw)
To: u-boot
Introduce mkimage_fit.sh which is modifed from
board/sunxi/mksunxi_fit_atf.sh.
ATF is dropped and modified for arm32 arch.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/mach-imx/mkimage_fit.sh | 63 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100755 arch/arm/mach-imx/mkimage_fit.sh
diff --git a/arch/arm/mach-imx/mkimage_fit.sh b/arch/arm/mach-imx/mkimage_fit.sh
new file mode 100755
index 0000000..18628de
--- /dev/null
+++ b/arch/arm/mach-imx/mkimage_fit.sh
@@ -0,0 +1,63 @@
+#!/bin/sh
+#
+# script to generate FIT image source for 32-bit imx boards with
+# multiple device trees (given on the command line)
+#
+# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+
+cat << __HEADER_EOF
+/dts-v1/;
+
+/ {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+
+ images {
+ uboot at 1 {
+ description = "U-Boot (32-bit)";
+ data = /incbin/("u-boot-nodtb.bin");
+ type = "standalone";
+ arch = "arm32";
+ compression = "none";
+ load = <0x17800000>;
+ };
+__HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+ cat << __FDT_IMAGE_EOF
+ fdt@$cnt {
+ description = "$(basename $dtname .dtb)";
+ data = /incbin/("$dtname");
+ type = "flat_dt";
+ compression = "none";
+ };
+__FDT_IMAGE_EOF
+ cnt=$((cnt+1))
+done
+
+cat << __CONF_HEADER_EOF
+ };
+ configurations {
+ default = "config at 1";
+
+__CONF_HEADER_EOF
+
+cnt=1
+for dtname in $*
+do
+ cat << __CONF_SECTION_EOF
+ config@$cnt {
+ description = "$(basename $dtname .dtb)";
+ firmware = "uboot@1";
+ fdt = "fdt@$cnt";
+ };
+__CONF_SECTION_EOF
+ cnt=$((cnt+1))
+done
+
+cat << __ITS_EOF
+ };
+};
+__ITS_EOF
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 06/13] imx: mx6sabresd: implement board_fit_config_name_match
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (4 preceding siblings ...)
2017-08-09 12:51 ` [U-Boot] [patch v2 05/13] imx: introduce mkimage_fit.sh Peng Fan
@ 2017-08-09 12:52 ` Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 07/13] imx: mx6sabresd: enable SPL FIT Peng Fan
` (6 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:52 UTC (permalink / raw)
To: u-boot
Implement board_fit_config_name_match.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
---
board/freescale/mx6sabresd/mx6sabresd.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index e416042..ff99a30 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -734,6 +734,19 @@ int spl_start_uboot(void)
}
#endif
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ if (is_mx6dq() && !strcmp(name, "imx6q-sabresd"))
+ return 0;
+ else if (is_mx6sdl() && !strcmp(name, "imx6dl-sabresd"))
+ return 0;
+ else if (is_mx6dqp() && !strcmp(name, "imx6qp-sabresd"))
+ return 0;
+ return -EINVAL;
+}
+#endif
+
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 07/13] imx: mx6sabresd: enable SPL FIT
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (5 preceding siblings ...)
2017-08-09 12:52 ` [U-Boot] [patch v2 06/13] imx: mx6sabresd: implement board_fit_config_name_match Peng Fan
@ 2017-08-09 12:52 ` Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 08/13] scripts: spl: Disable DM MMC when SPL DM not enabled Peng Fan
` (5 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:52 UTC (permalink / raw)
To: u-boot
Enable SPL FIT. Now DM drivers are not enabled, so boards boot as before
with only the difference that loading dtb.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
---
configs/mx6sabresd_defconfig | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index e42e9c8..be3a18c 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -9,6 +9,10 @@ CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_VIDEO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd"
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit.sh"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_BOOTDELAY=3
@@ -38,6 +42,8 @@ CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="imx6q-sabresd imx6dl-sabresd imx6qp-sabresd"
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
@@ -51,4 +57,3 @@ CONFIG_G_DNL_MANUFACTURER="FSL"
CONFIG_G_DNL_VENDOR_NUM=0x0525
CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_OF_LIBFDT=y
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 08/13] scripts: spl: Disable DM MMC when SPL DM not enabled
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (6 preceding siblings ...)
2017-08-09 12:52 ` [U-Boot] [patch v2 07/13] imx: mx6sabresd: enable SPL FIT Peng Fan
@ 2017-08-09 12:52 ` Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 09/13] mmc: fsl_esdhc: switch to use CONFIG_IS_ENABLED Peng Fan
` (4 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:52 UTC (permalink / raw)
To: u-boot
Disable DM MMC when SPL DM not enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
---
scripts/Makefile.uncmd_spl | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl
index b399411..983686f 100644
--- a/scripts/Makefile.uncmd_spl
+++ b/scripts/Makefile.uncmd_spl
@@ -12,6 +12,7 @@ CONFIG_DM_GPIO=
CONFIG_DM_I2C=
CONFIG_DM_SPI=
CONFIG_DM_SPI_FLASH=
+CONFIG_DM_MMC=
endif
endif
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 09/13] mmc: fsl_esdhc: switch to use CONFIG_IS_ENABLED
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (7 preceding siblings ...)
2017-08-09 12:52 ` [U-Boot] [patch v2 08/13] scripts: spl: Disable DM MMC when SPL DM not enabled Peng Fan
@ 2017-08-09 12:52 ` Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 10/13] power: pmic.h: include dm/ofnode.h Peng Fan
` (3 subsequent siblings)
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:52 UTC (permalink / raw)
To: u-boot
Switch to use CONFIG_IS_ENABLED.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
---
drivers/mmc/fsl_esdhc.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3abd2d3..5a1c7aa 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -107,7 +107,7 @@ struct fsl_esdhc_priv {
int non_removable;
int wp_enable;
int vs18_enable;
-#ifdef CONFIG_DM_GPIO
+#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc cd_gpio;
struct gpio_desc wp_gpio;
#endif
@@ -690,10 +690,10 @@ static int esdhc_getcd(struct mmc *mmc)
return 1;
#endif
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
if (priv->non_removable)
return 1;
-#ifdef CONFIG_DM_GPIO
+#if CONFIG_IS_ENABLED(DM_GPIO)
if (dm_gpio_is_valid(&priv->cd_gpio))
return dm_gpio_get_value(&priv->cd_gpio);
#endif
@@ -825,7 +825,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
return 0;
}
-#ifndef CONFIG_DM_MMC
+#if !CONFIG_IS_ENABLED(DM_MMC)
static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
struct fsl_esdhc_priv *priv)
{
@@ -956,7 +956,7 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd)
}
#endif
-#ifdef CONFIG_DM_MMC
+#if CONFIG_IS_ENABLED(DM_MMC)
#include <asm/arch/clock.h>
__weak void init_clk_usdhc(u32 index)
{
@@ -992,7 +992,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->non_removable = 1;
} else {
priv->non_removable = 0;
-#ifdef CONFIG_DM_GPIO
+#if CONFIG_IS_ENABLED(DM_GPIO)
gpio_request_by_name_nodev(offset_to_ofnode(node), "cd-gpios",
0, &priv->cd_gpio, GPIOD_IS_IN);
#endif
@@ -1000,7 +1000,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->wp_enable = 1;
-#ifdef CONFIG_DM_GPIO
+#if CONFIG_IS_ENABLED(DM_GPIO)
ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "wp-gpios", 0,
&priv->wp_gpio, GPIOD_IS_IN);
if (ret)
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 10/13] power: pmic.h: include dm/ofnode.h
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (8 preceding siblings ...)
2017-08-09 12:52 ` [U-Boot] [patch v2 09/13] mmc: fsl_esdhc: switch to use CONFIG_IS_ENABLED Peng Fan
@ 2017-08-09 12:52 ` Peng Fan
2017-08-13 21:36 ` Simon Glass
2017-08-09 12:52 ` [U-Boot] [patch v2 11/13] board: freescale: common: add pfuze dm code Peng Fan
` (2 subsequent siblings)
12 siblings, 1 reply; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:52 UTC (permalink / raw)
To: u-boot
Include dm/ofnode.h.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
---
include/power/pmic.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/power/pmic.h b/include/power/pmic.h
index 4b34316..f2fe537 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -11,6 +11,7 @@
#ifndef __CORE_PMIC_H_
#define __CORE_PMIC_H_
+#include <dm/ofnode.h>
#include <i2c.h>
#include <linux/list.h>
#include <power/power_chrg.h>
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 11/13] board: freescale: common: add pfuze dm code
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (9 preceding siblings ...)
2017-08-09 12:52 ` [U-Boot] [patch v2 10/13] power: pmic.h: include dm/ofnode.h Peng Fan
@ 2017-08-09 12:52 ` Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 12/13] imx: mx6sabresd: enable dm drivers Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 13/13] imx: mx6sabresd: update README Peng Fan
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:52 UTC (permalink / raw)
To: u-boot
Add pfuze dm code, this code does the same thing as pfuze.c, but
only effects when CONFIG_$(SPL_)DM_PMIC_PFUZE100 enabled.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
---
board/freescale/common/Makefile | 1 +
board/freescale/common/pfuze.h | 5 +++
board/freescale/common/pfuze_dm.c | 89 +++++++++++++++++++++++++++++++++++++++
3 files changed, 95 insertions(+)
create mode 100644 board/freescale/common/pfuze_dm.c
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 1c53fb6..620dced 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze_dm.o
obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
diff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h
index 53cfc99..9c4c92a 100644
--- a/board/freescale/common/pfuze.h
+++ b/board/freescale/common/pfuze.h
@@ -7,7 +7,12 @@
#ifndef __PFUZE_BOARD_HELPER__
#define __PFUZE_BOARD_HELPER__
+#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)
+struct udevice *pfuze_common_init(void);
+int pfuze_mode_init(struct udevice *dev, u32 mode);
+#else
struct pmic *pfuze_common_init(unsigned char i2cbus);
int pfuze_mode_init(struct pmic *p, u32 mode);
+#endif
#endif
diff --git a/board/freescale/common/pfuze_dm.c b/board/freescale/common/pfuze_dm.c
new file mode 100644
index 0000000..c6af627
--- /dev/null
+++ b/board/freescale/common/pfuze_dm.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+int pfuze_mode_init(struct udevice *dev, u32 mode)
+{
+ unsigned char offset, i, switch_num;
+ u32 id;
+ int ret;
+
+ id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+ id = id & 0xf;
+
+ if (id == 0) {
+ switch_num = 6;
+ offset = PFUZE100_SW1CMODE;
+ } else if (id == 1) {
+ switch_num = 4;
+ offset = PFUZE100_SW2MODE;
+ } else {
+ printf("Not supported, id=%d\n", id);
+ return -EINVAL;
+ }
+
+ ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
+ if (ret < 0) {
+ printf("Set SW1AB mode error!\n");
+ return ret;
+ }
+
+ for (i = 0; i < switch_num - 1; i++) {
+ ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
+ if (ret < 0) {
+ printf("Set switch 0x%x mode error!\n",
+ offset + i * SWITCH_SIZE);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+struct udevice *pfuze_common_init(void)
+{
+ struct udevice *dev;
+ int ret;
+ unsigned int reg, dev_id, rev_id;
+
+ ret = pmic_get("pfuze100", &dev);
+ if (ret == -ENODEV)
+ return NULL;
+
+ dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+ rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+ printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+ reg &= ~SW1x_STBY_MASK;
+ reg |= SW1x_0_975V;
+ pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+ reg &= ~SW1xCONF_DVSSPEED_MASK;
+ reg |= SW1xCONF_DVSSPEED_4US;
+ pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+ return dev;
+}
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 12/13] imx: mx6sabresd: enable dm drivers
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (10 preceding siblings ...)
2017-08-09 12:52 ` [U-Boot] [patch v2 11/13] board: freescale: common: add pfuze dm code Peng Fan
@ 2017-08-09 12:52 ` Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 13/13] imx: mx6sabresd: update README Peng Fan
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:52 UTC (permalink / raw)
To: u-boot
Enable DM MMC/I2C/PMIC/GPIO/REGULATOR.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
board/freescale/mx6sabresd/mx6sabresd.c | 326 +++++++++++++-------------------
configs/mx6sabresd_defconfig | 15 ++
include/configs/mx6sabresd.h | 15 +-
3 files changed, 146 insertions(+), 210 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index ff99a30..845b5b5 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -12,7 +12,6 @@
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
@@ -24,7 +23,6 @@
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
-#include <i2c.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
@@ -46,14 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
- PAD_CTL_ODE | PAD_CTL_SRE_FAST)
-
-#define I2C_PMIC 1
-
-#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
-
#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
@@ -93,6 +83,7 @@ static void setup_iomux_enet(void)
{
SETUP_IOMUX_PADS(enet_pads);
+ gpio_request(IMX_GPIO_NR(1, 25), "phy_rst");
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
mdelay(10);
@@ -100,47 +91,6 @@ static void setup_iomux_enet(void)
udelay(100);
}
-static iomux_v3_cfg_t const usdhc2_pads[] = {
- IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
- IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
- IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
- IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
static iomux_v3_cfg_t const ecspi1_pads[] = {
IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
@@ -187,6 +137,7 @@ static iomux_v3_cfg_t const bl_pads[] = {
static void enable_backlight(void)
{
SETUP_IOMUX_PADS(bl_pads);
+ gpio_request(DISP0_PWR_EN, "disp0_pwr_en");
gpio_direction_output(DISP0_PWR_EN, 1);
}
@@ -201,32 +152,6 @@ static void enable_lvds(struct display_info_t const *dev)
enable_backlight();
}
-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
- .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
- .scl = {
- .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
- .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 12)
- },
- .sda = {
- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
- .gp = IMX_GPIO_NR(4, 13)
- }
-};
-
static void setup_spi(void)
{
SETUP_IOMUX_PADS(ecspi1_pads);
@@ -253,121 +178,11 @@ static void setup_iomux_uart(void)
SETUP_IOMUX_PADS(uart1_pads);
}
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg usdhc_cfg[3] = {
- {USDHC2_BASE_ADDR},
- {USDHC3_BASE_ADDR},
- {USDHC4_BASE_ADDR},
-};
-
-#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
-#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
-
int board_mmc_get_env_dev(int devno)
{
return devno - 1;
}
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
-
- switch (cfg->esdhc_base) {
- case USDHC2_BASE_ADDR:
- ret = !gpio_get_value(USDHC2_CD_GPIO);
- break;
- case USDHC3_BASE_ADDR:
- ret = !gpio_get_value(USDHC3_CD_GPIO);
- break;
- case USDHC4_BASE_ADDR:
- ret = 1; /* eMMC/uSDHC4 is always present */
- break;
- }
-
- return ret;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-#ifndef CONFIG_SPL_BUILD
- int ret;
- int i;
-
- /*
- * According to the board_mmc_init() the following map is done:
- * (U-Boot device node) (Physical Port)
- * mmc0 SD2
- * mmc1 SD3
- * mmc2 eMMC
- */
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
- switch (i) {
- case 0:
- SETUP_IOMUX_PADS(usdhc2_pads);
- gpio_direction_input(USDHC2_CD_GPIO);
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- break;
- case 1:
- SETUP_IOMUX_PADS(usdhc3_pads);
- gpio_direction_input(USDHC3_CD_GPIO);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- break;
- case 2:
- SETUP_IOMUX_PADS(usdhc4_pads);
- usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- break;
- default:
- printf("Warning: you configured more USDHC controllers"
- "(%d) then supported by the board (%d)\n",
- i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return -EINVAL;
- }
-
- ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
- if (ret)
- return ret;
- }
-
- return 0;
-#else
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr1) >> 11;
- /*
- * Upon reading BOOT_CFG register the following map is done:
- * Bit 11 and 12 of BOOT_CFG register can determine the current
- * mmc port
- * 0x1 SD1
- * 0x2 SD2
- * 0x3 SD4
- */
-
- switch (reg & 0x3) {
- case 0x1:
- SETUP_IOMUX_PADS(usdhc2_pads);
- usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x2:
- SETUP_IOMUX_PADS(usdhc3_pads);
- usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- case 0x3:
- SETUP_IOMUX_PADS(usdhc4_pads);
- usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
- break;
- }
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
-#endif
-}
-#endif
-
static int ar8031_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
@@ -580,6 +395,8 @@ static void setup_usb(void)
imx_iomux_set_gpr_register(1, 13, 1, 0);
SETUP_IOMUX_PADS(usb_hc1_pads);
+
+ gpio_request(IMX_GPIO_NR(1, 29), "usb1");
}
int board_ehci_hcd_init(int port)
@@ -632,13 +449,13 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ gpio_request(IMX_GPIO_NR(3, 19), "pcie_power");
+ gpio_request(IMX_GPIO_NR(7, 12), "pcie_reset");
+
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- if (is_mx6dq() || is_mx6dqp())
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
- else
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
@@ -646,34 +463,36 @@ int board_init(void)
return 0;
}
+#ifndef CONFIG_SPL_BUILD
int power_init_board(void)
{
- struct pmic *p;
+ struct udevice *dev;
unsigned int reg;
int ret;
- p = pfuze_common_init(I2C_PMIC);
- if (!p)
+ dev = pfuze_common_init();
+ if (!dev)
return -ENODEV;
- ret = pfuze_mode_init(p, APS_PFM);
+ ret = pfuze_mode_init(dev, APS_PFM);
if (ret < 0)
return ret;
/* Increase VGEN3 from 2.5 to 2.8V */
- pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
+ reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_2_80V;
- pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+ pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
- pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
+ reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
reg &= ~LDO_VOL_MASK;
reg |= LDOB_3_00V;
- pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+ pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
return 0;
}
+#endif
#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
@@ -747,6 +566,115 @@ int board_fit_config_name_match(const char *name)
}
#endif
+#ifdef CONFIG_FSL_ESDHC
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
+ }
+
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(&psrc->sbmr1) >> 11;
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x1 SD1
+ * 0x2 SD2
+ * 0x3 SD4
+ */
+
+ switch (reg & 0x3) {
+ case 0x1:
+ SETUP_IOMUX_PADS(usdhc2_pads);
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x2:
+ SETUP_IOMUX_PADS(usdhc3_pads);
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x3:
+ SETUP_IOMUX_PADS(usdhc4_pads);
+ usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ }
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index be3a18c..7ec158f 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -37,6 +37,8 @@ CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -44,10 +46,23 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="imx6q-sabresd imx6dl-sabresd imx6qp-sabresd"
+# CONFIG_BLK is not set
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PCI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_PFUZE100=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 27e7672..95e1666 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -46,20 +46,9 @@
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
#endif
-/* I2C Configs */
-#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
-#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
#define CONFIG_SYS_I2C_SPEED 100000
-/* PMIC */
-#define CONFIG_POWER
-#define CONFIG_POWER_I2C
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
-
/* USB Configs */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -70,4 +59,8 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
#endif
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_SYS_I2C_MXC
+#endif
+
#endif /* __MX6SABRESD_CONFIG_H */
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 13/13] imx: mx6sabresd: update README
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
` (11 preceding siblings ...)
2017-08-09 12:52 ` [U-Boot] [patch v2 12/13] imx: mx6sabresd: enable dm drivers Peng Fan
@ 2017-08-09 12:52 ` Peng Fan
12 siblings, 0 replies; 15+ messages in thread
From: Peng Fan @ 2017-08-09 12:52 UTC (permalink / raw)
To: u-boot
Update README since we use FIT now.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
board/freescale/mx6sabresd/README | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/board/freescale/mx6sabresd/README b/board/freescale/mx6sabresd/README
index 4b4df06..8b10fe7 100644
--- a/board/freescale/mx6sabresd/README
+++ b/board/freescale/mx6sabresd/README
@@ -21,15 +21,15 @@ $ make mx6sabresd_defconfig
$ make
-This will generate the SPL and u-boot.img binaries.
+This will generate the SPL and u-boot.itb binaries.
- Flash the SPL binary into the SD card:
$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
-- Flash the u-boot.img binary into the SD card:
+- Flash the u-boot.itb binary into the SD card:
-$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
+$ sudo dd if=u-boot.itb of=/dev/sdX bs=1K seek=69 && sync
2. Booting from eMMC
@@ -39,7 +39,7 @@ $ make mx6sabresd_defconfig
$ make
-This will generate the SPL and u-boot.img binaries.
+This will generate the SPL and u-boot.itb binaries.
- Boot first from SD card as shown in the previous section
@@ -51,10 +51,10 @@ Mount the eMMC in the host PC:
=> ums 0 mmc 2
-- Flash SPL and u-boot.img binaries into the eMMC:
+- Flash SPL and u-boot.itb binaries into the eMMC:
$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 && sync
-$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 && sync
+$ sudo dd if=u-boot.itb of=/dev/sdX bs=1K seek=69 && sync
Set SW6 to eMMC 8-bit boot: 11010110
@@ -65,15 +65,15 @@ Set SW6 to eMMC 8-bit boot: 11010110
$ make mx6sabresd_defconfig
$ make
-This will generate the SPL image called SPL and the u-boot.img.
+This will generate the SPL image called SPL and the u-boot.itb.
- Flash the SPL image into the SD card:
$ sudo dd if=SPL of=/dev/sdX bs=1K seek=1 oflag=sync status=none && sync
-- Flash the u-boot.img image into the SD card:
+- Flash the u-boot.itb image into the SD card:
-$ sudo dd if=u-boot.img of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync
+$ sudo dd if=u-boot.itb of=/dev/sdX bs=1K seek=69 oflag=sync status=none && sync
Create a partition for root file system and extract it there:
--
2.6.2
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [patch v2 10/13] power: pmic.h: include dm/ofnode.h
2017-08-09 12:52 ` [U-Boot] [patch v2 10/13] power: pmic.h: include dm/ofnode.h Peng Fan
@ 2017-08-13 21:36 ` Simon Glass
0 siblings, 0 replies; 15+ messages in thread
From: Simon Glass @ 2017-08-13 21:36 UTC (permalink / raw)
To: u-boot
On 9 August 2017 at 06:52, Peng Fan <peng.fan@nxp.com> wrote:
> Include dm/ofnode.h.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> include/power/pmic.h | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass <sjg@chromium.org>
Please see below.
>
> diff --git a/include/power/pmic.h b/include/power/pmic.h
> index 4b34316..f2fe537 100644
> --- a/include/power/pmic.h
> +++ b/include/power/pmic.h
> @@ -11,6 +11,7 @@
> #ifndef __CORE_PMIC_H_
> #define __CORE_PMIC_H_
>
> +#include <dm/ofnode.h>
> #include <i2c.h>
Should be under i2c.h I think
> #include <linux/list.h>
> #include <power/power_chrg.h>
> --
> 2.6.2
>
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2017-08-13 21:36 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-09 12:51 [U-Boot] [patch v2 00/13] imx: mx6sabresd: support SPL FIT Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 01/13] scripts: spl: fix typo Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 02/13] arm: dts: include dts for imx6sabresd Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 03/13] power: pmic/regulator allow dm be omited by SPL Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 04/13] Makefile: build FIT image if CONFIG_SPL_FIT_GENERATOR defined Peng Fan
2017-08-09 12:51 ` [U-Boot] [patch v2 05/13] imx: introduce mkimage_fit.sh Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 06/13] imx: mx6sabresd: implement board_fit_config_name_match Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 07/13] imx: mx6sabresd: enable SPL FIT Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 08/13] scripts: spl: Disable DM MMC when SPL DM not enabled Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 09/13] mmc: fsl_esdhc: switch to use CONFIG_IS_ENABLED Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 10/13] power: pmic.h: include dm/ofnode.h Peng Fan
2017-08-13 21:36 ` Simon Glass
2017-08-09 12:52 ` [U-Boot] [patch v2 11/13] board: freescale: common: add pfuze dm code Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 12/13] imx: mx6sabresd: enable dm drivers Peng Fan
2017-08-09 12:52 ` [U-Boot] [patch v2 13/13] imx: mx6sabresd: update README Peng Fan
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.