* [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen
@ 2017-08-09 7:41 Yi Sun
2017-08-09 7:41 ` [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
` (12 more replies)
0 siblings, 13 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
Hi, all,
We plan to bring a new PSR (Platform Shared Resource) feature called
Intel Memory Bandwidth Allocation (MBA) to Xen.
Besides the MBA enabling, we change some interfaces to make them more
general but not only for CAT.
The implementation bases on below patch set which has been merged into
staging branch.
[PATCH v15 00/23] Enable L2 Cache Allocation Technology & Refactor psr.c
https://lists.xen.org/archives/html/xen-devel/2017-08/msg00029.html
Any comments are welcome!
You can find this patch set at:
https://github.com/yisun-git/xen_mba mba_v1
---
V1 change list comparing to RFC v2:
Patch 1:
- remove a special character to avoid the error when building pandoc.
Patch 2:
- add description about what to be changed in commit message.
(suggested by Wei Liu)
- bump sysctl/domctl version numbers.
(suggested by Wei Liu)
Patch 3:
- rebase codes onto L2 CAT v15.
- use '(1u << X)'.
(suggested by Wei Liu)
- move comment to appropriate place.
(suggested by Chao Peng)
- implement 'mba_init_feature' and keep 'cat_init_feature'.
(suggested by Chao Peng)
- keep 'regs.b' into a local variable to avoid reading CPUID every time.
(suggested by Chao Peng)
Patch 5:
- sort 'PSR_INFO_IDX_' macros as feature.
(suggested by Chao Peng)
- rename 'PSR_INFO_IDX_MBA_LINEAR' to 'PSR_INFO_IDX_MBA_FLAG'.
- rename 'linear' in 'struct mba_info' to 'flags' for future extension.
(suggested by Chao Peng)
Patch 7:
- rename 'check_change_val' to 'check_val'.
(suggested by Chao Peng)
- rename 'cat_check_change_val' to 'cat_check_cbm'.
(suggested by Chao Peng)
- rename 'mba_check_change_val' to 'mba_check_thrtl'.
(suggested by Chao Peng)
Patch 8:
- change 'uint32_t target' to 'unsigned int target'.
(suggested by Wei Liu)
- change 'int nr' to 'unsigned int nr'.
(suggested by Wei Liu)
- change 'int lvl' to 'unsigned int lvl'.
- change 'EXIT_FAILURE' to 'ERROR_FAIL'.
(suggested by Wei Liu)
- add 'dir=DIR_OUT' for 'libxl_psr_hw_info'.
(suggested by Wei Liu)
Patch 9:
- remove the pointless initialization for 'xc_psr_feat_type'.
(suggested by Wei Liu)
- use 'libxl__' for internal functions.
(suggested by Wei Liu)
- change error value '-1' to 'ERROR_INVAL'.
(suggested by Wei Liu)
- remove an extraneous space.
(suggested by Wei Liu)
- replace some 'int' to 'unsigned int'.
(suggested by Wei Liu)
- remove test to macro 'LIBXL_HAVE_PSR_MBA'.
(suggested by Wei Liu)
- change 'mba_info.linear' to 'mba_info.flags'.
(suggested by Chao Peng)
- adjust print info only to show the MBA info after successfully getting
HW info.
Patch 10:
- split this patch out from next 'get value' patch.
(suggested by Wei Liu)
Yi Sun (13):
docs: create Memory Bandwidth Allocation (MBA) feature document
Rename PSR sysctl/domctl interfaces and xsm policy to make them be
general
x86: rename 'cbm_type' to 'psr_val_type' to make it general
x86: implement data structure and CPU init flow for MBA
x86: implement get hw info flow for MBA
x86: implement get value interface for MBA
x86: implement set value flow for MBA
tools: create general interfaces to support psr allocation features
tools: implement the new get hw info interface suitable to all psr
allocation features
tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type'
tools: implemet new get value interface suitable for all psr
allocation features
tools: implemet new set value interface suitable for all psr
allocation features
docs: add MBA description in docs
docs/features/intel_psr_mba.pandoc | 247 ++++++++++++++++++++++
docs/man/xl.pod.1.in | 33 +++
docs/misc/xl-psr.markdown | 60 ++++++
tools/flask/policy/modules/dom0.te | 4 +-
tools/libxc/include/xenctrl.h | 47 ++++-
tools/libxc/xc_psr.c | 88 +++++---
tools/libxl/libxl.h | 35 +++-
tools/libxl/libxl_psr.c | 227 +++++++++++++++++----
tools/libxl/libxl_types.idl | 22 ++
tools/xl/xl.h | 2 +
tools/xl/xl_cmdtable.c | 12 ++
tools/xl/xl_psr.c | 273 +++++++++++++++++++------
xen/arch/x86/domctl.c | 65 +++---
xen/arch/x86/psr.c | 394 +++++++++++++++++++++++++++---------
xen/arch/x86/sysctl.c | 47 +++--
xen/include/asm-x86/msr-index.h | 1 +
xen/include/asm-x86/psr.h | 22 +-
xen/include/public/domctl.h | 14 +-
xen/include/public/sysctl.h | 20 +-
xen/xsm/flask/hooks.c | 8 +-
xen/xsm/flask/policy/access_vectors | 8 +-
21 files changed, 1323 insertions(+), 306 deletions(-)
create mode 100644 docs/features/intel_psr_mba.pandoc
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-14 7:35 ` Chao Peng
2017-08-15 10:08 ` Wei Liu
2017-08-09 7:41 ` [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
` (11 subsequent siblings)
12 siblings, 2 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch creates MBA feature document in doc/features/. It describes
key points to implement MBA which is described in details in Intel SDM
"Introduction to Memory Bandwidth Allocation".
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v1:
- remove a special character to avoid the error when building pandoc.
---
docs/features/intel_psr_mba.pandoc | 247 +++++++++++++++++++++++++++++++++++++
1 file changed, 247 insertions(+)
create mode 100644 docs/features/intel_psr_mba.pandoc
diff --git a/docs/features/intel_psr_mba.pandoc b/docs/features/intel_psr_mba.pandoc
new file mode 100644
index 0000000..7a42edf
--- /dev/null
+++ b/docs/features/intel_psr_mba.pandoc
@@ -0,0 +1,247 @@
+% Intel Memory Bandwidth Allocation (MBA) Feature
+% Revision 1.2
+
+\clearpage
+
+# Basics
+
+---------------- ----------------------------------------------------
+ Status: **Tech Preview**
+
+Architecture(s): Intel x86
+
+ Component(s): Hypervisor, toolstack
+
+ Hardware: MBA is supported on Skylake Server and beyond
+---------------- ----------------------------------------------------
+
+# Terminology
+
+* CAT Cache Allocation Technology
+* CBM Capacity BitMasks
+* CDP Code and Data Prioritization
+* COS/CLOS Class of Service
+* MBA Memory Bandwidth Allocation
+* MSRs Machine Specific Registers
+* PSR Intel Platform Shared Resource
+* THRTL Throttle value or delay value
+
+# Overview
+
+The Memory Bandwidth Allocation (MBA) feature provides indirect and approximate
+control over memory bandwidth available per-core. This feature provides OS/
+hypervisor the ability to slow misbehaving apps/domains or create advanced
+closed-loop control system via exposing control over a credit-based throttling
+mechanism.
+
+# User details
+
+* Feature Enabling:
+
+ Add "psr=mba" to boot line parameter to enable MBA feature.
+
+* xl interfaces:
+
+ 1. `psr-mba-show [domain-id]`:
+
+ Show memory bandwidth throttling for domain.
+
+ 2. `psr-mba-set [OPTIONS] domain-id throttling`:
+
+ Set memory bandwidth throttling for domain.
+
+ Options:
+ '-s': Specify the socket to process, otherwise all sockets are processed.
+
+ Throttling value set in register implies memory bandwidth blocked, i.e.
+ higher throttling value results in lower bandwidth. The max throttling
+ value can be got through CPUID.
+
+ The response of the throttling value could be linear mode or non-linear
+ mode.
+
+ Linear mode: the input precision is defined as 100-(MBA_MAX). For instance,
+ if the MBA_MAX value is 90, the input precision is 10%. Values not an even
+ multiple of the precision (e.g., 12%) will be rounded down (e.g., to 10%
+ delay applied) by HW automatically.
+
+ Non-linear mode: input delay values are powers-of-two from zero to the
+ MBA_MAX value from CPUID. In this case any values not a power of two will
+ be rounded down the next nearest power of two by HW automatically.
+
+# Technical details
+
+MBA is a member of Intel PSR features, it shares the base PSR infrastructure
+in Xen.
+
+## Hardware perspective
+
+ MBA defines a range of MSRs to support specifying a delay value (Thrtl) per
+ COS, with details below.
+
+ ```
+ +----------------------------+----------------+
+ | MSR (per socket) | Address |
+ +----------------------------+----------------+
+ | IA32_L2_QOS_Ext_BW_Thrtl_0 | 0xD50 |
+ +----------------------------+----------------+
+ | ... | ... |
+ +----------------------------+----------------+
+ | IA32_L2_QOS_Ext_BW_Thrtl_n | 0xD50+n (n<64) |
+ +----------------------------+----------------+
+ ```
+
+ When context switch happens, the COS ID of VCPU is written to per-thread MSR
+ `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation according
+ to the throttling value stored in the COS register.
+
+## The relationship between MBA and CAT/CDP
+
+ Generally speaking, MBA is completely independent of CAT/CDP, and any
+ combination may be applied at any time, e.g. enabling MBA with CAT
+ disabled.
+
+ But it needs to be noticed that MBA shares COS infrastructure with CAT,
+ although MBA is enumerated by different CPUID leaf from CAT (which
+ indicates that the max COS of MBA may be different from CAT). In some
+ cases, a domain is permitted to have a COS that is beyond one (or more)
+ of PSR features but within the others. For instance, let's assume the max
+ COS of MBA is 8 but the max COS of L3 CAT is 16, when a domain is assigned
+ 9 as COS, the L3 CAT CBM associated to COS 9 would be enforced, but for MBA,
+ the HW works as default value is set since COS 9 is beyond the max COS (8)
+ of MBA.
+
+## Design Overview
+
+* Core COS/Thrtl association
+
+ When enforcing Memory Bandwidth Allocation, all cores of domains have
+ the same default COS (COS0) which stores the same Thrtl (0). The default
+ COS is used only in hypervisor and is transparent to tool stack and user.
+
+ System administrator can change PSR allocation policy at runtime by
+ tool stack. Since MBA shares COS with CAT/CDP, a COS corresponds to a
+ 2-tuple, like [CBM, Thrtl] with only-CAT enalbed, when CDP is enabled,
+ the COS corresponds to a 3-tuple, like [Code_CBM, Data_CBM, Thrtl]. If
+ neither CAT nor CDP is enabled, things would be easier, one COS
+ corresponds to one Thrtl.
+
+* VCPU schedule
+
+ This part reuses CAT COS infrastructure.
+
+* Multi-sockets
+
+ Different sockets may have different MBA ability (like max COS)
+ although it is consistent on the same socket. So the capability
+ of per-socket MBA is specified.
+
+ This part reuses CAT COS infrastructure.
+
+## Implementation Description
+
+* Hypervisor interfaces:
+
+ 1. Boot line param: "psr=mba" to enable the feature.
+
+ 2. SYSCTL:
+ - XEN_SYSCTL_PSR_MBA_get_info: Get system MBA information.
+
+ 3. DOMCTL:
+ - XEN_DOMCTL_PSR_MBA_OP_GET_THRTL: Get throttling for a domain.
+ - XEN_DOMCTL_PSR_MBA_OP_SET_THRTL: Set throttling for a domain.
+
+* xl interfaces:
+
+ 1. psr-mba-show [domain-id]
+ Show system/domain runtime MBA throttling value.
+ => XEN_SYSCTL_PSR_MBA_get_info/XEN_DOMCTL_PSR_MBA_OP_GET_THRTL
+
+ 2. psr-mba-set [OPTIONS] domain-id throttling
+ Set bandwidth throttling for a domain.
+ => XEN_DOMCTL_PSR_MBA_OP_SET_THRTL
+
+ 3. psr-hwinfo
+ Show PSR HW information, including L3 CAT/CDP/L2 CAT/MBA.
+ => XEN_SYSCTL_PSR_MBA_get_info
+
+* Key data structure:
+
+ 1. Feature HW info
+
+ ```
+ struct {
+ unsigned int thrtl_max;
+ unsigned int linear;
+ } mba_info;
+
+ - Member `thrtl_max`
+
+ `thrtl_max` is the max throttling value to be set.
+
+ - Member `linear`
+
+ `linear` means the response of delay value is linear or not.
+
+ As mentioned above, MBA is a member of Intel PSR features, it would
+ share the base PSR infrastructure in Xen. For example, the 'cos_max'
+ is a common HW property for all features. So, for other data structure
+ details, please refer 'intel_psr_cat_cdp.pandoc'.
+
+# Limitations
+
+MBA can only work on HW which enables it (check by CPUID).
+
+# Testing
+
+We can execute these commands to verify MBA on different HWs supporting them.
+
+For example:
+ root@:~$ xl psr-hwinfo --mba
+ Memory Bandwidth Allocation (MBA):
+ Socket ID : 0
+ Linear Mode : Enabled
+ Maximum COS : 7
+ Maximum Throttling Value: 90
+ Default Throttling Value: 0
+
+ root@:~$ xl psr-mba-set 1 0xa
+
+ root@:~$ xl psr-mba-show 1
+ Socket ID : 0
+ Default THRTL : 0
+ ID NAME THRTL
+ 1 ubuntu14 0xa
+
+# Areas for improvement
+
+A hexadecimal number is used to show THRTL for a domain now. It may not be user-
+friendly.
+
+To improve this, the libxl interfaces can be wrapped in libvirt to provide more
+usr-friendly interfaces to user, e.g. a percentage number to show for linear
+mode.
+
+# Known issues
+
+N/A
+
+# References
+
+"INTEL RESOURCE DIRECTOR TECHNOLOGY (INTEL RDT) ALLOCATION FEATURES" [Intel 64 and IA-32 Architectures Software Developer Manuals, vol3](http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html)
+
+# History
+
+------------------------------------------------------------------------
+Date Revision Version Notes
+---------- -------- -------- -------------------------------------------
+2017-01-10 1.0 Xen 4.9 Design document written
+2017-07-10 1.1 Xen 4.10 Changes:
+ 1. Modify data structure according to latest
+ codes;
+ 2. Add content for 'Areas for improvement';
+ 3. Other minor changes.
+2017-08-09 1.2 Xen 4.10 Changes:
+ 1. Remove a special character to avoid error when
+ building pandoc.
+---------- -------- -------- -------------------------------------------
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-08-09 7:41 ` [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-15 10:12 ` Wei Liu
2017-08-15 14:03 ` Daniel De Graaf
2017-08-09 7:41 ` [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general Yi Sun
` (10 subsequent siblings)
12 siblings, 2 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch renames PSR sysctl/domctl interfaces and related xsm policy to
make them be general for all resource allocation features but not only
for CAT. Then, we can resuse the interfaces for all allocation features.
Basically, it changes 'cat' to 'alloc'. E.g.:
1. psr_cat_op -> psr_alloc_op
2. XEN_DOMCTL_psr_cat_op -> XEN_DOMCTL_psr_alloc_op
3. XEN_SYSCTL_psr_cat_op -> XEN_SYSCTL_psr_alloc_op
The sysctl/domctl version numbers are bumped.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v1:
- add description about what to be changed in commit message.
(suggested by Wei Liu)
- bump sysctl/domctl version numbers.
(suggested by Wei Liu)
---
tools/flask/policy/modules/dom0.te | 4 ++--
tools/libxc/xc_psr.c | 34 +++++++++++++++++-----------------
xen/arch/x86/domctl.c | 36 ++++++++++++++++++------------------
xen/arch/x86/sysctl.c | 24 ++++++++++++------------
xen/include/public/domctl.h | 12 ++++++------
xen/include/public/sysctl.h | 12 ++++++------
xen/xsm/flask/hooks.c | 8 ++++----
xen/xsm/flask/policy/access_vectors | 8 ++++----
8 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/tools/flask/policy/modules/dom0.te b/tools/flask/policy/modules/dom0.te
index d0a4d91..1a376ac 100644
--- a/tools/flask/policy/modules/dom0.te
+++ b/tools/flask/policy/modules/dom0.te
@@ -14,7 +14,7 @@ allow dom0_t xen_t:xen {
tmem_control getscheduler setscheduler
};
allow dom0_t xen_t:xen2 {
- resource_op psr_cmt_op psr_cat_op pmu_ctrl get_symbol
+ resource_op psr_cmt_op psr_alloc_op pmu_ctrl get_symbol
get_cpu_levelling_caps get_cpu_featureset livepatch_op
gcov_op
};
@@ -39,7 +39,7 @@ allow dom0_t dom0_t:domain {
};
allow dom0_t dom0_t:domain2 {
set_cpuid gettsc settsc setscheduler set_max_evtchn set_vnumainfo
- get_vnumainfo psr_cmt_op psr_cat_op
+ get_vnumainfo psr_cmt_op psr_alloc_op
};
allow dom0_t dom0_t:resource { add remove };
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 039b920..73d05f2 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -274,11 +274,11 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
return -1;
}
- domctl.cmd = XEN_DOMCTL_psr_cat_op;
+ domctl.cmd = XEN_DOMCTL_psr_alloc_op;
domctl.domain = (domid_t)domid;
- domctl.u.psr_cat_op.cmd = cmd;
- domctl.u.psr_cat_op.target = target;
- domctl.u.psr_cat_op.data = data;
+ domctl.u.psr_alloc_op.cmd = cmd;
+ domctl.u.psr_alloc_op.target = target;
+ domctl.u.psr_alloc_op.data = data;
return do_domctl(xch, &domctl);
}
@@ -310,15 +310,15 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
return -1;
}
- domctl.cmd = XEN_DOMCTL_psr_cat_op;
+ domctl.cmd = XEN_DOMCTL_psr_alloc_op;
domctl.domain = (domid_t)domid;
- domctl.u.psr_cat_op.cmd = cmd;
- domctl.u.psr_cat_op.target = target;
+ domctl.u.psr_alloc_op.cmd = cmd;
+ domctl.u.psr_alloc_op.target = target;
rc = do_domctl(xch, &domctl);
if ( !rc )
- *data = domctl.u.psr_cat_op.data;
+ *data = domctl.u.psr_alloc_op.data;
return rc;
}
@@ -329,29 +329,29 @@ int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
int rc = -1;
DECLARE_SYSCTL;
- sysctl.cmd = XEN_SYSCTL_psr_cat_op;
- sysctl.u.psr_cat_op.target = socket;
+ sysctl.cmd = XEN_SYSCTL_psr_alloc_op;
+ sysctl.u.psr_alloc_op.target = socket;
switch ( lvl )
{
case 2:
- sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
+ sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_cat_op.u.cat_info.cos_max;
- *cbm_len = sysctl.u.psr_cat_op.u.cat_info.cbm_len;
+ *cos_max = sysctl.u.psr_alloc_op.u.cat_info.cos_max;
+ *cbm_len = sysctl.u.psr_alloc_op.u.cat_info.cbm_len;
*cdp_enabled = false;
}
break;
case 3:
- sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
+ sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_cat_op.u.cat_info.cos_max;
- *cbm_len = sysctl.u.psr_cat_op.u.cat_info.cbm_len;
- *cdp_enabled = sysctl.u.psr_cat_op.u.cat_info.flags &
+ *cos_max = sysctl.u.psr_alloc_op.u.cat_info.cos_max;
+ *cbm_len = sysctl.u.psr_alloc_op.u.cat_info.cbm_len;
+ *cdp_enabled = sysctl.u.psr_alloc_op.u.cat_info.flags &
XEN_SYSCTL_PSR_CAT_L3_CDP;
}
break;
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 127c84e..24b998b 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1439,60 +1439,60 @@ long arch_do_domctl(
}
break;
- case XEN_DOMCTL_psr_cat_op:
- switch ( domctl->u.psr_cat_op.cmd )
+ case XEN_DOMCTL_psr_alloc_op:
+ switch ( domctl->u.psr_alloc_op.cmd )
{
uint32_t val32;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3_CODE);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L3_DATA);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
- ret = psr_set_val(d, domctl->u.psr_cat_op.target,
- domctl->u.psr_cat_op.data,
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
PSR_CBM_TYPE_L2);
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&val32, PSR_CBM_TYPE_L3);
- domctl->u.psr_cat_op.data = val32;
+ domctl->u.psr_alloc_op.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&val32, PSR_CBM_TYPE_L3_CODE);
- domctl->u.psr_cat_op.data = val32;
+ domctl->u.psr_alloc_op.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&val32, PSR_CBM_TYPE_L3_DATA);
- domctl->u.psr_cat_op.data = val32;
+ domctl->u.psr_alloc_op.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM:
- ret = psr_get_val(d, domctl->u.psr_cat_op.target,
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&val32, PSR_CBM_TYPE_L2);
- domctl->u.psr_cat_op.data = val32;
+ domctl->u.psr_alloc_op.data = val32;
copyback = true;
break;
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index 14c12b7..3051843 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -171,45 +171,45 @@ long arch_do_sysctl(
break;
- case XEN_SYSCTL_psr_cat_op:
- switch ( sysctl->u.psr_cat_op.cmd )
+ case XEN_SYSCTL_psr_alloc_op:
+ switch ( sysctl->u.psr_alloc_op.cmd )
{
uint32_t data[PSR_INFO_ARRAY_SIZE];
case XEN_SYSCTL_PSR_CAT_get_l3_info:
{
- ret = psr_get_info(sysctl->u.psr_cat_op.target,
+ ret = psr_get_info(sysctl->u.psr_alloc_op.target,
PSR_CBM_TYPE_L3, data, ARRAY_SIZE(data));
if ( ret )
break;
- sysctl->u.psr_cat_op.u.cat_info.cos_max =
+ sysctl->u.psr_alloc_op.u.cat_info.cos_max =
data[PSR_INFO_IDX_COS_MAX];
- sysctl->u.psr_cat_op.u.cat_info.cbm_len =
+ sysctl->u.psr_alloc_op.u.cat_info.cbm_len =
data[PSR_INFO_IDX_CAT_CBM_LEN];
- sysctl->u.psr_cat_op.u.cat_info.flags =
+ sysctl->u.psr_alloc_op.u.cat_info.flags =
data[PSR_INFO_IDX_CAT_FLAG];
- if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) )
+ if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc_op) )
ret = -EFAULT;
break;
}
case XEN_SYSCTL_PSR_CAT_get_l2_info:
{
- ret = psr_get_info(sysctl->u.psr_cat_op.target,
+ ret = psr_get_info(sysctl->u.psr_alloc_op.target,
PSR_CBM_TYPE_L2, data, ARRAY_SIZE(data));
if ( ret )
break;
- sysctl->u.psr_cat_op.u.cat_info.cos_max =
+ sysctl->u.psr_alloc_op.u.cat_info.cos_max =
data[PSR_INFO_IDX_COS_MAX];
- sysctl->u.psr_cat_op.u.cat_info.cbm_len =
+ sysctl->u.psr_alloc_op.u.cat_info.cbm_len =
data[PSR_INFO_IDX_CAT_CBM_LEN];
- sysctl->u.psr_cat_op.u.cat_info.flags =
+ sysctl->u.psr_alloc_op.u.cat_info.flags =
data[PSR_INFO_IDX_CAT_FLAG];
- if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) )
+ if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc_op) )
ret = -EFAULT;
break;
}
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 0669c31..4bb4399 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -37,7 +37,7 @@
#include "hvm/save.h"
#include "memory.h"
-#define XEN_DOMCTL_INTERFACE_VERSION 0x0000000e
+#define XEN_DOMCTL_INTERFACE_VERSION 0x0000000f
/*
* NB. xen_domctl.domain is an IN/OUT parameter for this operation.
@@ -1135,7 +1135,7 @@ struct xen_domctl_monitor_op {
typedef struct xen_domctl_monitor_op xen_domctl_monitor_op_t;
DEFINE_XEN_GUEST_HANDLE(xen_domctl_monitor_op_t);
-struct xen_domctl_psr_cat_op {
+struct xen_domctl_psr_alloc_op {
#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM 0
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM 1
#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE 2
@@ -1148,8 +1148,8 @@ struct xen_domctl_psr_cat_op {
uint32_t target; /* IN */
uint64_t data; /* IN/OUT */
};
-typedef struct xen_domctl_psr_cat_op xen_domctl_psr_cat_op_t;
-DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_cat_op_t);
+typedef struct xen_domctl_psr_alloc_op xen_domctl_psr_alloc_op_t;
+DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_alloc_op_t);
struct xen_domctl {
uint32_t cmd;
@@ -1226,7 +1226,7 @@ struct xen_domctl {
#define XEN_DOMCTL_setvnumainfo 74
#define XEN_DOMCTL_psr_cmt_op 75
#define XEN_DOMCTL_monitor_op 77
-#define XEN_DOMCTL_psr_cat_op 78
+#define XEN_DOMCTL_psr_alloc_op 78
#define XEN_DOMCTL_soft_reset 79
#define XEN_DOMCTL_gdbsx_guestmemio 1000
#define XEN_DOMCTL_gdbsx_pausevcpu 1001
@@ -1289,7 +1289,7 @@ struct xen_domctl {
struct xen_domctl_vnuma vnuma;
struct xen_domctl_psr_cmt_op psr_cmt_op;
struct xen_domctl_monitor_op monitor_op;
- struct xen_domctl_psr_cat_op psr_cat_op;
+ struct xen_domctl_psr_alloc_op psr_alloc_op;
uint8_t pad[128];
} u;
};
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 9e51af6..fcebab1 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -36,7 +36,7 @@
#include "physdev.h"
#include "tmem.h"
-#define XEN_SYSCTL_INTERFACE_VERSION 0x0000000F
+#define XEN_SYSCTL_INTERFACE_VERSION 0x00000010
/*
* Read console content from Xen buffer ring.
@@ -745,7 +745,7 @@ DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
#define XEN_SYSCTL_PSR_CAT_get_l2_info 1
-struct xen_sysctl_psr_cat_op {
+struct xen_sysctl_psr_alloc_op {
uint32_t cmd; /* IN: XEN_SYSCTL_PSR_CAT_* */
uint32_t target; /* IN */
union {
@@ -757,8 +757,8 @@ struct xen_sysctl_psr_cat_op {
} cat_info;
} u;
};
-typedef struct xen_sysctl_psr_cat_op xen_sysctl_psr_cat_op_t;
-DEFINE_XEN_GUEST_HANDLE(xen_sysctl_psr_cat_op_t);
+typedef struct xen_sysctl_psr_alloc_op xen_sysctl_psr_alloc_op_t;
+DEFINE_XEN_GUEST_HANDLE(xen_sysctl_psr_alloc_op_t);
#define XEN_SYSCTL_TMEM_OP_ALL_CLIENTS 0xFFFFU
@@ -1119,7 +1119,7 @@ struct xen_sysctl {
#define XEN_SYSCTL_gcov_op 20
#define XEN_SYSCTL_psr_cmt_op 21
#define XEN_SYSCTL_pcitopoinfo 22
-#define XEN_SYSCTL_psr_cat_op 23
+#define XEN_SYSCTL_psr_alloc_op 23
#define XEN_SYSCTL_tmem_op 24
#define XEN_SYSCTL_get_cpu_levelling_caps 25
#define XEN_SYSCTL_get_cpu_featureset 26
@@ -1147,7 +1147,7 @@ struct xen_sysctl {
struct xen_sysctl_scheduler_op scheduler_op;
struct xen_sysctl_gcov_op gcov_op;
struct xen_sysctl_psr_cmt_op psr_cmt_op;
- struct xen_sysctl_psr_cat_op psr_cat_op;
+ struct xen_sysctl_psr_alloc_op psr_alloc_op;
struct xen_sysctl_tmem_op tmem_op;
struct xen_sysctl_cpu_levelling_caps cpu_levelling_caps;
struct xen_sysctl_cpu_featureset cpu_featureset;
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index fd84ac0..95aff21 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -742,8 +742,8 @@ static int flask_domctl(struct domain *d, int cmd)
case XEN_DOMCTL_psr_cmt_op:
return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_CMT_OP);
- case XEN_DOMCTL_psr_cat_op:
- return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_CAT_OP);
+ case XEN_DOMCTL_psr_alloc_op:
+ return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_ALLOC_OP);
case XEN_DOMCTL_soft_reset:
return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__SOFT_RESET);
@@ -806,9 +806,9 @@ static int flask_sysctl(int cmd)
case XEN_SYSCTL_psr_cmt_op:
return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
XEN2__PSR_CMT_OP, NULL);
- case XEN_SYSCTL_psr_cat_op:
+ case XEN_SYSCTL_psr_alloc_op:
return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
- XEN2__PSR_CAT_OP, NULL);
+ XEN2__PSR_ALLOC_OP, NULL);
case XEN_SYSCTL_tmem_op:
return domain_has_xen(current->domain, XEN__TMEM_CONTROL);
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 1f7eb35..9d81e41 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -85,8 +85,8 @@ class xen2
resource_op
# XEN_SYSCTL_psr_cmt_op
psr_cmt_op
-# XEN_SYSCTL_psr_cat_op
- psr_cat_op
+# XEN_SYSCTL_psr_alloc_op
+ psr_alloc_op
# XENPF_get_symbol
get_symbol
# PMU control
@@ -244,8 +244,8 @@ class domain2
mem_paging
# XENMEM_sharing_op
mem_sharing
-# XEN_DOMCTL_psr_cat_op
- psr_cat_op
+# XEN_DOMCTL_psr_alloc_op
+ psr_alloc_op
}
# Similar to class domain, but primarily contains domctls related to HVM domains
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-08-09 7:41 ` [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-08-09 7:41 ` [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-15 10:13 ` Wei Liu
2017-08-16 2:17 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA Yi Sun
` (9 subsequent siblings)
12 siblings, 2 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch renames 'cbm_type' to 'psr_val_type' to make it be general.
Then, we can reuse this for all psr allocation features.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/domctl.c | 16 ++++++-------
xen/arch/x86/psr.c | 59 +++++++++++++++++++++++++----------------------
xen/arch/x86/sysctl.c | 4 ++--
xen/include/asm-x86/psr.h | 18 +++++++--------
4 files changed, 50 insertions(+), 47 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 24b998b..850742a 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1447,51 +1447,51 @@ long arch_do_domctl(
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM:
ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3);
+ PSR_VAL_TYPE_L3);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CODE:
ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3_CODE);
+ PSR_VAL_TYPE_L3_CODE);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L3_DATA:
ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L3_DATA);
+ PSR_VAL_TYPE_L3_DATA);
break;
case XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM:
ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
domctl->u.psr_alloc_op.data,
- PSR_CBM_TYPE_L2);
+ PSR_VAL_TYPE_L2);
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
- &val32, PSR_CBM_TYPE_L3);
+ &val32, PSR_VAL_TYPE_L3);
domctl->u.psr_alloc_op.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CODE:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
- &val32, PSR_CBM_TYPE_L3_CODE);
+ &val32, PSR_VAL_TYPE_L3_CODE);
domctl->u.psr_alloc_op.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
- &val32, PSR_CBM_TYPE_L3_DATA);
+ &val32, PSR_VAL_TYPE_L3_DATA);
domctl->u.psr_alloc_op.data = val32;
copyback = true;
break;
case XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
- &val32, PSR_CBM_TYPE_L2);
+ &val32, PSR_VAL_TYPE_L2);
domctl->u.psr_alloc_op.data = val32;
copyback = true;
break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 6ba070f..5ec00a9 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -100,24 +100,24 @@ static const struct feat_props {
unsigned int cos_num;
/*
- * An array to save all 'enum cbm_type' values of the feature. It is
+ * An array to save all 'enum psr_val_type' values of the feature. It is
* used with cos_num together to get/write a feature's COS registers
* values one by one.
*/
- enum cbm_type type[MAX_COS_NUM];
+ enum psr_val_type type[MAX_COS_NUM];
/*
* alt_type is 'alternative type'. When this 'alt_type' is input, the
* feature does some special operations.
*/
- enum cbm_type alt_type;
+ enum psr_val_type alt_type;
/* get_feat_info is used to return feature HW info through sysctl. */
bool (*get_feat_info)(const struct feat_node *feat,
uint32_t data[], unsigned int array_len);
/* write_msr is used to write out feature MSR register. */
- void (*write_msr)(unsigned int cos, uint32_t val, enum cbm_type type);
+ void (*write_msr)(unsigned int cos, uint32_t val, enum psr_val_type type);
} *feat_props[FEAT_TYPE_NUM];
/*
@@ -216,13 +216,13 @@ static void free_socket_resources(unsigned int socket)
bitmap_zero(info->dom_set, DOMID_IDLE + 1);
}
-static enum psr_feat_type psr_cbm_type_to_feat_type(enum cbm_type type)
+static enum psr_feat_type psr_val_type_to_feat_type(enum psr_val_type type)
{
enum psr_feat_type feat_type = FEAT_TYPE_UNKNOWN;
switch ( type )
{
- case PSR_CBM_TYPE_L3:
+ case PSR_VAL_TYPE_L3:
feat_type = FEAT_TYPE_L3_CAT;
/*
@@ -234,12 +234,12 @@ static enum psr_feat_type psr_cbm_type_to_feat_type(enum cbm_type type)
break;
- case PSR_CBM_TYPE_L3_DATA:
- case PSR_CBM_TYPE_L3_CODE:
+ case PSR_VAL_TYPE_L3_DATA:
+ case PSR_VAL_TYPE_L3_CODE:
feat_type = FEAT_TYPE_L3_CDP;
break;
- case PSR_CBM_TYPE_L2:
+ case PSR_VAL_TYPE_L2:
feat_type = FEAT_TYPE_L2_CAT;
break;
@@ -363,15 +363,16 @@ static bool cat_get_feat_info(const struct feat_node *feat,
}
/* L3 CAT props */
-static void l3_cat_write_msr(unsigned int cos, uint32_t val, enum cbm_type type)
+static void l3_cat_write_msr(unsigned int cos, uint32_t val,
+ enum psr_val_type type)
{
wrmsrl(MSR_IA32_PSR_L3_MASK(cos), val);
}
static const struct feat_props l3_cat_props = {
.cos_num = 1,
- .type[0] = PSR_CBM_TYPE_L3,
- .alt_type = PSR_CBM_TYPE_UNKNOWN,
+ .type[0] = PSR_VAL_TYPE_L3,
+ .alt_type = PSR_VAL_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l3_cat_write_msr,
};
@@ -388,9 +389,10 @@ static bool l3_cdp_get_feat_info(const struct feat_node *feat,
return true;
}
-static void l3_cdp_write_msr(unsigned int cos, uint32_t val, enum cbm_type type)
+static void l3_cdp_write_msr(unsigned int cos, uint32_t val,
+ enum psr_val_type type)
{
- wrmsrl(((type == PSR_CBM_TYPE_L3_DATA) ?
+ wrmsrl(((type == PSR_VAL_TYPE_L3_DATA) ?
MSR_IA32_PSR_L3_MASK_DATA(cos) :
MSR_IA32_PSR_L3_MASK_CODE(cos)),
val);
@@ -398,23 +400,24 @@ static void l3_cdp_write_msr(unsigned int cos, uint32_t val, enum cbm_type type)
static const struct feat_props l3_cdp_props = {
.cos_num = 2,
- .type[0] = PSR_CBM_TYPE_L3_DATA,
- .type[1] = PSR_CBM_TYPE_L3_CODE,
- .alt_type = PSR_CBM_TYPE_L3,
+ .type[0] = PSR_VAL_TYPE_L3_DATA,
+ .type[1] = PSR_VAL_TYPE_L3_CODE,
+ .alt_type = PSR_VAL_TYPE_L3,
.get_feat_info = l3_cdp_get_feat_info,
.write_msr = l3_cdp_write_msr,
};
/* L2 CAT props */
-static void l2_cat_write_msr(unsigned int cos, uint32_t val, enum cbm_type type)
+static void l2_cat_write_msr(unsigned int cos, uint32_t val,
+ enum psr_val_type type)
{
wrmsrl(MSR_IA32_PSR_L2_MASK(cos), val);
}
static const struct feat_props l2_cat_props = {
.cos_num = 1,
- .type[0] = PSR_CBM_TYPE_L2,
- .alt_type = PSR_CBM_TYPE_UNKNOWN,
+ .type[0] = PSR_VAL_TYPE_L2,
+ .alt_type = PSR_VAL_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l2_cat_write_msr,
};
@@ -655,7 +658,7 @@ static struct psr_socket_info *get_socket_info(unsigned int socket)
return socket_info + socket;
}
-int psr_get_info(unsigned int socket, enum cbm_type type,
+int psr_get_info(unsigned int socket, enum psr_val_type type,
uint32_t data[], unsigned int array_len)
{
const struct psr_socket_info *info = get_socket_info(socket);
@@ -667,7 +670,7 @@ int psr_get_info(unsigned int socket, enum cbm_type type,
if ( IS_ERR(info) )
return PTR_ERR(info);
- feat_type = psr_cbm_type_to_feat_type(type);
+ feat_type = psr_val_type_to_feat_type(type);
if ( feat_type >= ARRAY_SIZE(info->features) )
return -ENOENT;
@@ -688,7 +691,7 @@ int psr_get_info(unsigned int socket, enum cbm_type type,
}
int psr_get_val(struct domain *d, unsigned int socket,
- uint32_t *val, enum cbm_type type)
+ uint32_t *val, enum psr_val_type type)
{
const struct psr_socket_info *info = get_socket_info(socket);
const struct feat_node *feat;
@@ -700,7 +703,7 @@ int psr_get_val(struct domain *d, unsigned int socket,
if ( IS_ERR(info) )
return PTR_ERR(info);
- feat_type = psr_cbm_type_to_feat_type(type);
+ feat_type = psr_val_type_to_feat_type(type);
if ( feat_type >= ARRAY_SIZE(info->features) )
return -ENOENT;
@@ -830,7 +833,7 @@ static int insert_val_into_array(uint32_t val[],
unsigned int array_len,
const struct psr_socket_info *info,
enum psr_feat_type feat_type,
- enum cbm_type type,
+ enum psr_val_type type,
uint32_t new_val)
{
const struct feat_node *feat;
@@ -866,7 +869,7 @@ static int insert_val_into_array(uint32_t val[],
/*
* Value setting position is same as feature array.
* For CDP, user may set both DATA and CODE to same value. For such case,
- * user input 'PSR_CBM_TYPE_L3' as type. The alternative type of CDP is same
+ * user input 'PSR_VAL_TYPE_L3' as type. The alternative type of CDP is same
* as it. So we should set new_val to both of DATA and CODE under such case.
*/
for ( i = 0; i < props->cos_num; i++ )
@@ -1156,7 +1159,7 @@ static int write_psr_msrs(unsigned int socket, unsigned int cos,
}
int psr_set_val(struct domain *d, unsigned int socket,
- uint64_t new_val, enum cbm_type type)
+ uint64_t new_val, enum psr_val_type type)
{
unsigned int old_cos, array_len;
int cos, ret;
@@ -1172,7 +1175,7 @@ int psr_set_val(struct domain *d, unsigned int socket,
if ( new_val != val )
return -EINVAL;
- feat_type = psr_cbm_type_to_feat_type(type);
+ feat_type = psr_val_type_to_feat_type(type);
if ( feat_type >= ARRAY_SIZE(info->features) ||
!info->features[feat_type] )
return -ENOENT;
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index 3051843..b4fc1d5 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -179,7 +179,7 @@ long arch_do_sysctl(
case XEN_SYSCTL_PSR_CAT_get_l3_info:
{
ret = psr_get_info(sysctl->u.psr_alloc_op.target,
- PSR_CBM_TYPE_L3, data, ARRAY_SIZE(data));
+ PSR_VAL_TYPE_L3, data, ARRAY_SIZE(data));
if ( ret )
break;
@@ -198,7 +198,7 @@ long arch_do_sysctl(
case XEN_SYSCTL_PSR_CAT_get_l2_info:
{
ret = psr_get_info(sysctl->u.psr_alloc_op.target,
- PSR_CBM_TYPE_L2, data, ARRAY_SIZE(data));
+ PSR_VAL_TYPE_L2, data, ARRAY_SIZE(data));
if ( ret )
break;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 18a42f3..1b6f22f 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -53,12 +53,12 @@ struct psr_cmt {
struct psr_cmt_l3 l3;
};
-enum cbm_type {
- PSR_CBM_TYPE_L3,
- PSR_CBM_TYPE_L3_CODE,
- PSR_CBM_TYPE_L3_DATA,
- PSR_CBM_TYPE_L2,
- PSR_CBM_TYPE_UNKNOWN,
+enum psr_val_type {
+ PSR_VAL_TYPE_L3,
+ PSR_VAL_TYPE_L3_CODE,
+ PSR_VAL_TYPE_L3_DATA,
+ PSR_VAL_TYPE_L2,
+ PSR_VAL_TYPE_UNKNOWN,
};
extern struct psr_cmt *psr_cmt;
@@ -72,12 +72,12 @@ int psr_alloc_rmid(struct domain *d);
void psr_free_rmid(struct domain *d);
void psr_ctxt_switch_to(struct domain *d);
-int psr_get_info(unsigned int socket, enum cbm_type type,
+int psr_get_info(unsigned int socket, enum psr_val_type type,
uint32_t data[], unsigned int array_len);
int psr_get_val(struct domain *d, unsigned int socket,
- uint32_t *val, enum cbm_type type);
+ uint32_t *val, enum psr_val_type type);
int psr_set_val(struct domain *d, unsigned int socket,
- uint64_t val, enum cbm_type type);
+ uint64_t val, enum psr_val_type type);
void psr_domain_init(struct domain *d);
void psr_domain_free(struct domain *d);
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (2 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-15 10:50 ` Wei Liu
2017-08-16 3:14 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 05/13] x86: implement get hw info " Yi Sun
` (8 subsequent siblings)
12 siblings, 2 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch implements main data structures of MBA.
Like CAT features, MBA HW info has cos_max which means the max cos
registers number, and thrtl_max which means the max throttle value
(delay value). It also has a flag to represent if the throttle
value is linear or not.
One COS register of MBA stores a throttle value for one or more
domains. The throttle value means the transaction time between L2
cache and next level memory to be delayed.
This patch also implements init flow for MBA and register stub
callback functions.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v1:
- rebase codes onto L2 CAT v15.
- use '(1u << X)'.
(suggested by Wei Liu)
- move comment to appropriate place.
(suggested by Chao Peng)
- implement 'mba_init_feature' and keep 'cat_init_feature'.
(suggested by Chao Peng)
- keep 'regs.b' into a local variable to avoid reading CPUID every time.
(suggested by Chao Peng)
---
xen/arch/x86/psr.c | 144 ++++++++++++++++++++++++++++++++++------
xen/include/asm-x86/msr-index.h | 1 +
xen/include/asm-x86/psr.h | 2 +
3 files changed, 126 insertions(+), 21 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 5ec00a9..d94a5b1 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -27,13 +27,16 @@
* - CMT Cache Monitoring Technology
* - COS/CLOS Class of Service. Also mean COS registers.
* - COS_MAX Max number of COS for the feature (minus 1)
+ * - MBA Memory Bandwidth Allocation
* - MSRs Machine Specific Registers
* - PSR Intel Platform Shared Resource
+ * - THRTL_MAX Max throttle value (delay value) of MBA
*/
-#define PSR_CMT (1<<0)
-#define PSR_CAT (1<<1)
-#define PSR_CDP (1<<2)
+#define PSR_CMT (1u << 0)
+#define PSR_CAT (1u << 1)
+#define PSR_CDP (1u << 2)
+#define PSR_MBA (1u << 3)
#define CAT_CBM_LEN_MASK 0x1f
#define CAT_COS_MAX_MASK 0xffff
@@ -60,10 +63,14 @@
*/
#define MAX_COS_NUM 2
+#define MBA_LINEAR (1u << 2)
+#define MBA_THRTL_MAX_MASK 0xfff
+
enum psr_feat_type {
FEAT_TYPE_L3_CAT,
FEAT_TYPE_L3_CDP,
FEAT_TYPE_L2_CAT,
+ FEAT_TYPE_MBA,
FEAT_TYPE_NUM,
FEAT_TYPE_UNKNOWN,
};
@@ -71,7 +78,6 @@ enum psr_feat_type {
/*
* This structure represents one feature.
* cos_max - The max COS registers number got through CPUID.
- * cbm_len - The length of CBM got through CPUID.
* cos_reg_val - Array to store the values of COS registers. One entry stores
* the value of one COS register.
* For L3 CAT and L2 CAT, one entry corresponds to one COS_ID.
@@ -80,9 +86,23 @@ enum psr_feat_type {
* cos_reg_val[1] (Code).
*/
struct feat_node {
- /* cos_max and cbm_len are common values for all features so far. */
+ /* cos_max is common values for all features so far. */
unsigned int cos_max;
- unsigned int cbm_len;
+
+ /* Feature specific HW info. */
+ union {
+ struct {
+ /* The length of CBM got through CPUID. */
+ unsigned int cbm_len;
+ } cat_info;
+
+ struct {
+ /* The max throttling value got through CPUID. */
+ unsigned int thrtl_max;
+ unsigned int linear;
+ } mba_info;
+ };
+
uint32_t cos_reg_val[MAX_COS_REG_CNT];
};
@@ -161,6 +181,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
*/
static struct feat_node *feat_l3;
static struct feat_node *feat_l2_cat;
+static struct feat_node *feat_mba;
/* Common functions */
#define cat_default_val(len) (0xffffffff >> (32 - (len)))
@@ -273,7 +294,7 @@ static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
return true;
}
-/* CAT common functions implementation. */
+/* Implementation of allocation features' functions. */
static int cat_init_feature(const struct cpuid_leaf *regs,
struct feat_node *feat,
struct psr_socket_info *info,
@@ -289,7 +310,6 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
if ( !regs->a || !regs->d )
return -ENOENT;
- feat->cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1;
feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK);
switch ( type )
@@ -299,13 +319,15 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
if ( feat->cos_max < 1 )
return -ENOENT;
+ feat->cat_info.cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1;
+
/* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */
- feat->cos_reg_val[0] = cat_default_val(feat->cbm_len);
+ feat->cos_reg_val[0] = cat_default_val(feat->cat_info.cbm_len);
wrmsrl((type == FEAT_TYPE_L3_CAT ?
MSR_IA32_PSR_L3_MASK(0) :
MSR_IA32_PSR_L2_MASK(0)),
- cat_default_val(feat->cbm_len));
+ cat_default_val(feat->cat_info.cbm_len));
break;
@@ -316,15 +338,19 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
if ( feat->cos_max < 3 )
return -ENOENT;
+ feat->cat_info.cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1;
+
/* Cut half of cos_max when CDP is enabled. */
feat->cos_max = (feat->cos_max - 1) >> 1;
/* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */
- get_cdp_code(feat, 0) = cat_default_val(feat->cbm_len);
- get_cdp_data(feat, 0) = cat_default_val(feat->cbm_len);
+ get_cdp_code(feat, 0) = cat_default_val(feat->cat_info.cbm_len);
+ get_cdp_data(feat, 0) = cat_default_val(feat->cat_info.cbm_len);
- wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len));
- wrmsrl(MSR_IA32_PSR_L3_MASK(1), cat_default_val(feat->cbm_len));
+ wrmsrl(MSR_IA32_PSR_L3_MASK(0),
+ cat_default_val(feat->cat_info.cbm_len));
+ wrmsrl(MSR_IA32_PSR_L3_MASK(1),
+ cat_default_val(feat->cat_info.cbm_len));
rdmsrl(MSR_IA32_PSR_L3_QOS_CFG, val);
wrmsrl(MSR_IA32_PSR_L3_QOS_CFG,
val | (1ull << PSR_L3_QOS_CDP_ENABLE_BIT));
@@ -344,7 +370,45 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
cat_feat_name[type], cpu_to_socket(smp_processor_id()),
- feat->cos_max, feat->cbm_len);
+ feat->cos_max, feat->cat_info.cbm_len);
+
+ return 0;
+}
+
+static int mba_init_feature(const struct cpuid_leaf *regs,
+ struct feat_node *feat,
+ struct psr_socket_info *info,
+ enum psr_feat_type type)
+{
+ /* No valid value so do not enable feature. */
+ if ( !regs->a || !regs->d )
+ return -ENOENT;
+
+ if ( type != FEAT_TYPE_MBA )
+ return -ENOENT;
+
+ feat->cos_max = min(opt_cos_max, regs->d & CAT_COS_MAX_MASK);
+ if ( feat->cos_max < 1 )
+ return -ENOENT;
+
+ feat->mba_info.thrtl_max = (regs->a & MBA_THRTL_MAX_MASK) + 1;
+
+ if ( regs->c & MBA_LINEAR )
+ feat->mba_info.linear = 1;
+
+ feat->cos_reg_val[0] = 0;
+ wrmsrl(MSR_IA32_PSR_MBA_MASK(0), 0);
+
+ /* Add this feature into array. */
+ info->features[type] = feat;
+
+ if ( !opt_cpu_info )
+ return 0;
+
+ printk(XENLOG_INFO "MBA: enabled on socket %u, cos_max:%u,"
+ "thrtl_max:%u, linear:%u.\n",
+ cpu_to_socket(smp_processor_id()),
+ feat->cos_max, feat->mba_info.thrtl_max, feat->mba_info.linear);
return 0;
}
@@ -356,7 +420,7 @@ static bool cat_get_feat_info(const struct feat_node *feat,
return false;
data[PSR_INFO_IDX_COS_MAX] = feat->cos_max;
- data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cbm_len;
+ data[PSR_INFO_IDX_CAT_CBM_LEN] = feat->cat_info.cbm_len;
data[PSR_INFO_IDX_CAT_FLAG] = 0;
return true;
@@ -422,6 +486,26 @@ static const struct feat_props l2_cat_props = {
.write_msr = l2_cat_write_msr,
};
+/* MBA props */
+static bool mba_get_feat_info(const struct feat_node *feat,
+ uint32_t data[], unsigned int array_len)
+{
+ return false;
+}
+
+static void mba_write_msr(unsigned int cos, uint32_t val,
+ enum psr_val_type type)
+{
+}
+
+static const struct feat_props mba_props = {
+ .cos_num = 1,
+ .type[0] = PSR_VAL_TYPE_MBA,
+ .alt_type = PSR_VAL_TYPE_UNKNOWN,
+ .get_feat_info = mba_get_feat_info,
+ .write_msr = mba_write_msr,
+};
+
static void __init parse_psr_bool(char *s, char *value, char *feature,
unsigned int mask)
{
@@ -457,6 +541,7 @@ static void __init parse_psr_param(char *s)
parse_psr_bool(s, val_str, "cmt", PSR_CMT);
parse_psr_bool(s, val_str, "cat", PSR_CAT);
parse_psr_bool(s, val_str, "cdp", PSR_CDP);
+ parse_psr_bool(s, val_str, "mba", PSR_MBA);
if ( val_str && !strcmp(s, "rmid_max") )
opt_rmid_max = simple_strtoul(val_str, NULL, 0);
@@ -863,7 +948,7 @@ static int insert_val_into_array(uint32_t val[],
if ( array_len < props->cos_num )
return -ENOSPC;
- if ( !psr_check_cbm(feat->cbm_len, new_val) )
+ if ( !psr_check_cbm(feat->cat_info.cbm_len, new_val) )
return -EINVAL;
/*
@@ -1380,6 +1465,10 @@ static int psr_cpu_prepare(void)
(feat_l2_cat = xzalloc(struct feat_node)) == NULL )
return -ENOMEM;
+ if ( feat_mba == NULL &&
+ (feat_mba = xzalloc(struct feat_node)) == NULL )
+ return -ENOMEM;
+
return 0;
}
@@ -1389,6 +1478,7 @@ static void psr_cpu_init(void)
unsigned int socket, cpu = smp_processor_id();
struct feat_node *feat;
struct cpuid_leaf regs;
+ uint32_t reg_b;
if ( !psr_alloc_feat_enabled() || !boot_cpu_has(X86_FEATURE_PQE) )
goto assoc_init;
@@ -1407,7 +1497,8 @@ static void psr_cpu_init(void)
spin_lock_init(&info->ref_lock);
cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
- if ( regs.b & PSR_RESOURCE_TYPE_L3 )
+ reg_b = regs.b;
+ if ( reg_b & PSR_RESOURCE_TYPE_L3 )
{
cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 1, ®s);
@@ -1430,8 +1521,7 @@ static void psr_cpu_init(void)
}
}
- cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
- if ( regs.b & PSR_RESOURCE_TYPE_L2 )
+ if ( reg_b & PSR_RESOURCE_TYPE_L2 )
{
cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s);
@@ -1443,6 +1533,18 @@ static void psr_cpu_init(void)
feat_l2_cat = feat;
}
+ if ( reg_b & PSR_RESOURCE_TYPE_MBA )
+ {
+ cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 3, ®s);
+
+ feat = feat_mba;
+ feat_mba = NULL;
+ if ( !mba_init_feature(®s, feat, info, FEAT_TYPE_MBA) )
+ feat_props[FEAT_TYPE_MBA] = &mba_props;
+ else
+ feat_mba = feat;
+ }
+
info->feat_init = true;
assoc_init:
@@ -1502,7 +1604,7 @@ static int __init psr_presmp_init(void)
if ( (opt_psr & PSR_CMT) && opt_rmid_max )
init_psr_cmt(opt_rmid_max);
- if ( opt_psr & (PSR_CAT | PSR_CDP) )
+ if ( opt_psr & (PSR_CAT | PSR_CDP | PSR_MBA) )
init_psr();
if ( psr_cpu_prepare() )
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 4e08de6..41f1677 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -348,6 +348,7 @@
#define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1)
#define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2)
#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n))
+#define MSR_IA32_PSR_MBA_MASK(n) (0x00000d50 + (n))
/* Intel Model 6 */
#define MSR_P6_PERFCTR(n) (0x000000c1 + (n))
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 1b6f22f..551ccf3 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -24,6 +24,7 @@
/* Resource Type Enumeration */
#define PSR_RESOURCE_TYPE_L3 0x2
#define PSR_RESOURCE_TYPE_L2 0x4
+#define PSR_RESOURCE_TYPE_MBA 0x8
/* L3 Monitoring Features */
#define PSR_CMT_L3_OCCUPANCY 0x1
@@ -58,6 +59,7 @@ enum psr_val_type {
PSR_VAL_TYPE_L3_CODE,
PSR_VAL_TYPE_L3_DATA,
PSR_VAL_TYPE_L2,
+ PSR_VAL_TYPE_MBA,
PSR_VAL_TYPE_UNKNOWN,
};
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 05/13] x86: implement get hw info flow for MBA
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (3 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-16 3:23 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 06/13] x86: implement get value interface " Yi Sun
` (7 subsequent siblings)
12 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch implements get HW info flow for MBA including its callback
function and sysctl interface.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v1:
- sort 'PSR_INFO_IDX_' macros as feature.
(suggested by Chao Peng)
- rename 'PSR_INFO_IDX_MBA_LINEAR' to 'PSR_INFO_IDX_MBA_FLAG'.
- rename 'linear' in 'struct mba_info' to 'flags' for future extension.
(suggested by Chao Peng)
---
xen/arch/x86/psr.c | 13 ++++++++++++-
xen/arch/x86/sysctl.c | 19 +++++++++++++++++++
xen/include/asm-x86/psr.h | 2 ++
xen/include/public/sysctl.h | 8 ++++++++
4 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index d94a5b1..9455e67 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -264,6 +264,10 @@ static enum psr_feat_type psr_val_type_to_feat_type(enum psr_val_type type)
feat_type = FEAT_TYPE_L2_CAT;
break;
+ case PSR_VAL_TYPE_MBA:
+ feat_type = FEAT_TYPE_MBA;
+ break;
+
default:
ASSERT_UNREACHABLE();
}
@@ -490,7 +494,14 @@ static const struct feat_props l2_cat_props = {
static bool mba_get_feat_info(const struct feat_node *feat,
uint32_t data[], unsigned int array_len)
{
- return false;
+ if ( array_len != PSR_INFO_ARRAY_SIZE )
+ return false;
+
+ data[PSR_INFO_IDX_COS_MAX] = feat->cos_max;
+ data[PSR_INFO_IDX_MBA_THRTL_MAX] = feat->mba_info.thrtl_max;
+ data[PSR_INFO_IDX_MBA_FLAG] = feat->mba_info.linear;
+
+ return true;
}
static void mba_write_msr(unsigned int cos, uint32_t val,
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index b4fc1d5..2bf1543 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -214,6 +214,25 @@ long arch_do_sysctl(
break;
}
+ case XEN_SYSCTL_PSR_MBA_get_info:
+ {
+ ret = psr_get_info(sysctl->u.psr_alloc_op.target,
+ PSR_VAL_TYPE_MBA, data, ARRAY_SIZE(data));
+ if ( ret )
+ break;
+
+ sysctl->u.psr_alloc_op.u.mba_info.cos_max =
+ data[PSR_INFO_IDX_COS_MAX];
+ sysctl->u.psr_alloc_op.u.mba_info.thrtl_max =
+ data[PSR_INFO_IDX_MBA_THRTL_MAX];
+ sysctl->u.psr_alloc_op.u.mba_info.flags =
+ data[PSR_INFO_IDX_MBA_FLAG];
+
+ if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_alloc_op) )
+ ret = -EFAULT;
+ break;
+ }
+
default:
ret = -EOPNOTSUPP;
break;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 551ccf3..af7301f 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -39,6 +39,8 @@
#define PSR_INFO_IDX_COS_MAX 0
#define PSR_INFO_IDX_CAT_CBM_LEN 1
#define PSR_INFO_IDX_CAT_FLAG 2
+#define PSR_INFO_IDX_MBA_THRTL_MAX 1
+#define PSR_INFO_IDX_MBA_FLAG 2
#define PSR_INFO_ARRAY_SIZE 3
struct psr_cmt_l3 {
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index fcebab1..169e7e6 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -745,6 +745,7 @@ DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
#define XEN_SYSCTL_PSR_CAT_get_l2_info 1
+#define XEN_SYSCTL_PSR_MBA_get_info 2
struct xen_sysctl_psr_alloc_op {
uint32_t cmd; /* IN: XEN_SYSCTL_PSR_CAT_* */
uint32_t target; /* IN */
@@ -755,6 +756,13 @@ struct xen_sysctl_psr_alloc_op {
#define XEN_SYSCTL_PSR_CAT_L3_CDP (1u << 0)
uint32_t flags; /* OUT: CAT flags */
} cat_info;
+
+ struct {
+ uint32_t thrtl_max; /* OUT: Maximum throttle */
+ uint32_t cos_max; /* OUT: Maximum COS */
+#define XEN_SYSCTL_PSR_MBA_LINEAR (1u << 0)
+ uint32_t flags; /* OUT: MBA flags */
+ } mba_info;
} u;
};
typedef struct xen_sysctl_psr_alloc_op xen_sysctl_psr_alloc_op_t;
--
1.9.1
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 06/13] x86: implement get value interface for MBA
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (4 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 05/13] x86: implement get hw info " Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-16 6:38 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 07/13] x86: implement set value flow " Yi Sun
` (6 subsequent siblings)
12 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch implements get value domctl interface for MBA.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
xen/arch/x86/domctl.c | 7 +++++++
xen/include/public/domctl.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 850742a..fa5e6d4 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1496,6 +1496,13 @@ long arch_do_domctl(
copyback = true;
break;
+ case XEN_DOMCTL_PSR_MBA_OP_GET_THRTL:
+ ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
+ &val32, PSR_VAL_TYPE_MBA);
+ domctl->u.psr_alloc_op.data = val32;
+ copyback = true;
+ break;
+
default:
ret = -EOPNOTSUPP;
break;
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index 4bb4399..a577a3e 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1144,6 +1144,7 @@ struct xen_domctl_psr_alloc_op {
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
+#define XEN_DOMCTL_PSR_MBA_OP_GET_THRTL 9
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
uint32_t target; /* IN */
uint64_t data; /* IN/OUT */
--
1.9.1
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 07/13] x86: implement set value flow for MBA
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (5 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 06/13] x86: implement get value interface " Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-18 3:32 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 08/13] tools: create general interfaces to support psr allocation features Yi Sun
` (5 subsequent siblings)
12 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch implements set value flow for MBA including its callback
function and domctl interface.
It also changes the memebers in 'cos_write_info' to transfer the
feature array, feature properties array and value array. Then, we
can write all features values on the cos id into MSRs.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v1:
- rename 'check_change_val' to 'check_val'.
(suggested by Chao Peng)
- rename 'cat_check_change_val' to 'cat_check_cbm'.
(suggested by Chao Peng)
- rename 'mba_check_change_val' to 'mba_check_thrtl'.
(suggested by Chao Peng)
---
xen/arch/x86/domctl.c | 6 ++
xen/arch/x86/psr.c | 182 ++++++++++++++++++++++++++++++++------------
xen/include/public/domctl.h | 1 +
3 files changed, 141 insertions(+), 48 deletions(-)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index fa5e6d4..0aa9f34 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1468,6 +1468,12 @@ long arch_do_domctl(
PSR_VAL_TYPE_L2);
break;
+ case XEN_DOMCTL_PSR_MBA_OP_SET_THRTL:
+ ret = psr_set_val(d, domctl->u.psr_alloc_op.target,
+ domctl->u.psr_alloc_op.data,
+ PSR_VAL_TYPE_MBA);
+ break;
+
case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
ret = psr_get_val(d, domctl->u.psr_alloc_op.target,
&val32, PSR_VAL_TYPE_L3);
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 9455e67..bced251 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -138,6 +138,12 @@ static const struct feat_props {
/* write_msr is used to write out feature MSR register. */
void (*write_msr)(unsigned int cos, uint32_t val, enum psr_val_type type);
+
+ /*
+ * check_val is used to check if input val fulfills SDM requirement.
+ * Change it to valid value if SDM allows.
+ */
+ bool (*check_val)(const struct feat_node *feat, unsigned long *val);
} *feat_props[FEAT_TYPE_NUM];
/*
@@ -275,29 +281,6 @@ static enum psr_feat_type psr_val_type_to_feat_type(enum psr_val_type type)
return feat_type;
}
-static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
-{
- unsigned int first_bit, zero_bit;
-
- /* Set bits should only in the range of [0, cbm_len]. */
- if ( cbm & (~0ul << cbm_len) )
- return false;
-
- /* At least one bit need to be set. */
- if ( cbm == 0 )
- return false;
-
- first_bit = find_first_bit(&cbm, cbm_len);
- zero_bit = find_next_zero_bit(&cbm, cbm_len, first_bit);
-
- /* Set bits should be contiguous. */
- if ( zero_bit < cbm_len &&
- find_next_bit(&cbm, cbm_len, zero_bit) < cbm_len )
- return false;
-
- return true;
-}
-
/* Implementation of allocation features' functions. */
static int cat_init_feature(const struct cpuid_leaf *regs,
struct feat_node *feat,
@@ -430,6 +413,30 @@ static bool cat_get_feat_info(const struct feat_node *feat,
return true;
}
+static bool cat_check_cbm(const struct feat_node *feat, unsigned long *cbm)
+{
+ unsigned int first_bit, zero_bit;
+ unsigned int cbm_len = feat->cat_info.cbm_len;
+
+ /* Set bits should only in the range of [0, cbm_len]. */
+ if ( *cbm & (~0ul << cbm_len) )
+ return false;
+
+ /* At least one bit need to be set. */
+ if ( *cbm == 0 )
+ return false;
+
+ first_bit = find_first_bit(cbm, cbm_len);
+ zero_bit = find_next_zero_bit(cbm, cbm_len, first_bit);
+
+ /* Set bits should be contiguous. */
+ if ( zero_bit < cbm_len &&
+ find_next_bit(cbm, cbm_len, zero_bit) < cbm_len )
+ return false;
+
+ return true;
+}
+
/* L3 CAT props */
static void l3_cat_write_msr(unsigned int cos, uint32_t val,
enum psr_val_type type)
@@ -443,6 +450,7 @@ static const struct feat_props l3_cat_props = {
.alt_type = PSR_VAL_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l3_cat_write_msr,
+ .check_val = cat_check_cbm,
};
/* L3 CDP props */
@@ -473,6 +481,7 @@ static const struct feat_props l3_cdp_props = {
.alt_type = PSR_VAL_TYPE_L3,
.get_feat_info = l3_cdp_get_feat_info,
.write_msr = l3_cdp_write_msr,
+ .check_val = cat_check_cbm,
};
/* L2 CAT props */
@@ -488,6 +497,7 @@ static const struct feat_props l2_cat_props = {
.alt_type = PSR_VAL_TYPE_UNKNOWN,
.get_feat_info = cat_get_feat_info,
.write_msr = l2_cat_write_msr,
+ .check_val = cat_check_cbm,
};
/* MBA props */
@@ -507,6 +517,43 @@ static bool mba_get_feat_info(const struct feat_node *feat,
static void mba_write_msr(unsigned int cos, uint32_t val,
enum psr_val_type type)
{
+ wrmsrl(MSR_IA32_PSR_MBA_MASK(cos), val);
+}
+
+static bool mba_check_thrtl(const struct feat_node *feat, unsigned long *thrtl)
+{
+ if ( *thrtl > feat->mba_info.thrtl_max )
+ return false;
+
+ /*
+ * Per SDM (chapter "Memory Bandwidth Allocation Configuration"):
+ * 1. Linear mode: In the linear mode the input precision is defined
+ * as 100-(MBA_MAX). For instance, if the MBA_MAX value is 90, the
+ * input precision is 10%. Values not an even multiple of the
+ * precision (e.g., 12%) will be rounded down (e.g., to 10% delay
+ * applied).
+ * 2. Non-linear mode: Input delay values are powers-of-two from zero
+ * to the MBA_MAX value from CPUID. In this case any values not a
+ * power of two will be rounded down the next nearest power of two.
+ */
+ if ( feat->mba_info.linear )
+ {
+ unsigned int mod;
+
+ if ( feat->mba_info.thrtl_max >= 100 )
+ return false;
+
+ mod = *thrtl % (100 - feat->mba_info.thrtl_max);
+ *thrtl -= mod;
+ }
+ else
+ {
+ /* Not power of 2. */
+ if ( *thrtl & (*thrtl - 1) )
+ *thrtl = *thrtl & (1 << (flsl(*thrtl) - 1));
+ }
+
+ return true;
}
static const struct feat_props mba_props = {
@@ -515,6 +562,7 @@ static const struct feat_props mba_props = {
.alt_type = PSR_VAL_TYPE_UNKNOWN,
.get_feat_info = mba_get_feat_info,
.write_msr = mba_write_msr,
+ .check_val = mba_check_thrtl,
};
static void __init parse_psr_bool(char *s, char *value, char *feature,
@@ -935,6 +983,7 @@ static int insert_val_into_array(uint32_t val[],
const struct feat_node *feat;
const struct feat_props *props;
unsigned int i;
+ unsigned long check_val = new_val;
int ret;
ASSERT(feat_type < FEAT_TYPE_NUM);
@@ -959,9 +1008,11 @@ static int insert_val_into_array(uint32_t val[],
if ( array_len < props->cos_num )
return -ENOSPC;
- if ( !psr_check_cbm(feat->cat_info.cbm_len, new_val) )
+ if ( !props->check_val(feat, &check_val) )
return -EINVAL;
+ new_val = check_val;
+
/*
* Value setting position is same as feature array.
* For CDP, user may set both DATA and CODE to same value. For such case,
@@ -1187,28 +1238,74 @@ static unsigned int get_socket_cpu(unsigned int socket)
return nr_cpu_ids;
}
+/*
+ * Because multiple features may co-exist, we need handle all features to write
+ * values of them into a COS register with new COS ID. E.g:
+ * 1. L3 CAT and MBA co-exist.
+ * 2. Dom1 and Dom2 share a same COS ID (2). The L3 CAT CBM of Dom1 is 0x1ff,
+ * the MBA Thrtle of Dom1 is 0xa.
+ * 3. User wants to change MBA Thrtl of Dom1 to be 0x14. Because COS ID 2 is
+ * used by Dom2 too, we have to pick a new COS ID 3. The original values of
+ * Dom1 on COS ID 3 may be below:
+ * ---------
+ * | COS 3 |
+ * ---------
+ * L3 CAT | 0x7ff |
+ * ---------
+ * MBA | 0x0 |
+ * ---------
+ * 4. After setting, the L3 CAT CBM value of Dom1 should be kept and the new MBA
+ * Thrtl is set. So, the values on COS ID 3 should be below.
+ * ---------
+ * | COS 3 |
+ * ---------
+ * L3 CAT | 0x1ff |
+ * ---------
+ * MBA | 0x14 |
+ * ---------
+ *
+ * So, we should write all features values into their MSRs. That requires the
+ * feature array, feature properties array and value array are input.
+ */
struct cos_write_info
{
unsigned int cos;
- struct feat_node *feature;
+ struct feat_node **features;
const uint32_t *val;
- const struct feat_props *props;
+ unsigned int array_len;
+ const struct feat_props **props;
};
static void do_write_psr_msrs(void *data)
{
const struct cos_write_info *info = data;
- struct feat_node *feat = info->feature;
- const struct feat_props *props = info->props;
- unsigned int i, cos = info->cos, cos_num = props->cos_num;
+ unsigned int i, j, index = 0, array_len = info->array_len, cos = info->cos;
+ const uint32_t *val_array = info->val;
- for ( i = 0; i < cos_num; i++ )
+ for ( i = 0; i < ARRAY_SIZE(feat_props); i++ )
{
- if ( feat->cos_reg_val[cos * cos_num + i] != info->val[i] )
+ struct feat_node *feat = info->features[i];
+ const struct feat_props *props = info->props[i];
+ unsigned int cos_num;
+
+ if ( !feat || !props )
+ continue;
+
+ cos_num = props->cos_num;
+ if ( array_len < cos_num )
+ return;
+
+ for ( j = 0; j < cos_num; j++ )
{
- feat->cos_reg_val[cos * cos_num + i] = info->val[i];
- props->write_msr(cos, info->val[i], props->type[i]);
+ if ( feat->cos_reg_val[cos * cos_num + j] != val_array[index + j] )
+ {
+ feat->cos_reg_val[cos * cos_num + j] = val_array[index + j];
+ props->write_msr(cos, val_array[index + j], props->type[j]);
+ }
}
+
+ array_len -= cos_num;
+ index += cos_num;
}
}
@@ -1216,30 +1313,19 @@ static int write_psr_msrs(unsigned int socket, unsigned int cos,
const uint32_t val[], unsigned int array_len,
enum psr_feat_type feat_type)
{
- int ret;
struct psr_socket_info *info = get_socket_info(socket);
struct cos_write_info data =
{
.cos = cos,
- .feature = info->features[feat_type],
- .props = feat_props[feat_type],
+ .features = info->features,
+ .val = val,
+ .array_len = array_len,
+ .props = feat_props,
};
if ( cos > info->features[feat_type]->cos_max )
return -EINVAL;
- /* Skip to the feature's value head. */
- ret = skip_prior_features(&array_len, feat_type);
- if ( ret < 0 )
- return ret;
-
- val += ret;
-
- if ( array_len < feat_props[feat_type]->cos_num )
- return -ENOSPC;
-
- data.val = val;
-
if ( socket == cpu_to_socket(smp_processor_id()) )
do_write_psr_msrs(&data);
else
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index a577a3e..8826cfb 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1144,6 +1144,7 @@ struct xen_domctl_psr_alloc_op {
#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
#define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
#define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
+#define XEN_DOMCTL_PSR_MBA_OP_SET_THRTL 8
#define XEN_DOMCTL_PSR_MBA_OP_GET_THRTL 9
uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
uint32_t target; /* IN */
--
1.9.1
_______________________________________________
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Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 08/13] tools: create general interfaces to support psr allocation features
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (6 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 07/13] x86: implement set value flow " Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-21 10:12 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all " Yi Sun
` (4 subsequent siblings)
12 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch creates general interfaces in libxl to support all psr
allocation features.
Add 'LIBXL_HAVE_PSR_MBA' to indicate interface change.
Please note, the functionality cannot work until later patches
are applied.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v1:
- change 'uint32_t target' to 'unsigned int target'.
(suggested by Wei Liu)
- change 'int nr' to 'unsigned int nr'.
(suggested by Wei Liu)
- change 'int lvl' to 'unsigned int lvl'.
- change 'EXIT_FAILURE' to 'ERROR_FAIL'.
(suggested by Wei Liu)
- add 'dir=DIR_OUT' for 'libxl_psr_hw_info'.
(suggested by Wei Liu)
---
tools/libxl/libxl.h | 35 ++++++++++++++++++++++++++++++++++-
tools/libxl/libxl_psr.c | 25 +++++++++++++++++++++++++
tools/libxl/libxl_types.idl | 22 ++++++++++++++++++++++
3 files changed, 81 insertions(+), 1 deletion(-)
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 229e289..c1d804c 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -931,6 +931,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, const libxl_mac *src);
#define LIBXL_HAVE_PSR_L2_CAT 1
/*
+ * LIBXL_HAVE_PSR_MBA
+ *
+ * If this is defined, the Memory Bandwidth Allocation feature is supported.
+ */
+#define LIBXL_HAVE_PSR_MBA 1
+
+/*
* LIBXL_HAVE_MCA_CAPS
*
* If this is defined, setting MCA capabilities for HVM domain is supported.
@@ -2219,7 +2226,33 @@ int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
int libxl_psr_cat_get_l3_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
int *nr);
void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr);
-#endif
+
+#ifdef LIBXL_HAVE_PSR_MBA
+/*
+ * Function to set a domain's value. It operates on a single or multiple
+ * target(s) defined in 'target_map'. 'target_map' specifies all the sockets
+ * to be operated on.
+ */
+int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, libxl_bitmap *target_map,
+ uint64_t val);
+/*
+ * Function to get a domain's cbm. It operates on a single 'target'.
+ * 'target' specifies which socket to be operated on.
+ */
+int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, unsigned int target,
+ uint64_t *val);
+/*
+ * On success, the function returns an array of elements in 'info',
+ * and the length in 'nr'.
+ */
+int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
+ unsigned int *nr, libxl_psr_feat_type type,
+ unsigned int lvl);
+void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, unsigned int nr);
+#endif /* LIBXL_HAVE_PSR_MBA */
+#endif /* LIBXL_HAVE_PSR_CAT */
/* misc */
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index f55ba1e..cf368ba 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -425,6 +425,31 @@ void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr)
free(list);
}
+int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, libxl_bitmap *target_map,
+ uint64_t val)
+{
+ return ERROR_FAIL;
+}
+
+int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, unsigned int target,
+ uint64_t *val)
+{
+ return ERROR_FAIL;
+}
+
+int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
+ unsigned int *nr, libxl_psr_feat_type type,
+ unsigned int lvl)
+{
+ return ERROR_FAIL;
+}
+
+void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, unsigned int nr)
+{
+}
+
/*
* Local variables:
* mode: C
diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
index 6e80d36..10d317b 100644
--- a/tools/libxl/libxl_types.idl
+++ b/tools/libxl/libxl_types.idl
@@ -977,6 +977,7 @@ libxl_psr_cbm_type = Enumeration("psr_cbm_type", [
(2, "L3_CBM_CODE"),
(3, "L3_CBM_DATA"),
(4, "L2_CBM"),
+ (5, "MBA_THRTL"),
])
libxl_psr_cat_info = Struct("psr_cat_info", [
@@ -985,3 +986,24 @@ libxl_psr_cat_info = Struct("psr_cat_info", [
("cbm_len", uint32),
("cdp_enabled", bool),
])
+
+libxl_psr_feat_type = Enumeration("psr_feat_type", [
+ (1, "CAT_INFO"),
+ (2, "MBA_INFO"),
+ ])
+
+libxl_psr_hw_info = Struct("psr_hw_info", [
+ ("id", uint32),
+ ("u", KeyedUnion(None, libxl_psr_feat_type, "type",
+ [("cat_info", Struct(None, [
+ ("cos_max", uint32),
+ ("cbm_len", uint32),
+ ("cdp_enabled", bool),
+ ])),
+ ("mba_info", Struct(None, [
+ ("cos_max", uint32),
+ ("thrtl_max", uint32),
+ ("linear", bool),
+ ])),
+ ]))
+ ], dir=DIR_OUT)
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all psr allocation features
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (7 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 08/13] tools: create general interfaces to support psr allocation features Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-15 11:14 ` Wei Liu
2017-08-21 10:13 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type' Yi Sun
` (3 subsequent siblings)
12 siblings, 2 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch implements a new get hw info interface suitable for all psr allocation
features and the whole flow. It also enables MBA support in tools to get MBA
HW info.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v1:
- remove the pointless initialization for 'xc_psr_feat_type'.
(suggested by Wei Liu)
- use 'libxl__' for internal functions.
(suggested by Wei Liu)
- change error value '-1' to 'ERROR_INVAL'.
(suggested by Wei Liu)
- remove an extraneous space.
(suggested by Wei Liu)
- replace some 'int' to 'unsigned int'.
(suggested by Wei Liu)
- remove test to macro 'LIBXL_HAVE_PSR_MBA'.
(suggested by Wei Liu)
- change 'mba_info.linear' to 'mba_info.flags'.
(suggested by Chao Peng)
- adjust print info only to show the MBA info after successfully getting
HW info.
---
tools/libxc/include/xenctrl.h | 30 +++++++-
tools/libxc/xc_psr.c | 46 +++++++++----
tools/libxl/libxl_psr.c | 155 +++++++++++++++++++++++++++++++++++-------
tools/xl/xl_cmdtable.c | 1 +
tools/xl/xl_psr.c | 39 ++++++++++-
5 files changed, 230 insertions(+), 41 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index c7710b8..81a6f48 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2458,6 +2458,31 @@ enum xc_psr_cat_type {
};
typedef enum xc_psr_cat_type xc_psr_cat_type;
+enum xc_psr_feat_type {
+ XC_PSR_FEAT_UNKNOWN,
+ XC_PSR_FEAT_CAT_L3,
+ XC_PSR_FEAT_CAT_L2,
+ XC_PSR_FEAT_MBA,
+};
+typedef enum xc_psr_feat_type xc_psr_feat_type;
+
+struct xc_psr_hw_info {
+ union {
+ struct {
+ uint32_t cos_max;
+ uint32_t cbm_len;
+ bool cdp_enabled;
+ } xc_cat_info;
+
+ struct {
+ uint32_t cos_max;
+ uint32_t thrtl_max;
+ bool linear;
+ } xc_mba_info;
+ } u;
+};
+typedef struct xc_psr_hw_info xc_psr_hw_info;
+
int xc_psr_cmt_attach(xc_interface *xch, uint32_t domid);
int xc_psr_cmt_detach(xc_interface *xch, uint32_t domid);
int xc_psr_cmt_get_domain_rmid(xc_interface *xch, uint32_t domid,
@@ -2479,9 +2504,8 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_cat_type type, uint32_t target,
uint64_t *data);
-int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
- uint32_t *cos_max, uint32_t *cbm_len,
- bool *cdp_enabled);
+int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
+ xc_psr_feat_type type, xc_psr_hw_info *hw_info);
int xc_get_cpu_levelling_caps(xc_interface *xch, uint32_t *caps);
int xc_get_cpu_featureset(xc_interface *xch, uint32_t index,
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index 73d05f2..ba412e4 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -323,36 +323,58 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
return rc;
}
-int xc_psr_cat_get_info(xc_interface *xch, uint32_t socket, unsigned int lvl,
- uint32_t *cos_max, uint32_t *cbm_len, bool *cdp_enabled)
+int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
+ xc_psr_feat_type type, xc_psr_hw_info *hw_info)
{
int rc = -1;
DECLARE_SYSCTL;
+ if ( !hw_info )
+ return rc;
+
sysctl.cmd = XEN_SYSCTL_psr_alloc_op;
sysctl.u.psr_alloc_op.target = socket;
- switch ( lvl )
+ switch ( type )
{
- case 2:
+ case XC_PSR_FEAT_CAT_L2:
sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_CAT_get_l2_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_alloc_op.u.cat_info.cos_max;
- *cbm_len = sysctl.u.psr_alloc_op.u.cat_info.cbm_len;
- *cdp_enabled = false;
+ hw_info->u.xc_cat_info.cos_max =
+ sysctl.u.psr_alloc_op.u.cat_info.cos_max;
+ hw_info->u.xc_cat_info.cbm_len =
+ sysctl.u.psr_alloc_op.u.cat_info.cbm_len;
+ hw_info->u.xc_cat_info.cdp_enabled = false;
}
break;
- case 3:
+ case XC_PSR_FEAT_CAT_L3:
sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
rc = xc_sysctl(xch, &sysctl);
if ( !rc )
{
- *cos_max = sysctl.u.psr_alloc_op.u.cat_info.cos_max;
- *cbm_len = sysctl.u.psr_alloc_op.u.cat_info.cbm_len;
- *cdp_enabled = sysctl.u.psr_alloc_op.u.cat_info.flags &
- XEN_SYSCTL_PSR_CAT_L3_CDP;
+ hw_info->u.xc_cat_info.cos_max =
+ sysctl.u.psr_alloc_op.u.cat_info.cos_max;
+ hw_info->u.xc_cat_info.cbm_len =
+ sysctl.u.psr_alloc_op.u.cat_info.cbm_len;
+ hw_info->u.xc_cat_info.cdp_enabled =
+ sysctl.u.psr_alloc_op.u.cat_info.flags &
+ XEN_SYSCTL_PSR_CAT_L3_CDP;
+ }
+ break;
+ case XC_PSR_FEAT_MBA:
+ sysctl.u.psr_alloc_op.cmd = XEN_SYSCTL_PSR_MBA_get_info;
+ rc = xc_sysctl(xch, &sysctl);
+ if ( !rc )
+ {
+ hw_info->u.xc_mba_info.cos_max =
+ sysctl.u.psr_alloc_op.u.mba_info.cos_max;
+ hw_info->u.xc_mba_info.thrtl_max =
+ sysctl.u.psr_alloc_op.u.mba_info.thrtl_max;
+ hw_info->u.xc_mba_info.linear =
+ sysctl.u.psr_alloc_op.u.mba_info.flags &
+ XEN_SYSCTL_PSR_MBA_LINEAR;
}
break;
default:
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index cf368ba..cb928e7 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -361,47 +361,49 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
return rc;
}
+static inline int libxl__psr_hw_info_to_libxl_psr_cat_info(
+ libxl_psr_feat_type type, libxl_psr_hw_info *hw_info,
+ libxl_psr_cat_info *cat_info)
+{
+ if (type != LIBXL_PSR_FEAT_TYPE_CAT_INFO)
+ return ERROR_INVAL;
+
+ cat_info->id = hw_info->id;
+ cat_info->cos_max = hw_info->u.cat_info.cos_max;
+ cat_info->cbm_len = hw_info->u.cat_info.cbm_len;
+ cat_info->cdp_enabled = hw_info->u.cat_info.cdp_enabled;
+
+ return 0;
+}
+
int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
int *nr, unsigned int lvl)
{
GC_INIT(ctx);
int rc;
- int i = 0, socketid, nr_sockets;
- libxl_bitmap socketmap;
+ unsigned int i;
+ libxl_psr_hw_info *hw_info;
libxl_psr_cat_info *ptr;
- libxl_bitmap_init(&socketmap);
-
- rc = libxl__count_physical_sockets(gc, &nr_sockets);
- if (rc) {
- LOGE(ERROR, "failed to get system socket count");
+ rc = libxl_psr_get_hw_info(ctx, &hw_info, (unsigned int *)nr,
+ LIBXL_PSR_FEAT_TYPE_CAT_INFO, lvl);
+ if (rc)
goto out;
- }
- libxl_socket_bitmap_alloc(ctx, &socketmap, nr_sockets);
- rc = libxl_get_online_socketmap(ctx, &socketmap);
- if (rc < 0) {
- LOGE(ERROR, "failed to get available sockets");
- goto out;
- }
+ ptr = libxl__malloc(NOGC, *nr * sizeof(libxl_psr_cat_info));
- ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_cat_info));
-
- libxl_for_each_set_bit(socketid, socketmap) {
- ptr[i].id = socketid;
- if (xc_psr_cat_get_info(ctx->xch, socketid, lvl, &ptr[i].cos_max,
- &ptr[i].cbm_len, &ptr[i].cdp_enabled)) {
+ for (i = 0; i < *nr; i++) {
+ if (libxl__psr_hw_info_to_libxl_psr_cat_info(
+ LIBXL_PSR_FEAT_TYPE_CAT_INFO,
+ &hw_info[i], &ptr[i])) {
rc = ERROR_FAIL;
free(ptr);
goto out;
}
- i++;
}
*info = ptr;
- *nr = i;
out:
- libxl_bitmap_dispose(&socketmap);
GC_FREE;
return rc;
}
@@ -439,15 +441,120 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
return ERROR_FAIL;
}
+static inline xc_psr_feat_type libxl__psr_feat_type_to_libxc_psr_feat_type(
+ libxl_psr_feat_type type, unsigned int lvl)
+{
+ xc_psr_feat_type xc_type = XC_PSR_FEAT_UNKNOWN;
+
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT_INFO:
+ if (lvl == 3)
+ xc_type = XC_PSR_FEAT_CAT_L3;
+ if (lvl == 2)
+ xc_type = XC_PSR_FEAT_CAT_L2;
+ break;
+ case LIBXL_PSR_FEAT_TYPE_MBA_INFO:
+ xc_type = XC_PSR_FEAT_MBA;
+ default:
+ break;
+ }
+
+ return xc_type;
+}
+
+static inline int libxc__psr_hw_info_to_libxl_psr_hw_info(
+ libxl_psr_feat_type type, xc_psr_hw_info *xc_hw_info,
+ libxl_psr_hw_info *xl_hw_info)
+{
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT_INFO:
+ xl_hw_info->u.cat_info.cos_max = xc_hw_info->u.xc_cat_info.cos_max;
+ xl_hw_info->u.cat_info.cbm_len = xc_hw_info->u.xc_cat_info.cbm_len;
+ xl_hw_info->u.cat_info.cdp_enabled =
+ xc_hw_info->u.xc_cat_info.cdp_enabled;
+ break;
+ case LIBXL_PSR_FEAT_TYPE_MBA_INFO:
+ xl_hw_info->u.mba_info.cos_max = xc_hw_info->u.xc_mba_info.cos_max;
+ xl_hw_info->u.mba_info.thrtl_max = xc_hw_info->u.xc_mba_info.thrtl_max;
+ xl_hw_info->u.mba_info.linear = xc_hw_info->u.xc_mba_info.linear;
+ break;
+ default:
+ return ERROR_INVAL;
+ }
+
+ return 0;
+}
+
int libxl_psr_get_hw_info(libxl_ctx *ctx, libxl_psr_hw_info **info,
unsigned int *nr, libxl_psr_feat_type type,
unsigned int lvl)
{
- return ERROR_FAIL;
+ GC_INIT(ctx);
+ int rc, nr_sockets;
+ unsigned int i = 0, socketid;
+ libxl_bitmap socketmap;
+ libxl_psr_hw_info *ptr;
+ xc_psr_feat_type xc_type;
+ xc_psr_hw_info hw_info;
+
+ libxl_bitmap_init(&socketmap);
+
+ if (type == LIBXL_PSR_FEAT_TYPE_CAT_INFO && lvl != 3 && lvl != 2) {
+ LOGE(ERROR, "input lvl %d is wrong!\n", lvl);
+ rc = ERROR_FAIL;
+ goto out;
+ }
+
+ xc_type = libxl__psr_feat_type_to_libxc_psr_feat_type(type, lvl);
+
+ rc = libxl__count_physical_sockets(gc, &nr_sockets);
+ if (rc) {
+ LOGE(ERROR, "failed to get system socket count");
+ goto out;
+ }
+
+ libxl_socket_bitmap_alloc(ctx, &socketmap, nr_sockets);
+ rc = libxl_get_online_socketmap(ctx, &socketmap);
+ if (rc < 0) {
+ LOGE(ERROR, "failed to get available sockets");
+ goto out;
+ }
+
+ ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_hw_info));
+
+ libxl_for_each_set_bit(socketid, socketmap) {
+ ptr[i].id = socketid;
+ if (xc_psr_get_hw_info(ctx->xch, socketid, xc_type, &hw_info)) {
+ rc = ERROR_FAIL;
+ free(ptr);
+ goto out;
+ }
+
+ if (libxc__psr_hw_info_to_libxl_psr_hw_info(type, &hw_info, &ptr[i])) {
+ LOGE(ERROR, "Input type %d is wrong!\n", type);
+ rc = ERROR_FAIL;
+ free(ptr);
+ goto out;
+ }
+
+ i++;
+ }
+
+ *info = ptr;
+ *nr = i;
+out:
+ libxl_bitmap_dispose(&socketmap);
+ GC_FREE;
+ return rc;
}
void libxl_psr_hw_info_list_free(libxl_psr_hw_info *list, unsigned int nr)
{
+ unsigned int i;
+
+ for (i = 0; i < nr; i++)
+ libxl_psr_hw_info_dispose(&list[i]);
+ free(list);
}
/*
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 2c71a9f..5ac8a7e 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -524,6 +524,7 @@ struct cmd_spec cmd_table[] = {
"[options]",
"-m, --cmt Show Cache Monitoring Technology (CMT) hardware info\n"
"-a, --cat Show Cache Allocation Technology (CAT) hardware info\n"
+ "-b, --mba Show Memory Bandwidth Allocation (MBA) hardware info\n"
},
{ "psr-cmt-attach",
&main_psr_cmt_attach, 0, 1,
diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
index 7309d4f..bf41762 100644
--- a/tools/xl/xl_psr.c
+++ b/tools/xl/xl_psr.c
@@ -479,6 +479,33 @@ static int psr_l2_cat_hwinfo(void)
return rc;
}
+static int psr_mba_hwinfo(void)
+{
+ int rc;
+ unsigned int i, nr;
+ libxl_psr_hw_info *info;
+
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr,
+ LIBXL_PSR_FEAT_TYPE_MBA_INFO, 0);
+ if (rc)
+ return rc;
+
+ printf("Memory Bandwidth Allocation (MBA):\n");
+
+ for (i = 0; i < nr; i++) {
+ printf("%-16s: %u\n", "Socket ID", info[i].id);
+ printf("%-16s: %s\n", "Linear Mode",
+ info[i].u.mba_info.linear ? "Enabled" : "Disabled");
+ printf("%-16s: %u\n", "Maximum COS", info[i].u.mba_info.cos_max);
+ printf("%-16s: %u\n", "Maximum Throttling Value",
+ info[i].u.mba_info.thrtl_max);
+ printf("%-16s: %u\n", "Default Throttling Value", 0);
+ }
+
+ libxl_psr_hw_info_list_free(info, nr);
+ return rc;
+}
+
int main_psr_cat_cbm_set(int argc, char **argv)
{
uint32_t domid;
@@ -597,20 +624,24 @@ int main_psr_cat_show(int argc, char **argv)
int main_psr_hwinfo(int argc, char **argv)
{
int opt, ret = 0;
- bool all = true, cmt = false, cat = false;
+ bool all = true, cmt = false, cat = false, mba = false;
static struct option opts[] = {
{"cmt", 0, 0, 'm'},
{"cat", 0, 0, 'a'},
+ {"mba", 0, 0, 'b'},
COMMON_LONG_OPTS
};
- SWITCH_FOREACH_OPT(opt, "ma", opts, "psr-hwinfo", 0) {
+ SWITCH_FOREACH_OPT(opt, "mab", opts, "psr-hwinfo", 0) {
case 'm':
all = false; cmt = true;
break;
case 'a':
all = false; cat = true;
break;
+ case 'b':
+ all = false; mba = true;
+ break;
}
if (!ret && (all || cmt))
@@ -623,6 +654,10 @@ int main_psr_hwinfo(int argc, char **argv)
if (all || cat)
ret = psr_l2_cat_hwinfo();
+ /* MBA is independent of CMT and CAT */
+ if (all || mba)
+ ret = psr_mba_hwinfo();
+
return ret;
}
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type'
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (8 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all " Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-15 11:15 ` Wei Liu
2017-08-21 10:13 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features Yi Sun
` (2 subsequent siblings)
12 siblings, 2 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch renames 'xc_psr_cat_type' to 'xc_psr_val_type' so that
the structure name is common for all allocation features.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
v1:
- split this patch out from next 'get value' patch.
(suggested by Wei Liu)
---
tools/libxc/include/xenctrl.h | 8 ++++----
tools/libxc/xc_psr.c | 4 ++--
tools/libxl/libxl_psr.c | 12 ++++++------
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index 81a6f48..f1c629e 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2450,13 +2450,13 @@ enum xc_psr_cmt_type {
};
typedef enum xc_psr_cmt_type xc_psr_cmt_type;
-enum xc_psr_cat_type {
+enum xc_psr_val_type {
XC_PSR_CAT_L3_CBM = 1,
XC_PSR_CAT_L3_CBM_CODE = 2,
XC_PSR_CAT_L3_CBM_DATA = 3,
XC_PSR_CAT_L2_CBM = 4,
};
-typedef enum xc_psr_cat_type xc_psr_cat_type;
+typedef enum xc_psr_val_type xc_psr_val_type;
enum xc_psr_feat_type {
XC_PSR_FEAT_UNKNOWN,
@@ -2499,10 +2499,10 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
int xc_psr_cmt_enabled(xc_interface *xch);
int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_val_type type, uint32_t target,
uint64_t data);
int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_val_type type, uint32_t target,
uint64_t *data);
int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
xc_psr_feat_type type, xc_psr_hw_info *hw_info);
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index ba412e4..c69e943 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -249,7 +249,7 @@ int xc_psr_cmt_enabled(xc_interface *xch)
return 0;
}
int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_val_type type, uint32_t target,
uint64_t data)
{
DECLARE_DOMCTL;
@@ -284,7 +284,7 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
}
int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_cat_type type, uint32_t target,
+ xc_psr_val_type type, uint32_t target,
uint64_t *data)
{
int rc;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index cb928e7..1d75f33 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -303,11 +303,11 @@ out:
return rc;
}
-static inline xc_psr_cat_type libxl__psr_cbm_type_to_libxc_psr_cat_type(
+static inline xc_psr_val_type libxl__psr_cbm_type_to_libxc_psr_val_type(
libxl_psr_cbm_type type)
{
- BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_cat_type));
- return (xc_psr_cat_type)type;
+ BUILD_BUG_ON(sizeof(libxl_psr_cbm_type) != sizeof(xc_psr_val_type));
+ return (xc_psr_val_type)type;
}
int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
@@ -325,12 +325,12 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
}
libxl_for_each_set_bit(socketid, *target_map) {
- xc_psr_cat_type xc_type;
+ xc_psr_val_type xc_type;
if (socketid >= nr_sockets)
break;
- xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
+ xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
socketid, cbm)) {
libxl__psr_cat_log_err_msg(gc, errno);
@@ -349,7 +349,7 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
{
GC_INIT(ctx);
int rc = 0;
- xc_psr_cat_type xc_type = libxl__psr_cbm_type_to_libxc_psr_cat_type(type);
+ xc_psr_val_type xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
if (xc_psr_cat_get_domain_data(ctx->xch, domid, xc_type,
target, cbm_r)) {
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (9 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type' Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-15 11:24 ` Wei Liu
2017-08-21 10:14 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 12/13] tools: implemet new set " Yi Sun
2017-08-09 7:41 ` [PATCH v1 13/13] docs: add MBA description in docs Yi Sun
12 siblings, 2 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch implements a new get value interface in tools suitable for all psr
allocation features and the whole flow. It also enables MBA support in tools
to get MBA value.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/libxc/include/xenctrl.h | 7 +-
tools/libxc/xc_psr.c | 9 ++-
tools/libxl/libxl_psr.c | 51 +++++++-----
tools/xl/xl.h | 1 +
tools/xl/xl_cmdtable.c | 5 ++
tools/xl/xl_psr.c | 179 +++++++++++++++++++++++++++++-------------
6 files changed, 173 insertions(+), 79 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index f1c629e..d7eabfb 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2455,6 +2455,7 @@ enum xc_psr_val_type {
XC_PSR_CAT_L3_CBM_CODE = 2,
XC_PSR_CAT_L3_CBM_DATA = 3,
XC_PSR_CAT_L2_CBM = 4,
+ XC_PSR_MBA_THRTL = 5,
};
typedef enum xc_psr_val_type xc_psr_val_type;
@@ -2501,9 +2502,9 @@ int xc_psr_cmt_enabled(xc_interface *xch);
int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_val_type type, uint32_t target,
uint64_t data);
-int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_val_type type, uint32_t target,
- uint64_t *data);
+int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_val_type type, uint32_t target,
+ uint64_t *data);
int xc_psr_get_hw_info(xc_interface *xch, uint32_t socket,
xc_psr_feat_type type, xc_psr_hw_info *hw_info);
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index c69e943..de501b0 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -283,9 +283,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
return do_domctl(xch, &domctl);
}
-int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_val_type type, uint32_t target,
- uint64_t *data)
+int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_val_type type, uint32_t target,
+ uint64_t *data)
{
int rc;
DECLARE_DOMCTL;
@@ -305,6 +305,9 @@ int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
case XC_PSR_CAT_L2_CBM:
cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM;
break;
+ case XC_PSR_MBA_THRTL:
+ cmd = XEN_DOMCTL_PSR_MBA_OP_GET_THRTL;
+ break;
default:
errno = EINVAL;
return -1;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 1d75f33..4b91e9b 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -71,16 +71,30 @@ static void libxl__psr_cmt_log_err_msg(libxl__gc *gc, int err)
LOGE(ERROR, "%s", msg);
}
-static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
+static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
+ int err,
+ libxl_psr_cbm_type type)
{
+ /*
+ * Index is 'libxl_psr_cbm_type' so we set two 'CDP' to correspond to
+ * DATA and CODE.
+ */
+ const char * const feat_name[6] = {
+ "UNKNOWN",
+ "L3 CAT",
+ "CDP",
+ "CDP",
+ "L2 CAT",
+ "MBA",
+ };
char *msg;
switch (err) {
case ENODEV:
- msg = "CAT is not supported in this system";
+ msg = "is not supported in this system";
break;
case ENOENT:
- msg = "CAT is not enabled on the socket";
+ msg = "is not enabled on the socket";
break;
case EOVERFLOW:
msg = "no free COS available";
@@ -106,7 +120,7 @@ static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
return;
}
- LOGE(ERROR, "%s", msg);
+ LOGE(ERROR, "%s: %s", feat_name[type], msg);
}
static int libxl__pick_socket_cpu(libxl__gc *gc, uint32_t socketid)
@@ -333,7 +347,7 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
socketid, cbm)) {
- libxl__psr_cat_log_err_msg(gc, errno);
+ libxl__psr_alloc_log_err_msg(gc, errno, type);
rc = ERROR_FAIL;
}
}
@@ -347,18 +361,7 @@ int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, uint32_t target,
uint64_t *cbm_r)
{
- GC_INIT(ctx);
- int rc = 0;
- xc_psr_val_type xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
-
- if (xc_psr_cat_get_domain_data(ctx->xch, domid, xc_type,
- target, cbm_r)) {
- libxl__psr_cat_log_err_msg(gc, errno);
- rc = ERROR_FAIL;
- }
-
- GC_FREE;
- return rc;
+ return libxl_psr_get_val(ctx, domid, type, target, cbm_r);
}
static inline int libxl__psr_hw_info_to_libxl_psr_cat_info(
@@ -438,7 +441,19 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, unsigned int target,
uint64_t *val)
{
- return ERROR_FAIL;
+ GC_INIT(ctx);
+ int rc = 0;
+
+ xc_psr_val_type xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
+
+ if (xc_psr_get_domain_data(ctx->xch, domid, xc_type,
+ target, val)) {
+ libxl__psr_alloc_log_err_msg(gc, errno, type);
+ rc = ERROR_FAIL;
+ }
+
+ GC_FREE;
+ return rc;
}
static inline xc_psr_feat_type libxl__psr_feat_type_to_libxc_psr_feat_type(
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index aa95b77..59065c4 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -206,6 +206,7 @@ int main_psr_cmt_show(int argc, char **argv);
#ifdef LIBXL_HAVE_PSR_CAT
int main_psr_cat_cbm_set(int argc, char **argv);
int main_psr_cat_show(int argc, char **argv);
+int main_psr_mba_show(int argc, char **argv);
#endif
int main_qemu_monitor_command(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 5ac8a7e..19e5004 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -562,6 +562,11 @@ struct cmd_spec cmd_table[] = {
"[options] <Domain>",
"-l <level> Specify the cache level to process, otherwise L3 cache is processed\n"
},
+ { "psr-mba-show",
+ &main_psr_mba_show, 0, 1,
+ "Show Memory Bandwidth Allocation information",
+ "<Domain>",
+ },
#endif
{ "usbctrl-attach",
diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
index bf41762..d7edab2 100644
--- a/tools/xl/xl_psr.c
+++ b/tools/xl/xl_psr.c
@@ -330,19 +330,21 @@ out:
return rc;
}
-static void psr_cat_print_one_domain_cbm_type(uint32_t domid, uint32_t socketid,
- libxl_psr_cbm_type type)
+static void psr_print_one_domain_val_type(uint32_t domid, uint32_t socketid,
+ libxl_psr_cbm_type type)
{
- uint64_t cbm;
+ uint64_t val;
- if (!libxl_psr_cat_get_cbm(ctx, domid, type, socketid, &cbm))
- printf("%#16"PRIx64, cbm);
+ if (!libxl_psr_get_val(ctx, domid, type, socketid, &val))
+ printf("%#16"PRIx64, val);
else
printf("%16s", "error");
}
-static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socketid,
- bool cdp_enabled, unsigned int lvl)
+static void psr_print_one_domain_val(uint32_t domid,
+ libxl_psr_hw_info *info,
+ libxl_psr_feat_type type,
+ unsigned int lvl)
{
char *domain_name;
@@ -350,106 +352,152 @@ static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socketid,
printf("%5d%25s", domid, domain_name);
free(domain_name);
- switch (lvl) {
- case 3:
- if (!cdp_enabled) {
- psr_cat_print_one_domain_cbm_type(domid, socketid,
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT_INFO:
+ switch (lvl) {
+ case 3:
+ if (!info->u.cat_info.cdp_enabled) {
+ psr_print_one_domain_val_type(domid, info->id,
LIBXL_PSR_CBM_TYPE_L3_CBM);
- } else {
- psr_cat_print_one_domain_cbm_type(domid, socketid,
+ } else {
+ psr_print_one_domain_val_type(domid, info->id,
LIBXL_PSR_CBM_TYPE_L3_CBM_CODE);
- psr_cat_print_one_domain_cbm_type(domid, socketid,
+ psr_print_one_domain_val_type(domid, info->id,
LIBXL_PSR_CBM_TYPE_L3_CBM_DATA);
- }
- break;
- case 2:
- psr_cat_print_one_domain_cbm_type(domid, socketid,
+ }
+ break;
+ case 2:
+ psr_print_one_domain_val_type(domid, info->id,
LIBXL_PSR_CBM_TYPE_L2_CBM);
+ break;
+ default:
+ printf("Input lvl %d is wrong!", lvl);
+ }
break;
- default:
- printf("Input lvl %d is wrong!", lvl);
+
+ case LIBXL_PSR_FEAT_TYPE_MBA_INFO:
+ psr_print_one_domain_val_type(domid, info->id,
+ LIBXL_PSR_CBM_TYPE_MBA_THRTL);
break;
}
printf("\n");
}
-static int psr_cat_print_domain_cbm(uint32_t domid, uint32_t socketid,
- bool cdp_enabled, unsigned int lvl)
+static int psr_print_domain_val(uint32_t domid,
+ libxl_psr_hw_info *info,
+ libxl_psr_feat_type type,
+ unsigned int lvl)
{
int i, nr_domains;
libxl_dominfo *list;
if (domid != INVALID_DOMID) {
- psr_cat_print_one_domain_cbm(domid, socketid, cdp_enabled, lvl);
+ psr_print_one_domain_val(domid, info, type, lvl);
return 0;
}
if (!(list = libxl_list_domain(ctx, &nr_domains))) {
- fprintf(stderr, "Failed to get domain list for cbm display\n");
- return -1;
+ fprintf(stderr, "Failed to get domain list for value display\n");
+ return EXIT_FAILURE;
}
for (i = 0; i < nr_domains; i++)
- psr_cat_print_one_domain_cbm(list[i].domid, socketid, cdp_enabled, lvl);
+ psr_print_one_domain_val(list[i].domid, info, type, lvl);
libxl_dominfo_list_free(list, nr_domains);
return 0;
}
-static int psr_cat_print_socket(uint32_t domid, libxl_psr_cat_info *info,
- unsigned int lvl)
+static int psr_print_socket(uint32_t domid,
+ libxl_psr_hw_info *info,
+ libxl_psr_feat_type type,
+ unsigned int lvl)
{
- int rc;
- uint32_t l3_cache_size;
-
printf("%-16s: %u\n", "Socket ID", info->id);
- /* So far, CMT only supports L3 cache. */
- if (lvl == 3) {
- rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, &l3_cache_size);
- if (rc) {
- fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
- info->id);
- return -1;
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT_INFO:
+ {
+ int rc;
+ uint32_t l3_cache_size;
+
+ /* So far, CMT only supports L3 cache. */
+ if (lvl == 3) {
+ rc = libxl_psr_cmt_get_l3_cache_size(ctx, info->id, &l3_cache_size);
+ if (rc) {
+ fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
+ info->id);
+ return -1;
+ }
+ printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
}
- printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
+
+ printf("%-16s: %#llx\n", "Default CBM",
+ (1ull << info->u.cat_info.cbm_len) - 1);
+ if (info->u.cat_info.cdp_enabled)
+ printf("%5s%25s%16s%16s\n", "ID", "NAME", "CBM (code)", "CBM (data)");
+ else
+ printf("%5s%25s%16s\n", "ID", "NAME", "CBM");
+
+ break;
}
- printf("%-16s: %#llx\n", "Default CBM", (1ull << info->cbm_len) - 1);
- if (info->cdp_enabled)
- printf("%5s%25s%16s%16s\n", "ID", "NAME", "CBM (code)", "CBM (data)");
- else
- printf("%5s%25s%16s\n", "ID", "NAME", "CBM");
+ case LIBXL_PSR_FEAT_TYPE_MBA_INFO:
+ printf("%-16s: %u\n", "Default THRTL", 0);
+ printf("%5s%25s%16s\n", "ID", "NAME", "THRTL");
+ break;
- return psr_cat_print_domain_cbm(domid, info->id, info->cdp_enabled, lvl);
+ default:
+ fprintf(stderr, "Input feature type %d is wrong\n", type);
+ return EXIT_FAILURE;
+ }
+
+ return psr_print_domain_val(domid, info, type, lvl);
}
-static int psr_cat_show(uint32_t domid, unsigned int lvl)
+static int psr_val_show(uint32_t domid,
+ libxl_psr_feat_type type,
+ unsigned int lvl)
{
- int i, nr;
+ unsigned int i, nr;
int rc;
- libxl_psr_cat_info *info;
+ libxl_psr_hw_info *info;
- if (lvl != 2 && lvl != 3) {
- fprintf(stderr, "Input lvl %d is wrong\n", lvl);
+ switch (type) {
+ case LIBXL_PSR_FEAT_TYPE_CAT_INFO:
+ if (lvl != 2 && lvl != 3) {
+ fprintf(stderr, "Input lvl %d is wrong\n", lvl);
+ return EXIT_FAILURE;
+ }
+ break;
+
+ case LIBXL_PSR_FEAT_TYPE_MBA_INFO:
+ if (lvl) {
+ fprintf(stderr, "Input lvl %d is wrong\n", lvl);
+ return EXIT_FAILURE;
+ }
+ break;
+
+ default:
+ fprintf(stderr, "Input feature type %d is wrong\n", type);
return EXIT_FAILURE;
}
- rc = libxl_psr_cat_get_info(ctx, &info, &nr, lvl);
+ rc = libxl_psr_get_hw_info(ctx, &info, &nr, type, lvl);
if (rc) {
- fprintf(stderr, "Failed to get %s cat info\n", (lvl == 3)?"L3":"L2");
+ fprintf(stderr, "Failed to get info\n");
return rc;
}
for (i = 0; i < nr; i++) {
- rc = psr_cat_print_socket(domid, info + i, lvl);
+ rc = psr_print_socket(domid, info + i, type, lvl);
if (rc)
goto out;
}
out:
- libxl_psr_cat_info_list_free(info, nr);
+ libxl_psr_hw_info_list_free(info, nr);
return rc;
}
@@ -479,6 +527,27 @@ static int psr_l2_cat_hwinfo(void)
return rc;
}
+int main_psr_mba_show(int argc, char **argv)
+{
+ int opt;
+ uint32_t domid;
+
+ SWITCH_FOREACH_OPT(opt, "", NULL, "psr-mba-show", 0) {
+ /* No options */
+ }
+
+ if (optind >= argc)
+ domid = INVALID_DOMID;
+ else if (optind == argc - 1)
+ domid = find_domain(argv[optind]);
+ else {
+ help("psr-mba-show");
+ return 2;
+ }
+
+ return psr_val_show(domid, LIBXL_PSR_FEAT_TYPE_MBA_INFO, 0);
+}
+
static int psr_mba_hwinfo(void)
{
int rc;
@@ -618,7 +687,7 @@ int main_psr_cat_show(int argc, char **argv)
return 2;
}
- return psr_cat_show(domid, lvl);
+ return psr_val_show(domid, LIBXL_PSR_FEAT_TYPE_CAT_INFO, lvl);
}
int main_psr_hwinfo(int argc, char **argv)
--
1.9.1
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 12/13] tools: implemet new set value interface suitable for all psr allocation features
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (10 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-15 11:25 ` Wei Liu
2017-08-09 7:41 ` [PATCH v1 13/13] docs: add MBA description in docs Yi Sun
12 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch implements a new set value interface in tools suitable for all psr
allocation features and the whole flow. It also enables MBA support to set
MBA value in tools.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
tools/libxc/include/xenctrl.h | 6 ++---
tools/libxc/xc_psr.c | 9 ++++---
tools/libxl/libxl_psr.c | 56 +++++++++++++++++++++----------------------
tools/xl/xl.h | 1 +
tools/xl/xl_cmdtable.c | 6 +++++
tools/xl/xl_psr.c | 55 ++++++++++++++++++++++++++++++++++++++++++
6 files changed, 99 insertions(+), 34 deletions(-)
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index d7eabfb..3161bf6 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2499,9 +2499,9 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
uint64_t *tsc);
int xc_psr_cmt_enabled(xc_interface *xch);
-int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_val_type type, uint32_t target,
- uint64_t data);
+int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_val_type type, uint32_t target,
+ uint64_t data);
int xc_psr_get_domain_data(xc_interface *xch, uint32_t domid,
xc_psr_val_type type, uint32_t target,
uint64_t *data);
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index de501b0..4dde76f 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -248,9 +248,9 @@ int xc_psr_cmt_enabled(xc_interface *xch)
return 0;
}
-int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
- xc_psr_val_type type, uint32_t target,
- uint64_t data)
+int xc_psr_set_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_val_type type, uint32_t target,
+ uint64_t data)
{
DECLARE_DOMCTL;
uint32_t cmd;
@@ -269,6 +269,9 @@ int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
case XC_PSR_CAT_L2_CBM:
cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM;
break;
+ case XC_PSR_MBA_THRTL:
+ cmd = XEN_DOMCTL_PSR_MBA_OP_SET_THRTL;
+ break;
default:
errno = EINVAL;
return -1;
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 4b91e9b..fe0a868 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -328,33 +328,7 @@ int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, libxl_bitmap *target_map,
uint64_t cbm)
{
- GC_INIT(ctx);
- int rc;
- int socketid, nr_sockets;
-
- rc = libxl__count_physical_sockets(gc, &nr_sockets);
- if (rc) {
- LOGED(ERROR, domid, "failed to get system socket count");
- goto out;
- }
-
- libxl_for_each_set_bit(socketid, *target_map) {
- xc_psr_val_type xc_type;
-
- if (socketid >= nr_sockets)
- break;
-
- xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
- if (xc_psr_cat_set_domain_data(ctx->xch, domid, xc_type,
- socketid, cbm)) {
- libxl__psr_alloc_log_err_msg(gc, errno, type);
- rc = ERROR_FAIL;
- }
- }
-
-out:
- GC_FREE;
- return rc;
+ return libxl_psr_set_val(ctx, domid, type, target_map, cbm);
}
int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
@@ -434,7 +408,33 @@ int libxl_psr_set_val(libxl_ctx *ctx, uint32_t domid,
libxl_psr_cbm_type type, libxl_bitmap *target_map,
uint64_t val)
{
- return ERROR_FAIL;
+ GC_INIT(ctx);
+ int rc;
+ int socketid, nr_sockets;
+
+ rc = libxl__count_physical_sockets(gc, &nr_sockets);
+ if (rc) {
+ LOGED(ERROR, domid, "failed to get system socket count");
+ goto out;
+ }
+
+ libxl_for_each_set_bit(socketid, *target_map) {
+ xc_psr_val_type xc_type;
+
+ if (socketid >= nr_sockets)
+ break;
+
+ xc_type = libxl__psr_cbm_type_to_libxc_psr_val_type(type);
+ if (xc_psr_set_domain_data(ctx->xch, domid, xc_type,
+ socketid, val)) {
+ libxl__psr_alloc_log_err_msg(gc, errno, type);
+ rc = ERROR_FAIL;
+ }
+ }
+
+out:
+ GC_FREE;
+ return rc;
}
int libxl_psr_get_val(libxl_ctx *ctx, uint32_t domid,
diff --git a/tools/xl/xl.h b/tools/xl/xl.h
index 59065c4..2cbe89c 100644
--- a/tools/xl/xl.h
+++ b/tools/xl/xl.h
@@ -206,6 +206,7 @@ int main_psr_cmt_show(int argc, char **argv);
#ifdef LIBXL_HAVE_PSR_CAT
int main_psr_cat_cbm_set(int argc, char **argv);
int main_psr_cat_show(int argc, char **argv);
+int main_psr_mba_set(int argc, char **argv);
int main_psr_mba_show(int argc, char **argv);
#endif
int main_qemu_monitor_command(int argc, char **argv);
diff --git a/tools/xl/xl_cmdtable.c b/tools/xl/xl_cmdtable.c
index 19e5004..5f7122d 100644
--- a/tools/xl/xl_cmdtable.c
+++ b/tools/xl/xl_cmdtable.c
@@ -562,6 +562,12 @@ struct cmd_spec cmd_table[] = {
"[options] <Domain>",
"-l <level> Specify the cache level to process, otherwise L3 cache is processed\n"
},
+ { "psr-mba-set",
+ &main_psr_mba_set, 0, 1,
+ "Set throttling value (THRTL) for a domain",
+ "[options] <Domain> <THRTL>",
+ "-s <socket> Specify the socket to process, otherwise all sockets are processed\n"
+ },
{ "psr-mba-show",
&main_psr_mba_show, 0, 1,
"Show Memory Bandwidth Allocation information",
diff --git a/tools/xl/xl_psr.c b/tools/xl/xl_psr.c
index d7edab2..e6e5458 100644
--- a/tools/xl/xl_psr.c
+++ b/tools/xl/xl_psr.c
@@ -548,6 +548,61 @@ int main_psr_mba_show(int argc, char **argv)
return psr_val_show(domid, LIBXL_PSR_FEAT_TYPE_MBA_INFO, 0);
}
+int main_psr_mba_set(int argc, char **argv)
+{
+ uint32_t domid;
+ libxl_psr_cbm_type type;
+ uint64_t thrtl;
+ int ret, opt = 0;
+ libxl_bitmap target_map;
+ char *value;
+ libxl_string_list socket_list;
+ unsigned long start, end;
+ unsigned int i, j, len;
+
+ static struct option opts[] = {
+ {"socket", 1, 0, 's'},
+ COMMON_LONG_OPTS
+ };
+
+ libxl_socket_bitmap_alloc(ctx, &target_map, 0);
+ libxl_bitmap_set_none(&target_map);
+
+ SWITCH_FOREACH_OPT(opt, "s:", opts, "psr-mba-set", 0) {
+ case 's':
+ trim(isspace, optarg, &value);
+ split_string_into_string_list(value, ",", &socket_list);
+ len = libxl_string_list_length(&socket_list);
+ for (i = 0; i < len; i++) {
+ parse_range(socket_list[i], &start, &end);
+ for (j = start; j <= end; j++)
+ libxl_bitmap_set(&target_map, j);
+ }
+
+ libxl_string_list_dispose(&socket_list);
+ free(value);
+ break;
+ }
+
+ type = LIBXL_PSR_CBM_TYPE_MBA_THRTL;
+
+ if (libxl_bitmap_is_empty(&target_map))
+ libxl_bitmap_set_any(&target_map);
+
+ if (argc != optind + 2) {
+ help("psr-mba-set");
+ return 2;
+ }
+
+ domid = find_domain(argv[optind]);
+ thrtl = strtoll(argv[optind + 1], NULL , 0);
+
+ ret = libxl_psr_set_val(ctx, domid, type, &target_map, thrtl);
+
+ libxl_bitmap_dispose(&target_map);
+ return ret;
+}
+
static int psr_mba_hwinfo(void)
{
int rc;
--
1.9.1
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^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v1 13/13] docs: add MBA description in docs
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
` (11 preceding siblings ...)
2017-08-09 7:41 ` [PATCH v1 12/13] tools: implemet new set " Yi Sun
@ 2017-08-09 7:41 ` Yi Sun
2017-08-15 11:26 ` Wei Liu
12 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-09 7:41 UTC (permalink / raw)
To: xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, Yi Sun, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
This patch adds MBA description in related documents.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
docs/man/xl.pod.1.in | 33 ++++++++++++++++++++++++++
docs/misc/xl-psr.markdown | 60 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 93 insertions(+)
diff --git a/docs/man/xl.pod.1.in b/docs/man/xl.pod.1.in
index 16c8306..61f5bcb 100644
--- a/docs/man/xl.pod.1.in
+++ b/docs/man/xl.pod.1.in
@@ -1798,6 +1798,39 @@ processed.
=back
+=head2 Memory Bandwidth Allocation
+
+Intel Skylake and later server platforms offer capabilities to configure and
+make use of the Memory Bandwidth Allocation (MBA) mechanisms, which provides
+OS/VMMs the ability to slow misbehaving apps/VMs or create advanced closed-loop
+control system via exposing control over a credit-based throttling mechanism.
+In the Xen implementation, MBA is used to control memory bandwidth on VM basis.
+To enforce bandwidth on a specific domain, just set throttling value (THRTL)
+for the domain.
+
+=over 4
+
+=item B<psr-mba-set> [I<OPTIONS>] I<domain-id> I<thrtl>
+
+Set throttling value (THRTL) for a domain. For how to specify I<thrtl>
+please refer to L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html>.
+
+B<OPTIONS>
+
+=over 4
+
+=item B<-s SOCKET>, B<--socket=SOCKET>
+
+Specify the socket to process, otherwise all sockets are processed.
+
+=back
+
+=item B<psr-mba-show> [I<domain-id>]
+
+Show MBA settings for a certain domain or all domains.
+
+=back
+
=head1 IGNORED FOR COMPATIBILITY WITH XM
xl is mostly command-line compatible with the old xm utility used with
diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
index 04dd957..59d93ef 100644
--- a/docs/misc/xl-psr.markdown
+++ b/docs/misc/xl-psr.markdown
@@ -186,6 +186,66 @@ Setting data CBM for a domain:
Setting the same code and data CBM for a domain:
`xl psr-cat-set <domid> <cbm>`
+## Memory Bandwidth Allocation (MBA)
+
+Memory Bandwidth Allocation (MBA) is a new feature available on Intel
+Skylake and later server platforms that allows an OS or Hypervisor/VMM to
+slow misbehaving apps/VMs or create advanced closed-loop control system via
+exposing control over a credit-based throttling mechanism. To enforce bandwidth
+on a specific domain, just set throttling value (THRTL) into Class of Service
+(COS). MBA provides two THRTL mode. One is linear mode and the other is
+non-linear mode.
+
+In the linear mode the input precision is defined as 100-(THRTL_MAX). Values
+not an even multiple of the precision (e.g., 12%) will be rounded down (e.g.,
+to 10% delay applied).
+
+If linear values are not supported then input delay values are powers-of-two
+from zero to the THRTL_MAX value from CPUID. In this case any values not a power
+of two will be rounded down the next nearest power of two.
+
+For example, assuming a system with 2 domains:
+
+ * A THRTL of 0x0 for every domain means each domain can access the whole cache
+ without any delay. This is the default.
+
+ * Linear mode: Giving one domain a THRTL of 0xC and the other domain's 0 means
+ that the first domain gets 10% delay to access the cache and the other one
+ without any delay.
+
+ * Non-linear mode: Giving one domain a THRTL of 0xC and the other domain's 0
+ means that the first domain gets 8% delay to access the cache and the other
+ one without any delay.
+
+For more detailed information please refer to Intel SDM chapter
+"Introduction to Memory Bandwidth Allocation".
+
+In Xen's implementation, THRTL can be configured with libxl/xl interfaces but
+COS is maintained in hypervisor only. The cache partition granularity is per
+domain, each domain has COS=0 assigned by default, the corresponding THRTL is
+0, which means all the cache resource can be accessed without delay.
+
+### xl interfaces
+
+System MBA information such as maximum COS and maximum THRTL can be obtained by:
+
+`xl psr-hwinfo --mba`
+
+The simplest way to change a domain's THRTL from its default is running:
+
+`xl psr-mba-set [OPTIONS] <domid> <thrtl>`
+
+In a multi-socket system, the same thrtl will be set on each socket by default.
+Per socket thrtl can be specified with the `--socket SOCKET` option.
+
+Setting the THRTL may not be successful if insufficient COS is available. In
+such case unused COS(es) may be freed by setting THRTL of all related domains to
+its default value(0).
+
+Per domain THRTL settings can be shown by:
+
+`xl psr-mba-show [OPTIONS] <domid>`
+
## Reference
[1] Intel SDM
--
1.9.1
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^ permalink raw reply related [flat|nested] 50+ messages in thread
* Re: [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-08-09 7:41 ` [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
@ 2017-08-14 7:35 ` Chao Peng
2017-08-14 8:23 ` Yi Sun
2017-08-15 10:08 ` Wei Liu
1 sibling, 1 reply; 50+ messages in thread
From: Chao Peng @ 2017-08-14 7:35 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
> + Linear mode: the input precision is defined as 100-(MBA_MAX).
> For instance,
> + if the MBA_MAX value is 90, the input precision is 10%. Values
> not an even
> + multiple of the precision (e.g., 12%) will be rounded down
> (e.g., to 10%
> + delay applied) by HW automatically.
No sure if all people unterstand HW, if not then I prefer Hardware. If
you do this then all places though the document should be replaced.
> + When context switch happens, the COS ID of VCPU is written to per-
> thread MSR
COS ID is per-domain other than per-vCPU at this time. So 'COS ID of
domain' is more accurate.
> + `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation
> according
> + to the throttling value stored in the COS register.
There is no COS register in fact. COS exists just a concept.
> +For example:
> + root@:~$ xl psr-hwinfo --mba
> + Memory Bandwidth Allocation (MBA):
> + Socket ID : 0
> + Linear Mode : Enabled
> + Maximum COS : 7
> + Maximum Throttling Value: 90
> + Default Throttling Value: 0
> +
> + root@:~$ xl psr-mba-set 1 0xa
> +
> + root@:~$ xl psr-mba-show 1
> + Socket ID : 0
> + Default THRTL : 0
> + ID NAME THRTL
> + 1 ubuntu14 0xa
> +
> +# Areas for improvement
> +
> +A hexadecimal number is used to show THRTL for a domain now. It may
> not be user-
> +friendly.
> +
> +To improve this, the libxl interfaces can be wrapped in libvirt to
> provide more
> +usr-friendly interfaces to user, e.g. a percentage number to show for
> linear
> +mode.
I suggest we can do this even for 'xl psr-mba-show', as we know we are
in linear mode or not. A hex number is just not easy to understand for
people. And for 'xl psr-mba-set' it is also much straighforward to set a
percentage number in linear mode.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-08-14 7:35 ` Chao Peng
@ 2017-08-14 8:23 ` Yi Sun
2017-08-14 9:36 ` Chao Peng
0 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-14 8:23 UTC (permalink / raw)
To: Chao Peng
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On 17-08-14 15:35:38, Chao Peng wrote:
>
> > + Linear mode: the input precision is defined as 100-(MBA_MAX).
> > For instance,
> > + if the MBA_MAX value is 90, the input precision is 10%. Values
> > not an even
> > + multiple of the precision (e.g., 12%) will be rounded down
> > (e.g., to 10%
> > + delay applied) by HW automatically.
>
> No sure if all people unterstand HW, if not then I prefer Hardware. If
> you do this then all places though the document should be replaced.
>
We may explain 'HW' in 'Terminology'.
>
> > + When context switch happens, the COS ID of VCPU is written to per-
> > thread MSR
>
> COS ID is per-domain other than per-vCPU at this time. So 'COS ID of
> domain' is more accurate.
>
Yes, thanks.
> > + `IA32_PQR_ASSOC`, and then hardware enforces bandwidth allocation
> > according
> > + to the throttling value stored in the COS register.
>
> There is no COS register in fact. COS exists just a concept.
>
Ok, I will state the formal register name defined in SDM here.
> > +For example:
> > + root@:~$ xl psr-hwinfo --mba
> > + Memory Bandwidth Allocation (MBA):
> > + Socket ID : 0
> > + Linear Mode : Enabled
> > + Maximum COS : 7
> > + Maximum Throttling Value: 90
> > + Default Throttling Value: 0
> > +
> > + root@:~$ xl psr-mba-set 1 0xa
> > +
> > + root@:~$ xl psr-mba-show 1
> > + Socket ID : 0
> > + Default THRTL : 0
> > + ID NAME THRTL
> > + 1 ubuntu14 0xa
> > +
> > +# Areas for improvement
> > +
> > +A hexadecimal number is used to show THRTL for a domain now. It may
> > not be user-
> > +friendly.
> > +
> > +To improve this, the libxl interfaces can be wrapped in libvirt to
> > provide more
> > +usr-friendly interfaces to user, e.g. a percentage number to show for
> > linear
> > +mode.
>
> I suggest we can do this even for 'xl psr-mba-show', as we know we are
> in linear mode or not. A hex number is just not easy to understand for
So your suggestion is to show decimal value for linear mode, right? How about
non-linear mode, still show hexadecimal value?
> people. And for 'xl psr-mba-set' it is also much straighforward to set a
> percentage number in linear mode.
>
For set, we do not have any limitation. User can input decimal or hexadecimal
value.
> Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-08-14 8:23 ` Yi Sun
@ 2017-08-14 9:36 ` Chao Peng
0 siblings, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-14 9:36 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
> > > +
> > > +# Areas for improvement
> > > +
> > > +A hexadecimal number is used to show THRTL for a domain now. It
> > > may
> > > not be user-
> > > +friendly.
> > > +
> > > +To improve this, the libxl interfaces can be wrapped in libvirt
> > > to
> > > provide more
> > > +usr-friendly interfaces to user, e.g. a percentage number to show
> > > for
> > > linear
> > > +mode.
> >
> > I suggest we can do this even for 'xl psr-mba-show', as we know we
> > are
> > in linear mode or not. A hex number is just not easy to understand
> > for
>
> So your suggestion is to show decimal value for linear mode, right?
> How about
> non-linear mode, still show hexadecimal value?
Exactly.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-08-09 7:41 ` [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-08-14 7:35 ` Chao Peng
@ 2017-08-15 10:08 ` Wei Liu
2017-08-16 2:51 ` Yi Sun
1 sibling, 1 reply; 50+ messages in thread
From: Wei Liu @ 2017-08-15 10:08 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, roger.pau
On Wed, Aug 09, 2017 at 03:41:40PM +0800, Yi Sun wrote:
> +# Overview
> +
> +The Memory Bandwidth Allocation (MBA) feature provides indirect and approximate
> +control over memory bandwidth available per-core. This feature provides OS/
> +hypervisor the ability to slow misbehaving apps/domains or create advanced
> +closed-loop control system via exposing control over a credit-based throttling
> +mechanism.
> +
> +# User details
> +
> +* Feature Enabling:
> +
> + Add "psr=mba" to boot line parameter to enable MBA feature.
> +
> +* xl interfaces:
> +
> + 1. `psr-mba-show [domain-id]`:
> +
> + Show memory bandwidth throttling for domain.
> +
> + 2. `psr-mba-set [OPTIONS] domain-id throttling`:
> +
When specifying arguments to a command, we normally use the form
<mandatory_argument> and [optional_argument].
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general
2017-08-09 7:41 ` [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
@ 2017-08-15 10:12 ` Wei Liu
2017-08-16 2:48 ` Yi Sun
2017-08-15 14:03 ` Daniel De Graaf
1 sibling, 1 reply; 50+ messages in thread
From: Wei Liu @ 2017-08-15 10:12 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, Daniel De Graaf, roger.pau
You forgot to CC XSM maintainer. I have done that for you.
On Wed, Aug 09, 2017 at 03:41:41PM +0800, Yi Sun wrote:
> This patch renames PSR sysctl/domctl interfaces and related xsm policy to
> make them be general for all resource allocation features but not only
> for CAT. Then, we can resuse the interfaces for all allocation features.
>
> Basically, it changes 'cat' to 'alloc'. E.g.:
> 1. psr_cat_op -> psr_alloc_op
> 2. XEN_DOMCTL_psr_cat_op -> XEN_DOMCTL_psr_alloc_op
> 3. XEN_SYSCTL_psr_cat_op -> XEN_SYSCTL_psr_alloc_op
>
> The sysctl/domctl version numbers are bumped.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Subject to an ack / review from relevant maintainers:
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general
2017-08-09 7:41 ` [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general Yi Sun
@ 2017-08-15 10:13 ` Wei Liu
2017-08-16 2:17 ` Chao Peng
1 sibling, 0 replies; 50+ messages in thread
From: Wei Liu @ 2017-08-15 10:13 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, roger.pau
On Wed, Aug 09, 2017 at 03:41:42PM +0800, Yi Sun wrote:
> This patch renames 'cbm_type' to 'psr_val_type' to make it be general.
> Then, we can reuse this for all psr allocation features.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Subject to ack / review from relevant maintainers:
Reviewed-by: Wei Liu <wei.liu2@citrix.com>
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* Re: [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA
2017-08-09 7:41 ` [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA Yi Sun
@ 2017-08-15 10:50 ` Wei Liu
2017-08-16 7:18 ` Yi Sun
2017-08-16 3:14 ` Chao Peng
1 sibling, 1 reply; 50+ messages in thread
From: Wei Liu @ 2017-08-15 10:50 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, roger.pau
On Wed, Aug 09, 2017 at 03:41:43PM +0800, Yi Sun wrote:
> This patch implements main data structures of MBA.
>
> Like CAT features, MBA HW info has cos_max which means the max cos
> registers number, and thrtl_max which means the max throttle value
> (delay value). It also has a flag to represent if the throttle
> value is linear or not.
>
> One COS register of MBA stores a throttle value for one or more
> domains. The throttle value means the transaction time between L2
> cache and next level memory to be delayed.
>
> This patch also implements init flow for MBA and register stub
> callback functions.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v1:
> - rebase codes onto L2 CAT v15.
> - use '(1u << X)'.
> (suggested by Wei Liu)
> - move comment to appropriate place.
> (suggested by Chao Peng)
> - implement 'mba_init_feature' and keep 'cat_init_feature'.
> (suggested by Chao Peng)
> - keep 'regs.b' into a local variable to avoid reading CPUID every time.
> (suggested by Chao Peng)
> ---
> xen/arch/x86/psr.c | 144 ++++++++++++++++++++++++++++++++++------
> xen/include/asm-x86/msr-index.h | 1 +
> xen/include/asm-x86/psr.h | 2 +
> 3 files changed, 126 insertions(+), 21 deletions(-)
>
> diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> index 5ec00a9..d94a5b1 100644
> --- a/xen/arch/x86/psr.c
> +++ b/xen/arch/x86/psr.c
> @@ -27,13 +27,16 @@
> * - CMT Cache Monitoring Technology
> * - COS/CLOS Class of Service. Also mean COS registers.
> * - COS_MAX Max number of COS for the feature (minus 1)
> + * - MBA Memory Bandwidth Allocation
> * - MSRs Machine Specific Registers
> * - PSR Intel Platform Shared Resource
> + * - THRTL_MAX Max throttle value (delay value) of MBA
> */
>
> -#define PSR_CMT (1<<0)
> -#define PSR_CAT (1<<1)
> -#define PSR_CDP (1<<2)
> +#define PSR_CMT (1u << 0)
> +#define PSR_CAT (1u << 1)
> +#define PSR_CDP (1u << 2)
> +#define PSR_MBA (1u << 3)
I would split this part out to a separate patch so that it can be
applied immediately.
>
> #define CAT_CBM_LEN_MASK 0x1f
> #define CAT_COS_MAX_MASK 0xffff
> @@ -60,10 +63,14 @@
> */
> #define MAX_COS_NUM 2
>
> +#define MBA_LINEAR (1u << 2)
> +#define MBA_THRTL_MAX_MASK 0xfff
> +
> enum psr_feat_type {
> FEAT_TYPE_L3_CAT,
> FEAT_TYPE_L3_CDP,
> FEAT_TYPE_L2_CAT,
> + FEAT_TYPE_MBA,
> FEAT_TYPE_NUM,
> FEAT_TYPE_UNKNOWN,
> };
> @@ -71,7 +78,6 @@ enum psr_feat_type {
> /*
> * This structure represents one feature.
> * cos_max - The max COS registers number got through CPUID.
> - * cbm_len - The length of CBM got through CPUID.
> * cos_reg_val - Array to store the values of COS registers. One entry stores
> * the value of one COS register.
> * For L3 CAT and L2 CAT, one entry corresponds to one COS_ID.
> @@ -80,9 +86,23 @@ enum psr_feat_type {
> * cos_reg_val[1] (Code).
> */
> struct feat_node {
> - /* cos_max and cbm_len are common values for all features so far. */
> + /* cos_max is common values for all features so far. */
> unsigned int cos_max;
> - unsigned int cbm_len;
> +
> + /* Feature specific HW info. */
> + union {
> + struct {
> + /* The length of CBM got through CPUID. */
> + unsigned int cbm_len;
> + } cat_info;
> +
> + struct {
> + /* The max throttling value got through CPUID. */
> + unsigned int thrtl_max;
> + unsigned int linear;
> + } mba_info;
> + };
> +
I suggest you add a tag to specify which struct is in effect in the
union and ASSERT accordingly in their respective type specific
functions.
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all psr allocation features
2017-08-09 7:41 ` [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all " Yi Sun
@ 2017-08-15 11:14 ` Wei Liu
2017-08-21 10:13 ` Chao Peng
1 sibling, 0 replies; 50+ messages in thread
From: Wei Liu @ 2017-08-15 11:14 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, roger.pau
On Wed, Aug 09, 2017 at 03:41:48PM +0800, Yi Sun wrote:
> This patch implements a new get hw info interface suitable for all psr allocation
> features and the whole flow. It also enables MBA support in tools to get MBA
> HW info.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
I would suggest you add to the commit message to better describe
the content of the patch. Like:
Introduce a bunch of things in libxc ... Implement a new function on
libxl to do XXX, the existing function libxl_psr_cat_get_info is
changed to use the new function ...
And then you will discover certain things are better split out to
separate patches so reviewers can more easily review / ack them.
I have gone through this patch. The code looks sensible but I'm not yet
confident to say it is alright. I would appreciate you break this patch
down a bit if possible.
I will leave reviewing the xl bits to Chao -- he knows the relationship
between various features better than I do.
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type'
2017-08-09 7:41 ` [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type' Yi Sun
@ 2017-08-15 11:15 ` Wei Liu
2017-08-21 10:13 ` Chao Peng
1 sibling, 0 replies; 50+ messages in thread
From: Wei Liu @ 2017-08-15 11:15 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, roger.pau
On Wed, Aug 09, 2017 at 03:41:49PM +0800, Yi Sun wrote:
> This patch renames 'xc_psr_cat_type' to 'xc_psr_val_type' so that
> the structure name is common for all allocation features.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
A patch like this is much easier to review.
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features
2017-08-09 7:41 ` [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features Yi Sun
@ 2017-08-15 11:24 ` Wei Liu
2017-08-21 10:14 ` Chao Peng
1 sibling, 0 replies; 50+ messages in thread
From: Wei Liu @ 2017-08-15 11:24 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, roger.pau
On Wed, Aug 09, 2017 at 03:41:50PM +0800, Yi Sun wrote:
> This patch implements a new get value interface in tools suitable for all psr
> allocation features and the whole flow. It also enables MBA support in tools
> to get MBA value.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Again, I would appreciate you write down what is done in this patch in
the commit message.
Luckily this patch doesn't look too complex so:
Acked-by: Wei Liu <wei.liu2@citrix.com>
I would also like an ack or review from Chao on the xl bits, to confirm
he is okay with the command line interface.
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 12/13] tools: implemet new set value interface suitable for all psr allocation features
2017-08-09 7:41 ` [PATCH v1 12/13] tools: implemet new set " Yi Sun
@ 2017-08-15 11:25 ` Wei Liu
2017-08-21 10:15 ` Chao Peng
0 siblings, 1 reply; 50+ messages in thread
From: Wei Liu @ 2017-08-15 11:25 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, roger.pau
On Wed, Aug 09, 2017 at 03:41:51PM +0800, Yi Sun wrote:
> This patch implements a new set value interface in tools suitable for all psr
> allocation features and the whole flow. It also enables MBA support to set
> MBA value in tools.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Same comment on commit message in previous patch applies here, too.
And Chao please confirm you're okay with the xl interface.
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 13/13] docs: add MBA description in docs
2017-08-09 7:41 ` [PATCH v1 13/13] docs: add MBA description in docs Yi Sun
@ 2017-08-15 11:26 ` Wei Liu
0 siblings, 0 replies; 50+ messages in thread
From: Wei Liu @ 2017-08-15 11:26 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
xen-devel, roger.pau
On Wed, Aug 09, 2017 at 03:41:52PM +0800, Yi Sun wrote:
> This patch adds MBA description in related documents.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Wei Liu <wei.liu2@citrix.com>
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general
2017-08-09 7:41 ` [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
2017-08-15 10:12 ` Wei Liu
@ 2017-08-15 14:03 ` Daniel De Graaf
1 sibling, 0 replies; 50+ messages in thread
From: Daniel De Graaf @ 2017-08-15 14:03 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, chao.p.peng,
roger.pau
On 08/09/2017 03:41 AM, Yi Sun wrote:
> This patch renames PSR sysctl/domctl interfaces and related xsm policy to
> make them be general for all resource allocation features but not only
> for CAT. Then, we can resuse the interfaces for all allocation features.
>
> Basically, it changes 'cat' to 'alloc'. E.g.:
> 1. psr_cat_op -> psr_alloc_op
> 2. XEN_DOMCTL_psr_cat_op -> XEN_DOMCTL_psr_alloc_op
> 3. XEN_SYSCTL_psr_cat_op -> XEN_SYSCTL_psr_alloc_op
>
> The sysctl/domctl version numbers are bumped.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Acked-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general
2017-08-09 7:41 ` [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general Yi Sun
2017-08-15 10:13 ` Wei Liu
@ 2017-08-16 2:17 ` Chao Peng
1 sibling, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-16 2:17 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
> -enum cbm_type {
> - PSR_CBM_TYPE_L3,
> - PSR_CBM_TYPE_L3_CODE,
> - PSR_CBM_TYPE_L3_DATA,
> - PSR_CBM_TYPE_L2,
> - PSR_CBM_TYPE_UNKNOWN,
> +enum psr_val_type {
> + PSR_VAL_TYPE_L3,
> + PSR_VAL_TYPE_L3_CODE,
> + PSR_VAL_TYPE_L3_DATA,
> + PSR_VAL_TYPE_L2,
> + PSR_VAL_TYPE_UNKNOWN,
I'd like to change PSR_CBM_TYPE_* to PSR_VAL_TYPE_*_CBM to be more
specific, E.g. PSR_CBM_TYPE_L3 => PSR_VAL_TYPE_L3_CBM.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general
2017-08-15 10:12 ` Wei Liu
@ 2017-08-16 2:48 ` Yi Sun
0 siblings, 0 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-16 2:48 UTC (permalink / raw)
To: Wei Liu
Cc: kevin.tian, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel,
Daniel De Graaf, roger.pau
On 17-08-15 11:12:36, Wei Liu wrote:
> You forgot to CC XSM maintainer. I have done that for you.
>
Thank you!
> On Wed, Aug 09, 2017 at 03:41:41PM +0800, Yi Sun wrote:
> > This patch renames PSR sysctl/domctl interfaces and related xsm policy to
> > make them be general for all resource allocation features but not only
> > for CAT. Then, we can resuse the interfaces for all allocation features.
> >
> > Basically, it changes 'cat' to 'alloc'. E.g.:
> > 1. psr_cat_op -> psr_alloc_op
> > 2. XEN_DOMCTL_psr_cat_op -> XEN_DOMCTL_psr_alloc_op
> > 3. XEN_SYSCTL_psr_cat_op -> XEN_SYSCTL_psr_alloc_op
> >
> > The sysctl/domctl version numbers are bumped.
> >
> > Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
>
> Subject to an ack / review from relevant maintainers:
>
> Reviewed-by: Wei Liu <wei.liu2@citrix.com>
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document
2017-08-15 10:08 ` Wei Liu
@ 2017-08-16 2:51 ` Yi Sun
0 siblings, 0 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-16 2:51 UTC (permalink / raw)
To: Wei Liu
Cc: kevin.tian, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel,
roger.pau
On 17-08-15 11:08:32, Wei Liu wrote:
> On Wed, Aug 09, 2017 at 03:41:40PM +0800, Yi Sun wrote:
> > +# Overview
> > +
> > +The Memory Bandwidth Allocation (MBA) feature provides indirect and approximate
> > +control over memory bandwidth available per-core. This feature provides OS/
> > +hypervisor the ability to slow misbehaving apps/domains or create advanced
> > +closed-loop control system via exposing control over a credit-based throttling
> > +mechanism.
> > +
> > +# User details
> > +
> > +* Feature Enabling:
> > +
> > + Add "psr=mba" to boot line parameter to enable MBA feature.
> > +
> > +* xl interfaces:
> > +
> > + 1. `psr-mba-show [domain-id]`:
> > +
> > + Show memory bandwidth throttling for domain.
> > +
> > + 2. `psr-mba-set [OPTIONS] domain-id throttling`:
> > +
>
> When specifying arguments to a command, we normally use the form
> <mandatory_argument> and [optional_argument].
Got it, thanks! Will change these.
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA
2017-08-09 7:41 ` [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA Yi Sun
2017-08-15 10:50 ` Wei Liu
@ 2017-08-16 3:14 ` Chao Peng
1 sibling, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-16 3:14 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
On Wed, 2017-08-09 at 15:41 +0800, Yi Sun wrote:
> This patch implements main data structures of MBA.
>
> Like CAT features, MBA HW info has cos_max which means the max cos
> registers number, and thrtl_max which means the max throttle value
Similarly, there is no existence of 'cos register', 'cos number' is even
better or anything else.
> (delay value). It also has a flag to represent if the throttle
> value is linear or not.
>
> One COS register of MBA stores a throttle value for one or more
Ditto.
^s
...
> -/* CAT common functions implementation. */
> +/* Implementation of allocation features' functions. */
> static int cat_init_feature(const struct cpuid_leaf *regs,
> struct feat_node *feat,
> struct psr_socket_info *info,
> @@ -289,7 +310,6 @@ static int cat_init_feature(const struct
> cpuid_leaf *regs,
> if ( !regs->a || !regs->d )
> return -ENOENT;
>
> - feat->cbm_len = (regs->a & CAT_CBM_LEN_MASK) + 1;
Does this have to be moved?
...
> +
> + feat->cos_reg_val[0] = 0;
> + wrmsrl(MSR_IA32_PSR_MBA_MASK(0), 0);
It's better to have a comment here to explain what the defaul value '0'
stands for in both linear mode and non-linear mode.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 05/13] x86: implement get hw info flow for MBA
2017-08-09 7:41 ` [PATCH v1 05/13] x86: implement get hw info " Yi Sun
@ 2017-08-16 3:23 ` Chao Peng
0 siblings, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-16 3:23 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
On Wed, 2017-08-09 at 15:41 +0800, Yi Sun wrote:
> This patch implements get HW info flow for MBA including its callback
> function and sysctl interface.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
> v1:
> - sort 'PSR_INFO_IDX_' macros as feature.
> (suggested by Chao Peng)
> - rename 'PSR_INFO_IDX_MBA_LINEAR' to 'PSR_INFO_IDX_MBA_FLAG'.
> - rename 'linear' in 'struct mba_info' to 'flags' for future
> extension.
> (suggested by Chao Peng)
> ---
> xen/arch/x86/psr.c | 13 ++++++++++++-
> xen/arch/x86/sysctl.c | 19 +++++++++++++++++++
> xen/include/asm-x86/psr.h | 2 ++
> xen/include/public/sysctl.h | 8 ++++++++
> 4 files changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
> index d94a5b1..9455e67 100644
> --- a/xen/arch/x86/psr.c
> +++ b/xen/arch/x86/psr.c
> @@ -264,6 +264,10 @@ static enum psr_feat_type
> psr_val_type_to_feat_type(enum psr_val_type type)
> feat_type = FEAT_TYPE_L2_CAT;
> break;
>
> + case PSR_VAL_TYPE_MBA:
> + feat_type = FEAT_TYPE_MBA;
> + break;
> +
> default:
> ASSERT_UNREACHABLE();
> }
> @@ -490,7 +494,14 @@ static const struct feat_props l2_cat_props = {
> static bool mba_get_feat_info(const struct feat_node *feat,
> uint32_t data[], unsigned int
> array_len)
> {
> - return false;
> + if ( array_len != PSR_INFO_ARRAY_SIZE )
> + return false;
> +
> + data[PSR_INFO_IDX_COS_MAX] = feat->cos_max;
> + data[PSR_INFO_IDX_MBA_THRTL_MAX] = feat->mba_info.thrtl_max;
> + data[PSR_INFO_IDX_MBA_FLAG] = feat->mba_info.linear;
Once it becomes a flag, then good practice would be operating it as a
flag. E.g. here assigning a bool value to a flag bit is error-prone once
more bits get used. Like XEN_SYSCTL_PSR_CAT_L3_CDP, you can set/clear
XEN_SYSCTL_PSR_MBA_LINEAR bit respectively.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 06/13] x86: implement get value interface for MBA
2017-08-09 7:41 ` [PATCH v1 06/13] x86: implement get value interface " Yi Sun
@ 2017-08-16 6:38 ` Chao Peng
2017-08-16 6:43 ` Yi Sun
0 siblings, 1 reply; 50+ messages in thread
From: Chao Peng @ 2017-08-16 6:38 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
On Wed, 2017-08-09 at 15:41 +0800, Yi Sun wrote:
> This patch implements get value domctl interface for MBA.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> ---
...
> --- a/xen/include/public/domctl.h
> +++ b/xen/include/public/domctl.h
> @@ -1144,6 +1144,7 @@ struct xen_domctl_psr_alloc_op {
> #define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
> #define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
> #define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
> +#define XEN_DOMCTL_PSR_MBA_OP_GET_THRTL 9
Why use 9 instead of 8?
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 06/13] x86: implement get value interface for MBA
2017-08-16 6:38 ` Chao Peng
@ 2017-08-16 6:43 ` Yi Sun
2017-08-17 7:51 ` Chao Peng
0 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-16 6:43 UTC (permalink / raw)
To: Chao Peng
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On 17-08-16 14:38:28, Chao Peng wrote:
> On Wed, 2017-08-09 at 15:41 +0800, Yi Sun wrote:
> > This patch implements get value domctl interface for MBA.
> >
> > Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> > ---
>
> ...
>
> > --- a/xen/include/public/domctl.h
> > +++ b/xen/include/public/domctl.h
> > @@ -1144,6 +1144,7 @@ struct xen_domctl_psr_alloc_op {
> > #define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
> > #define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
> > #define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
> > +#define XEN_DOMCTL_PSR_MBA_OP_GET_THRTL 9
>
> Why use 9 instead of 8?
>
8 is reserved for SET_THRTL. Follow the convention of CAT/CDP above. :)
> Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA
2017-08-15 10:50 ` Wei Liu
@ 2017-08-16 7:18 ` Yi Sun
2017-08-17 9:49 ` Wei Liu
0 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-16 7:18 UTC (permalink / raw)
To: Wei Liu
Cc: kevin.tian, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel,
roger.pau
On 17-08-15 11:50:15, Wei Liu wrote:
> On Wed, Aug 09, 2017 at 03:41:43PM +0800, Yi Sun wrote:
> > -#define PSR_CAT (1<<1)
> > -#define PSR_CDP (1<<2)
> > +#define PSR_CMT (1u << 0)
> > +#define PSR_CAT (1u << 1)
> > +#define PSR_CDP (1u << 2)
> > +#define PSR_MBA (1u << 3)
>
> I would split this part out to a separate patch so that it can be
> applied immediately.
>
A fix patch has been sent out.
> > struct feat_node {
> > - /* cos_max and cbm_len are common values for all features so far. */
> > + /* cos_max is common values for all features so far. */
> > unsigned int cos_max;
> > - unsigned int cbm_len;
> > +
> > + /* Feature specific HW info. */
> > + union {
> > + struct {
> > + /* The length of CBM got through CPUID. */
> > + unsigned int cbm_len;
> > + } cat_info;
> > +
> > + struct {
> > + /* The max throttling value got through CPUID. */
> > + unsigned int thrtl_max;
> > + unsigned int linear;
> > + } mba_info;
> > + };
> > +
>
> I suggest you add a tag to specify which struct is in effect in the
> union and ASSERT accordingly in their respective type specific
> functions.
Before using struct in this union at all places, there is check to make sure the
correct feature node is used. So, is it necessary to add an additional flag to
check? Thanks!
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 06/13] x86: implement get value interface for MBA
2017-08-16 6:43 ` Yi Sun
@ 2017-08-17 7:51 ` Chao Peng
0 siblings, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-17 7:51 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On Wed, 2017-08-16 at 14:43 +0800, Yi Sun wrote:
> On 17-08-16 14:38:28, Chao Peng wrote:
> >
> > On Wed, 2017-08-09 at 15:41 +0800, Yi Sun wrote:
> > >
> > > This patch implements get value domctl interface for MBA.
> > >
> > > Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
> > > ---
> >
> > ...
> >
> > >
> > > --- a/xen/include/public/domctl.h
> > > +++ b/xen/include/public/domctl.h
> > > @@ -1144,6 +1144,7 @@ struct xen_domctl_psr_alloc_op {
> > > #define XEN_DOMCTL_PSR_CAT_OP_GET_L3_DATA 5
> > > #define XEN_DOMCTL_PSR_CAT_OP_SET_L2_CBM 6
> > > #define XEN_DOMCTL_PSR_CAT_OP_GET_L2_CBM 7
> > > +#define XEN_DOMCTL_PSR_MBA_OP_GET_THRTL 9
> >
> > Why use 9 instead of 8?
> >
> 8 is reserved for SET_THRTL. Follow the convention of CAT/CDP above.
> :)
Understand. Then probably SET_THRTL patch should come first.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA
2017-08-16 7:18 ` Yi Sun
@ 2017-08-17 9:49 ` Wei Liu
0 siblings, 0 replies; 50+ messages in thread
From: Wei Liu @ 2017-08-17 9:49 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, Wei Liu, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, chao.p.peng, xen-devel,
roger.pau
On Wed, Aug 16, 2017 at 03:18:13PM +0800, Yi Sun wrote:
> On 17-08-15 11:50:15, Wei Liu wrote:
> > > struct feat_node {
> > > - /* cos_max and cbm_len are common values for all features so far. */
> > > + /* cos_max is common values for all features so far. */
> > > unsigned int cos_max;
> > > - unsigned int cbm_len;
> > > +
> > > + /* Feature specific HW info. */
> > > + union {
> > > + struct {
> > > + /* The length of CBM got through CPUID. */
> > > + unsigned int cbm_len;
> > > + } cat_info;
> > > +
> > > + struct {
> > > + /* The max throttling value got through CPUID. */
> > > + unsigned int thrtl_max;
> > > + unsigned int linear;
> > > + } mba_info;
> > > + };
> > > +
> >
> > I suggest you add a tag to specify which struct is in effect in the
> > union and ASSERT accordingly in their respective type specific
> > functions.
>
> Before using struct in this union at all places, there is check to make sure the
> correct feature node is used. So, is it necessary to add an additional flag to
> check? Thanks!
OK, in that case I think it is fine to not add a tag.
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 07/13] x86: implement set value flow for MBA
2017-08-09 7:41 ` [PATCH v1 07/13] x86: implement set value flow " Yi Sun
@ 2017-08-18 3:32 ` Chao Peng
2017-08-18 9:25 ` Yi Sun
0 siblings, 1 reply; 50+ messages in thread
From: Chao Peng @ 2017-08-18 3:32 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
> + if ( feat->mba_info.linear )
> + {
> + unsigned int mod;
> +
> + if ( feat->mba_info.thrtl_max >= 100 )
> + return false;
Can we do this check earlier, e.g. when it gets enumerated from CPUID?
> +
> + mod = *thrtl % (100 - feat->mba_info.thrtl_max);
> + *thrtl -= mod;
> + }
> + else
> + {
> + /* Not power of 2. */
> + if ( *thrtl & (*thrtl - 1) )
> + *thrtl = *thrtl & (1 << (flsl(*thrtl) - 1));
> + }
> +
Is it possible for *thrtl to be zero? Otherwise we need check that at
the beginning.
>
> +/*
> + * Because multiple features may co-exist, we need handle all
> features to write
> + * values of them into a COS register with new COS ID. E.g:
> + * 1. L3 CAT and MBA co-exist.
> + * 2. Dom1 and Dom2 share a same COS ID (2). The L3 CAT CBM of Dom1
> is 0x1ff,
> + * the MBA Thrtle of Dom1 is 0xa.
> + * 3. User wants to change MBA Thrtl of Dom1 to be 0x14. Because COS
> ID 2 is
> + * used by Dom2 too, we have to pick a new COS ID 3. The original
> values of
> + * Dom1 on COS ID 3 may be below:
> + * ---------
> + * | COS 3 |
> + * ---------
> + * L3 CAT | 0x7ff |
> + * ---------
> + * MBA | 0x0 |
> + * ---------
> + * 4. After setting, the L3 CAT CBM value of Dom1 should be kept and
> the new MBA
> + * Thrtl is set. So, the values on COS ID 3 should be below.
> + * ---------
> + * | COS 3 |
> + * ---------
> + * L3 CAT | 0x1ff |
> + * ---------
> + * MBA | 0x14 |
> + * ---------
> + *
> + * So, we should write all features values into their MSRs. That
> requires the
> + * feature array, feature properties array and value array are input.
> + */
Although I understand them, I still have a feeling of the necessity to
reword these comments.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 07/13] x86: implement set value flow for MBA
2017-08-18 3:32 ` Chao Peng
@ 2017-08-18 9:25 ` Yi Sun
2017-08-21 7:54 ` Chao Peng
0 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-18 9:25 UTC (permalink / raw)
To: Chao Peng
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On 17-08-18 11:32:08, Chao Peng wrote:
>
> > + if ( feat->mba_info.linear )
> > + {
> > + unsigned int mod;
> > +
> > + if ( feat->mba_info.thrtl_max >= 100 )
> > + return false;
>
> Can we do this check earlier, e.g. when it gets enumerated from CPUID?
>
Ok, sound reasonable.
> > +
> > + mod = *thrtl % (100 - feat->mba_info.thrtl_max);
> > + *thrtl -= mod;
> > + }
> > + else
> > + {
> > + /* Not power of 2. */
> > + if ( *thrtl & (*thrtl - 1) )
> > + *thrtl = *thrtl & (1 << (flsl(*thrtl) - 1));
> > + }
> > +
>
> Is it possible for *thrtl to be zero? Otherwise we need check that at
> the beginning.
>
Yes, it could be 0. I missed this. Code should be:
if ( *thrtl && (*thrtl & (*thrtl - 1)) )
> >
> > +/*
> > + * Because multiple features may co-exist, we need handle all
> > features to write
> > + * values of them into a COS register with new COS ID. E.g:
> > + * 1. L3 CAT and MBA co-exist.
> > + * 2. Dom1 and Dom2 share a same COS ID (2). The L3 CAT CBM of Dom1
> > is 0x1ff,
> > + * the MBA Thrtle of Dom1 is 0xa.
> > + * 3. User wants to change MBA Thrtl of Dom1 to be 0x14. Because COS
> > ID 2 is
> > + * used by Dom2 too, we have to pick a new COS ID 3. The original
> > values of
> > + * Dom1 on COS ID 3 may be below:
> > + * ---------
> > + * | COS 3 |
> > + * ---------
> > + * L3 CAT | 0x7ff |
> > + * ---------
> > + * MBA | 0x0 |
> > + * ---------
> > + * 4. After setting, the L3 CAT CBM value of Dom1 should be kept and
> > the new MBA
> > + * Thrtl is set. So, the values on COS ID 3 should be below.
> > + * ---------
> > + * | COS 3 |
> > + * ---------
> > + * L3 CAT | 0x1ff |
> > + * ---------
> > + * MBA | 0x14 |
> > + * ---------
> > + *
> > + * So, we should write all features values into their MSRs. That
> > requires the
> > + * feature array, feature properties array and value array are input.
> > + */
>
> Although I understand them, I still have a feeling of the necessity to
> reword these comments.
>
How about move comments into commit message?
> Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 07/13] x86: implement set value flow for MBA
2017-08-18 9:25 ` Yi Sun
@ 2017-08-21 7:54 ` Chao Peng
0 siblings, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-21 7:54 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
> > >
> > >
> > > +/*
> > > + * Because multiple features may co-exist, we need handle all
> > > features to write
> > > + * values of them into a COS register with new COS ID. E.g:
> > > + * 1. L3 CAT and MBA co-exist.
> > > + * 2. Dom1 and Dom2 share a same COS ID (2). The L3 CAT CBM of
> > > Dom1
> > > is 0x1ff,
> > > + * the MBA Thrtle of Dom1 is 0xa.
> > > + * 3. User wants to change MBA Thrtl of Dom1 to be 0x14. Because
> > > COS
> > > ID 2 is
> > > + * used by Dom2 too, we have to pick a new COS ID 3. The
> > > original
> > > values of
> > > + * Dom1 on COS ID 3 may be below:
> > > + * ---------
> > > + * | COS 3 |
> > > + * ---------
> > > + * L3 CAT | 0x7ff |
> > > + * ---------
> > > + * MBA | 0x0 |
> > > + * ---------
> > > + * 4. After setting, the L3 CAT CBM value of Dom1 should be kept
> > > and
> > > the new MBA
> > > + * Thrtl is set. So, the values on COS ID 3 should be below.
> > > + * ---------
> > > + * | COS 3 |
> > > + * ---------
> > > + * L3 CAT | 0x1ff |
> > > + * ---------
> > > + * MBA | 0x14 |
> > > + * ---------
> > > + *
> > > + * So, we should write all features values into their MSRs. That
> > > requires the
> > > + * feature array, feature properties array and value array are
> > > input.
> > > + */
> >
> > Although I understand them, I still have a feeling of the necessity
> > to
> > reword these comments.
> >
> How about move comments into commit message?
Fine to me.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 08/13] tools: create general interfaces to support psr allocation features
2017-08-09 7:41 ` [PATCH v1 08/13] tools: create general interfaces to support psr allocation features Yi Sun
@ 2017-08-21 10:12 ` Chao Peng
2017-08-22 2:38 ` Yi Sun
0 siblings, 1 reply; 50+ messages in thread
From: Chao Peng @ 2017-08-21 10:12 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
> * mode: C
> diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
> index 6e80d36..10d317b 100644
> --- a/tools/libxl/libxl_types.idl
> +++ b/tools/libxl/libxl_types.idl
> @@ -977,6 +977,7 @@ libxl_psr_cbm_type = Enumeration("psr_cbm_type", [
> (2, "L3_CBM_CODE"),
> (3, "L3_CBM_DATA"),
> (4, "L2_CBM"),
> + (5, "MBA_THRTL"),
This is not quite appropriate as MBA_THRTL is actually not a 'cbm_type'.
> ])
>
> libxl_psr_cat_info = Struct("psr_cat_info", [
> @@ -985,3 +986,24 @@ libxl_psr_cat_info = Struct("psr_cat_info", [
> ("cbm_len", uint32),
> ("cdp_enabled", bool),
> ])
> +
> +libxl_psr_feat_type = Enumeration("psr_feat_type", [
> + (1, "CAT_INFO"),
> + (2, "MBA_INFO"),
> + ])
'_INFO' can be removed so that it can be used for other purpose in the
future.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all psr allocation features
2017-08-09 7:41 ` [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all " Yi Sun
2017-08-15 11:14 ` Wei Liu
@ 2017-08-21 10:13 ` Chao Peng
2017-08-22 2:38 ` Yi Sun
1 sibling, 1 reply; 50+ messages in thread
From: Chao Peng @ 2017-08-21 10:13 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
> int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
> int *nr, unsigned int lvl)
> {
> GC_INIT(ctx);
> int rc;
> - int i = 0, socketid, nr_sockets;
> - libxl_bitmap socketmap;
> + unsigned int i;
> + libxl_psr_hw_info *hw_info;
> libxl_psr_cat_info *ptr;
>
> - libxl_bitmap_init(&socketmap);
> -
> - rc = libxl__count_physical_sockets(gc, &nr_sockets);
> - if (rc) {
> - LOGE(ERROR, "failed to get system socket count");
> + rc = libxl_psr_get_hw_info(ctx, &hw_info, (unsigned int *)nr,
> + LIBXL_PSR_FEAT_TYPE_CAT_INFO, lvl);
> + if (rc)
> goto out;
> - }
>
> - libxl_socket_bitmap_alloc(ctx, &socketmap, nr_sockets);
> - rc = libxl_get_online_socketmap(ctx, &socketmap);
> - if (rc < 0) {
> - LOGE(ERROR, "failed to get available sockets");
> - goto out;
> - }
> + ptr = libxl__malloc(NOGC, *nr * sizeof(libxl_psr_cat_info));
>
> - ptr = libxl__malloc(NOGC, nr_sockets *
> sizeof(libxl_psr_cat_info));
> -
> - libxl_for_each_set_bit(socketid, socketmap) {
> - ptr[i].id = socketid;
> - if (xc_psr_cat_get_info(ctx->xch, socketid, lvl,
> &ptr[i].cos_max,
> - &ptr[i].cbm_len,
> &ptr[i].cdp_enabled)) {
> + for (i = 0; i < *nr; i++) {
> + if (libxl__psr_hw_info_to_libxl_psr_cat_info(
> + LIBXL_PSR_FEAT_TYPE_CAT_INFO,
> + &hw_info[i], &ptr[i])) {
> rc = ERROR_FAIL;
> free(ptr);
> goto out;
> }
> - i++;
> }
>
> *info = ptr;
> - *nr = i;
> out:
> - libxl_bitmap_dispose(&socketmap);
You probably need to call libxl_psr_hw_info_list_free some where.
Chao
> GC_FREE;
> return rc;
> }
> @@ -439,15 +441,120 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t
> domid,
> return ERROR_FAIL;
> }
>
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type'
2017-08-09 7:41 ` [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type' Yi Sun
2017-08-15 11:15 ` Wei Liu
@ 2017-08-21 10:13 ` Chao Peng
1 sibling, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-21 10:13 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
On Wed, 2017-08-09 at 15:41 +0800, Yi Sun wrote:
> This patch renames 'xc_psr_cat_type' to 'xc_psr_val_type' so that
> the structure name is common for all allocation features.
>
> Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Reviewed-by: Chao Peng <chao.p.peng@linux.intel.com>
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features
2017-08-09 7:41 ` [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features Yi Sun
2017-08-15 11:24 ` Wei Liu
@ 2017-08-21 10:14 ` Chao Peng
2017-08-22 2:24 ` Yi Sun
1 sibling, 1 reply; 50+ messages in thread
From: Chao Peng @ 2017-08-21 10:14 UTC (permalink / raw)
To: Yi Sun, xen-devel
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, roger.pau
>
> -static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> +static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
> + int err,
> + libxl_psr_cbm_type type)
> {
> + /*
> + * Index is 'libxl_psr_cbm_type' so we set two 'CDP' to
> correspond to
> + * DATA and CODE.
> + */
Or just use "CDP CODE" and "CDP DATA" respectively?
> + const char * const feat_name[6] = {
> + "UNKNOWN",
> + "L3 CAT",
> + "CDP",
> + "CDP",
> + "L2 CAT",
> + "MBA",
> + };
> char *msg;
>
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 12/13] tools: implemet new set value interface suitable for all psr allocation features
2017-08-15 11:25 ` Wei Liu
@ 2017-08-21 10:15 ` Chao Peng
0 siblings, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-21 10:15 UTC (permalink / raw)
To: Wei Liu, Yi Sun
Cc: kevin.tian, andrew.cooper3, dario.faggioli, ian.jackson,
julien.grall, mengxu, jbeulich, xen-devel, roger.pau
On Tue, 2017-08-15 at 12:25 +0100, Wei Liu wrote:
> On Wed, Aug 09, 2017 at 03:41:51PM +0800, Yi Sun wrote:
> >
> > This patch implements a new set value interface in tools suitable
> > for all psr
> > allocation features and the whole flow. It also enables MBA support
> > to set
> > MBA value in tools.
> >
> > Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
>
> Same comment on commit message in previous patch applies here, too.
>
> And Chao please confirm you're okay with the xl interface.
I'm fine with it.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features
2017-08-21 10:14 ` Chao Peng
@ 2017-08-22 2:24 ` Yi Sun
2017-08-22 6:44 ` Chao Peng
0 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-22 2:24 UTC (permalink / raw)
To: Chao Peng
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On 17-08-21 18:14:49, Chao Peng wrote:
>
> >
> > -static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> > +static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
> > + int err,
> > + libxl_psr_cbm_type type)
> > {
> > + /*
> > + * Index is 'libxl_psr_cbm_type' so we set two 'CDP' to
> > correspond to
> > + * DATA and CODE.
> > + */
>
> Or just use "CDP CODE" and "CDP DATA" respectively?
>
They are just value type but not feature name. So, I duplicate 'CDP'
here.
> > + const char * const feat_name[6] = {
> > + "UNKNOWN",
> > + "L3 CAT",
> > + "CDP",
> > + "CDP",
> > + "L2 CAT",
> > + "MBA",
> > + };
> > char *msg;
> >
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 08/13] tools: create general interfaces to support psr allocation features
2017-08-21 10:12 ` Chao Peng
@ 2017-08-22 2:38 ` Yi Sun
2017-08-22 6:42 ` Chao Peng
0 siblings, 1 reply; 50+ messages in thread
From: Yi Sun @ 2017-08-22 2:38 UTC (permalink / raw)
To: Chao Peng
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On 17-08-21 18:12:18, Chao Peng wrote:
>
> > * mode: C
> > diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
> > index 6e80d36..10d317b 100644
> > --- a/tools/libxl/libxl_types.idl
> > +++ b/tools/libxl/libxl_types.idl
> > @@ -977,6 +977,7 @@ libxl_psr_cbm_type = Enumeration("psr_cbm_type", [
> > (2, "L3_CBM_CODE"),
> > (3, "L3_CBM_DATA"),
> > (4, "L2_CBM"),
> > + (5, "MBA_THRTL"),
>
> This is not quite appropriate as MBA_THRTL is actually not a 'cbm_type'.
>
MBA_THRTL is not 'cbm_type'. But I do not want to create a new generic
value type structure here. It looks redundant. So, I use the 'psr_cbm_type'
to include MBA too.
> > ])
> >
> > libxl_psr_cat_info = Struct("psr_cat_info", [
> > @@ -985,3 +986,24 @@ libxl_psr_cat_info = Struct("psr_cat_info", [
> > ("cbm_len", uint32),
> > ("cdp_enabled", bool),
> > ])
> > +
> > +libxl_psr_feat_type = Enumeration("psr_feat_type", [
> > + (1, "CAT_INFO"),
> > + (2, "MBA_INFO"),
> > + ])
>
> '_INFO' can be removed so that it can be used for other purpose in the
> future.
>
Ok, will remove it.
> Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all psr allocation features
2017-08-21 10:13 ` Chao Peng
@ 2017-08-22 2:38 ` Yi Sun
0 siblings, 0 replies; 50+ messages in thread
From: Yi Sun @ 2017-08-22 2:38 UTC (permalink / raw)
To: Chao Peng
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On 17-08-21 18:13:07, Chao Peng wrote:
>
> > int libxl_psr_cat_get_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
> > int *nr, unsigned int lvl)
> > {
> > GC_INIT(ctx);
> > int rc;
> > - int i = 0, socketid, nr_sockets;
> > - libxl_bitmap socketmap;
> > + unsigned int i;
> > + libxl_psr_hw_info *hw_info;
> > libxl_psr_cat_info *ptr;
> >
> > - libxl_bitmap_init(&socketmap);
> > -
> > - rc = libxl__count_physical_sockets(gc, &nr_sockets);
> > - if (rc) {
> > - LOGE(ERROR, "failed to get system socket count");
> > + rc = libxl_psr_get_hw_info(ctx, &hw_info, (unsigned int *)nr,
> > + LIBXL_PSR_FEAT_TYPE_CAT_INFO, lvl);
> > + if (rc)
> > goto out;
> > - }
> >
> > - libxl_socket_bitmap_alloc(ctx, &socketmap, nr_sockets);
> > - rc = libxl_get_online_socketmap(ctx, &socketmap);
> > - if (rc < 0) {
> > - LOGE(ERROR, "failed to get available sockets");
> > - goto out;
> > - }
> > + ptr = libxl__malloc(NOGC, *nr * sizeof(libxl_psr_cat_info));
> >
> > - ptr = libxl__malloc(NOGC, nr_sockets *
> > sizeof(libxl_psr_cat_info));
> > -
> > - libxl_for_each_set_bit(socketid, socketmap) {
> > - ptr[i].id = socketid;
> > - if (xc_psr_cat_get_info(ctx->xch, socketid, lvl,
> > &ptr[i].cos_max,
> > - &ptr[i].cbm_len,
> > &ptr[i].cdp_enabled)) {
> > + for (i = 0; i < *nr; i++) {
> > + if (libxl__psr_hw_info_to_libxl_psr_cat_info(
> > + LIBXL_PSR_FEAT_TYPE_CAT_INFO,
> > + &hw_info[i], &ptr[i])) {
> > rc = ERROR_FAIL;
> > free(ptr);
> > goto out;
> > }
> > - i++;
> > }
> >
> > *info = ptr;
> > - *nr = i;
> > out:
> > - libxl_bitmap_dispose(&socketmap);
>
> You probably need to call libxl_psr_hw_info_list_free some where.
>
Yes, you are right. Thanks!
> Chao
> > GC_FREE;
> > return rc;
> > }
> > @@ -439,15 +441,120 @@ int libxl_psr_get_val(libxl_ctx *ctx, uint32_t
> > domid,
> > return ERROR_FAIL;
> > }
> >
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 08/13] tools: create general interfaces to support psr allocation features
2017-08-22 2:38 ` Yi Sun
@ 2017-08-22 6:42 ` Chao Peng
0 siblings, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-22 6:42 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On Tue, 2017-08-22 at 10:38 +0800, Yi Sun wrote:
> On 17-08-21 18:12:18, Chao Peng wrote:
> >
> >
> > >
> > > * mode: C
> > > diff --git a/tools/libxl/libxl_types.idl
> > > b/tools/libxl/libxl_types.idl
> > > index 6e80d36..10d317b 100644
> > > --- a/tools/libxl/libxl_types.idl
> > > +++ b/tools/libxl/libxl_types.idl
> > > @@ -977,6 +977,7 @@ libxl_psr_cbm_type =
> > > Enumeration("psr_cbm_type", [
> > > (2, "L3_CBM_CODE"),
> > > (3, "L3_CBM_DATA"),
> > > (4, "L2_CBM"),
> > > + (5, "MBA_THRTL"),
> >
> > This is not quite appropriate as MBA_THRTL is actually not a
> > 'cbm_type'.
> >
> MBA_THRTL is not 'cbm_type'. But I do not want to create a new generic
> value type structure here. It looks redundant. So, I use the
> 'psr_cbm_type'
> to include MBA too.
I don't strongly insist on it. If others don't object, I'm OK with it.
Chao
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features
2017-08-22 2:24 ` Yi Sun
@ 2017-08-22 6:44 ` Chao Peng
0 siblings, 0 replies; 50+ messages in thread
From: Chao Peng @ 2017-08-22 6:44 UTC (permalink / raw)
To: Yi Sun
Cc: kevin.tian, wei.liu2, andrew.cooper3, dario.faggioli,
ian.jackson, julien.grall, mengxu, jbeulich, xen-devel,
roger.pau
On Tue, 2017-08-22 at 10:24 +0800, Yi Sun wrote:
> On 17-08-21 18:14:49, Chao Peng wrote:
> >
> >
> > >
> > >
> > > -static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
> > > +static void libxl__psr_alloc_log_err_msg(libxl__gc *gc,
> > > + int err,
> > > + libxl_psr_cbm_type type)
> > > {
> > > + /*
> > > + * Index is 'libxl_psr_cbm_type' so we set two 'CDP' to
> > > correspond to
> > > + * DATA and CODE.
> > > + */
> >
> > Or just use "CDP CODE" and "CDP DATA" respectively?
> >
> They are just value type but not feature name. So, I duplicate 'CDP'
> here.
I'm fine.
Chao
>
> >
> > >
> > > + const char * const feat_name[6] = {
> > > + "UNKNOWN",
> > > + "L3 CAT",
> > > + "CDP",
> > > + "CDP",
> > > + "L2 CAT",
> > > + "MBA",
> > > + };
> > > char *msg;
> > >
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^ permalink raw reply [flat|nested] 50+ messages in thread
end of thread, other threads:[~2017-08-22 6:45 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-08-09 7:41 [PATCH v1 00/13] Enable Memory Bandwidth Allocation in Xen Yi Sun
2017-08-09 7:41 ` [PATCH v1 01/13] docs: create Memory Bandwidth Allocation (MBA) feature document Yi Sun
2017-08-14 7:35 ` Chao Peng
2017-08-14 8:23 ` Yi Sun
2017-08-14 9:36 ` Chao Peng
2017-08-15 10:08 ` Wei Liu
2017-08-16 2:51 ` Yi Sun
2017-08-09 7:41 ` [PATCH v1 02/13] Rename PSR sysctl/domctl interfaces and xsm policy to make them be general Yi Sun
2017-08-15 10:12 ` Wei Liu
2017-08-16 2:48 ` Yi Sun
2017-08-15 14:03 ` Daniel De Graaf
2017-08-09 7:41 ` [PATCH v1 03/13] x86: rename 'cbm_type' to 'psr_val_type' to make it general Yi Sun
2017-08-15 10:13 ` Wei Liu
2017-08-16 2:17 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 04/13] x86: implement data structure and CPU init flow for MBA Yi Sun
2017-08-15 10:50 ` Wei Liu
2017-08-16 7:18 ` Yi Sun
2017-08-17 9:49 ` Wei Liu
2017-08-16 3:14 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 05/13] x86: implement get hw info " Yi Sun
2017-08-16 3:23 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 06/13] x86: implement get value interface " Yi Sun
2017-08-16 6:38 ` Chao Peng
2017-08-16 6:43 ` Yi Sun
2017-08-17 7:51 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 07/13] x86: implement set value flow " Yi Sun
2017-08-18 3:32 ` Chao Peng
2017-08-18 9:25 ` Yi Sun
2017-08-21 7:54 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 08/13] tools: create general interfaces to support psr allocation features Yi Sun
2017-08-21 10:12 ` Chao Peng
2017-08-22 2:38 ` Yi Sun
2017-08-22 6:42 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 09/13] tools: implement the new get hw info interface suitable to all " Yi Sun
2017-08-15 11:14 ` Wei Liu
2017-08-21 10:13 ` Chao Peng
2017-08-22 2:38 ` Yi Sun
2017-08-09 7:41 ` [PATCH v1 10/13] tools: rename 'xc_psr_cat_type' to 'xc_psr_val_type' Yi Sun
2017-08-15 11:15 ` Wei Liu
2017-08-21 10:13 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 11/13] tools: implemet new get value interface suitable for all psr allocation features Yi Sun
2017-08-15 11:24 ` Wei Liu
2017-08-21 10:14 ` Chao Peng
2017-08-22 2:24 ` Yi Sun
2017-08-22 6:44 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 12/13] tools: implemet new set " Yi Sun
2017-08-15 11:25 ` Wei Liu
2017-08-21 10:15 ` Chao Peng
2017-08-09 7:41 ` [PATCH v1 13/13] docs: add MBA description in docs Yi Sun
2017-08-15 11:26 ` Wei Liu
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