[PATCH v2 0/2] Patches to add support pdm controller for rk3328

[PATCH v2 0/2] Patches to add support pdm controller for rk3328

[Sugar Zhang]

These patches to add support pdm for rk3328 socs.

Changes in v2:
- separate pinctrl pins
  remove unused fsync clk, it's debug pins

Sugar Zhang (2):
  arm64: dts: rockchip: add rk3328 pdm node
  ASoC: rockchip: separate pinctrl pins from each other

 .../devicetree/bindings/sound/rockchip,pdm.txt     |  7 +-
 arch/arm64/boot/dts/rockchip/rk3328.dtsi           | 77 ++++++++++++++++++++++
 2 files changed, 82 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH v2 0/2] Patches to add support pdm controller for rk3328

[Sugar Zhang]

These patches to add support pdm for rk3328 socs.

Changes in v2:
- separate pinctrl pins
  remove unused fsync clk, it's debug pins

Sugar Zhang (2):
  arm64: dts: rockchip: add rk3328 pdm node
  ASoC: rockchip: separate pinctrl pins from each other

 .../devicetree/bindings/sound/rockchip,pdm.txt     |  7 +-
 arch/arm64/boot/dts/rockchip/rk3328.dtsi           | 77 ++++++++++++++++++++++
 2 files changed, 82 insertions(+), 2 deletions(-)

-- 
2.7.4


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[PATCH v2 0/2] Patches to add support pdm controller for rk3328

[Sugar Zhang]

These patches to add support pdm for rk3328 socs.

Changes in v2:
- separate pinctrl pins
  remove unused fsync clk, it's debug pins

Sugar Zhang (2):
  arm64: dts: rockchip: add rk3328 pdm node
  ASoC: rockchip: separate pinctrl pins from each other

 .../devicetree/bindings/sound/rockchip,pdm.txt     |  7 +-
 arch/arm64/boot/dts/rockchip/rk3328.dtsi           | 77 ++++++++++++++++++++++
 2 files changed, 82 insertions(+), 2 deletions(-)

-- 
2.7.4

[PATCH v2 1/2] arm64: dts: rockchip: add rk3328 pdm node

[Sugar Zhang]

This patch add pdm controller device node for rk3328.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

---

Changes in v2:
- separate pinctrl pins
  remove unused fsync clk, it's debug pins

 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 77 ++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 0be96ce..c4f52ec 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -156,6 +156,27 @@
 		clock-output-names = "xin24m";
 	};
 
+	pdm: pdm@ff040000 {
+		compatible = "rockchip,pdm";
+		reg = <0x0 0xff040000 0x0 0x1000>;
+		clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
+		clock-names = "pdm_clk", "pdm_hclk";
+		dmas = <&dmac 16>;
+		dma-names = "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pdmm0_clk
+			     &pdmm0_sdi0
+			     &pdmm0_sdi1
+			     &pdmm0_sdi2
+			     &pdmm0_sdi3>;
+		pinctrl-1 = <&pdmm0_clk_sleep
+			     &pdmm0_sdi0_sleep
+			     &pdmm0_sdi1_sleep
+			     &pdmm0_sdi2_sleep
+			     &pdmm0_sdi3_sleep>;
+		status = "disabled";
+	};
+
 	grf: syscon@ff100000 {
 		compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xff100000 0x0 0x1000>;
@@ -734,6 +755,62 @@
 			};
 		};
 
+		pdm-0 {
+			pdmm0_clk: pdmm0-clk {
+				rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_fsync: pdmm0-fsync {
+				rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_sdi0: pdmm0-sdi0 {
+				rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_sdi1: pdmm0-sdi1 {
+				rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_sdi2: pdmm0-sdi2 {
+				rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_sdi3: pdmm0-sdi3 {
+				rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_clk_sleep: pdmm0-clk-sleep {
+				rockchip,pins =
+					<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
+				rockchip,pins =
+					<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
+				rockchip,pins =
+					<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
+				rockchip,pins =
+					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
+				rockchip,pins =
+					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_fsync_sleep: pdmm0-fsync-sleep {
+				rockchip,pins =
+					<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+		};
+
 		i2s1 {
 			i2s1_mclk: i2s1-mclk {
 				rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
-- 
2.7.4

[PATCH v2 1/2] arm64: dts: rockchip: add rk3328 pdm node

[Sugar Zhang]

This patch add pdm controller device node for rk3328.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

---

Changes in v2:
- separate pinctrl pins
  remove unused fsync clk, it's debug pins

 arch/arm64/boot/dts/rockchip/rk3328.dtsi | 77 ++++++++++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 0be96ce..c4f52ec 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -156,6 +156,27 @@
 		clock-output-names = "xin24m";
 	};
 
+	pdm: pdm at ff040000 {
+		compatible = "rockchip,pdm";
+		reg = <0x0 0xff040000 0x0 0x1000>;
+		clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
+		clock-names = "pdm_clk", "pdm_hclk";
+		dmas = <&dmac 16>;
+		dma-names = "rx";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&pdmm0_clk
+			     &pdmm0_sdi0
+			     &pdmm0_sdi1
+			     &pdmm0_sdi2
+			     &pdmm0_sdi3>;
+		pinctrl-1 = <&pdmm0_clk_sleep
+			     &pdmm0_sdi0_sleep
+			     &pdmm0_sdi1_sleep
+			     &pdmm0_sdi2_sleep
+			     &pdmm0_sdi3_sleep>;
+		status = "disabled";
+	};
+
 	grf: syscon at ff100000 {
 		compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xff100000 0x0 0x1000>;
@@ -734,6 +755,62 @@
 			};
 		};
 
+		pdm-0 {
+			pdmm0_clk: pdmm0-clk {
+				rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_fsync: pdmm0-fsync {
+				rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_sdi0: pdmm0-sdi0 {
+				rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_sdi1: pdmm0-sdi1 {
+				rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_sdi2: pdmm0-sdi2 {
+				rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_sdi3: pdmm0-sdi3 {
+				rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
+			};
+
+			pdmm0_clk_sleep: pdmm0-clk-sleep {
+				rockchip,pins =
+					<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
+				rockchip,pins =
+					<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
+				rockchip,pins =
+					<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
+				rockchip,pins =
+					<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
+				rockchip,pins =
+					<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+
+			pdmm0_fsync_sleep: pdmm0-fsync-sleep {
+				rockchip,pins =
+					<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
+			};
+		};
+
 		i2s1 {
 			i2s1_mclk: i2s1-mclk {
 				rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
-- 
2.7.4

[PATCH v2 2/2] ASoC: rockchip: separate pinctrl pins from each other

[Sugar Zhang]

pdm sdi0~3 pins are optional, for example, if 4ch required,
only sdi0~1 need to be enabled.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
---

Changes in v2: None

 Documentation/devicetree/bindings/sound/rockchip,pdm.txt | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/rockchip,pdm.txt b/Documentation/devicetree/bindings/sound/rockchip,pdm.txt
index 921729d..2ad66f6 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,pdm.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,pdm.txt
@@ -29,11 +29,14 @@ pdm: pdm@ff040000 {
 	dma-names = "rx";
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pdmm0_clk
-		     &pdmm0_fsync
 		     &pdmm0_sdi0
 		     &pdmm0_sdi1
 		     &pdmm0_sdi2
 		     &pdmm0_sdi3>;
-	pinctrl-1 = <&pdmm0_sleep>;
+	pinctrl-1 = <&pdmm0_clk_sleep
+		     &pdmm0_sdi0_sleep
+		     &pdmm0_sdi1_sleep
+		     &pdmm0_sdi2_sleep
+		     &pdmm0_sdi3_sleep>;
 	status = "disabled";
 };
-- 
2.7.4

[PATCH v2 2/2] ASoC: rockchip: separate pinctrl pins from each other

[Sugar Zhang]

pdm sdi0~3 pins are optional, for example, if 4ch required,
only sdi0~1 need to be enabled.

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
---

Changes in v2: None

 Documentation/devicetree/bindings/sound/rockchip,pdm.txt | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/rockchip,pdm.txt b/Documentation/devicetree/bindings/sound/rockchip,pdm.txt
index 921729d..2ad66f6 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,pdm.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,pdm.txt
@@ -29,11 +29,14 @@ pdm: pdm at ff040000 {
 	dma-names = "rx";
 	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pdmm0_clk
-		     &pdmm0_fsync
 		     &pdmm0_sdi0
 		     &pdmm0_sdi1
 		     &pdmm0_sdi2
 		     &pdmm0_sdi3>;
-	pinctrl-1 = <&pdmm0_sleep>;
+	pinctrl-1 = <&pdmm0_clk_sleep
+		     &pdmm0_sdi0_sleep
+		     &pdmm0_sdi1_sleep
+		     &pdmm0_sdi2_sleep
+		     &pdmm0_sdi3_sleep>;
 	status = "disabled";
 };
-- 
2.7.4

Re: [PATCH v2 2/2] ASoC: rockchip: separate pinctrl pins from each other

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:25:07 CEST schrieb Sugar Zhang:
> pdm sdi0~3 pins are optional, for example, if 4ch required,
> only sdi0~1 need to be enabled.
> 
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

But you might want to adapt the subject a bit and include that
you're actually only change the example in the devicetree binding.


Heiko

Re: [PATCH v2 2/2] ASoC: rockchip: separate pinctrl pins from each other

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:25:07 CEST schrieb Sugar Zhang:
> pdm sdi0~3 pins are optional, for example, if 4ch required,
> only sdi0~1 need to be enabled.
> 
> Signed-off-by: Sugar Zhang <sugar.zhang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Reviewed-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>

But you might want to adapt the subject a bit and include that
you're actually only change the example in the devicetree binding.


Heiko
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[PATCH v2 2/2] ASoC: rockchip: separate pinctrl pins from each other

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:25:07 CEST schrieb Sugar Zhang:
> pdm sdi0~3 pins are optional, for example, if 4ch required,
> only sdi0~1 need to be enabled.
> 
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

But you might want to adapt the subject a bit and include that
you're actually only change the example in the devicetree binding.


Heiko

Re: [PATCH v2 1/2] arm64: dts: rockchip: add rk3328 pdm node

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:25:06 CEST schrieb Sugar Zhang:
> This patch add pdm controller device node for rk3328.
> 
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

applied for 4.14


Thanks
Heiko

[PATCH v2 1/2] arm64: dts: rockchip: add rk3328 pdm node

[Heiko Stuebner]

Am Montag, 21. August 2017, 16:25:06 CEST schrieb Sugar Zhang:
> This patch add pdm controller device node for rk3328.
> 
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>

applied for 4.14


Thanks
Heiko

Re: [PATCH v2 2/2] ASoC: rockchip: separate pinctrl pins from each other

[Rob Herring]

On Mon, Aug 21, 2017 at 04:25:07PM +0800, Sugar Zhang wrote:
> pdm sdi0~3 pins are optional, for example, if 4ch required,
> only sdi0~1 need to be enabled.
> 
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> ---
> 
> Changes in v2: None
> 
>  Documentation/devicetree/bindings/sound/rockchip,pdm.txt | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 2/2] ASoC: rockchip: separate pinctrl pins from each other

[Rob Herring]

On Mon, Aug 21, 2017 at 04:25:07PM +0800, Sugar Zhang wrote:
> pdm sdi0~3 pins are optional, for example, if 4ch required,
> only sdi0~1 need to be enabled.
> 
> Signed-off-by: Sugar Zhang <sugar.zhang-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> 
> Changes in v2: None
> 
>  Documentation/devicetree/bindings/sound/rockchip,pdm.txt | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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[PATCH v2 2/2] ASoC: rockchip: separate pinctrl pins from each other

[Rob Herring]

On Mon, Aug 21, 2017 at 04:25:07PM +0800, Sugar Zhang wrote:
> pdm sdi0~3 pins are optional, for example, if 4ch required,
> only sdi0~1 need to be enabled.
> 
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> ---
> 
> Changes in v2: None
> 
>  Documentation/devicetree/bindings/sound/rockchip,pdm.txt | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>