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From: Paul Mackerras <paulus@ozlabs.org>
To: linuxppc-dev@ozlabs.org
Subject: [PATCH v2 03/10] powerpc: Fix emulation of the isel instruction
Date: Fri, 25 Aug 2017 15:41:55 +1000	[thread overview]
Message-ID: <1503639722-19121-4-git-send-email-paulus@ozlabs.org> (raw)
In-Reply-To: <1503639722-19121-1-git-send-email-paulus@ozlabs.org>

The case added for the isel instruction was added inside a switch
statement which uses the 10-bit minor opcode field in the 0x7fe
bits of the instruction word.  However, for the isel instruction,
the minor opcode field is only the 0x3e bits, and the 0x7c0 bits
are used for the "BC" field, which indicates which CR bit to use
to select the result.

Therefore, for the isel emulation to work correctly when BC != 0,
we need to match on ((instr >> 1) & 0x1f) == 15).  To do this, we
pull the isel case out of the switch statement and put it in an
if statement of its own.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
 arch/powerpc/lib/sstep.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index f9c973c..7921b2a 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -1219,6 +1219,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
 		return 0;
 
 	case 31:
+		/* isel occupies 32 minor opcodes */
+		if (((instr >> 1) & 0x1f) == 15) {
+			mb = (instr >> 6) & 0x1f; /* bc field */
+			val = (regs->ccr >> (31 - mb)) & 1;
+			val2 = (ra) ? regs->gpr[ra] : 0;
+
+			op->val = (val) ? val2 : regs->gpr[rb];
+			goto compute_done;
+		}
+
 		switch ((instr >> 1) & 0x3ff) {
 		case 4:		/* tw */
 			if (rd == 0x1f ||
@@ -1444,14 +1454,6 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
 /*
  * Logical instructions
  */
-		case 15:	/* isel */
-			mb = (instr >> 6) & 0x1f; /* bc */
-			val = (regs->ccr >> (31 - mb)) & 1;
-			val2 = (ra) ? regs->gpr[ra] : 0;
-
-			op->val = (val) ? val2 : regs->gpr[rb];
-			goto compute_done;
-
 		case 26:	/* cntlzw */
 			op->val = __builtin_clz((unsigned int) regs->gpr[rd]);
 			goto logical_done;
-- 
2.7.4

  parent reply	other threads:[~2017-08-25  6:02 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-25  5:41 [PATCH v2 0/10] powerpc: Beef up single-stepping/instruction emulation infrastructure Paul Mackerras
2017-08-25  5:41 ` [PATCH v2 01/10] powerpc: Handle most loads and stores in instruction emulation code Paul Mackerras
2017-08-26 14:56   ` Segher Boessenkool
2017-08-28  5:48   ` Michael Ellerman
2017-08-25  5:41 ` [PATCH v2 02/10] powerpc: Change analyse_instr so it doesn't modify *regs Paul Mackerras
2017-08-25  5:41 ` Paul Mackerras [this message]
2017-08-25  5:41 ` [PATCH v2 04/10] powerpc: Add emulation for the addpcis instruction Paul Mackerras
2017-08-25  5:41 ` [PATCH v2 05/10] powerpc: Make load/store emulation use larger memory accesses Paul Mackerras
2017-08-25  5:41 ` [PATCH v2 06/10] powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live Paul Mackerras
2017-08-25  5:41 ` [PATCH v2 07/10] powerpc: Handle vector element load/stores in emulation code Paul Mackerras
2017-08-25  5:42 ` [PATCH v2 08/10] powerpc: Emulate load/store floating double pair instructions Paul Mackerras
2017-08-25  5:42 ` [PATCH v2 09/10] powerpc: Handle opposite-endian processes in emulation code Paul Mackerras
2017-08-25  5:42 ` [PATCH v2 10/10] powerpc/64: Fix update forms of loads and stores to write 64-bit EA Paul Mackerras

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