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* [PATCH] MIPS: mt7620: Rename uartlite to serial
@ 2017-09-01 14:53 ` Harvey Hunt
  0 siblings, 0 replies; 6+ messages in thread
From: Harvey Hunt @ 2017-09-01 14:53 UTC (permalink / raw)
  To: harvey.hunt, robh+dt, mark.rutland, ralf, john
  Cc: matt.redfearn, devicetree, linux-mips, linux-kernel

Previously, mt7620.c defined the clocks for uarts with the names
uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
the devicetree node names.

Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
 arch/mips/boot/dts/ralink/mt7620a.dtsi |  2 +-
 arch/mips/boot/dts/ralink/mt7628a.dtsi |  6 +++---
 arch/mips/ralink/mt7620.c              | 14 +++++++-------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 793c0c7..58bd002 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -45,7 +45,7 @@
 			reg = <0x300 0x100>;
 		};
 
-		uartlite@c00 {
+		serial0@c00 {
 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 9ff7e8f..fe3fe9a 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -62,7 +62,7 @@
 			reg = <0x300 0x100>;
 		};
 
-		uart0: uartlite@c00 {
+		uart0: serial0@c00 {
 			compatible = "ns16550a";
 			reg = <0xc00 0x100>;
 
@@ -75,7 +75,7 @@
 			reg-shift = <2>;
 		};
 
-		uart1: uart1@d00 {
+		uart1: serial1@d00 {
 			compatible = "ns16550a";
 			reg = <0xd00 0x100>;
 
@@ -88,7 +88,7 @@
 			reg-shift = <2>;
 		};
 
-		uart2: uart2@e00 {
+		uart2: serial2@e00 {
 			compatible = "ns16550a";
 			reg = <0xe00 0x100>;
 
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 9be8b08..f623ceb 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -54,7 +54,7 @@ static int dram_type;
 
 static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
 static struct rt2880_pmx_func mdio_grp[] = {
 	FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
 	FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
@@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
 	GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
 		MT7620_GPIO_MODE_UART0_SHIFT),
 	GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
-	GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
+	GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
 	GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
 		MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
 	GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
@@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
 		periph_rate = MHZ(40);
 		pcmi2s_rate = MHZ(480);
 
-		ralink_clk_add("10000d00.uartlite", periph_rate);
-		ralink_clk_add("10000e00.uartlite", periph_rate);
+		ralink_clk_add("10000d00.serial0", periph_rate);
+		ralink_clk_add("10000e00.serial0", periph_rate);
 	} else {
 		cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
 		pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
@@ -566,9 +566,9 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("10000a00.i2s", pcmi2s_rate);
 	ralink_clk_add("10000b00.spi", sys_rate);
 	ralink_clk_add("10000b40.spi", sys_rate);
-	ralink_clk_add("10000c00.uartlite", periph_rate);
-	ralink_clk_add("10000d00.uart1", periph_rate);
-	ralink_clk_add("10000e00.uart2", periph_rate);
+	ralink_clk_add("10000c00.serial0", periph_rate);
+	ralink_clk_add("10000d00.serial1", periph_rate);
+	ralink_clk_add("10000e00.serial2", periph_rate);
 	ralink_clk_add("10180000.wmac", xtal_rate);
 
 	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] MIPS: mt7620: Rename uartlite to serial
@ 2017-09-01 14:53 ` Harvey Hunt
  0 siblings, 0 replies; 6+ messages in thread
From: Harvey Hunt @ 2017-09-01 14:53 UTC (permalink / raw)
  To: harvey.hunt-1AXoQHu6uovQT0dZR+AlfA,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	ralf-6z/3iImG2C8G8FEW9MqTrA, john-Pj+rj9U5foFAfugRpC6u6w
  Cc: matt.redfearn-1AXoQHu6uovQT0dZR+AlfA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-mips-6z/3iImG2C8G8FEW9MqTrA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

Previously, mt7620.c defined the clocks for uarts with the names
uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
the devicetree node names.

Signed-off-by: Harvey Hunt <harvey.hunt-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/mips/boot/dts/ralink/mt7620a.dtsi |  2 +-
 arch/mips/boot/dts/ralink/mt7628a.dtsi |  6 +++---
 arch/mips/ralink/mt7620.c              | 14 +++++++-------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 793c0c7..58bd002 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -45,7 +45,7 @@
 			reg = <0x300 0x100>;
 		};
 
-		uartlite@c00 {
+		serial0@c00 {
 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 9ff7e8f..fe3fe9a 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -62,7 +62,7 @@
 			reg = <0x300 0x100>;
 		};
 
-		uart0: uartlite@c00 {
+		uart0: serial0@c00 {
 			compatible = "ns16550a";
 			reg = <0xc00 0x100>;
 
@@ -75,7 +75,7 @@
 			reg-shift = <2>;
 		};
 
-		uart1: uart1@d00 {
+		uart1: serial1@d00 {
 			compatible = "ns16550a";
 			reg = <0xd00 0x100>;
 
@@ -88,7 +88,7 @@
 			reg-shift = <2>;
 		};
 
-		uart2: uart2@e00 {
+		uart2: serial2@e00 {
 			compatible = "ns16550a";
 			reg = <0xe00 0x100>;
 
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 9be8b08..f623ceb 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -54,7 +54,7 @@ static int dram_type;
 
 static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
 static struct rt2880_pmx_func mdio_grp[] = {
 	FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
 	FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
@@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
 	GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
 		MT7620_GPIO_MODE_UART0_SHIFT),
 	GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
-	GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
+	GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
 	GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
 		MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
 	GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
@@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
 		periph_rate = MHZ(40);
 		pcmi2s_rate = MHZ(480);
 
-		ralink_clk_add("10000d00.uartlite", periph_rate);
-		ralink_clk_add("10000e00.uartlite", periph_rate);
+		ralink_clk_add("10000d00.serial0", periph_rate);
+		ralink_clk_add("10000e00.serial0", periph_rate);
 	} else {
 		cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
 		pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
@@ -566,9 +566,9 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("10000a00.i2s", pcmi2s_rate);
 	ralink_clk_add("10000b00.spi", sys_rate);
 	ralink_clk_add("10000b40.spi", sys_rate);
-	ralink_clk_add("10000c00.uartlite", periph_rate);
-	ralink_clk_add("10000d00.uart1", periph_rate);
-	ralink_clk_add("10000e00.uart2", periph_rate);
+	ralink_clk_add("10000c00.serial0", periph_rate);
+	ralink_clk_add("10000d00.serial1", periph_rate);
+	ralink_clk_add("10000e00.serial2", periph_rate);
 	ralink_clk_add("10180000.wmac", xtal_rate);
 
 	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
-- 
2.7.4

--
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^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH] MIPS: mt7620: Rename uartlite to serial
@ 2017-09-01 14:53 ` Harvey Hunt
  0 siblings, 0 replies; 6+ messages in thread
From: Harvey Hunt @ 2017-09-01 14:53 UTC (permalink / raw)
  To: harvey.hunt, robh+dt, mark.rutland, ralf, john
  Cc: matt.redfearn, devicetree, linux-mips, linux-kernel

Previously, mt7620.c defined the clocks for uarts with the names
uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
the devicetree node names.

Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
---
 arch/mips/boot/dts/ralink/mt7620a.dtsi |  2 +-
 arch/mips/boot/dts/ralink/mt7628a.dtsi |  6 +++---
 arch/mips/ralink/mt7620.c              | 14 +++++++-------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
index 793c0c7..58bd002 100644
--- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
@@ -45,7 +45,7 @@
 			reg = <0x300 0x100>;
 		};
 
-		uartlite@c00 {
+		serial0@c00 {
 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
 			reg = <0xc00 0x100>;
 
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
index 9ff7e8f..fe3fe9a 100644
--- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -62,7 +62,7 @@
 			reg = <0x300 0x100>;
 		};
 
-		uart0: uartlite@c00 {
+		uart0: serial0@c00 {
 			compatible = "ns16550a";
 			reg = <0xc00 0x100>;
 
@@ -75,7 +75,7 @@
 			reg-shift = <2>;
 		};
 
-		uart1: uart1@d00 {
+		uart1: serial1@d00 {
 			compatible = "ns16550a";
 			reg = <0xd00 0x100>;
 
@@ -88,7 +88,7 @@
 			reg-shift = <2>;
 		};
 
-		uart2: uart2@e00 {
+		uart2: serial2@e00 {
 			compatible = "ns16550a";
 			reg = <0xe00 0x100>;
 
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 9be8b08..f623ceb 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -54,7 +54,7 @@ static int dram_type;
 
 static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
 static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
-static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
+static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
 static struct rt2880_pmx_func mdio_grp[] = {
 	FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
 	FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
@@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
 	GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
 		MT7620_GPIO_MODE_UART0_SHIFT),
 	GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
-	GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
+	GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
 	GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
 		MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
 	GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
@@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
 		periph_rate = MHZ(40);
 		pcmi2s_rate = MHZ(480);
 
-		ralink_clk_add("10000d00.uartlite", periph_rate);
-		ralink_clk_add("10000e00.uartlite", periph_rate);
+		ralink_clk_add("10000d00.serial0", periph_rate);
+		ralink_clk_add("10000e00.serial0", periph_rate);
 	} else {
 		cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
 		pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
@@ -566,9 +566,9 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("10000a00.i2s", pcmi2s_rate);
 	ralink_clk_add("10000b00.spi", sys_rate);
 	ralink_clk_add("10000b40.spi", sys_rate);
-	ralink_clk_add("10000c00.uartlite", periph_rate);
-	ralink_clk_add("10000d00.uart1", periph_rate);
-	ralink_clk_add("10000e00.uart2", periph_rate);
+	ralink_clk_add("10000c00.serial0", periph_rate);
+	ralink_clk_add("10000d00.serial1", periph_rate);
+	ralink_clk_add("10000e00.serial2", periph_rate);
 	ralink_clk_add("10180000.wmac", xtal_rate);
 
 	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
-- 
2.7.4

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] MIPS: mt7620: Rename uartlite to serial
  2017-09-01 14:53 ` Harvey Hunt
  (?)
  (?)
@ 2017-09-06  7:52 ` John Crispin
  -1 siblings, 0 replies; 6+ messages in thread
From: John Crispin @ 2017-09-06  7:52 UTC (permalink / raw)
  To: Harvey Hunt, robh+dt, mark.rutland, ralf
  Cc: matt.redfearn, devicetree, linux-mips, linux-kernel

Hi,


comments inline


On 01/09/17 16:53, Harvey Hunt wrote:
> Previously, mt7620.c defined the clocks for uarts with the names
> uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
> the devicetree node names.
>
> Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-mips@linux-mips.org
> Cc: linux-kernel@vger.kernel.org
> ---
>   arch/mips/boot/dts/ralink/mt7620a.dtsi |  2 +-
>   arch/mips/boot/dts/ralink/mt7628a.dtsi |  6 +++---
>   arch/mips/ralink/mt7620.c              | 14 +++++++-------
>   3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
> index 793c0c7..58bd002 100644
> --- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
> +++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
> @@ -45,7 +45,7 @@
>   			reg = <0x300 0x100>;
>   		};
>   
> -		uartlite@c00 {
> +		serial0@c00 {
the uartlite is indeed not a full uart, having only rx/tx lines and 
missing various other features. i would prefer to keep it as is. you 
cannot connect a modem to the port for example as that would require HW 
handshake for example. Also making these changes will break 
compatibility with existing devicetrees.

     John

>   			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
>   			reg = <0xc00 0x100>;
>   
> diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> index 9ff7e8f..fe3fe9a 100644
> --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
> +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> @@ -62,7 +62,7 @@
>   			reg = <0x300 0x100>;
>   		};
>   
> -		uart0: uartlite@c00 {
> +		uart0: serial0@c00 {
>   			compatible = "ns16550a";
>   			reg = <0xc00 0x100>;
>   
> @@ -75,7 +75,7 @@
>   			reg-shift = <2>;
>   		};
>   
> -		uart1: uart1@d00 {
> +		uart1: serial1@d00 {
>   			compatible = "ns16550a";
>   			reg = <0xd00 0x100>;
>   
> @@ -88,7 +88,7 @@
>   			reg-shift = <2>;
>   		};
>   
> -		uart2: uart2@e00 {
> +		uart2: serial2@e00 {
>   			compatible = "ns16550a";
>   			reg = <0xe00 0x100>;
>   
> diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
> index 9be8b08..f623ceb 100644
> --- a/arch/mips/ralink/mt7620.c
> +++ b/arch/mips/ralink/mt7620.c
> @@ -54,7 +54,7 @@ static int dram_type;
>   
>   static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
>   static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
> -static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
> +static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
>   static struct rt2880_pmx_func mdio_grp[] = {
>   	FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
>   	FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
> @@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
>   	GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
>   		MT7620_GPIO_MODE_UART0_SHIFT),
>   	GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
> -	GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
> +	GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
>   	GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
>   		MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
>   	GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
> @@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
>   		periph_rate = MHZ(40);
>   		pcmi2s_rate = MHZ(480);
>   
> -		ralink_clk_add("10000d00.uartlite", periph_rate);
> -		ralink_clk_add("10000e00.uartlite", periph_rate);
> +		ralink_clk_add("10000d00.serial0", periph_rate);
> +		ralink_clk_add("10000e00.serial0", periph_rate);
>   	} else {
>   		cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
>   		pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
> @@ -566,9 +566,9 @@ void __init ralink_clk_init(void)
>   	ralink_clk_add("10000a00.i2s", pcmi2s_rate);
>   	ralink_clk_add("10000b00.spi", sys_rate);
>   	ralink_clk_add("10000b40.spi", sys_rate);
> -	ralink_clk_add("10000c00.uartlite", periph_rate);
> -	ralink_clk_add("10000d00.uart1", periph_rate);
> -	ralink_clk_add("10000e00.uart2", periph_rate);
> +	ralink_clk_add("10000c00.serial0", periph_rate);
> +	ralink_clk_add("10000d00.serial1", periph_rate);
> +	ralink_clk_add("10000e00.serial2", periph_rate);
>   	ralink_clk_add("10180000.wmac", xtal_rate);
>   
>   	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] MIPS: mt7620: Rename uartlite to serial
@ 2017-09-06  9:45   ` Geert Uytterhoeven
  0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2017-09-06  9:45 UTC (permalink / raw)
  To: Harvey Hunt
  Cc: Rob Herring, Mark Rutland, Ralf Baechle, John Crispin,
	Matt Redfearn, devicetree, Linux MIPS Mailing List, linux-kernel

On Fri, Sep 1, 2017 at 4:53 PM, Harvey Hunt <harvey.hunt@imgtec.com> wrote:
> Previously, mt7620.c defined the clocks for uarts with the names
> uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
> the devicetree node names.
>
> Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-mips@linux-mips.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  arch/mips/boot/dts/ralink/mt7620a.dtsi |  2 +-
>  arch/mips/boot/dts/ralink/mt7628a.dtsi |  6 +++---
>  arch/mips/ralink/mt7620.c              | 14 +++++++-------
>  3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
> index 793c0c7..58bd002 100644
> --- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
> +++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
> @@ -45,7 +45,7 @@
>                         reg = <0x300 0x100>;
>                 };
>
> -               uartlite@c00 {
> +               serial0@c00 {

Device node names should use generic names and no numerical suffix
=> "serial@c00"

>                         compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
>                         reg = <0xc00 0x100>;
>
> diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> index 9ff7e8f..fe3fe9a 100644
> --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
> +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> @@ -62,7 +62,7 @@
>                         reg = <0x300 0x100>;
>                 };
>
> -               uart0: uartlite@c00 {
> +               uart0: serial0@c00 {

uart0: serial@c00

>                         compatible = "ns16550a";
>                         reg = <0xc00 0x100>;
>
> @@ -75,7 +75,7 @@
>                         reg-shift = <2>;
>                 };
>
> -               uart1: uart1@d00 {
> +               uart1: serial1@d00 {

uart1: serial@d00

>                         compatible = "ns16550a";
>                         reg = <0xd00 0x100>;
>
> @@ -88,7 +88,7 @@
>                         reg-shift = <2>;
>                 };
>
> -               uart2: uart2@e00 {
> +               uart2: serial2@e00 {

uart2: serial@e00

>                         compatible = "ns16550a";
>                         reg = <0xe00 0x100>;
>
> diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
> index 9be8b08..f623ceb 100644
> --- a/arch/mips/ralink/mt7620.c
> +++ b/arch/mips/ralink/mt7620.c
> @@ -54,7 +54,7 @@ static int dram_type;
>
>  static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
>  static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
> -static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
> +static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
>  static struct rt2880_pmx_func mdio_grp[] = {
>         FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
>         FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
> @@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
>         GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
>                 MT7620_GPIO_MODE_UART0_SHIFT),
>         GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
> -       GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
> +       GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
>         GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
>                 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
>         GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
> @@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
>                 periph_rate = MHZ(40);
>                 pcmi2s_rate = MHZ(480);
>
> -               ralink_clk_add("10000d00.uartlite", periph_rate);
> -               ralink_clk_add("10000e00.uartlite", periph_rate);
> +               ralink_clk_add("10000d00.serial0", periph_rate);
> +               ralink_clk_add("10000e00.serial0", periph_rate);

Ugh, you're relying on the actual node names in DT?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] MIPS: mt7620: Rename uartlite to serial
@ 2017-09-06  9:45   ` Geert Uytterhoeven
  0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2017-09-06  9:45 UTC (permalink / raw)
  To: Harvey Hunt
  Cc: Rob Herring, Mark Rutland, Ralf Baechle, John Crispin,
	Matt Redfearn, devicetree-u79uwXL29TY76Z2rM5mHXA,
	Linux MIPS Mailing List, linux-kernel-u79uwXL29TY76Z2rM5mHXA

On Fri, Sep 1, 2017 at 4:53 PM, Harvey Hunt <harvey.hunt-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org> wrote:
> Previously, mt7620.c defined the clocks for uarts with the names
> uartlite, uart1 and uart2. Rename them to serial{0,1,2} and update
> the devicetree node names.
>
> Signed-off-by: Harvey Hunt <harvey.hunt-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-mips-6z/3iImG2C8G8FEW9MqTrA@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  arch/mips/boot/dts/ralink/mt7620a.dtsi |  2 +-
>  arch/mips/boot/dts/ralink/mt7628a.dtsi |  6 +++---
>  arch/mips/ralink/mt7620.c              | 14 +++++++-------
>  3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/mips/boot/dts/ralink/mt7620a.dtsi b/arch/mips/boot/dts/ralink/mt7620a.dtsi
> index 793c0c7..58bd002 100644
> --- a/arch/mips/boot/dts/ralink/mt7620a.dtsi
> +++ b/arch/mips/boot/dts/ralink/mt7620a.dtsi
> @@ -45,7 +45,7 @@
>                         reg = <0x300 0x100>;
>                 };
>
> -               uartlite@c00 {
> +               serial0@c00 {

Device node names should use generic names and no numerical suffix
=> "serial@c00"

>                         compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
>                         reg = <0xc00 0x100>;
>
> diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> index 9ff7e8f..fe3fe9a 100644
> --- a/arch/mips/boot/dts/ralink/mt7628a.dtsi
> +++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
> @@ -62,7 +62,7 @@
>                         reg = <0x300 0x100>;
>                 };
>
> -               uart0: uartlite@c00 {
> +               uart0: serial0@c00 {

uart0: serial@c00

>                         compatible = "ns16550a";
>                         reg = <0xc00 0x100>;
>
> @@ -75,7 +75,7 @@
>                         reg-shift = <2>;
>                 };
>
> -               uart1: uart1@d00 {
> +               uart1: serial1@d00 {

uart1: serial@d00

>                         compatible = "ns16550a";
>                         reg = <0xd00 0x100>;
>
> @@ -88,7 +88,7 @@
>                         reg-shift = <2>;
>                 };
>
> -               uart2: uart2@e00 {
> +               uart2: serial2@e00 {

uart2: serial@e00

>                         compatible = "ns16550a";
>                         reg = <0xe00 0x100>;
>
> diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
> index 9be8b08..f623ceb 100644
> --- a/arch/mips/ralink/mt7620.c
> +++ b/arch/mips/ralink/mt7620.c
> @@ -54,7 +54,7 @@ static int dram_type;
>
>  static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 1, 2) };
>  static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
> -static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
> +static struct rt2880_pmx_func serial_grp[] = { FUNC("serial", 0, 15, 2) };
>  static struct rt2880_pmx_func mdio_grp[] = {
>         FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
>         FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
> @@ -92,7 +92,7 @@ static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
>         GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
>                 MT7620_GPIO_MODE_UART0_SHIFT),
>         GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
> -       GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
> +       GRP("serial", serial_grp, 1, MT7620_GPIO_MODE_UART1),
>         GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
>                 MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
>         GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
> @@ -530,8 +530,8 @@ void __init ralink_clk_init(void)
>                 periph_rate = MHZ(40);
>                 pcmi2s_rate = MHZ(480);
>
> -               ralink_clk_add("10000d00.uartlite", periph_rate);
> -               ralink_clk_add("10000e00.uartlite", periph_rate);
> +               ralink_clk_add("10000d00.serial0", periph_rate);
> +               ralink_clk_add("10000e00.serial0", periph_rate);

Ugh, you're relying on the actual node names in DT?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-09-06  9:45 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-01 14:53 [PATCH] MIPS: mt7620: Rename uartlite to serial Harvey Hunt
2017-09-01 14:53 ` Harvey Hunt
2017-09-01 14:53 ` Harvey Hunt
2017-09-06  7:52 ` John Crispin
2017-09-06  9:45 ` Geert Uytterhoeven
2017-09-06  9:45   ` Geert Uytterhoeven

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