* [PATCH 1/2] drm/i915: Nuke some bogus tabs from the pcode defines
@ 2017-09-12 15:34 Ville Syrjala
2017-09-12 15:34 ` [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit Ville Syrjala
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Ville Syrjala @ 2017-09-12 15:34 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b03260a3967..f9f9fcc833c5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7954,8 +7954,8 @@ enum {
#define GEN7_PCODE_TIMEOUT 0x2
#define GEN7_PCODE_ILLEGAL_DATA 0x3
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
-#define GEN6_PCODE_WRITE_RC6VIDS 0x4
-#define GEN6_PCODE_READ_RC6VIDS 0x5
+#define GEN6_PCODE_WRITE_RC6VIDS 0x4
+#define GEN6_PCODE_READ_RC6VIDS 0x5
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
@@ -7974,7 +7974,7 @@ enum {
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
#define DISPLAY_IPS_CONTROL 0x19
-#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
+#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN9_PCODE_SAGV_CONTROL 0x21
#define GEN9_SAGV_DISABLE 0x0
#define GEN9_SAGV_IS_DISABLED 0x1
--
2.13.5
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit
2017-09-12 15:34 [PATCH 1/2] drm/i915: Nuke some bogus tabs from the pcode defines Ville Syrjala
@ 2017-09-12 15:34 ` Ville Syrjala
2017-09-12 16:31 ` Chris Wilson
2017-09-12 16:16 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Nuke some bogus tabs from the pcode defines Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Ville Syrjala @ 2017-09-12 15:34 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Give a name to the bit which tells pcode to control IPS.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f9f9fcc833c5..91d5a8cbe79d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7974,6 +7974,7 @@ enum {
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
#define DISPLAY_IPS_CONTROL 0x19
+#define IPS_PCODE_CONTROL (1 << 30)
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN9_PCODE_SAGV_CONTROL 0x21
#define GEN9_SAGV_DISABLE 0x0
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0871807850a9..524217d6292e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4956,7 +4956,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
assert_plane_enabled(dev_priv, crtc->plane);
if (IS_BROADWELL(dev_priv)) {
mutex_lock(&dev_priv->rps.hw_lock);
- WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
+ WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
+ IPS_ENABLE | IPS_PCODE_CONTROL));
mutex_unlock(&dev_priv->rps.hw_lock);
/* Quoting Art Runyan: "its not safe to expect any particular
* value in IPS_CTL bit 31 after enabling IPS through the
--
2.13.5
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Nuke some bogus tabs from the pcode defines
2017-09-12 15:34 [PATCH 1/2] drm/i915: Nuke some bogus tabs from the pcode defines Ville Syrjala
2017-09-12 15:34 ` [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit Ville Syrjala
@ 2017-09-12 16:16 ` Patchwork
2017-09-12 16:29 ` [PATCH 1/2] " Chris Wilson
2017-09-12 21:15 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-09-12 16:16 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Nuke some bogus tabs from the pcode defines
URL : https://patchwork.freedesktop.org/series/30218/
State : success
== Summary ==
Series 30218v1 series starting with [1/2] drm/i915: Nuke some bogus tabs from the pcode defines
https://patchwork.freedesktop.org/api/1.0/series/30218/revisions/1/mbox/
Test chamelium:
Subgroup dp-crc-fast:
fail -> PASS (fi-kbl-7500u) fdo#102514
Test kms_flip:
Subgroup basic-flip-vs-modeset:
skip -> PASS (fi-skl-x1585l) fdo#101781
fdo#102514 https://bugs.freedesktop.org/show_bug.cgi?id=102514
fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:448s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:459s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:378s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:532s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:268s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:509s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:509s
fi-byt-n2820 total:289 pass:250 dwarn:1 dfail:0 fail:0 skip:38 time:495s
fi-cfl-s total:289 pass:250 dwarn:4 dfail:0 fail:0 skip:35 time:457s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:451s
fi-glk-2a total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:598s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:433s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:407s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:433s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:487s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:460s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:494s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:581s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:585s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:555s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:454s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:528s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:499s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:460s
fi-skl-x1585l total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:568s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:422s
694f07d3df18c02da3f526ae0e1238eb12534e1e drm-tip: 2017y-09m-12d-09h-59m-00s UTC integration manifest
b410d5815ac2 drm/i915: Name the IPS_PCODE_CONTROL bit
7323034cc7a3 drm/i915: Nuke some bogus tabs from the pcode defines
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5663/
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915: Nuke some bogus tabs from the pcode defines
2017-09-12 15:34 [PATCH 1/2] drm/i915: Nuke some bogus tabs from the pcode defines Ville Syrjala
2017-09-12 15:34 ` [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit Ville Syrjala
2017-09-12 16:16 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Nuke some bogus tabs from the pcode defines Patchwork
@ 2017-09-12 16:29 ` Chris Wilson
2017-09-12 21:15 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2017-09-12 16:29 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2017-09-12 16:34:10)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0b03260a3967..f9f9fcc833c5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7954,8 +7954,8 @@ enum {
> #define GEN7_PCODE_TIMEOUT 0x2
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> -#define GEN6_PCODE_WRITE_RC6VIDS 0x4
> -#define GEN6_PCODE_READ_RC6VIDS 0x5
> +#define GEN6_PCODE_WRITE_RC6VIDS 0x4
> +#define GEN6_PCODE_READ_RC6VIDS 0x5
> #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
> #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
> #define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
> @@ -7974,7 +7974,7 @@ enum {
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> #define DISPLAY_IPS_CONTROL 0x19
> -#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
> +#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
> #define GEN9_PCODE_SAGV_CONTROL 0x21
> #define GEN9_SAGV_DISABLE 0x0
> #define GEN9_SAGV_IS_DISABLED 0x1
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit
2017-09-12 15:34 ` [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit Ville Syrjala
@ 2017-09-12 16:31 ` Chris Wilson
2017-09-12 16:41 ` Ville Syrjälä
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2017-09-12 16:31 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2017-09-12 16:34:11)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Give a name to the bit which tells pcode to control IPS.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f9f9fcc833c5..91d5a8cbe79d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7974,6 +7974,7 @@ enum {
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> #define DISPLAY_IPS_CONTROL 0x19
/* See also IPS_CTL */
?
> +#define IPS_PCODE_CONTROL (1 << 30)
> #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
> #define GEN9_PCODE_SAGV_CONTROL 0x21
> #define GEN9_SAGV_DISABLE 0x0
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0871807850a9..524217d6292e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4956,7 +4956,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> assert_plane_enabled(dev_priv, crtc->plane);
> if (IS_BROADWELL(dev_priv)) {
> mutex_lock(&dev_priv->rps.hw_lock);
> - WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
> + WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> + IPS_ENABLE | IPS_PCODE_CONTROL));
Numbers match up, so
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit
2017-09-12 16:31 ` Chris Wilson
@ 2017-09-12 16:41 ` Ville Syrjälä
0 siblings, 0 replies; 7+ messages in thread
From: Ville Syrjälä @ 2017-09-12 16:41 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Tue, Sep 12, 2017 at 05:31:09PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2017-09-12 16:34:11)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Give a name to the bit which tells pcode to control IPS.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 3 ++-
> > 2 files changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f9f9fcc833c5..91d5a8cbe79d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7974,6 +7974,7 @@ enum {
> > #define GEN6_PCODE_WRITE_D_COMP 0x11
> > #define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
> > #define DISPLAY_IPS_CONTROL 0x19
>
> /* See also IPS_CTL */
Seems like a decent idea.
> ?
>
> > +#define IPS_PCODE_CONTROL (1 << 30)
> > #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
> > #define GEN9_PCODE_SAGV_CONTROL 0x21
> > #define GEN9_SAGV_DISABLE 0x0
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 0871807850a9..524217d6292e 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4956,7 +4956,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> > assert_plane_enabled(dev_priv, crtc->plane);
> > if (IS_BROADWELL(dev_priv)) {
> > mutex_lock(&dev_priv->rps.hw_lock);
> > - WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
> > + WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> > + IPS_ENABLE | IPS_PCODE_CONTROL));
>
> Numbers match up, so
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
--
Ville Syrjälä
Intel OTC
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^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Nuke some bogus tabs from the pcode defines
2017-09-12 15:34 [PATCH 1/2] drm/i915: Nuke some bogus tabs from the pcode defines Ville Syrjala
` (2 preceding siblings ...)
2017-09-12 16:29 ` [PATCH 1/2] " Chris Wilson
@ 2017-09-12 21:15 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-09-12 21:15 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Nuke some bogus tabs from the pcode defines
URL : https://patchwork.freedesktop.org/series/30218/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
pass -> FAIL (shard-hsw) fdo#99912
Test gem_eio:
Subgroup in-flight:
pass -> FAIL (shard-hsw) fdo#102616
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102616 https://bugs.freedesktop.org/show_bug.cgi?id=102616
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
shard-hsw total:2301 pass:1235 dwarn:0 dfail:0 fail:14 skip:1052 time:9429s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5663/shards.html
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-09-12 21:15 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-12 15:34 [PATCH 1/2] drm/i915: Nuke some bogus tabs from the pcode defines Ville Syrjala
2017-09-12 15:34 ` [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit Ville Syrjala
2017-09-12 16:31 ` Chris Wilson
2017-09-12 16:41 ` Ville Syrjälä
2017-09-12 16:16 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Nuke some bogus tabs from the pcode defines Patchwork
2017-09-12 16:29 ` [PATCH 1/2] " Chris Wilson
2017-09-12 21:15 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
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