From: Nickey Yang <nickey.yang@rock-chips.com> To: mark.yao@rock-chips.com, robh+dt@kernel.org, heiko@sntech.de, mark.rutland@arm.com, airlied@linux.ie Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, seanpaul@chromium.org, briannorris@chromium.org, hl@rock-chips.com, zyw@rock-chips.com, bivvy.bi@rock-chips.com, xbl@rock-chips.com, nickey.yang@rock-chips.com Subject: [PATCH v2 6/8] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock Date: Tue, 26 Sep 2017 15:55:21 +0800 [thread overview] Message-ID: <1506412523-1766-6-git-send-email-nickey.yang@rock-chips.com> (raw) In-Reply-To: <1506412523-1766-1-git-send-email-nickey.yang@rock-chips.com> Mipi-dphy's ref_clk connect to clk_dphy_pll inside rk3399. clk_24m -> Gate11[14] -> clk_mipidphy_ref -> Gate21[0] -> clk_dphy_pll So correct it. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3..6aa43fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1629,7 +1629,7 @@ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_DPHY_TX0_CFG>; clock-names = "ref", "pclk", "phy_cfg"; power-domains = <&power RK3399_PD_VIO>; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Nickey Yang <nickey.yang@rock-chips.com> To: mark.yao@rock-chips.com, robh+dt@kernel.org, heiko@sntech.de, mark.rutland@arm.com, airlied@linux.ie Cc: bivvy.bi@rock-chips.com, hl@rock-chips.com, briannorris@chromium.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, nickey.yang@rock-chips.com, zyw@rock-chips.com, xbl@rock-chips.com Subject: [PATCH v2 6/8] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock Date: Tue, 26 Sep 2017 15:55:21 +0800 [thread overview] Message-ID: <1506412523-1766-6-git-send-email-nickey.yang@rock-chips.com> (raw) In-Reply-To: <1506412523-1766-1-git-send-email-nickey.yang@rock-chips.com> Mipi-dphy's ref_clk connect to clk_dphy_pll inside rk3399. clk_24m -> Gate11[14] -> clk_mipidphy_ref -> Gate21[0] -> clk_dphy_pll So correct it. Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com> --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3..6aa43fd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1629,7 +1629,7 @@ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0x0 0xff960000 0x0 0x8000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_DPHY_TX0_CFG>; clock-names = "ref", "pclk", "phy_cfg"; power-domains = <&power RK3399_PD_VIO>; -- 1.9.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
next prev parent reply other threads:[~2017-09-26 7:56 UTC|newest] Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-09-26 7:55 [PATCH v2 1/8] drm/rockchip/dsi: correct Feedback divider setting Nickey Yang 2017-09-26 7:55 ` Nickey Yang 2017-09-26 7:55 ` [PATCH v2 2/8] drm/rockchip/dsi: add dual mipi channel support Nickey Yang 2017-09-26 7:55 ` Nickey Yang 2017-09-27 1:25 ` Matthias Kaehlcke 2017-09-27 1:25 ` Matthias Kaehlcke 2017-09-27 7:05 ` Mark yao 2017-10-12 13:53 ` Sean Paul 2017-10-12 13:53 ` Sean Paul 2017-10-13 8:18 ` Archit Taneja 2017-09-26 7:55 ` [PATCH v2 3/8] dt-bindings: add the rockchip,dual-channel for dw-mipi-dsi Nickey Yang 2017-09-26 7:55 ` [PATCH v2 4/8] drm/rockchip/dsi: correct phy parameter setting Nickey Yang 2017-09-26 7:55 ` Nickey Yang 2017-09-27 17:56 ` Matthias Kaehlcke 2017-10-12 13:58 ` Sean Paul 2017-10-12 13:58 ` Sean Paul 2017-09-26 7:55 ` [PATCH v2 5/8] drm/rockchip/dsi: Use DRM_DEV_ERROR instead of dev_err Nickey Yang 2017-09-26 7:55 ` Nickey Yang 2017-09-27 6:09 ` Mark yao 2017-09-27 6:09 ` Mark yao 2017-09-26 7:55 ` Nickey Yang [this message] 2017-09-26 7:55 ` [PATCH v2 6/8] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock Nickey Yang 2017-09-26 14:00 ` Heiko Stuebner 2017-09-26 14:00 ` Heiko Stuebner 2017-09-26 7:55 ` [PATCH v2 7/8] arm64: dts: rockchip: add a grf clk for dw-mipi-dsi Nickey Yang 2017-09-26 7:55 ` Nickey Yang 2017-09-26 14:01 ` Heiko Stuebner 2017-09-26 14:01 ` Heiko Stuebner 2017-09-26 7:55 ` [PATCH v2 8/8] arm64: dts: rockchip: add mipi_dsi1 support for rk3399 Nickey Yang 2017-09-27 6:44 ` [PATCH v2 1/8] drm/rockchip/dsi: correct Feedback divider setting Mark yao 2017-09-27 19:51 ` Sean Paul 2017-10-11 21:26 ` Kristian Kristensen 2017-10-11 21:26 ` Kristian Kristensen 2017-10-13 8:09 ` Archit Taneja 2017-10-13 8:09 ` Archit Taneja
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