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* Determine if ECC is enabled on Vega10.
@ 2017-09-26 22:25 David Panariti
       [not found] ` <1506464709-22467-1-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 5+ messages in thread
From: David Panariti @ 2017-09-26 22:25 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

VBIOS decides whether or not to enabled ECC.  During init, we check and
report the state.

[PATCH 1/2] drm/amdgpu: New header for fields needed to determine
[PATCH 2/2] drm/amdgpu: Add ability to determine and report if board
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 1/2] drm/amdgpu: New header for fields needed to determine state of ECC.
       [not found] ` <1506464709-22467-1-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-26 22:25   ` David Panariti
  2017-09-26 22:25   ` [PATCH 2/2] drm/amdgpu: Add ability to determine and report if board supports ECC David Panariti
  1 sibling, 0 replies; 5+ messages in thread
From: David Panariti @ 2017-09-26 22:25 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: David Panariti

Add header files with ECC related definitions
(MASKs, SHIFTs, DEFAULTs and OFFSETS).

Change-Id: I6e420f11db8e701402088a5bc47f641d5ac41c47
Signed-off-by: David Panariti <David.Panariti@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 .../include/asic_reg/vega10/UMC/umc_6_0_default.h  | 31 +++++++++++++
 .../include/asic_reg/vega10/UMC/umc_6_0_offset.h   | 52 ++++++++++++++++++++++
 .../include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h  | 36 +++++++++++++++
 3 files changed, 119 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h
new file mode 100644
index 0000000..128a18f
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_DEFAULT_HEADER
+#define _umc_6_0_DEFAULT_HEADER
+
+#define mmUMCCH0_0_EccCtrl_DEFAULT				0x00000000
+
+#define mmUMCCH0_0_UMC_CONFIG_DEFAULT				0x00000203
+
+#define mmUMCCH0_0_UmcLocalCap_DEFAULT				0x00000000
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h
new file mode 100644
index 0000000..6985dbb
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_OFFSET_H_
+#define _umc_6_0_OFFSET_H_
+
+#define mmUMCCH0_0_EccCtrl				0x0053
+#define mmUMCCH0_0_EccCtrl_BASE_IDX			0
+#define mmUMCCH1_0_EccCtrl				0x0853
+#define mmUMCCH1_0_EccCtrl_BASE_IDX			0
+#define mmUMCCH2_0_EccCtrl				0x1053
+#define mmUMCCH2_0_EccCtrl_BASE_IDX			0
+#define mmUMCCH3_0_EccCtrl				0x1853
+#define mmUMCCH3_0_EccCtrl_BASE_IDX			0
+
+#define mmUMCCH0_0_UMC_CONFIG				0x0040
+#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX			0
+#define mmUMCCH1_0_UMC_CONFIG				0x0840
+#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX			0
+#define mmUMCCH2_0_UMC_CONFIG				0x1040
+#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX			0
+#define mmUMCCH3_0_UMC_CONFIG				0x1840
+#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX			0
+
+#define mmUMCCH0_0_UmcLocalCap				0x0306
+#define mmUMCCH0_0_UmcLocalCap_BASE_IDX			0
+#define mmUMCCH1_0_UmcLocalCap				0x0b06
+#define mmUMCCH1_0_UmcLocalCap_BASE_IDX			0
+#define mmUMCCH2_0_UmcLocalCap				0x1306
+#define mmUMCCH2_0_UmcLocalCap_BASE_IDX			0
+#define mmUMCCH3_0_UmcLocalCap				0x1b06
+#define mmUMCCH3_0_UmcLocalCap_BASE_IDX			0
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h
new file mode 100644
index 0000000..3e857d1
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_SH_MASK_HEADER
+#define _umc_6_0_SH_MASK_HEADER
+
+#define UMCCH0_0_EccCtrl__RdEccEn_MASK   0x00000400L
+#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT   0xa
+#define UMCCH0_0_EccCtrl__WrEccEn_MASK   0x00000001L
+#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT   0x0
+
+#define UMCCH0_0_UMC_CONFIG__DramReady_MASK   0x80000000L
+#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT   0x1f
+
+#define UMCCH0_0_UmcLocalCap__EccDis_MASK   0x00000001L
+#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT   0x0
+
+#endif
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/amdgpu: Add ability to determine and report if board supports ECC.
       [not found] ` <1506464709-22467-1-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
  2017-09-26 22:25   ` [PATCH 1/2] drm/amdgpu: New header for fields needed to determine state of ECC David Panariti
@ 2017-09-26 22:25   ` David Panariti
  1 sibling, 0 replies; 5+ messages in thread
From: David Panariti @ 2017-09-26 22:25 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: David Panariti

Make initialization code check the ECC related registers, which are initialized
by the VBIOS, to see if ECC is present and initialized and DRM_INFO() the
result.

Change-Id: I8617269809cf3641c5151291ad5d964f55f7f835
Signed-off-by: David Panariti <David.Panariti@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 207 ++++++++++++++++++++++++++++++++++
 1 file changed, 207 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index bc7b9c7..67f3f56 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -34,6 +34,7 @@
 #include "vega10/vega10_enum.h"
 
 #include "soc15_common.h"
+#include "vega10/UMC/umc_6_0_sh_mask.h"
 
 #include "nbio_v6_1.h"
 #include "nbio_v7_0.h"
@@ -71,6 +72,122 @@ static const u32 golden_settings_vega10_hdp[] =
 	0xf6e, 0x0fffffff, 0x00000000,
 };
 
+/* Ecc related register addresses, (BASE + reg offset) */
+
+/* Universal Memory Controller caps (may be fused). */
+/* UMCCH:UmcLocalCap */
+#define UMCLOCALCAPS_ADDR0	(0x00014306 + 0x00000000)
+#define UMCLOCALCAPS_ADDR1	(0x00014306 + 0x00000800)
+#define UMCLOCALCAPS_ADDR2	(0x00014306 + 0x00001000)
+#define UMCLOCALCAPS_ADDR3	(0x00014306 + 0x00001800)
+#define UMCLOCALCAPS_ADDR4	(0x00054306 + 0x00000000)
+#define UMCLOCALCAPS_ADDR5	(0x00054306 + 0x00000800)
+#define UMCLOCALCAPS_ADDR6	(0x00054306 + 0x00001000)
+#define UMCLOCALCAPS_ADDR7	(0x00054306 + 0x00001800)
+#define UMCLOCALCAPS_ADDR8	(0x00094306 + 0x00000000)
+#define UMCLOCALCAPS_ADDR9	(0x00094306 + 0x00000800)
+#define UMCLOCALCAPS_ADDR10	(0x00094306 + 0x00001000)
+#define UMCLOCALCAPS_ADDR11	(0x00094306 + 0x00001800)
+#define UMCLOCALCAPS_ADDR12	(0x000d4306 + 0x00000000)
+#define UMCLOCALCAPS_ADDR13	(0x000d4306 + 0x00000800)
+#define UMCLOCALCAPS_ADDR14	(0x000d4306 + 0x00001000)
+#define UMCLOCALCAPS_ADDR15	(0x000d4306 + 0x00001800)
+
+/* Universal Memory Controller Channel config. */
+/* UMCCH:UMC_CONFIG */
+#define UMCCH_UMC_CONFIG_ADDR0	(0x00014040 + 0x00000000)
+#define UMCCH_UMC_CONFIG_ADDR1	(0x00014040 + 0x00000800)
+#define UMCCH_UMC_CONFIG_ADDR2	(0x00014040 + 0x00001000)
+#define UMCCH_UMC_CONFIG_ADDR3	(0x00014040 + 0x00001800)
+#define UMCCH_UMC_CONFIG_ADDR4	(0x00054040 + 0x00000000)
+#define UMCCH_UMC_CONFIG_ADDR5	(0x00054040 + 0x00000800)
+#define UMCCH_UMC_CONFIG_ADDR6	(0x00054040 + 0x00001000)
+#define UMCCH_UMC_CONFIG_ADDR7	(0x00054040 + 0x00001800)
+#define UMCCH_UMC_CONFIG_ADDR8	(0x00094040 + 0x00000000)
+#define UMCCH_UMC_CONFIG_ADDR9	(0x00094040 + 0x00000800)
+#define UMCCH_UMC_CONFIG_ADDR10	(0x00094040 + 0x00001000)
+#define UMCCH_UMC_CONFIG_ADDR11	(0x00094040 + 0x00001800)
+#define UMCCH_UMC_CONFIG_ADDR12	(0x000d4040 + 0x00000000)
+#define UMCCH_UMC_CONFIG_ADDR13	(0x000d4040 + 0x00000800)
+#define UMCCH_UMC_CONFIG_ADDR14	(0x000d4040 + 0x00001000)
+#define UMCCH_UMC_CONFIG_ADDR15	(0x000d4040 + 0x00001800)
+
+/* Universal Memory Controller Channel Ecc config. */
+/* UMCCH:EccCtrl */
+#define UMCCH_ECCCTRL_ADDR0	(0x00014053 + 0x00000000)
+#define UMCCH_ECCCTRL_ADDR1	(0x00014053 + 0x00000800)
+#define UMCCH_ECCCTRL_ADDR2	(0x00014053 + 0x00001000)
+#define UMCCH_ECCCTRL_ADDR3	(0x00014053 + 0x00001800)
+#define UMCCH_ECCCTRL_ADDR4	(0x00054053 + 0x00000000)
+#define UMCCH_ECCCTRL_ADDR5	(0x00054053 + 0x00000800)
+#define UMCCH_ECCCTRL_ADDR6	(0x00054053 + 0x00001000)
+#define UMCCH_ECCCTRL_ADDR7	(0x00054053 + 0x00001800)
+#define UMCCH_ECCCTRL_ADDR8	(0x00094053 + 0x00000000)
+#define UMCCH_ECCCTRL_ADDR9	(0x00094053 + 0x00000800)
+#define UMCCH_ECCCTRL_ADDR10	(0x00094053 + 0x00001000)
+#define UMCCH_ECCCTRL_ADDR11	(0x00094053 + 0x00001800)
+#define UMCCH_ECCCTRL_ADDR12	(0x000d4053 + 0x00000000)
+#define UMCCH_ECCCTRL_ADDR13	(0x000d4053 + 0x00000800)
+#define UMCCH_ECCCTRL_ADDR14	(0x000d4053 + 0x00001000)
+#define UMCCH_ECCCTRL_ADDR15	(0x000d4053 + 0x00001800)
+
+static const uint32_t ecc_umclocalcap_addrs[] = {
+	UMCLOCALCAPS_ADDR0,
+	UMCLOCALCAPS_ADDR1,
+	UMCLOCALCAPS_ADDR2,
+	UMCLOCALCAPS_ADDR3,
+	UMCLOCALCAPS_ADDR4,
+	UMCLOCALCAPS_ADDR5,
+	UMCLOCALCAPS_ADDR6,
+	UMCLOCALCAPS_ADDR7,
+	UMCLOCALCAPS_ADDR8,
+	UMCLOCALCAPS_ADDR9,
+	UMCLOCALCAPS_ADDR10,
+	UMCLOCALCAPS_ADDR11,
+	UMCLOCALCAPS_ADDR12,
+	UMCLOCALCAPS_ADDR13,
+	UMCLOCALCAPS_ADDR14,
+	UMCLOCALCAPS_ADDR15,
+};
+
+static const uint32_t ecc_umcch_umc_config_addrs[] = {
+	UMCCH_UMC_CONFIG_ADDR0,
+	UMCCH_UMC_CONFIG_ADDR1,
+	UMCCH_UMC_CONFIG_ADDR2,
+	UMCCH_UMC_CONFIG_ADDR3,
+	UMCCH_UMC_CONFIG_ADDR4,
+	UMCCH_UMC_CONFIG_ADDR5,
+	UMCCH_UMC_CONFIG_ADDR6,
+	UMCCH_UMC_CONFIG_ADDR7,
+	UMCCH_UMC_CONFIG_ADDR8,
+	UMCCH_UMC_CONFIG_ADDR9,
+	UMCCH_UMC_CONFIG_ADDR10,
+	UMCCH_UMC_CONFIG_ADDR11,
+	UMCCH_UMC_CONFIG_ADDR12,
+	UMCCH_UMC_CONFIG_ADDR13,
+	UMCCH_UMC_CONFIG_ADDR14,
+	UMCCH_UMC_CONFIG_ADDR15,
+};
+
+static const uint32_t ecc_umcch_eccctrl_addrs[] = {
+	UMCCH_ECCCTRL_ADDR0,
+	UMCCH_ECCCTRL_ADDR1,
+	UMCCH_ECCCTRL_ADDR2,
+	UMCCH_ECCCTRL_ADDR3,
+	UMCCH_ECCCTRL_ADDR4,
+	UMCCH_ECCCTRL_ADDR5,
+	UMCCH_ECCCTRL_ADDR6,
+	UMCCH_ECCCTRL_ADDR7,
+	UMCCH_ECCCTRL_ADDR8,
+	UMCCH_ECCCTRL_ADDR9,
+	UMCCH_ECCCTRL_ADDR10,
+	UMCCH_ECCCTRL_ADDR11,
+	UMCCH_ECCCTRL_ADDR12,
+	UMCCH_ECCCTRL_ADDR13,
+	UMCCH_ECCCTRL_ADDR14,
+	UMCCH_ECCCTRL_ADDR15,
+};
+
 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 					struct amdgpu_irq_src *src,
 					unsigned type,
@@ -392,11 +509,91 @@ static int gmc_v9_0_early_init(void *handle)
 	return 0;
 }
 
+static int gmc_v9_0_ecc_available(struct amdgpu_device *adev)
+{
+	uint32_t reg_val;
+	uint32_t reg_addr;
+	uint32_t field_val;
+	size_t i;
+	uint32_t fv2;
+	size_t lost_sheep;
+
+	DRM_DEBUG("ecc: gmc_v9_0_ecc_available()\n");
+
+	lost_sheep = 0;
+	for (i = 0; i < ARRAY_SIZE(ecc_umclocalcap_addrs); ++i) {
+		reg_addr = ecc_umclocalcap_addrs[i];
+		DRM_DEBUG("ecc: "
+			  "UMCCH_UmcLocalCap[%zu]: reg_addr: 0x%08x\n",
+			  i, reg_addr);
+		reg_val = RREG32(reg_addr);
+		field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UmcLocalCap,
+					  EccDis);
+		DRM_DEBUG("ecc: "
+			  "reg_val: 0x%08x, "
+			  "EccDis: 0x%08x, ",
+			  reg_val, field_val);
+		if (field_val) {
+			DRM_ERROR("ecc: UmcLocalCap:EccDis is set.\n");
+			++lost_sheep;
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ecc_umcch_umc_config_addrs); ++i) {
+		reg_addr = ecc_umcch_umc_config_addrs[i];
+		DRM_DEBUG("ecc: "
+			  "UMCCH0_0_UMC_CONFIG[%zu]: reg_addr: 0x%08x",
+			  i, reg_addr);
+		reg_val = RREG32(reg_addr);
+		field_val = REG_GET_FIELD(reg_val, UMCCH0_0_UMC_CONFIG,
+					  DramReady);
+		DRM_DEBUG("ecc: "
+			  "reg_val: 0x%08x, "
+			  "DramReady: 0x%08x\n",
+			  reg_val, field_val);
+
+		if (!field_val) {
+			DRM_ERROR("ecc: UMC_CONFIG:DramReady is not set.\n");
+			++lost_sheep;
+		}
+	}
+
+	for (i = 0; i < ARRAY_SIZE(ecc_umcch_eccctrl_addrs); ++i) {
+		reg_addr = ecc_umcch_eccctrl_addrs[i];
+		DRM_DEBUG("ecc: "
+			  "UMCCH_EccCtrl[%zu]: reg_addr: 0x%08x, ",
+			  i, reg_addr);
+		reg_val = RREG32(reg_addr);
+		field_val = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
+					  WrEccEn);
+		fv2 = REG_GET_FIELD(reg_val, UMCCH0_0_EccCtrl,
+				    RdEccEn);
+		DRM_DEBUG("ecc: "
+			  "reg_val: 0x%08x, "
+			  "WrEccEn: 0x%08x, "
+			  "RdEccEn: 0x%08x\n",
+			  reg_val, field_val, fv2);
+
+		if (!field_val) {
+			DRM_ERROR("ecc: WrEccEn is not set\n");
+			++lost_sheep;
+		}
+		if (!fv2) {
+			DRM_ERROR("ecc: RdEccEn is not set\n");
+			++lost_sheep;
+		}
+	}
+
+	DRM_DEBUG("ecc: lost_sheep: %zu\n", lost_sheep);
+	return lost_sheep == 0;
+}
+
 static int gmc_v9_0_late_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
 	unsigned i;
+	int r;
 
 	for(i = 0; i < adev->num_rings; ++i) {
 		struct amdgpu_ring *ring = adev->rings[i];
@@ -412,6 +609,16 @@ static int gmc_v9_0_late_init(void *handle)
 	for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
 		BUG_ON(vm_inv_eng[i] > 17);
 
+	r = gmc_v9_0_ecc_available(adev);
+	if (r == 1) {
+		DRM_INFO("ECC is active.\n");
+	} else if (r == 0) {
+		DRM_INFO("ECC is not present.\n");
+	} else {
+		DRM_ERROR("gmc_v9_0_ecc_available() failed. r: %d\n", r);
+		return r;
+	}
+
 	return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
 }
 
-- 
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
* RE: [PATCH 1/2] drm/amdgpu: New header for fields needed to determine state of ECC.
       [not found]     ` <1506102603-14695-2-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-25 15:53       ` Deucher, Alexander
  0 siblings, 0 replies; 5+ messages in thread
From: Deucher, Alexander @ 2017-09-25 15:53 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Panariti, David

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of David Panariti
> Sent: Friday, September 22, 2017 1:50 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Panariti, David
> Subject: [PATCH 1/2] drm/amdgpu: New header for fields needed to
> determine state of ECC.
> 
> Add header file with ECC field definitions (MASKs and SHIFTs).
> 
> Change-Id: I6e420f11db8e701402088a5bc47f641d5ac41c47
> Signed-off-by: David Panariti <David.Panariti@amd.com>

Can you add the defaults and offsets headers as well (_offset.h and _default.h)?  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Alex

> ---
>  .../include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h  | 34
> ++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
>  create mode 100644
> drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h
> 
> diff --git
> a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.
> h
> b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.
> h
> new file mode 100644
> index 0000000..1ec5633
> --- /dev/null
> +++
> b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.
> h
> @@ -0,0 +1,34 @@
> +/*
> + * Copyright (C) 2017  Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included
> + * in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> OTHER LIABILITY, WHETHER IN
> + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
> OF OR IN
> + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> THE SOFTWARE.
> + */
> +
> +#ifndef _umc_6_0_SH_MASK_HEADER
> +#define _umc_6_0_SH_MASK_HEADER
> +
> +#define UMCCH0_0_EccCtrl__RdEccEn_MASK   0x00000400L
> +#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT   0xa
> +#define UMCCH0_0_EccCtrl__WrEccEn_MASK   0x00000001L
> +#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT   0x0
> +#define UMCCH0_0_UMC_CONFIG__DramReady_MASK   0x80000000L
> +#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT   0x1f
> +#define UMCCH0_0_UmcLocalCap__EccDis_MASK   0x00000001L
> +#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT   0x0
> +
> +#endif
> --
> 2.7.4
> 
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [PATCH 1/2] drm/amdgpu: New header for fields needed to determine state of ECC.
       [not found] ` <1506102603-14695-1-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-22 17:50   ` David Panariti
       [not found]     ` <1506102603-14695-2-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 5+ messages in thread
From: David Panariti @ 2017-09-22 17:50 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: David Panariti

Add header file with ECC field definitions (MASKs and SHIFTs).

Change-Id: I6e420f11db8e701402088a5bc47f641d5ac41c47
Signed-off-by: David Panariti <David.Panariti@amd.com>
---
 .../include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h  | 34 ++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h

diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h
new file mode 100644
index 0000000..1ec5633
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2017  Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _umc_6_0_SH_MASK_HEADER
+#define _umc_6_0_SH_MASK_HEADER
+
+#define UMCCH0_0_EccCtrl__RdEccEn_MASK   0x00000400L
+#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT   0xa
+#define UMCCH0_0_EccCtrl__WrEccEn_MASK   0x00000001L
+#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT   0x0
+#define UMCCH0_0_UMC_CONFIG__DramReady_MASK   0x80000000L
+#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT   0x1f
+#define UMCCH0_0_UmcLocalCap__EccDis_MASK   0x00000001L
+#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT   0x0
+
+#endif
-- 
2.7.4

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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-09-26 22:25 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-26 22:25 Determine if ECC is enabled on Vega10 David Panariti
     [not found] ` <1506464709-22467-1-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
2017-09-26 22:25   ` [PATCH 1/2] drm/amdgpu: New header for fields needed to determine state of ECC David Panariti
2017-09-26 22:25   ` [PATCH 2/2] drm/amdgpu: Add ability to determine and report if board supports ECC David Panariti
  -- strict thread matches above, loose matches on Subject: below --
2017-09-22 17:50 Report if ECC is enabled on Vega10 David Panariti
     [not found] ` <1506102603-14695-1-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
2017-09-22 17:50   ` [PATCH 1/2] drm/amdgpu: New header for fields needed to determine state of ECC David Panariti
     [not found]     ` <1506102603-14695-2-git-send-email-David.Panariti-5C7GfCeVMHo@public.gmane.org>
2017-09-25 15:53       ` Deucher, Alexander

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