* [PATCH 1/3] drm/amdgpu: move DC and PP shared data structures to dm_pp_interface.h
@ 2017-09-28 9:40 Rex Zhu
[not found] ` <1506591633-5352-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Rex Zhu @ 2017-09-28 9:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Ia86696344d6e6bfd97d7b55101231fcad65beb49
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/include/dm_pp_interface.h | 144 ++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 143 ---------------------
2 files changed, 144 insertions(+), 143 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 7343aed..7214731 100644
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -25,6 +25,145 @@
#define PP_MAX_CLOCK_LEVELS 8
+enum amd_pp_display_config_type{
+ AMD_PP_DisplayConfigType_None = 0,
+ AMD_PP_DisplayConfigType_DP54 ,
+ AMD_PP_DisplayConfigType_DP432 ,
+ AMD_PP_DisplayConfigType_DP324 ,
+ AMD_PP_DisplayConfigType_DP27,
+ AMD_PP_DisplayConfigType_DP243,
+ AMD_PP_DisplayConfigType_DP216,
+ AMD_PP_DisplayConfigType_DP162,
+ AMD_PP_DisplayConfigType_HDMI6G ,
+ AMD_PP_DisplayConfigType_HDMI297 ,
+ AMD_PP_DisplayConfigType_HDMI162,
+ AMD_PP_DisplayConfigType_LVDS,
+ AMD_PP_DisplayConfigType_DVI,
+ AMD_PP_DisplayConfigType_WIRELESS,
+ AMD_PP_DisplayConfigType_VGA
+};
+
+struct single_display_configuration
+{
+ uint32_t controller_index;
+ uint32_t controller_id;
+ uint32_t signal_type;
+ uint32_t display_state;
+ /* phy id for the primary internal transmitter */
+ uint8_t primary_transmitter_phyi_d;
+ /* bitmap with the active lanes */
+ uint8_t primary_transmitter_active_lanemap;
+ /* phy id for the secondary internal transmitter (for dual-link dvi) */
+ uint8_t secondary_transmitter_phy_id;
+ /* bitmap with the active lanes */
+ uint8_t secondary_transmitter_active_lanemap;
+ /* misc phy settings for SMU. */
+ uint32_t config_flags;
+ uint32_t display_type;
+ uint32_t view_resolution_cx;
+ uint32_t view_resolution_cy;
+ enum amd_pp_display_config_type displayconfigtype;
+ uint32_t vertical_refresh; /* for active display */
+};
+
+#define MAX_NUM_DISPLAY 32
+
+struct amd_pp_display_configuration {
+ bool nb_pstate_switch_disable;/* controls NB PState switch */
+ bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
+ bool cpu_pstate_disable;
+ uint32_t cpu_pstate_separation_time;
+
+ uint32_t num_display; /* total number of display*/
+ uint32_t num_path_including_non_display;
+ uint32_t crossfire_display_index;
+ uint32_t min_mem_set_clock;
+ uint32_t min_core_set_clock;
+ /* unit 10KHz x bit*/
+ uint32_t min_bus_bandwidth;
+ /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
+ uint32_t min_core_set_clock_in_sr;
+
+ struct single_display_configuration displays[MAX_NUM_DISPLAY];
+
+ uint32_t vrefresh; /* for active display*/
+
+ uint32_t min_vblank_time; /* for active display*/
+ bool multi_monitor_in_sync;
+ /* Controller Index of primary display - used in MCLK SMC switching hang
+ * SW Workaround*/
+ uint32_t crtc_index;
+ /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
+ uint32_t line_time_in_us;
+ bool invalid_vblank_time;
+
+ uint32_t display_clk;
+ /*
+ * for given display configuration if multimonitormnsync == false then
+ * Memory clock DPMS with this latency or below is allowed, DPMS with
+ * higher latency not allowed.
+ */
+ uint32_t dce_tolerable_mclk_in_active_latency;
+ uint32_t min_dcef_set_clk;
+ uint32_t min_dcef_deep_sleep_set_clk;
+};
+
+struct amd_pp_simple_clock_info {
+ uint32_t engine_max_clock;
+ uint32_t memory_max_clock;
+ uint32_t level;
+};
+
+enum PP_DAL_POWERLEVEL {
+ PP_DAL_POWERLEVEL_INVALID = 0,
+ PP_DAL_POWERLEVEL_ULTRALOW,
+ PP_DAL_POWERLEVEL_LOW,
+ PP_DAL_POWERLEVEL_NOMINAL,
+ PP_DAL_POWERLEVEL_PERFORMANCE,
+
+ PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
+ PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
+ PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
+ PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
+ PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
+ PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
+ PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
+ PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
+};
+
+struct amd_pp_clock_info {
+ uint32_t min_engine_clock;
+ uint32_t max_engine_clock;
+ uint32_t min_memory_clock;
+ uint32_t max_memory_clock;
+ uint32_t min_bus_bandwidth;
+ uint32_t max_bus_bandwidth;
+ uint32_t max_engine_clock_in_sr;
+ uint32_t min_engine_clock_in_sr;
+ enum PP_DAL_POWERLEVEL max_clocks_state;
+};
+
+enum amd_pp_clock_type {
+ amd_pp_disp_clock = 1,
+ amd_pp_sys_clock,
+ amd_pp_mem_clock,
+ amd_pp_dcef_clock,
+ amd_pp_soc_clock,
+ amd_pp_pixel_clock,
+ amd_pp_phy_clock,
+ amd_pp_dcf_clock,
+ amd_pp_dpp_clock,
+ amd_pp_f_clock = amd_pp_dcef_clock,
+};
+
+#define MAX_NUM_CLOCKS 16
+
+struct amd_pp_clocks {
+ uint32_t count;
+ uint32_t clock[MAX_NUM_CLOCKS];
+ uint32_t latency[MAX_NUM_CLOCKS];
+};
+
struct pp_clock_with_latency {
uint32_t clocks_in_khz;
uint32_t latency_in_us;
@@ -45,6 +184,11 @@ struct pp_clock_levels_with_voltage {
struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS];
};
+struct pp_display_clock_request {
+ enum amd_pp_clock_type clock_type;
+ uint32_t clock_freq_in_khz;
+};
+
#define PP_MAX_WM_SETS 4
enum pp_wm_set_id {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index 95932cc..da2e6ee 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -64,144 +64,6 @@ struct amd_pp_init {
uint32_t feature_mask;
};
-enum amd_pp_display_config_type{
- AMD_PP_DisplayConfigType_None = 0,
- AMD_PP_DisplayConfigType_DP54 ,
- AMD_PP_DisplayConfigType_DP432 ,
- AMD_PP_DisplayConfigType_DP324 ,
- AMD_PP_DisplayConfigType_DP27,
- AMD_PP_DisplayConfigType_DP243,
- AMD_PP_DisplayConfigType_DP216,
- AMD_PP_DisplayConfigType_DP162,
- AMD_PP_DisplayConfigType_HDMI6G ,
- AMD_PP_DisplayConfigType_HDMI297 ,
- AMD_PP_DisplayConfigType_HDMI162,
- AMD_PP_DisplayConfigType_LVDS,
- AMD_PP_DisplayConfigType_DVI,
- AMD_PP_DisplayConfigType_WIRELESS,
- AMD_PP_DisplayConfigType_VGA
-};
-
-struct single_display_configuration
-{
- uint32_t controller_index;
- uint32_t controller_id;
- uint32_t signal_type;
- uint32_t display_state;
- /* phy id for the primary internal transmitter */
- uint8_t primary_transmitter_phyi_d;
- /* bitmap with the active lanes */
- uint8_t primary_transmitter_active_lanemap;
- /* phy id for the secondary internal transmitter (for dual-link dvi) */
- uint8_t secondary_transmitter_phy_id;
- /* bitmap with the active lanes */
- uint8_t secondary_transmitter_active_lanemap;
- /* misc phy settings for SMU. */
- uint32_t config_flags;
- uint32_t display_type;
- uint32_t view_resolution_cx;
- uint32_t view_resolution_cy;
- enum amd_pp_display_config_type displayconfigtype;
- uint32_t vertical_refresh; /* for active display */
-};
-
-#define MAX_NUM_DISPLAY 32
-
-struct amd_pp_display_configuration {
- bool nb_pstate_switch_disable;/* controls NB PState switch */
- bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
- bool cpu_pstate_disable;
- uint32_t cpu_pstate_separation_time;
-
- uint32_t num_display; /* total number of display*/
- uint32_t num_path_including_non_display;
- uint32_t crossfire_display_index;
- uint32_t min_mem_set_clock;
- uint32_t min_core_set_clock;
- /* unit 10KHz x bit*/
- uint32_t min_bus_bandwidth;
- /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
- uint32_t min_core_set_clock_in_sr;
-
- struct single_display_configuration displays[MAX_NUM_DISPLAY];
-
- uint32_t vrefresh; /* for active display*/
-
- uint32_t min_vblank_time; /* for active display*/
- bool multi_monitor_in_sync;
- /* Controller Index of primary display - used in MCLK SMC switching hang
- * SW Workaround*/
- uint32_t crtc_index;
- /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
- uint32_t line_time_in_us;
- bool invalid_vblank_time;
-
- uint32_t display_clk;
- /*
- * for given display configuration if multimonitormnsync == false then
- * Memory clock DPMS with this latency or below is allowed, DPMS with
- * higher latency not allowed.
- */
- uint32_t dce_tolerable_mclk_in_active_latency;
- uint32_t min_dcef_set_clk;
- uint32_t min_dcef_deep_sleep_set_clk;
-};
-
-struct amd_pp_simple_clock_info {
- uint32_t engine_max_clock;
- uint32_t memory_max_clock;
- uint32_t level;
-};
-
-enum PP_DAL_POWERLEVEL {
- PP_DAL_POWERLEVEL_INVALID = 0,
- PP_DAL_POWERLEVEL_ULTRALOW,
- PP_DAL_POWERLEVEL_LOW,
- PP_DAL_POWERLEVEL_NOMINAL,
- PP_DAL_POWERLEVEL_PERFORMANCE,
-
- PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
- PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
- PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
- PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
- PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
- PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
- PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
- PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
-};
-
-struct amd_pp_clock_info {
- uint32_t min_engine_clock;
- uint32_t max_engine_clock;
- uint32_t min_memory_clock;
- uint32_t max_memory_clock;
- uint32_t min_bus_bandwidth;
- uint32_t max_bus_bandwidth;
- uint32_t max_engine_clock_in_sr;
- uint32_t min_engine_clock_in_sr;
- enum PP_DAL_POWERLEVEL max_clocks_state;
-};
-
-enum amd_pp_clock_type {
- amd_pp_disp_clock = 1,
- amd_pp_sys_clock,
- amd_pp_mem_clock,
- amd_pp_dcef_clock,
- amd_pp_soc_clock,
- amd_pp_pixel_clock,
- amd_pp_phy_clock,
- amd_pp_dcf_clock,
- amd_pp_dpp_clock,
- amd_pp_f_clock = amd_pp_dcef_clock,
-};
-
-#define MAX_NUM_CLOCKS 16
-
-struct amd_pp_clocks {
- uint32_t count;
- uint32_t clock[MAX_NUM_CLOCKS];
- uint32_t latency[MAX_NUM_CLOCKS];
-};
enum {
@@ -223,11 +85,6 @@ struct pp_gpu_power {
uint32_t average_gpu_power;
};
-struct pp_display_clock_request {
- enum amd_pp_clock_type clock_type;
- uint32_t clock_freq_in_khz;
-};
-
#define PP_GROUP_MASK 0xF0000000
#define PP_GROUP_SHIFT 28
--
1.9.1
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amd-gfx@lists.freedesktop.org
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* [PATCH 2/3] drm/amd/powerplay: move functions to amd_pm_funcs table
[not found] ` <1506591633-5352-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-28 9:40 ` Rex Zhu
2017-09-28 9:40 ` [PATCH 3/3] drm/amd/powerplay: delete flag PP_VALID Rex Zhu
1 sibling, 0 replies; 4+ messages in thread
From: Rex Zhu @ 2017-09-28 9:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
those functions are exported to DC
Change-Id: I67637337ee40a6da6ecdd15fd78af0335f4c8414
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 29 +++--
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 140 +++++++++++----------
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 32 -----
3 files changed, 93 insertions(+), 108 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index aefd9eb..56bc7cc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -185,11 +185,12 @@ bool dm_pp_apply_display_requirements(
adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
/* TODO: complete implementation of
- * amd_powerplay_display_configuration_change().
+ * pp_display_configuration_change().
* Follow example of:
* PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
* PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
- amd_powerplay_display_configuration_change(
+ if (adev->powerplay.pp_funcs->display_configuration_change)
+ adev->powerplay.pp_funcs->display_configuration_change(
adev->powerplay.pp_handle,
&adev->pm.pm_display_cfg);
@@ -318,22 +319,26 @@ bool dm_pp_get_clock_levels_by_type(
struct amd_pp_simple_clock_info validation_clks = { 0 };
uint32_t i;
- if (amd_powerplay_get_clock_by_type(pp_handle,
+ if (adev->powerplay.pp_funcs->get_clock_by_type) {
+ if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
dc_to_pp_clock_type(clk_type), &pp_clks)) {
/* Error in pplib. Provide default values. */
- get_default_clock_levels(clk_type, dc_clks);
- return true;
+ get_default_clock_levels(clk_type, dc_clks);
+ return true;
+ }
}
pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
- if (amd_powerplay_get_display_mode_validation_clocks(pp_handle,
- &validation_clks)) {
- /* Error in pplib. Provide default values. */
- DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
- validation_clks.engine_max_clock = 72000;
- validation_clks.memory_max_clock = 80000;
- validation_clks.level = 0;
+ if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
+ if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
+ pp_handle, &validation_clks)) {
+ /* Error in pplib. Provide default values. */
+ DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
+ validation_clks.engine_max_clock = 72000;
+ validation_clks.memory_max_clock = 80000;
+ validation_clks.level = 0;
+ }
}
DRM_INFO("DM_PPLIB: Validation clocks:\n");
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 03999a6..a0f08ec 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -781,6 +781,29 @@ static int pp_dpm_get_pp_table(void *handle, char **table)
return size;
}
+static int amd_powerplay_reset(void *handle)
+{
+ struct pp_instance *instance = (struct pp_instance *)handle;
+ int ret;
+
+ if (!instance->pm_en)
+ return 0;
+
+ ret = pp_check(instance);
+ if (ret)
+ return ret;
+
+ ret = pp_hw_fini(instance);
+ if (ret)
+ return ret;
+
+ ret = hwmgr_hw_init(instance);
+ if (ret)
+ return ret;
+
+ return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
+}
+
static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
{
struct pp_hwmgr *hwmgr;
@@ -1136,64 +1159,9 @@ static int pp_dpm_switch_power_profile(void *handle,
return 0;
}
-const struct amd_pm_funcs pp_dpm_funcs = {
- .get_temperature = pp_dpm_get_temperature,
- .load_firmware = pp_dpm_load_fw,
- .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
- .force_performance_level = pp_dpm_force_performance_level,
- .get_performance_level = pp_dpm_get_performance_level,
- .get_current_power_state = pp_dpm_get_current_power_state,
- .get_sclk = pp_dpm_get_sclk,
- .get_mclk = pp_dpm_get_mclk,
- .powergate_vce = pp_dpm_powergate_vce,
- .powergate_uvd = pp_dpm_powergate_uvd,
- .dispatch_tasks = pp_dpm_dispatch_tasks,
- .set_fan_control_mode = pp_dpm_set_fan_control_mode,
- .get_fan_control_mode = pp_dpm_get_fan_control_mode,
- .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
- .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
- .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
- .get_pp_num_states = pp_dpm_get_pp_num_states,
- .get_pp_table = pp_dpm_get_pp_table,
- .set_pp_table = pp_dpm_set_pp_table,
- .force_clock_level = pp_dpm_force_clock_level,
- .print_clock_levels = pp_dpm_print_clock_levels,
- .get_sclk_od = pp_dpm_get_sclk_od,
- .set_sclk_od = pp_dpm_set_sclk_od,
- .get_mclk_od = pp_dpm_get_mclk_od,
- .set_mclk_od = pp_dpm_set_mclk_od,
- .read_sensor = pp_dpm_read_sensor,
- .get_vce_clock_state = pp_dpm_get_vce_clock_state,
- .reset_power_profile_state = pp_dpm_reset_power_profile_state,
- .get_power_profile_state = pp_dpm_get_power_profile_state,
- .set_power_profile_state = pp_dpm_set_power_profile_state,
- .switch_power_profile = pp_dpm_switch_power_profile,
- .set_clockgating_by_smu = pp_set_clockgating_by_smu,
-};
-
-int amd_powerplay_reset(void *handle)
-{
- struct pp_instance *instance = (struct pp_instance *)handle;
- int ret;
-
- ret = pp_check(instance);
- if (ret)
- return ret;
-
- ret = pp_hw_fini(instance);
- if (ret)
- return ret;
-
- ret = hwmgr_hw_init(instance);
- if (ret)
- return ret;
-
- return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
-}
-
/* export this function to DAL */
-int amd_powerplay_display_configuration_change(void *handle,
+static int pp_display_configuration_change(void *handle,
const struct amd_pp_display_configuration *display_config)
{
struct pp_hwmgr *hwmgr;
@@ -1212,7 +1180,7 @@ int amd_powerplay_display_configuration_change(void *handle,
return 0;
}
-int amd_powerplay_get_display_power_level(void *handle,
+static int pp_get_display_power_level(void *handle,
struct amd_pp_simple_clock_info *output)
{
struct pp_hwmgr *hwmgr;
@@ -1235,7 +1203,7 @@ int amd_powerplay_get_display_power_level(void *handle,
return ret;
}
-int amd_powerplay_get_current_clocks(void *handle,
+static int pp_get_current_clocks(void *handle,
struct amd_pp_clock_info *clocks)
{
struct amd_pp_simple_clock_info simple_clocks;
@@ -1289,7 +1257,7 @@ int amd_powerplay_get_current_clocks(void *handle,
return 0;
}
-int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
+static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
{
struct pp_hwmgr *hwmgr;
struct pp_instance *pp_handle = (struct pp_instance *)handle;
@@ -1311,7 +1279,7 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s
return ret;
}
-int amd_powerplay_get_clock_by_type_with_latency(void *handle,
+static int pp_get_clock_by_type_with_latency(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_latency *clocks)
{
@@ -1333,7 +1301,7 @@ int amd_powerplay_get_clock_by_type_with_latency(void *handle,
return ret;
}
-int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
+static int pp_get_clock_by_type_with_voltage(void *handle,
enum amd_pp_clock_type type,
struct pp_clock_levels_with_voltage *clocks)
{
@@ -1358,7 +1326,7 @@ int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
return ret;
}
-int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
+static int pp_set_watermarks_for_clocks_ranges(void *handle,
struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
{
struct pp_hwmgr *hwmgr;
@@ -1382,7 +1350,7 @@ int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
return ret;
}
-int amd_powerplay_display_clock_voltage_request(void *handle,
+static int pp_display_clock_voltage_request(void *handle,
struct pp_display_clock_request *clock)
{
struct pp_hwmgr *hwmgr;
@@ -1405,7 +1373,7 @@ int amd_powerplay_display_clock_voltage_request(void *handle,
return ret;
}
-int amd_powerplay_get_display_mode_validation_clocks(void *handle,
+static int pp_get_display_mode_validation_clocks(void *handle,
struct amd_pp_simple_clock_info *clocks)
{
struct pp_hwmgr *hwmgr;
@@ -1431,3 +1399,47 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle,
return ret;
}
+const struct amd_pm_funcs pp_dpm_funcs = {
+ .get_temperature = pp_dpm_get_temperature,
+ .load_firmware = pp_dpm_load_fw,
+ .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
+ .force_performance_level = pp_dpm_force_performance_level,
+ .get_performance_level = pp_dpm_get_performance_level,
+ .get_current_power_state = pp_dpm_get_current_power_state,
+ .powergate_vce = pp_dpm_powergate_vce,
+ .powergate_uvd = pp_dpm_powergate_uvd,
+ .dispatch_tasks = pp_dpm_dispatch_tasks,
+ .set_fan_control_mode = pp_dpm_set_fan_control_mode,
+ .get_fan_control_mode = pp_dpm_get_fan_control_mode,
+ .set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
+ .get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
+ .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
+ .get_pp_num_states = pp_dpm_get_pp_num_states,
+ .get_pp_table = pp_dpm_get_pp_table,
+ .set_pp_table = pp_dpm_set_pp_table,
+ .force_clock_level = pp_dpm_force_clock_level,
+ .print_clock_levels = pp_dpm_print_clock_levels,
+ .get_sclk_od = pp_dpm_get_sclk_od,
+ .set_sclk_od = pp_dpm_set_sclk_od,
+ .get_mclk_od = pp_dpm_get_mclk_od,
+ .set_mclk_od = pp_dpm_set_mclk_od,
+ .read_sensor = pp_dpm_read_sensor,
+ .get_vce_clock_state = pp_dpm_get_vce_clock_state,
+ .reset_power_profile_state = pp_dpm_reset_power_profile_state,
+ .get_power_profile_state = pp_dpm_get_power_profile_state,
+ .set_power_profile_state = pp_dpm_set_power_profile_state,
+ .switch_power_profile = pp_dpm_switch_power_profile,
+ .set_clockgating_by_smu = pp_set_clockgating_by_smu,
+/* export to DC */
+ .get_sclk = pp_dpm_get_sclk,
+ .get_mclk = pp_dpm_get_mclk,
+ .display_configuration_change = pp_display_configuration_change,
+ .get_display_power_level = pp_get_display_power_level,
+ .get_current_clocks = pp_get_current_clocks,
+ .get_clock_by_type = pp_get_clock_by_type,
+ .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
+ .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
+ .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
+ .display_clock_voltage_request = pp_display_clock_voltage_request,
+ .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
+};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
index da2e6ee..006954e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h
@@ -129,37 +129,5 @@ struct amd_powerplay {
const struct amd_pm_funcs *pp_funcs;
};
-int amd_powerplay_reset(void *handle);
-
-int amd_powerplay_display_configuration_change(void *handle,
- const struct amd_pp_display_configuration *input);
-
-int amd_powerplay_get_display_power_level(void *handle,
- struct amd_pp_simple_clock_info *output);
-
-int amd_powerplay_get_current_clocks(void *handle,
- struct amd_pp_clock_info *output);
-
-int amd_powerplay_get_clock_by_type(void *handle,
- enum amd_pp_clock_type type,
- struct amd_pp_clocks *clocks);
-
-int amd_powerplay_get_clock_by_type_with_latency(void *handle,
- enum amd_pp_clock_type type,
- struct pp_clock_levels_with_latency *clocks);
-
-int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
- enum amd_pp_clock_type type,
- struct pp_clock_levels_with_voltage *clocks);
-
-int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
- struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
-
-int amd_powerplay_display_clock_voltage_request(void *handle,
- struct pp_display_clock_request *clock);
-
-int amd_powerplay_get_display_mode_validation_clocks(void *handle,
- struct amd_pp_simple_clock_info *output);
-
#endif /* _AMD_POWERPLAY_H_ */
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/3] drm/amd/powerplay: delete flag PP_VALID
[not found] ` <1506591633-5352-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-09-28 9:40 ` [PATCH 2/3] drm/amd/powerplay: move functions to amd_pm_funcs table Rex Zhu
@ 2017-09-28 9:40 ` Rex Zhu
[not found] ` <1506591633-5352-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
1 sibling, 1 reply; 4+ messages in thread
From: Rex Zhu @ 2017-09-28 9:40 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
don't need to check pp_valid, all pp
export functions are moved to ip_funcs
and pp_funcs. so just need to check the
function point.
Change-Id: Ib75cebece8fb9ebc7307f5d3cf084a813b5493db
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 +--
drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 3 ---
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index a0f08ec..94f85db 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -35,7 +35,7 @@ static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
static inline int pp_check(struct pp_instance *handle)
{
- if (handle == NULL || handle->pp_valid != PP_VALID)
+ if (handle == NULL)
return -EINVAL;
if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs == NULL ||
@@ -60,7 +60,6 @@ static int amd_powerplay_create(struct amd_pp_init *pp_init,
if (instance == NULL)
return -ENOMEM;
- instance->pp_valid = PP_VALID;
instance->chip_family = pp_init->chip_family;
instance->chip_id = pp_init->chip_id;
instance->pm_en = pp_init->pm_en;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
index 25fb146..7d1eec5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
@@ -25,10 +25,7 @@
#include "hwmgr.h"
-#define PP_VALID 0x1F1F1F1F
-
struct pp_instance {
- uint32_t pp_valid;
uint32_t chip_family;
uint32_t chip_id;
bool pm_en;
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* RE: [PATCH 3/3] drm/amd/powerplay: delete flag PP_VALID
[not found] ` <1506591633-5352-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-09-28 18:49 ` Deucher, Alexander
0 siblings, 0 replies; 4+ messages in thread
From: Deucher, Alexander @ 2017-09-28 18:49 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Zhu, Rex
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Rex Zhu
> Sent: Thursday, September 28, 2017 5:41 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhu, Rex
> Subject: [PATCH 3/3] drm/amd/powerplay: delete flag PP_VALID
>
> don't need to check pp_valid, all pp
> export functions are moved to ip_funcs
> and pp_funcs. so just need to check the
> function point.
>
> Change-Id: Ib75cebece8fb9ebc7307f5d3cf084a813b5493db
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 3 +--
> drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 3 ---
> 2 files changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index a0f08ec..94f85db 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -35,7 +35,7 @@ static int pp_dpm_dispatch_tasks(void *handle, enum
> amd_pp_task task_id,
>
> static inline int pp_check(struct pp_instance *handle)
> {
> - if (handle == NULL || handle->pp_valid != PP_VALID)
> + if (handle == NULL)
> return -EINVAL;
>
> if (handle->hwmgr == NULL || handle->hwmgr->smumgr_funcs ==
> NULL ||
> @@ -60,7 +60,6 @@ static int amd_powerplay_create(struct amd_pp_init
> *pp_init,
> if (instance == NULL)
> return -ENOMEM;
>
> - instance->pp_valid = PP_VALID;
> instance->chip_family = pp_init->chip_family;
> instance->chip_id = pp_init->chip_id;
> instance->pm_en = pp_init->pm_en;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> index 25fb146..7d1eec5 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/pp_instance.h
> @@ -25,10 +25,7 @@
>
> #include "hwmgr.h"
>
> -#define PP_VALID 0x1F1F1F1F
> -
> struct pp_instance {
> - uint32_t pp_valid;
> uint32_t chip_family;
> uint32_t chip_id;
> bool pm_en;
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-09-28 18:49 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-09-28 9:40 [PATCH 1/3] drm/amdgpu: move DC and PP shared data structures to dm_pp_interface.h Rex Zhu
[not found] ` <1506591633-5352-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-09-28 9:40 ` [PATCH 2/3] drm/amd/powerplay: move functions to amd_pm_funcs table Rex Zhu
2017-09-28 9:40 ` [PATCH 3/3] drm/amd/powerplay: delete flag PP_VALID Rex Zhu
[not found] ` <1506591633-5352-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-09-28 18:49 ` Deucher, Alexander
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