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From: Sagar Arun Kamble <sagar.a.kamble@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v2 05/11] drm/i915: Separate RPS and RC6 handling for CHV
Date: Fri,  6 Oct 2017 17:43:34 +0530	[thread overview]
Message-ID: <1507292020-14212-6-git-send-email-sagar.a.kamble@intel.com> (raw)
In-Reply-To: <1507292020-14212-1-git-send-email-sagar.a.kamble@intel.com>

This patch separates enable/disable of RC6 and RPS for CHV.

v2: Fixed comment.

Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++------
 1 file changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a55cee4..843fdc7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6343,11 +6343,16 @@ static void gen6_disable_rps(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN6_RP_CONTROL, 0);
 }
 
-static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
+static void cherryview_disable_rc6(struct drm_i915_private *dev_priv)
 {
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 }
 
+static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(GEN6_RP_CONTROL, 0);
+}
+
 static void valleyview_disable_rc6(struct drm_i915_private *dev_priv)
 {
 	/* We're doing forcewake before Disabling RC6,
@@ -7198,11 +7203,11 @@ static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
 	valleyview_cleanup_pctx(dev_priv);
 }
 
-static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
+static void cherryview_enable_rc6(struct drm_i915_private *dev_priv)
 {
 	struct intel_engine_cs *engine;
 	enum intel_engine_id id;
-	u32 gtfifodbg, val, rc6_mode = 0, pcbr;
+	u32 gtfifodbg, rc6_mode = 0, pcbr;
 
 	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 
@@ -7235,7 +7240,7 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 	/* TO threshold set to 500 us ( 0x186 * 1.28 us) */
 	I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
 
-	/* allows RC6 residency counter to work */
+	/* Allows RC6 residency counter to work */
 	I915_WRITE(VLV_COUNTER_CONTROL,
 		   _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
 				      VLV_MEDIA_RC6_COUNT_EN |
@@ -7251,7 +7256,18 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 
 	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
 
-	/* 4 Program defaults and thresholds for RPS*/
+	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+}
+
+static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
+
+	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+
+	/* 1: Program defaults and thresholds for RPS*/
 	I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
 	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
 	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
@@ -7260,7 +7276,7 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
 
 	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 
-	/* 5: Enable RPS */
+	/* 2: Enable RPS */
 	I915_WRITE(GEN6_RP_CONTROL,
 		   GEN6_RP_MEDIA_HW_NORMAL_MODE |
 		   GEN6_RP_MEDIA_IS_GFX |
@@ -7957,6 +7973,7 @@ void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 		gen9_disable_rc6(dev_priv);
 		gen9_disable_rps(dev_priv);
 	} else if (IS_CHERRYVIEW(dev_priv)) {
+		cherryview_disable_rc6(dev_priv);
 		cherryview_disable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_disable_rc6(dev_priv);
@@ -7987,6 +8004,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
 	mutex_lock(&dev_priv->rps.hw_lock);
 
 	if (IS_CHERRYVIEW(dev_priv)) {
+		cherryview_enable_rc6(dev_priv);
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rc6(dev_priv);
-- 
1.9.1

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  parent reply	other threads:[~2017-10-06 12:10 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-06 12:13 [PATCH v2 00/11] drm/i915: Separate RC6, RPS, LLC ring Frequency management Sagar Arun Kamble
2017-10-06 12:13 ` [PATCH v2 01/11] drm/i915: Separate RPS and RC6 handling for gen6+ Sagar Arun Kamble
2017-10-06 12:13 ` [PATCH v2 02/11] drm/i915: Remove superfluous IS_BDW checks and non-BDW changes from gen8_enable_rps Sagar Arun Kamble
2017-10-06 12:24   ` Chris Wilson
2017-10-06 12:13 ` [PATCH v2 03/11] drm/i915: Separate RPS and RC6 handling for BDW Sagar Arun Kamble
2017-10-06 12:13 ` [PATCH v2 04/11] drm/i915: Separate RPS and RC6 handling for VLV Sagar Arun Kamble
2017-10-06 12:13 ` Sagar Arun Kamble [this message]
2017-10-06 12:13 ` [PATCH v2 06/11] drm/i915: Name i915_runtime_pm structure in dev_priv as "rpm" Sagar Arun Kamble
2017-10-06 12:40   ` Chris Wilson
2017-10-06 15:00     ` Sagar Arun Kamble
2017-10-06 12:13 ` [PATCH v2 07/11] drm/i915: Name structure in dev_priv that contains RPS/RC6 state as "pm" Sagar Arun Kamble
2017-10-06 12:13 ` [PATCH v2 08/11] drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled Sagar Arun Kamble
2017-10-06 12:13 ` [PATCH v2 09/11] drm/i915: Create generic function to setup LLC ring frequency table Sagar Arun Kamble
2017-10-06 12:43   ` Chris Wilson
2017-10-06 12:13 ` [PATCH v2 10/11] drm/i915: Create generic functions to control RC6, RPS Sagar Arun Kamble
2017-10-06 12:46   ` Chris Wilson
2017-10-06 15:02     ` Sagar Arun Kamble
2017-10-06 12:13 ` [PATCH v2 11/11] drm/i915: Introduce separate status variable for RC6 and LLC ring frequency setup Sagar Arun Kamble
2017-10-06 12:55   ` Chris Wilson
2017-10-06 15:08     ` Sagar Arun Kamble
2017-10-06 14:10 ` ✓ Fi.CI.BAT: success for drm/i915: Separate RC6, RPS, LLC ring Frequency management Patchwork
2017-10-06 18:06 ` ✓ Fi.CI.IGT: " Patchwork

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