[PATCH 0/8] KFD SDMA support for GFX7 and GFX8 v2

[PATCH 0/8] KFD SDMA support for GFX7 and GFX8 v2

[Felix Kuehling]

This patch series fixes SDMA user mode queue support for GFX7 and adds
support for GFX8.

v2: Rebased. radeon_kfd.c doesn't exist any more.

Felix Kuehling (5):
  drm/amdgpu: Correct SDMA load/unload sequence on HWS disabled mode
  drm/amdkfd: Fix SDMA oversubsription handling
  drm/amd: Update kgd_kfd interface for resuming SDMA queues
  drm/amdgpu: Add support for resuming SDMA queues w/o HWS
  drm/amdkfd: Use ASIC-specific SDMA MQD type

Philip Cox (2):
  drm/amdgpu: Implement amdgpu SDMA functions for VI
  drm/amdkfd: Implement amdkfd SDMA functions for VI

shaoyunl (1):
  drm/amdkfd: Correct SDMA ring buffer size

 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  |  73 ++++++++++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  | 100 +++++++++++++++----
 drivers/gpu/drm/amd/amdgpu/vid.h                   |   2 +
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c   |  21 ++--
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c    | 108 ++++++++++++++++++++-
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h              |   2 -
 .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  18 ++++
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h    |   3 +-
 drivers/gpu/drm/amd/include/vi_structs.h           |   2 +
 9 files changed, 277 insertions(+), 52 deletions(-)

-- 
2.7.4

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[PATCH 1/8] drm/amdgpu: Correct SDMA load/unload sequence on HWS disabled mode

[Felix Kuehling]

Fix the SDMA load and unload sequence as suggested by HW document.

Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 47 ++++++++++++++++-------
 1 file changed, 34 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 47d1c13..1e3e9be 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -379,29 +379,50 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
 	struct cik_sdma_rlc_registers *m;
+	unsigned long end_jiffies;
 	uint32_t sdma_base_addr;
+	uint32_t data;
 
 	m = get_sdma_mqd(mqd);
 	sdma_base_addr = get_sdma_base_addr(m);
 
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
-			m->sdma_rlc_virtual_addr);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+		m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
 
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE,
-			m->sdma_rlc_rb_base);
+	end_jiffies = msecs_to_jiffies(2000) + jiffies;
+	while (true) {
+		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+			break;
+		if (time_after(jiffies, end_jiffies))
+			return -ETIME;
+		usleep_range(500, 1000);
+	}
+	if (m->sdma_engine_id) {
+		data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
+		data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
+				RESUME_CTX, 0);
+		WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
+	} else {
+		data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
+		data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+				RESUME_CTX, 0);
+		WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
+	}
 
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
+				m->sdma_rlc_doorbell);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
+				m->sdma_rlc_virtual_addr);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
 			m->sdma_rlc_rb_base_hi);
-
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
 			m->sdma_rlc_rb_rptr_addr_lo);
-
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 			m->sdma_rlc_rb_rptr_addr_hi);
-
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
-			m->sdma_rlc_doorbell);
-
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
 			m->sdma_rlc_rb_cntl);
 
@@ -574,9 +595,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 	}
 
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
 	return 0;
 }
-- 
2.7.4

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[PATCH 2/8] drm/amdkfd: Correct SDMA ring buffer size

[Felix Kuehling]

From: shaoyunl <Shaoyun.Liu@amd.com>

ffs function return the position of the first bit set on 1 based.
(bit zero returns 1).

Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index 4859d26..4728fad 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -202,8 +202,8 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 	struct cik_sdma_rlc_registers *m;
 
 	m = get_sdma_mqd(mqd);
-	m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) <<
-			SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
+	m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
+			<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 			q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
 			1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 			6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
-- 
2.7.4

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[PATCH 3/8] drm/amdkfd: Fix SDMA oversubsription handling

[Felix Kuehling]

SDMA only supports a fixed number of queues. HWS cannot handle
oversubscription.

Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
index 2bec902..a3f1e62 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
@@ -191,6 +191,24 @@ int pqm_create_queue(struct process_queue_manager *pqm,
 
 	switch (type) {
 	case KFD_QUEUE_TYPE_SDMA:
+		if (dev->dqm->queue_count >=
+			CIK_SDMA_QUEUES_PER_ENGINE * CIK_SDMA_ENGINE_NUM) {
+			pr_err("Over-subscription is not allowed for SDMA.\n");
+			retval = -EPERM;
+			goto err_create_queue;
+		}
+
+		retval = create_cp_queue(pqm, dev, &q, properties, f, *qid);
+		if (retval != 0)
+			goto err_create_queue;
+		pqn->q = q;
+		pqn->kq = NULL;
+		retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd,
+						&q->properties.vmid);
+		pr_debug("DQM returned %d for create_queue\n", retval);
+		print_queue(q);
+		break;
+
 	case KFD_QUEUE_TYPE_COMPUTE:
 		/* check if there is over subscription */
 		if ((sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
-- 
2.7.4

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[PATCH 4/8] drm/amd: Update kgd_kfd interface for resuming SDMA queues

[Felix Kuehling]

Add wptr and mm parameters to hqd_sdma_load and pass these parameters
from device_queue_manager through the mqd_manager.

SDMA doesn't support polling while the engine believes it's idle. The
driver must update the wptr. The new parameters will be used for looking
up the updated value from the specified mm when SDMA queues are resumed
after being disabled.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 6 ++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 6 ++++--
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c  | 4 +++-
 drivers/gpu/drm/amd/include/kgd_kfd_interface.h   | 3 ++-
 4 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index 1e3e9be..a55d794 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -105,7 +105,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 			uint32_t queue_id, uint32_t __user *wptr,
 			uint32_t wptr_shift, uint32_t wptr_mask,
 			struct mm_struct *mm);
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+			     uint32_t __user *wptr, struct mm_struct *mm);
 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 				uint32_t pipe_id, uint32_t queue_id);
 
@@ -375,7 +376,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 	return 0;
 }
 
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+			     uint32_t __user *wptr, struct mm_struct *mm)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
 	struct cik_sdma_rlc_registers *m;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 056929b..1017ff5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -64,7 +64,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 			uint32_t queue_id, uint32_t __user *wptr,
 			uint32_t wptr_shift, uint32_t wptr_mask,
 			struct mm_struct *mm);
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+			     uint32_t __user *wptr, struct mm_struct *mm);
 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 		uint32_t pipe_id, uint32_t queue_id);
 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
@@ -358,7 +359,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 	return 0;
 }
 
-static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
+static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
+			     uint32_t __user *wptr, struct mm_struct *mm)
 {
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index 4728fad..ea02bfa 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -160,7 +160,9 @@ static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
 			 uint32_t pipe_id, uint32_t queue_id,
 			 struct queue_properties *p, struct mm_struct *mms)
 {
-	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd);
+	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
+					       (uint32_t __user *)p->write_ptr,
+					       mms);
 }
 
 static int update_mqd(struct mqd_manager *mm, void *mqd,
diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
index f516fd1..c6d4e64 100644
--- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
@@ -184,7 +184,8 @@ struct kfd2kgd_calls {
 			uint32_t wptr_shift, uint32_t wptr_mask,
 			struct mm_struct *mm);
 
-	int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd);
+	int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
+			     uint32_t __user *wptr, struct mm_struct *mm);
 
 	bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
 				uint32_t pipe_id, uint32_t queue_id);
-- 
2.7.4

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[PATCH 5/8] drm/amdgpu: Add support for resuming SDMA queues w/o HWS

[Felix Kuehling]

Save wptr in hqd_sdma_destroy, restore it in hqd_sdma_load. Also
read updated wptr from user mode when resuming an SDMA queue.

Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 30 +++++++++++++++--------
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c |  9 ++++---
 2 files changed, 25 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index a55d794..14333af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -412,10 +412,17 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 		WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
 	}
 
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
-				m->sdma_rlc_doorbell);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
+	data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
+			     ENABLE, 1);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
+
+	if (read_user_wptr(mm, wptr, data))
+		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
+	else
+		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+		       m->sdma_rlc_rb_rptr);
+
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
 				m->sdma_rlc_virtual_addr);
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
@@ -425,8 +432,10 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 			m->sdma_rlc_rb_rptr_addr_lo);
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
 			m->sdma_rlc_rb_rptr_addr_hi);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
-			m->sdma_rlc_rb_cntl);
+
+	data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
+			     RB_ENABLE, 1);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
 
 	return 0;
 }
@@ -577,7 +586,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 	struct cik_sdma_rlc_registers *m;
 	uint32_t sdma_base_addr;
 	uint32_t temp;
-	int timeout = utimeout;
+	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 
 	m = get_sdma_mqd(mqd);
 	sdma_base_addr = get_sdma_base_addr(m);
@@ -590,10 +599,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 		if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
 			break;
-		if (timeout <= 0)
+		if (time_after(jiffies, end_jiffies))
 			return -ETIME;
-		msleep(20);
-		timeout -= 20;
+		usleep_range(500, 1000);
 	}
 
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
@@ -601,6 +609,8 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
 		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
+	m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 1017ff5..03c564d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -514,7 +514,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 	struct cik_sdma_rlc_registers *m;
 	uint32_t sdma_base_addr;
 	uint32_t temp;
-	int timeout = utimeout;
+	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
 
 	m = get_sdma_mqd(mqd);
 	sdma_base_addr = get_sdma_base_addr(m);
@@ -527,10 +527,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
 		if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
 			break;
-		if (timeout <= 0)
+		if (time_after(jiffies, end_jiffies))
 			return -ETIME;
-		msleep(20);
-		timeout -= 20;
+		usleep_range(500, 1000);
 	}
 
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
@@ -538,6 +537,8 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
 
+	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
+
 	return 0;
 }
 
-- 
2.7.4

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[PATCH 6/8] drm/amdgpu: Implement amdgpu SDMA functions for VI

[Felix Kuehling]

From: Philip Cox <Philip.Cox@amd.com>

Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 85 ++++++++++++++++++++---
 drivers/gpu/drm/amd/amdgpu/vid.h                  |  2 +
 drivers/gpu/drm/amd/include/vi_structs.h          |  2 +
 3 files changed, 78 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 03c564d..1d989e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -45,7 +45,7 @@ enum hqd_dequeue_request_type {
 	RESET_WAVES
 };
 
-struct cik_sdma_rlc_registers;
+struct vi_sdma_mqd;
 
 /*
  * Register access functions
@@ -269,9 +269,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
 	return 0;
 }
 
-static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
+static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
 {
-	return 0;
+	uint32_t retval;
+
+	retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
+		m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
+	pr_debug("kfd: sdma base address: 0x%x\n", retval);
+
+	return retval;
 }
 
 static inline struct vi_mqd *get_mqd(void *mqd)
@@ -279,9 +285,9 @@ static inline struct vi_mqd *get_mqd(void *mqd)
 	return (struct vi_mqd *)mqd;
 }
 
-static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
+static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
 {
-	return (struct cik_sdma_rlc_registers *)mqd;
+	return (struct vi_sdma_mqd *)mqd;
 }
 
 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
@@ -362,6 +368,63 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
 			     uint32_t __user *wptr, struct mm_struct *mm)
 {
+	struct amdgpu_device *adev = get_amdgpu_device(kgd);
+	struct vi_sdma_mqd *m;
+	unsigned long end_jiffies;
+	uint32_t sdma_base_addr;
+	uint32_t data;
+
+	m = get_sdma_mqd(mqd);
+	sdma_base_addr = get_sdma_base_addr(m);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+		m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
+
+	end_jiffies = msecs_to_jiffies(2000) + jiffies;
+	while (true) {
+		data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
+		if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
+			break;
+		if (time_after(jiffies, end_jiffies))
+			return -ETIME;
+		usleep_range(500, 1000);
+	}
+	if (m->sdma_engine_id) {
+		data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
+		data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
+				RESUME_CTX, 0);
+		WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
+	} else {
+		data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
+		data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
+				RESUME_CTX, 0);
+		WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
+	}
+
+	data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
+			     ENABLE, 1);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
+
+	if (read_user_wptr(mm, wptr, data))
+		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
+	else
+		WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
+		       m->sdmax_rlcx_rb_rptr);
+
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
+				m->sdmax_rlcx_virtual_addr);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
+			m->sdmax_rlcx_rb_base_hi);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
+			m->sdmax_rlcx_rb_rptr_addr_lo);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
+			m->sdmax_rlcx_rb_rptr_addr_hi);
+
+	data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
+			     RB_ENABLE, 1);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
+
 	return 0;
 }
 
@@ -390,7 +453,7 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-	struct cik_sdma_rlc_registers *m;
+	struct vi_sdma_mqd *m;
 	uint32_t sdma_base_addr;
 	uint32_t sdma_rlc_rb_cntl;
 
@@ -511,7 +574,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 				unsigned int utimeout)
 {
 	struct amdgpu_device *adev = get_amdgpu_device(kgd);
-	struct cik_sdma_rlc_registers *m;
+	struct vi_sdma_mqd *m;
 	uint32_t sdma_base_addr;
 	uint32_t temp;
 	unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
@@ -525,7 +588,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 
 	while (true) {
 		temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
-		if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
+		if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
 			break;
 		if (time_after(jiffies, end_jiffies))
 			return -ETIME;
@@ -533,9 +596,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
 	}
 
 	WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
-	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
+	WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
+		RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
+		SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
 
 	m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index dbf3703..19ddd23 100644
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -27,6 +27,8 @@
 #define SDMA1_REGISTER_OFFSET                             0x200 /* not a register */
 #define SDMA_MAX_INSTANCE 2
 
+#define KFD_VI_SDMA_QUEUE_OFFSET                      0x80 /* not a register */
+
 /* crtc instance offsets */
 #define CRTC0_REGISTER_OFFSET                 (0x1b9c - 0x1b9c)
 #define CRTC1_REGISTER_OFFSET                 (0x1d9c - 0x1b9c)
diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h
index 2023482..717fbae 100644
--- a/drivers/gpu/drm/amd/include/vi_structs.h
+++ b/drivers/gpu/drm/amd/include/vi_structs.h
@@ -153,6 +153,8 @@ struct vi_sdma_mqd {
 	uint32_t reserved_125;
 	uint32_t reserved_126;
 	uint32_t reserved_127;
+	uint32_t sdma_engine_id;
+	uint32_t sdma_queue_id;
 };
 
 struct vi_mqd {
-- 
2.7.4

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[PATCH 7/8] drm/amdkfd: Use ASIC-specific SDMA MQD type

[Felix Kuehling]

Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 13 +++++--------
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  |  5 +++++
 drivers/gpu/drm/amd/amdkfd/kfd_priv.h            |  2 --
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index ea02bfa..9873929 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -36,6 +36,11 @@ static inline struct cik_mqd *get_mqd(void *mqd)
 	return (struct cik_mqd *)mqd;
 }
 
+static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
+{
+	return (struct cik_sdma_rlc_registers *)mqd;
+}
+
 static int init_mqd(struct mqd_manager *mm, void **mqd,
 		struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
 		struct queue_properties *q)
@@ -362,14 +367,6 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
 	return 0;
 }
 
-struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
-{
-	struct cik_sdma_rlc_registers *m;
-
-	m = (struct cik_sdma_rlc_registers *)mqd;
-
-	return m;
-}
 
 struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
 		struct kfd_dev *dev)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index 4ea854f..dc92497 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -38,6 +38,11 @@ static inline struct vi_mqd *get_mqd(void *mqd)
 	return (struct vi_mqd *)mqd;
 }
 
+static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
+{
+	return (struct vi_sdma_mqd *)mqd;
+}
+
 static int init_mqd(struct mqd_manager *mm, void **mqd,
 			struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
 			struct queue_properties *q)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 9e4134c..4750473 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -643,8 +643,6 @@ int kgd2kfd_resume(struct kfd_dev *kfd);
 int kfd_init_apertures(struct kfd_process *process);
 
 /* Queue Context Management */
-struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd);
-
 int init_queue(struct queue **q, const struct queue_properties *properties);
 void uninit_queue(struct queue *q);
 void print_queue_properties(struct queue_properties *q);
-- 
2.7.4

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[PATCH 8/8] drm/amdkfd: Implement amdkfd SDMA functions for VI

[Felix Kuehling]

From: Philip Cox <Philip.Cox@amd.com>

Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 103 +++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index dc92497..a117d2b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -30,7 +30,7 @@
 #include "vi_structs.h"
 #include "gca/gfx_8_0_sh_mask.h"
 #include "gca/gfx_8_0_enum.h"
-
+#include "oss/oss_3_0_sh_mask.h"
 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
 
 static inline struct vi_mqd *get_mqd(void *mqd)
@@ -239,6 +239,101 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
 	return retval;
 }
 
+static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+		struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
+		struct queue_properties *q)
+{
+	int retval;
+	struct vi_sdma_mqd *m;
+
+
+	retval = kfd_gtt_sa_allocate(mm->dev,
+			sizeof(struct vi_sdma_mqd),
+			mqd_mem_obj);
+
+	if (retval != 0)
+		return -ENOMEM;
+
+	m = (struct vi_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr;
+
+	memset(m, 0, sizeof(struct vi_sdma_mqd));
+
+	*mqd = m;
+	if (gart_addr != NULL)
+		*gart_addr = (*mqd_mem_obj)->gpu_addr;
+
+	retval = mm->update_mqd(mm, m, q);
+
+	return retval;
+}
+
+static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
+		struct kfd_mem_obj *mqd_mem_obj)
+{
+	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
+}
+
+static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
+		uint32_t pipe_id, uint32_t queue_id,
+		struct queue_properties *p, struct mm_struct *mms)
+{
+	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
+					       (uint32_t __user *)p->write_ptr,
+					       mms);
+}
+
+static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
+		struct queue_properties *q)
+{
+	struct vi_sdma_mqd *m;
+
+	m = get_sdma_mqd(mqd);
+	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
+		<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
+		q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
+		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
+		6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
+
+	m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
+	m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
+	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
+	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
+	m->sdmax_rlcx_doorbell =
+		q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
+
+	m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
+
+	m->sdma_engine_id = q->sdma_engine_id;
+	m->sdma_queue_id = q->sdma_queue_id;
+
+	q->is_active = (q->queue_size > 0 &&
+			q->queue_address != 0 &&
+			q->queue_percent > 0);
+
+	return 0;
+}
+
+/*
+ *  * preempt type here is ignored because there is only one way
+ *  * to preempt sdma queue
+ */
+static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
+		enum kfd_preempt_type type,
+		unsigned int timeout, uint32_t pipe_id,
+		uint32_t queue_id)
+{
+	return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
+}
+
+static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
+		uint64_t queue_address, uint32_t pipe_id,
+		uint32_t queue_id)
+{
+	return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
+}
+
+
+
 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
 		struct kfd_dev *dev)
 {
@@ -272,6 +367,12 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
 		mqd->is_occupied = is_occupied;
 		break;
 	case KFD_MQD_TYPE_SDMA:
+		mqd->init_mqd = init_mqd_sdma;
+		mqd->uninit_mqd = uninit_mqd_sdma;
+		mqd->load_mqd = load_mqd_sdma;
+		mqd->update_mqd = update_mqd_sdma;
+		mqd->destroy_mqd = destroy_mqd_sdma;
+		mqd->is_occupied = is_occupied_sdma;
 		break;
 	default:
 		kfree(mqd);
-- 
2.7.4

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Re: [PATCH 2/8] drm/amdkfd: Correct SDMA ring buffer size

[Christian König]

Am 02.11.2017 um 00:21 schrieb Felix Kuehling:
> From: shaoyunl <Shaoyun.Liu@amd.com>
>
> ffs function return the position of the first bit set on 1 based.
> (bit zero returns 1).
>
> Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>   drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> index 4859d26..4728fad 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> @@ -202,8 +202,8 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
>   	struct cik_sdma_rlc_registers *m;
>   
>   	m = get_sdma_mqd(mqd);
> -	m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) <<
> -			SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
> +	m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
> +			<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>   			q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |

Usually we use order_base_2 for this. See cik_sdma.c for example:

rb_bufsz = order_base_2(ring->ring_size / 4);

Additional to that I won't expect that sizeof(unsigned int) is ever 
something else than 4 on any CPU that Linux supports, but that we need 
to divide the value by 4 is a programming detail of our hardware and not 
something dependent on the CPU/Compiler in use.

So I think using 4 over sizeof(unsigned int) is cleaner and easier to 
understand.

Regards,
Christian.

>   			1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
>   			6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;


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Re: [PATCH 1/8] drm/amdgpu: Correct SDMA load/unload sequence on HWS disabled mode

[Oded Gabbay]

On Thu, Nov 2, 2017 at 1:21 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> Fix the SDMA load and unload sequence as suggested by HW document.
>
> Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 47 ++++++++++++++++-------
>  1 file changed, 34 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> index 47d1c13..1e3e9be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> @@ -379,29 +379,50 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
>  {
>         struct amdgpu_device *adev = get_amdgpu_device(kgd);
>         struct cik_sdma_rlc_registers *m;
> +       unsigned long end_jiffies;
>         uint32_t sdma_base_addr;
> +       uint32_t data;
>
>         m = get_sdma_mqd(mqd);
>         sdma_base_addr = get_sdma_base_addr(m);
>
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
> -                       m->sdma_rlc_virtual_addr);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
> +               m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
>
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE,
> -                       m->sdma_rlc_rb_base);
> +       end_jiffies = msecs_to_jiffies(2000) + jiffies;
> +       while (true) {
> +               data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
> +               if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
> +                       break;
> +               if (time_after(jiffies, end_jiffies))
> +                       return -ETIME;
> +               usleep_range(500, 1000);
> +       }
> +       if (m->sdma_engine_id) {
> +               data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
> +               data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
> +                               RESUME_CTX, 0);
> +               WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
> +       } else {
> +               data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
> +               data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
> +                               RESUME_CTX, 0);
> +               WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
> +       }
>
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
> +                               m->sdma_rlc_doorbell);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
> +                               m->sdma_rlc_virtual_addr);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
>                         m->sdma_rlc_rb_base_hi);
> -
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
>                         m->sdma_rlc_rb_rptr_addr_lo);
> -
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
>                         m->sdma_rlc_rb_rptr_addr_hi);
> -
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
> -                       m->sdma_rlc_doorbell);
> -
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
>                         m->sdma_rlc_rb_cntl);
>
> @@ -574,9 +595,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>         }
>
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
> +               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
> +               SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
>
>         return 0;
>  }
> --
> 2.7.4
>

This patch is:
Acked-by: Oded Gabbay <oded.gabbay@gmail.com>
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Re: [PATCH 3/8] drm/amdkfd: Fix SDMA oversubsription handling

[Oded Gabbay]

On Thu, Nov 2, 2017 at 1:21 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> SDMA only supports a fixed number of queues. HWS cannot handle
> oversubscription.
>
> Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> index 2bec902..a3f1e62 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c
> @@ -191,6 +191,24 @@ int pqm_create_queue(struct process_queue_manager *pqm,
>
>         switch (type) {
>         case KFD_QUEUE_TYPE_SDMA:
> +               if (dev->dqm->queue_count >=
> +                       CIK_SDMA_QUEUES_PER_ENGINE * CIK_SDMA_ENGINE_NUM) {
> +                       pr_err("Over-subscription is not allowed for SDMA.\n");
> +                       retval = -EPERM;
> +                       goto err_create_queue;
> +               }
> +
> +               retval = create_cp_queue(pqm, dev, &q, properties, f, *qid);
> +               if (retval != 0)
> +                       goto err_create_queue;
> +               pqn->q = q;
> +               pqn->kq = NULL;
> +               retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd,
> +                                               &q->properties.vmid);
> +               pr_debug("DQM returned %d for create_queue\n", retval);
> +               print_queue(q);
> +               break;
> +
>         case KFD_QUEUE_TYPE_COMPUTE:
>                 /* check if there is over subscription */
>                 if ((sched_policy == KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
> --
> 2.7.4
>
This patch is:
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
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Re: [PATCH 4/8] drm/amd: Update kgd_kfd interface for resuming SDMA queues

[Oded Gabbay]

On Thu, Nov 2, 2017 at 1:21 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> Add wptr and mm parameters to hqd_sdma_load and pass these parameters
> from device_queue_manager through the mqd_manager.
>
> SDMA doesn't support polling while the engine believes it's idle. The
> driver must update the wptr. The new parameters will be used for looking
> up the updated value from the specified mm when SDMA queues are resumed
> after being disabled.
>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 6 ++++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 6 ++++--
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c  | 4 +++-
>  drivers/gpu/drm/amd/include/kgd_kfd_interface.h   | 3 ++-
>  4 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> index 1e3e9be..a55d794 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> @@ -105,7 +105,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>                         uint32_t queue_id, uint32_t __user *wptr,
>                         uint32_t wptr_shift, uint32_t wptr_mask,
>                         struct mm_struct *mm);
> -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
> +static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
> +                            uint32_t __user *wptr, struct mm_struct *mm);
>  static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
>                                 uint32_t pipe_id, uint32_t queue_id);
>
> @@ -375,7 +376,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>         return 0;
>  }
>
> -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
> +static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
> +                            uint32_t __user *wptr, struct mm_struct *mm)
>  {
>         struct amdgpu_device *adev = get_amdgpu_device(kgd);
>         struct cik_sdma_rlc_registers *m;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> index 056929b..1017ff5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> @@ -64,7 +64,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>                         uint32_t queue_id, uint32_t __user *wptr,
>                         uint32_t wptr_shift, uint32_t wptr_mask,
>                         struct mm_struct *mm);
> -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
> +static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
> +                            uint32_t __user *wptr, struct mm_struct *mm);
>  static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
>                 uint32_t pipe_id, uint32_t queue_id);
>  static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
> @@ -358,7 +359,8 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>         return 0;
>  }
>
> -static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
> +static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
> +                            uint32_t __user *wptr, struct mm_struct *mm)
>  {
>         return 0;
>  }
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> index 4728fad..ea02bfa 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> @@ -160,7 +160,9 @@ static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
>                          uint32_t pipe_id, uint32_t queue_id,
>                          struct queue_properties *p, struct mm_struct *mms)
>  {
> -       return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd);
> +       return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
> +                                              (uint32_t __user *)p->write_ptr,
> +                                              mms);
>  }
>
>  static int update_mqd(struct mqd_manager *mm, void *mqd,
> diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> index f516fd1..c6d4e64 100644
> --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h
> @@ -184,7 +184,8 @@ struct kfd2kgd_calls {
>                         uint32_t wptr_shift, uint32_t wptr_mask,
>                         struct mm_struct *mm);
>
> -       int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd);
> +       int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
> +                            uint32_t __user *wptr, struct mm_struct *mm);
>
>         bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
>                                 uint32_t pipe_id, uint32_t queue_id);
> --
> 2.7.4
>
This patch is:
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
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Re: [PATCH 2/8] drm/amdkfd: Correct SDMA ring buffer size

[Felix Kuehling]

On 2017-11-02 08:03 AM, Christian König wrote:
> Am 02.11.2017 um 00:21 schrieb Felix Kuehling:
>> From: shaoyunl <Shaoyun.Liu@amd.com>
>>
>> ffs function return the position of the first bit set on 1 based.
>> (bit zero returns 1).
>>
>> Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
>> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4 ++--
>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> index 4859d26..4728fad 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> @@ -202,8 +202,8 @@ static int update_mqd_sdma(struct mqd_manager
>> *mm, void *mqd,
>>       struct cik_sdma_rlc_registers *m;
>>         m = get_sdma_mqd(mqd);
>> -    m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) <<
>> -            SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>> +    m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int))
>> - 1)
>> +            << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>>               q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
>
> Usually we use order_base_2 for this. See cik_sdma.c for example:
>
> rb_bufsz = order_base_2(ring->ring_size / 4);
>
> Additional to that I won't expect that sizeof(unsigned int) is ever
> something else than 4 on any CPU that Linux supports, but that we need
> to divide the value by 4 is a programming detail of our hardware and
> not something dependent on the CPU/Compiler in use.
>
> So I think using 4 over sizeof(unsigned int) is cleaner and easier to
> understand.

Thanks for pointing those out. I'd address that with a separate cleanup
commit, because we're using ffs like this and dividing by sizeof(various
32-bit integer types) in a bunch more places.

Regards,
  Felix

>
> Regards,
> Christian.
>
>>               1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
>>               6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
>
>

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Re: [PATCH 5/8] drm/amdgpu: Add support for resuming SDMA queues w/o HWS

[Oded Gabbay]

On Thu, Nov 2, 2017 at 1:21 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> Save wptr in hqd_sdma_destroy, restore it in hqd_sdma_load. Also
> read updated wptr from user mode when resuming an SDMA queue.
>
> Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
> Signed-off-by: Yong Zhao <yong.zhao@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 30 +++++++++++++++--------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c |  9 ++++---
>  2 files changed, 25 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> index a55d794..14333af 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> @@ -412,10 +412,17 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
>                 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
>         }
>
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL,
> -                               m->sdma_rlc_doorbell);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
> +       data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL,
> +                            ENABLE, 1);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr);
> +
> +       if (read_user_wptr(mm, wptr, data))
> +               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
> +       else
> +               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
> +                      m->sdma_rlc_rb_rptr);
> +
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
>                                 m->sdma_rlc_virtual_addr);
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
> @@ -425,8 +432,10 @@ static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
>                         m->sdma_rlc_rb_rptr_addr_lo);
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
>                         m->sdma_rlc_rb_rptr_addr_hi);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
> -                       m->sdma_rlc_rb_cntl);
> +
> +       data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL,
> +                            RB_ENABLE, 1);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
>
>         return 0;
>  }
> @@ -577,7 +586,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>         struct cik_sdma_rlc_registers *m;
>         uint32_t sdma_base_addr;
>         uint32_t temp;
> -       int timeout = utimeout;
> +       unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
>
>         m = get_sdma_mqd(mqd);
>         sdma_base_addr = get_sdma_base_addr(m);
> @@ -590,10 +599,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
>                 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
>                         break;
> -               if (timeout <= 0)
> +               if (time_after(jiffies, end_jiffies))
>                         return -ETIME;
> -               msleep(20);
> -               timeout -= 20;
> +               usleep_range(500, 1000);
>         }
>
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
> @@ -601,6 +609,8 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>                 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
>                 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
>
> +       m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
> +
>         return 0;
>  }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> index 1017ff5..03c564d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> @@ -514,7 +514,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>         struct cik_sdma_rlc_registers *m;
>         uint32_t sdma_base_addr;
>         uint32_t temp;
> -       int timeout = utimeout;
> +       unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
>
>         m = get_sdma_mqd(mqd);
>         sdma_base_addr = get_sdma_base_addr(m);
> @@ -527,10 +527,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
>                 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
>                         break;
> -               if (timeout <= 0)
> +               if (time_after(jiffies, end_jiffies))
>                         return -ETIME;
> -               msleep(20);
> -               timeout -= 20;
> +               usleep_range(500, 1000);
>         }
>
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
> @@ -538,6 +537,8 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
>
> +       m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
> +
>         return 0;
>  }
>
> --
> 2.7.4
>

This patch is:
Acked-by: Oded Gabbay <oded.gabbay@gmail.com>
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Re: [PATCH 6/8] drm/amdgpu: Implement amdgpu SDMA functions for VI

[Oded Gabbay]

On Thu, Nov 2, 2017 at 1:22 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> From: Philip Cox <Philip.Cox@amd.com>
>
> Signed-off-by: Philip Cox <Philip.Cox@amd.com>
> Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
> Signed-off-by: Yong Zhao <yong.zhao@amd.com>
> Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 85 ++++++++++++++++++++---
>  drivers/gpu/drm/amd/amdgpu/vid.h                  |  2 +
>  drivers/gpu/drm/amd/include/vi_structs.h          |  2 +
>  3 files changed, 78 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> index 03c564d..1d989e4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> @@ -45,7 +45,7 @@ enum hqd_dequeue_request_type {
>         RESET_WAVES
>  };
>
> -struct cik_sdma_rlc_registers;
> +struct vi_sdma_mqd;
>
>  /*
>   * Register access functions
> @@ -269,9 +269,15 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
>         return 0;
>  }
>
> -static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
> +static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m)
>  {
> -       return 0;
> +       uint32_t retval;
> +
> +       retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET +
> +               m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET;
> +       pr_debug("kfd: sdma base address: 0x%x\n", retval);
> +
> +       return retval;
>  }
>
>  static inline struct vi_mqd *get_mqd(void *mqd)
> @@ -279,9 +285,9 @@ static inline struct vi_mqd *get_mqd(void *mqd)
>         return (struct vi_mqd *)mqd;
>  }
>
> -static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
> +static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
>  {
> -       return (struct cik_sdma_rlc_registers *)mqd;
> +       return (struct vi_sdma_mqd *)mqd;
>  }
>
>  static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
> @@ -362,6 +368,63 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>  static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd,
>                              uint32_t __user *wptr, struct mm_struct *mm)
>  {
> +       struct amdgpu_device *adev = get_amdgpu_device(kgd);
> +       struct vi_sdma_mqd *m;
> +       unsigned long end_jiffies;
> +       uint32_t sdma_base_addr;
> +       uint32_t data;
> +
> +       m = get_sdma_mqd(mqd);
> +       sdma_base_addr = get_sdma_base_addr(m);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
> +               m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK));
> +
> +       end_jiffies = msecs_to_jiffies(2000) + jiffies;
> +       while (true) {
> +               data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
> +               if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
> +                       break;
> +               if (time_after(jiffies, end_jiffies))
> +                       return -ETIME;
> +               usleep_range(500, 1000);
> +       }
> +       if (m->sdma_engine_id) {
> +               data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
> +               data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL,
> +                               RESUME_CTX, 0);
> +               WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);
> +       } else {
> +               data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
> +               data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL,
> +                               RESUME_CTX, 0);
> +               WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);
> +       }
> +
> +       data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL,
> +                            ENABLE, 1);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);
> +
> +       if (read_user_wptr(mm, wptr, data))
> +               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);
> +       else
> +               WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,
> +                      m->sdmax_rlcx_rb_rptr);
> +
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,
> +                               m->sdmax_rlcx_virtual_addr);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,
> +                       m->sdmax_rlcx_rb_base_hi);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
> +                       m->sdmax_rlcx_rb_rptr_addr_lo);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
> +                       m->sdmax_rlcx_rb_rptr_addr_hi);
> +
> +       data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL,
> +                            RB_ENABLE, 1);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);
> +
>         return 0;
>  }
>
> @@ -390,7 +453,7 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
>  static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
>  {
>         struct amdgpu_device *adev = get_amdgpu_device(kgd);
> -       struct cik_sdma_rlc_registers *m;
> +       struct vi_sdma_mqd *m;
>         uint32_t sdma_base_addr;
>         uint32_t sdma_rlc_rb_cntl;
>
> @@ -511,7 +574,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>                                 unsigned int utimeout)
>  {
>         struct amdgpu_device *adev = get_amdgpu_device(kgd);
> -       struct cik_sdma_rlc_registers *m;
> +       struct vi_sdma_mqd *m;
>         uint32_t sdma_base_addr;
>         uint32_t temp;
>         unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies;
> @@ -525,7 +588,7 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>
>         while (true) {
>                 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
> -               if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
> +               if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK)
>                         break;
>                 if (time_after(jiffies, end_jiffies))
>                         return -ETIME;
> @@ -533,9 +596,9 @@ static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
>         }
>
>         WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
> -       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
> +       WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,
> +               RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
> +               SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK);
>
>         m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
> index dbf3703..19ddd23 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vid.h
> +++ b/drivers/gpu/drm/amd/amdgpu/vid.h
> @@ -27,6 +27,8 @@
>  #define SDMA1_REGISTER_OFFSET                             0x200 /* not a register */
>  #define SDMA_MAX_INSTANCE 2
>
> +#define KFD_VI_SDMA_QUEUE_OFFSET                      0x80 /* not a register */
> +
>  /* crtc instance offsets */
>  #define CRTC0_REGISTER_OFFSET                 (0x1b9c - 0x1b9c)
>  #define CRTC1_REGISTER_OFFSET                 (0x1d9c - 0x1b9c)
> diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h
> index 2023482..717fbae 100644
> --- a/drivers/gpu/drm/amd/include/vi_structs.h
> +++ b/drivers/gpu/drm/amd/include/vi_structs.h
> @@ -153,6 +153,8 @@ struct vi_sdma_mqd {
>         uint32_t reserved_125;
>         uint32_t reserved_126;
>         uint32_t reserved_127;
> +       uint32_t sdma_engine_id;
> +       uint32_t sdma_queue_id;
>  };
>
>  struct vi_mqd {
> --
> 2.7.4
>

This patch is:
Acked-by: Oded Gabbay <oded.gabbay@gmail.com>
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Re: [PATCH 7/8] drm/amdkfd: Use ASIC-specific SDMA MQD type

[Oded Gabbay]

On Thu, Nov 2, 2017 at 1:22 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 13 +++++--------
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  |  5 +++++
>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h            |  2 --
>  3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> index ea02bfa..9873929 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> @@ -36,6 +36,11 @@ static inline struct cik_mqd *get_mqd(void *mqd)
>         return (struct cik_mqd *)mqd;
>  }
>
> +static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
> +{
> +       return (struct cik_sdma_rlc_registers *)mqd;
> +}
> +
>  static int init_mqd(struct mqd_manager *mm, void **mqd,
>                 struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
>                 struct queue_properties *q)
> @@ -362,14 +367,6 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
>         return 0;
>  }
>
> -struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
> -{
> -       struct cik_sdma_rlc_registers *m;
> -
> -       m = (struct cik_sdma_rlc_registers *)mqd;
> -
> -       return m;
> -}
>
>  struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type,
>                 struct kfd_dev *dev)
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> index 4ea854f..dc92497 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> @@ -38,6 +38,11 @@ static inline struct vi_mqd *get_mqd(void *mqd)
>         return (struct vi_mqd *)mqd;
>  }
>
> +static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
> +{
> +       return (struct vi_sdma_mqd *)mqd;
> +}
> +
>  static int init_mqd(struct mqd_manager *mm, void **mqd,
>                         struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
>                         struct queue_properties *q)
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> index 9e4134c..4750473 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
> @@ -643,8 +643,6 @@ int kgd2kfd_resume(struct kfd_dev *kfd);
>  int kfd_init_apertures(struct kfd_process *process);
>
>  /* Queue Context Management */
> -struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd);
> -
>  int init_queue(struct queue **q, const struct queue_properties *properties);
>  void uninit_queue(struct queue *q);
>  void print_queue_properties(struct queue_properties *q);
> --
> 2.7.4
>
This patch is:
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
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Re: [PATCH 8/8] drm/amdkfd: Implement amdkfd SDMA functions for VI

[Oded Gabbay]

On Thu, Nov 2, 2017 at 1:22 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> From: Philip Cox <Philip.Cox@amd.com>
>
> Signed-off-by: Philip Cox <Philip.Cox@amd.com>
> Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
> Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 103 +++++++++++++++++++++++-
>  1 file changed, 102 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> index dc92497..a117d2b 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> @@ -30,7 +30,7 @@
>  #include "vi_structs.h"
>  #include "gca/gfx_8_0_sh_mask.h"
>  #include "gca/gfx_8_0_enum.h"
> -
> +#include "oss/oss_3_0_sh_mask.h"
>  #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
>
>  static inline struct vi_mqd *get_mqd(void *mqd)
> @@ -239,6 +239,101 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
>         return retval;
>  }
>
> +static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
> +               struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
> +               struct queue_properties *q)
> +{
> +       int retval;
> +       struct vi_sdma_mqd *m;
> +
> +
> +       retval = kfd_gtt_sa_allocate(mm->dev,
> +                       sizeof(struct vi_sdma_mqd),
> +                       mqd_mem_obj);
> +
> +       if (retval != 0)
> +               return -ENOMEM;
> +
> +       m = (struct vi_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr;
> +
> +       memset(m, 0, sizeof(struct vi_sdma_mqd));
> +
> +       *mqd = m;
> +       if (gart_addr != NULL)
> +               *gart_addr = (*mqd_mem_obj)->gpu_addr;
> +
> +       retval = mm->update_mqd(mm, m, q);
> +
> +       return retval;
> +}
> +
> +static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
> +               struct kfd_mem_obj *mqd_mem_obj)
> +{
> +       kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
> +}
> +
> +static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
> +               uint32_t pipe_id, uint32_t queue_id,
> +               struct queue_properties *p, struct mm_struct *mms)
> +{
> +       return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
> +                                              (uint32_t __user *)p->write_ptr,
> +                                              mms);
> +}
> +
> +static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
> +               struct queue_properties *q)
> +{
> +       struct vi_sdma_mqd *m;
> +
> +       m = get_sdma_mqd(mqd);
> +       m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
> +               << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
> +               q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
> +               1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
> +               6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
> +
> +       m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
> +       m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
> +       m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
> +       m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
> +       m->sdmax_rlcx_doorbell =
> +               q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
> +
> +       m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
> +
> +       m->sdma_engine_id = q->sdma_engine_id;
> +       m->sdma_queue_id = q->sdma_queue_id;
> +
> +       q->is_active = (q->queue_size > 0 &&
> +                       q->queue_address != 0 &&
> +                       q->queue_percent > 0);
> +
> +       return 0;
> +}
> +
> +/*
> + *  * preempt type here is ignored because there is only one way
> + *  * to preempt sdma queue
> + */
> +static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
> +               enum kfd_preempt_type type,
> +               unsigned int timeout, uint32_t pipe_id,
> +               uint32_t queue_id)
> +{
> +       return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
> +}
> +
> +static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
> +               uint64_t queue_address, uint32_t pipe_id,
> +               uint32_t queue_id)
> +{
> +       return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
> +}
> +
> +
> +
>  struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
>                 struct kfd_dev *dev)
>  {
> @@ -272,6 +367,12 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
>                 mqd->is_occupied = is_occupied;
>                 break;
>         case KFD_MQD_TYPE_SDMA:
> +               mqd->init_mqd = init_mqd_sdma;
> +               mqd->uninit_mqd = uninit_mqd_sdma;
> +               mqd->load_mqd = load_mqd_sdma;
> +               mqd->update_mqd = update_mqd_sdma;
> +               mqd->destroy_mqd = destroy_mqd_sdma;
> +               mqd->is_occupied = is_occupied_sdma;
>                 break;
>         default:
>                 kfree(mqd);
> --
> 2.7.4
>
This patch is:
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
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Re: [PATCH 0/8] KFD SDMA support for GFX7 and GFX8 v2

[Oded Gabbay]

Thanks!
Taken to -next, but it will only be for 4.16 I'm afraid

On Thu, Nov 2, 2017 at 1:21 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> This patch series fixes SDMA user mode queue support for GFX7 and adds
> support for GFX8.
>
> v2: Rebased. radeon_kfd.c doesn't exist any more.
>
> Felix Kuehling (5):
>   drm/amdgpu: Correct SDMA load/unload sequence on HWS disabled mode
>   drm/amdkfd: Fix SDMA oversubsription handling
>   drm/amd: Update kgd_kfd interface for resuming SDMA queues
>   drm/amdgpu: Add support for resuming SDMA queues w/o HWS
>   drm/amdkfd: Use ASIC-specific SDMA MQD type
>
> Philip Cox (2):
>   drm/amdgpu: Implement amdgpu SDMA functions for VI
>   drm/amdkfd: Implement amdkfd SDMA functions for VI
>
> shaoyunl (1):
>   drm/amdkfd: Correct SDMA ring buffer size
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  |  73 ++++++++++----
>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  | 100 +++++++++++++++----
>  drivers/gpu/drm/amd/amdgpu/vid.h                   |   2 +
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c   |  21 ++--
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c    | 108 ++++++++++++++++++++-
>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h              |   2 -
>  .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  18 ++++
>  drivers/gpu/drm/amd/include/kgd_kfd_interface.h    |   3 +-
>  drivers/gpu/drm/amd/include/vi_structs.h           |   2 +
>  9 files changed, 277 insertions(+), 52 deletions(-)
>
> --
> 2.7.4
>
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Re: [PATCH 2/8] drm/amdkfd: Correct SDMA ring buffer size

[Oded Gabbay]

On Thu, Nov 2, 2017 at 1:21 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
> From: shaoyunl <Shaoyun.Liu@amd.com>
>
> ffs function return the position of the first bit set on 1 based.
> (bit zero returns 1).
>
> Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> index 4859d26..4728fad 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> @@ -202,8 +202,8 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
>         struct cik_sdma_rlc_registers *m;
>
>         m = get_sdma_mqd(mqd);
> -       m->sdma_rlc_rb_cntl = ffs(q->queue_size / sizeof(unsigned int)) <<
> -                       SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
> +       m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
> +                       << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>                         q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
>                         1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
>                         6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
> --
> 2.7.4
>

As Felix promised a cleanup later for all the sizeof(unsigned int)
things, this patch is:
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
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Re: [PATCH 0/8] KFD SDMA support for GFX7 and GFX8 v2

[Felix Kuehling]

Thanks.

I've given up on targeting a specific kernel release. This whole
upstreaming process is way more work than I expected, and is taking much
longer than I thought when I started. If I'm making this harder for
myself than necessary, please let me know. But I'm quite sure that this
is just the cost of turning our messy history into something sensible
and reviewable.

For example, most of the SDMA work was originally done after adding dGPU
support. Also, much of it was done on GFX8 first and later ported back
to GFX7. However, to make more sense for upstreaming and to avoid
duplicate reviews, I reordered the history to fix GFX7 first and
introduce GFX8 support in its final, fixed form.

In that sense, SDMA support is a recursive mini-instance of what I'm
doing with dGPU support. Many of the fixes and cleanups I have already
upstreamed were originally done on top of (or rather in the middle of)
dGPU support. I had to disentangle all of that to upstream the changes
that are applicable to CZ and KV, so that I can eventually upstream dGPU
support in its final form, skipping all the broken intermediate steps,
with all the hind-sight we have gained in the mean time.

Looking at the work that's left to do, and the likely feedback I'll get
when I get to the dGPU memory management parts, this is going to take
months, not weeks, until most of KFD is upstream. Especially if I also
want to rebase/upstream our libhsakmt and open-source KFDTest. Maybe I
can delegate some of this ...

Regards,
  Felix


On 2017-11-02 11:04 AM, Oded Gabbay wrote:
> Thanks!
> Taken to -next, but it will only be for 4.16 I'm afraid
>
> On Thu, Nov 2, 2017 at 1:21 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
>> This patch series fixes SDMA user mode queue support for GFX7 and adds
>> support for GFX8.
>>
>> v2: Rebased. radeon_kfd.c doesn't exist any more.
>>
>> Felix Kuehling (5):
>>   drm/amdgpu: Correct SDMA load/unload sequence on HWS disabled mode
>>   drm/amdkfd: Fix SDMA oversubsription handling
>>   drm/amd: Update kgd_kfd interface for resuming SDMA queues
>>   drm/amdgpu: Add support for resuming SDMA queues w/o HWS
>>   drm/amdkfd: Use ASIC-specific SDMA MQD type
>>
>> Philip Cox (2):
>>   drm/amdgpu: Implement amdgpu SDMA functions for VI
>>   drm/amdkfd: Implement amdkfd SDMA functions for VI
>>
>> shaoyunl (1):
>>   drm/amdkfd: Correct SDMA ring buffer size
>>
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  |  73 ++++++++++----
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  | 100 +++++++++++++++----
>>  drivers/gpu/drm/amd/amdgpu/vid.h                   |   2 +
>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c   |  21 ++--
>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c    | 108 ++++++++++++++++++++-
>>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h              |   2 -
>>  .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  18 ++++
>>  drivers/gpu/drm/amd/include/kgd_kfd_interface.h    |   3 +-
>>  drivers/gpu/drm/amd/include/vi_structs.h           |   2 +
>>  9 files changed, 277 insertions(+), 52 deletions(-)
>>
>> --
>> 2.7.4
>>

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Re: [PATCH 0/8] KFD SDMA support for GFX7 and GFX8 v2

[Oded Gabbay]

On Thu, Nov 2, 2017 at 5:22 PM, Felix Kuehling <felix.kuehling@amd.com> wrote:
> Thanks.
>
> I've given up on targeting a specific kernel release. This whole
> upstreaming process is way more work than I expected, and is taking much
> longer than I thought when I started. If I'm making this harder for
> myself than necessary, please let me know. But I'm quite sure that this
> is just the cost of turning our messy history into something sensible
> and reviewable.
>
I feel your pain, but I honestly think this is the price of not
keeping the upstream driver synced with the internal development for
the last 2.5 years.
I also think that without the great work you are doing, the code would
never get upstreamed, so I encourage you to keep it up :)
Oded


> For example, most of the SDMA work was originally done after adding dGPU
> support. Also, much of it was done on GFX8 first and later ported back
> to GFX7. However, to make more sense for upstreaming and to avoid
> duplicate reviews, I reordered the history to fix GFX7 first and
> introduce GFX8 support in its final, fixed form.
>
> In that sense, SDMA support is a recursive mini-instance of what I'm
> doing with dGPU support. Many of the fixes and cleanups I have already
> upstreamed were originally done on top of (or rather in the middle of)
> dGPU support. I had to disentangle all of that to upstream the changes
> that are applicable to CZ and KV, so that I can eventually upstream dGPU
> support in its final form, skipping all the broken intermediate steps,
> with all the hind-sight we have gained in the mean time.
>
> Looking at the work that's left to do, and the likely feedback I'll get
> when I get to the dGPU memory management parts, this is going to take
> months, not weeks, until most of KFD is upstream. Especially if I also
> want to rebase/upstream our libhsakmt and open-source KFDTest. Maybe I
> can delegate some of this ...
>
> Regards,
>   Felix
>
>
> On 2017-11-02 11:04 AM, Oded Gabbay wrote:
>> Thanks!
>> Taken to -next, but it will only be for 4.16 I'm afraid
>>
>> On Thu, Nov 2, 2017 at 1:21 AM, Felix Kuehling <Felix.Kuehling@amd.com> wrote:
>>> This patch series fixes SDMA user mode queue support for GFX7 and adds
>>> support for GFX8.
>>>
>>> v2: Rebased. radeon_kfd.c doesn't exist any more.
>>>
>>> Felix Kuehling (5):
>>>   drm/amdgpu: Correct SDMA load/unload sequence on HWS disabled mode
>>>   drm/amdkfd: Fix SDMA oversubsription handling
>>>   drm/amd: Update kgd_kfd interface for resuming SDMA queues
>>>   drm/amdgpu: Add support for resuming SDMA queues w/o HWS
>>>   drm/amdkfd: Use ASIC-specific SDMA MQD type
>>>
>>> Philip Cox (2):
>>>   drm/amdgpu: Implement amdgpu SDMA functions for VI
>>>   drm/amdkfd: Implement amdkfd SDMA functions for VI
>>>
>>> shaoyunl (1):
>>>   drm/amdkfd: Correct SDMA ring buffer size
>>>
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c  |  73 ++++++++++----
>>>  drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c  | 100 +++++++++++++++----
>>>  drivers/gpu/drm/amd/amdgpu/vid.h                   |   2 +
>>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c   |  21 ++--
>>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c    | 108 ++++++++++++++++++++-
>>>  drivers/gpu/drm/amd/amdkfd/kfd_priv.h              |   2 -
>>>  .../gpu/drm/amd/amdkfd/kfd_process_queue_manager.c |  18 ++++
>>>  drivers/gpu/drm/amd/include/kgd_kfd_interface.h    |   3 +-
>>>  drivers/gpu/drm/amd/include/vi_structs.h           |   2 +
>>>  9 files changed, 277 insertions(+), 52 deletions(-)
>>>
>>> --
>>> 2.7.4
>>>
>
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[PATCH 8/8] drm/amdkfd: Implement amdkfd SDMA functions for VI

[Felix Kuehling]

From: Philip Cox <Philip.Cox@amd.com>

Signed-off-by: Philip Cox <Philip.Cox@amd.com>
Signed-off-by: shaoyun liu <shaoyun.liu@amd.com>
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 103 +++++++++++++++++++++++-
 1 file changed, 102 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index dc92497..a117d2b 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -30,7 +30,7 @@
 #include "vi_structs.h"
 #include "gca/gfx_8_0_sh_mask.h"
 #include "gca/gfx_8_0_enum.h"
-
+#include "oss/oss_3_0_sh_mask.h"
 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
 
 static inline struct vi_mqd *get_mqd(void *mqd)
@@ -239,6 +239,101 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
 	return retval;
 }
 
+static int init_mqd_sdma(struct mqd_manager *mm, void **mqd,
+		struct kfd_mem_obj **mqd_mem_obj, uint64_t *gart_addr,
+		struct queue_properties *q)
+{
+	int retval;
+	struct vi_sdma_mqd *m;
+
+
+	retval = kfd_gtt_sa_allocate(mm->dev,
+			sizeof(struct vi_sdma_mqd),
+			mqd_mem_obj);
+
+	if (retval != 0)
+		return -ENOMEM;
+
+	m = (struct vi_sdma_mqd *) (*mqd_mem_obj)->cpu_ptr;
+
+	memset(m, 0, sizeof(struct vi_sdma_mqd));
+
+	*mqd = m;
+	if (gart_addr != NULL)
+		*gart_addr = (*mqd_mem_obj)->gpu_addr;
+
+	retval = mm->update_mqd(mm, m, q);
+
+	return retval;
+}
+
+static void uninit_mqd_sdma(struct mqd_manager *mm, void *mqd,
+		struct kfd_mem_obj *mqd_mem_obj)
+{
+	kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
+}
+
+static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
+		uint32_t pipe_id, uint32_t queue_id,
+		struct queue_properties *p, struct mm_struct *mms)
+{
+	return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
+					       (uint32_t __user *)p->write_ptr,
+					       mms);
+}
+
+static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
+		struct queue_properties *q)
+{
+	struct vi_sdma_mqd *m;
+
+	m = get_sdma_mqd(mqd);
+	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
+		<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
+		q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
+		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
+		6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
+
+	m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
+	m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
+	m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
+	m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
+	m->sdmax_rlcx_doorbell =
+		q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
+
+	m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
+
+	m->sdma_engine_id = q->sdma_engine_id;
+	m->sdma_queue_id = q->sdma_queue_id;
+
+	q->is_active = (q->queue_size > 0 &&
+			q->queue_address != 0 &&
+			q->queue_percent > 0);
+
+	return 0;
+}
+
+/*
+ *  * preempt type here is ignored because there is only one way
+ *  * to preempt sdma queue
+ */
+static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
+		enum kfd_preempt_type type,
+		unsigned int timeout, uint32_t pipe_id,
+		uint32_t queue_id)
+{
+	return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
+}
+
+static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
+		uint64_t queue_address, uint32_t pipe_id,
+		uint32_t queue_id)
+{
+	return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
+}
+
+
+
 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
 		struct kfd_dev *dev)
 {
@@ -272,6 +367,12 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
 		mqd->is_occupied = is_occupied;
 		break;
 	case KFD_MQD_TYPE_SDMA:
+		mqd->init_mqd = init_mqd_sdma;
+		mqd->uninit_mqd = uninit_mqd_sdma;
+		mqd->load_mqd = load_mqd_sdma;
+		mqd->update_mqd = update_mqd_sdma;
+		mqd->destroy_mqd = destroy_mqd_sdma;
+		mqd->is_occupied = is_occupied_sdma;
 		break;
 	default:
 		kfree(mqd);
-- 
2.7.4

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