[Qemu-devel] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads

[Qemu-devel] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads

[Peter Maydell]

Fix an incorrect mask expression in the handling of v7M MPU_RBAR
reads that meant that we would always report the ADDR field as zero.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Doesn't affect v8M, which is a different codepath.

 hw/intc/armv7m_nvic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index be46639..5d9c883 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -977,7 +977,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
         if (region >= cpu->pmsav7_dregion) {
             return 0;
         }
-        return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
+        return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf);
     }
     case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
     case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
-- 
2.7.4

Re: [Qemu-devel] [Qemu-arm] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads

[Alex Bennée]

Peter Maydell <peter.maydell@linaro.org> writes:

> Fix an incorrect mask expression in the handling of v7M MPU_RBAR
> reads that meant that we would always report the ADDR field as zero.

nit: you could extend that to: "..as zero because we mask it when
written".

As I see you do:
  cpu->env.pmsav7.drbar[region] = value & ~0x1f;

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Doesn't affect v8M, which is a different codepath.
>
>  hw/intc/armv7m_nvic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index be46639..5d9c883 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -977,7 +977,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
>          if (region >= cpu->pmsav7_dregion) {
>              return 0;
>          }
> -        return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf);
> +        return (cpu->env.pmsav7.drbar[region] & ~0x1f) | (region & 0xf);
>      }
>      case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
>      case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */


--
Alex Bennée

Re: [Qemu-devel] [Qemu-arm] [PATCH] nvic: Fix ARMv7M MPU_RBAR reads

[Peter Maydell]

On 6 November 2017 at 16:20, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> Peter Maydell <peter.maydell@linaro.org> writes:
>
>> Fix an incorrect mask expression in the handling of v7M MPU_RBAR
>> reads that meant that we would always report the ADDR field as zero.
>
> nit: you could extend that to: "..as zero because we mask it when
> written".

The ADDR field is bits [31:5], so it's true even if we don't
mask on writes.

thanks
-- PMM