[PATCH 1/2] drm/amdkfd: Hardware DWORD size is 4 bytes

[PATCH 1/2] drm/amdkfd: Hardware DWORD size is 4 bytes

[Felix Kuehling]

Don't use sizeof(uint32_t) or similar types for hardware or firmware
DWORD size. The hardware and firmware don't care about Linux types.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c          | 14 +++++---------
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c    |  2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 10 ++++------
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  |  9 ++++-----
 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c  |  2 +-
 5 files changed, 15 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
index c407f6b..afb26f2 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c
@@ -95,7 +95,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
 	ib_packet->bitfields3.ib_base_hi = largep->u.high_part;
 
 	ib_packet->control = (1 << 23) | (1 << 31) |
-			((size_in_bytes / sizeof(uint32_t)) & 0xfffff);
+			((size_in_bytes / 4) & 0xfffff);
 
 	ib_packet->bitfields5.pasid = pasid;
 
@@ -126,8 +126,7 @@ static int dbgdev_diq_submit_ib(struct kfd_dbgdev *dbgdev,
 
 	rm_packet->header.opcode = IT_RELEASE_MEM;
 	rm_packet->header.type = PM4_TYPE_3;
-	rm_packet->header.count = sizeof(struct pm4__release_mem) /
-					sizeof(unsigned int) - 2;
+	rm_packet->header.count = sizeof(struct pm4__release_mem) / 4 - 2;
 
 	rm_packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
 	rm_packet->bitfields2.event_index =
@@ -652,8 +651,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
 	packets_vec[0].header.opcode = IT_SET_UCONFIG_REG;
 	packets_vec[0].header.type = PM4_TYPE_3;
 	packets_vec[0].bitfields2.reg_offset =
-			GRBM_GFX_INDEX / (sizeof(uint32_t)) -
-				USERCONFIG_REG_BASE;
+			GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE;
 
 	packets_vec[0].bitfields2.insert_vmid = 0;
 	packets_vec[0].reg_data[0] = reg_gfx_index.u32All;
@@ -661,8 +659,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
 	packets_vec[1].header.count = 1;
 	packets_vec[1].header.opcode = IT_SET_CONFIG_REG;
 	packets_vec[1].header.type = PM4_TYPE_3;
-	packets_vec[1].bitfields2.reg_offset = SQ_CMD / (sizeof(uint32_t)) -
-						AMD_CONFIG_REG_BASE;
+	packets_vec[1].bitfields2.reg_offset = SQ_CMD / 4 - AMD_CONFIG_REG_BASE;
 
 	packets_vec[1].bitfields2.vmid_shift = SQ_CMD_VMID_OFFSET;
 	packets_vec[1].bitfields2.insert_vmid = 1;
@@ -678,8 +675,7 @@ static int dbgdev_wave_control_diq(struct kfd_dbgdev *dbgdev,
 
 	packets_vec[2].ordinal1 = packets_vec[0].ordinal1;
 	packets_vec[2].bitfields2.reg_offset =
-				GRBM_GFX_INDEX / (sizeof(uint32_t)) -
-					USERCONFIG_REG_BASE;
+				GRBM_GFX_INDEX / 4 - USERCONFIG_REG_BASE;
 
 	packets_vec[2].bitfields2.insert_vmid = 0;
 	packets_vec[2].reg_data[0] = reg_gfx_index.u32All;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
index 8b0c064..5dc6567 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c
@@ -218,7 +218,7 @@ static int acquire_packet_buffer(struct kernel_queue *kq,
 	rptr = *kq->rptr_kernel;
 	wptr = *kq->wptr_kernel;
 	queue_address = (unsigned int *)kq->pq_kernel_addr;
-	queue_size_dwords = kq->queue->properties.queue_size / sizeof(uint32_t);
+	queue_size_dwords = kq->queue->properties.queue_size / 4;
 
 	pr_debug("rptr: %d\n", rptr);
 	pr_debug("wptr: %d\n", wptr);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index 9873929..efed6ef 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -154,7 +154,7 @@ static int load_mqd(struct mqd_manager *mm, void *mqd, uint32_t pipe_id,
 {
 	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
 	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
-	uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1);
+	uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
 
 	return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
 					  (uint32_t __user *)p->write_ptr,
@@ -183,8 +183,7 @@ static int update_mqd(struct mqd_manager *mm, void *mqd,
 	 * Calculating queue size which is log base 2 of actual queue size -1
 	 * dwords and another -1 for ffs
 	 */
-	m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int))
-								- 1 - 1;
+	m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
 	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
 	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
@@ -209,7 +208,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 	struct cik_sdma_rlc_registers *m;
 
 	m = get_sdma_mqd(mqd);
-	m->sdma_rlc_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
+	m->sdma_rlc_rb_cntl = (ffs(q->queue_size / 4) - 1)
 			<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 			q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
 			1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
@@ -350,8 +349,7 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
 	 * Calculating queue size which is log base 2 of actual queue
 	 * size -1 dwords
 	 */
-	m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int))
-								- 1 - 1;
+	m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
 	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
 	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index a117d2b..85e1b67 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -103,7 +103,7 @@ static int load_mqd(struct mqd_manager *mm, void *mqd,
 {
 	/* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
 	uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
-	uint32_t wptr_mask = (uint32_t)((p->queue_size / sizeof(uint32_t)) - 1);
+	uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
 
 	return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
 					  (uint32_t __user *)p->write_ptr,
@@ -121,8 +121,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd,
 	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
 			atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
 			mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
-	m->cp_hqd_pq_control |=
-			ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1;
+	m->cp_hqd_pq_control |=	ffs(q->queue_size / 4) - 1 - 1;
 	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
 
 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
@@ -152,7 +151,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd,
 	 * is safe, giving a maximum field value of 0xA.
 	 */
 	m->cp_hqd_eop_control |= min(0xA,
-		ffs(q->eop_ring_buffer_size / sizeof(unsigned int)) - 1 - 1);
+		ffs(q->eop_ring_buffer_size / 4) - 1 - 1);
 	m->cp_hqd_eop_base_addr_lo =
 			lower_32_bits(q->eop_ring_buffer_address >> 8);
 	m->cp_hqd_eop_base_addr_hi =
@@ -288,7 +287,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 	struct vi_sdma_mqd *m;
 
 	m = get_sdma_mqd(mqd);
-	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / sizeof(unsigned int)) - 1)
+	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1)
 		<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 		q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
 		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
index 16da8ad..69c147a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c
@@ -45,7 +45,7 @@ static unsigned int build_pm4_header(unsigned int opcode, size_t packet_size)
 
 	header.u32All = 0;
 	header.opcode = opcode;
-	header.count = packet_size/sizeof(uint32_t) - 2;
+	header.count = packet_size / 4 - 2;
 	header.type = PM4_TYPE_3;
 
 	return header.u32All;
-- 
2.7.4

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[PATCH 2/2] drm/amdkfd: Use order_base_2 to get log2 of buffes sizes

[Felix Kuehling]

Replace (ffs(size) - 1) with order_base_2(size) as a more straight
forward way to get log2 of buffer sizes.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 6 +++---
 drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
index efed6ef..7aa57ab 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
@@ -183,7 +183,7 @@ static int update_mqd(struct mqd_manager *mm, void *mqd,
 	 * Calculating queue size which is log base 2 of actual queue size -1
 	 * dwords and another -1 for ffs
 	 */
-	m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
+	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
 	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
 	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
@@ -208,7 +208,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 	struct cik_sdma_rlc_registers *m;
 
 	m = get_sdma_mqd(mqd);
-	m->sdma_rlc_rb_cntl = (ffs(q->queue_size / 4) - 1)
+	m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
 			<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 			q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
 			1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
@@ -349,7 +349,7 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd,
 	 * Calculating queue size which is log base 2 of actual queue
 	 * size -1 dwords
 	 */
-	m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
+	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
 	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
 	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
index 85e1b67..2ba7cea 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
@@ -121,7 +121,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd,
 	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
 			atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
 			mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
-	m->cp_hqd_pq_control |=	ffs(q->queue_size / 4) - 1 - 1;
+	m->cp_hqd_pq_control |=	order_base_2(q->queue_size / 4) - 1;
 	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
 
 	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
@@ -151,7 +151,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd,
 	 * is safe, giving a maximum field value of 0xA.
 	 */
 	m->cp_hqd_eop_control |= min(0xA,
-		ffs(q->eop_ring_buffer_size / 4) - 1 - 1);
+		order_base_2(q->eop_ring_buffer_size / 4) - 1);
 	m->cp_hqd_eop_base_addr_lo =
 			lower_32_bits(q->eop_ring_buffer_address >> 8);
 	m->cp_hqd_eop_base_addr_hi =
@@ -287,7 +287,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd,
 	struct vi_sdma_mqd *m;
 
 	m = get_sdma_mqd(mqd);
-	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1)
+	m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
 		<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
 		q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
 		1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
-- 
2.7.4

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RE: [PATCH 2/2] drm/amdkfd: Use order_base_2 to get log2 of buffes sizes

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Felix Kuehling
> Sent: Monday, November 06, 2017 2:52 PM
> To: amd-gfx@lists.freedesktop.org; oded.gabbay@gmail.com
> Cc: Kuehling, Felix
> Subject: [PATCH 2/2] drm/amdkfd: Use order_base_2 to get log2 of buffes
> sizes
> 
> Replace (ffs(size) - 1) with order_base_2(size) as a more straight
> forward way to get log2 of buffer sizes.
> 
> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 6 +++---
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  | 6 +++---
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> index efed6ef..7aa57ab 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
> @@ -183,7 +183,7 @@ static int update_mqd(struct mqd_manager *mm,
> void *mqd,
>  	 * Calculating queue size which is log base 2 of actual queue size -1
>  	 * dwords and another -1 for ffs
>  	 */
> -	m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
> +	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
>  	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
> >queue_address >> 8);
>  	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q-
> >queue_address >> 8);
>  	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q-
> >read_ptr);
> @@ -208,7 +208,7 @@ static int update_mqd_sdma(struct mqd_manager
> *mm, void *mqd,
>  	struct cik_sdma_rlc_registers *m;
> 
>  	m = get_sdma_mqd(mqd);
> -	m->sdma_rlc_rb_cntl = (ffs(q->queue_size / 4) - 1)
> +	m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
>  			<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>  			q->vmid <<
> SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
>  			1 <<
> SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
> @@ -349,7 +349,7 @@ static int update_mqd_hiq(struct mqd_manager
> *mm, void *mqd,
>  	 * Calculating queue size which is log base 2 of actual queue
>  	 * size -1 dwords
>  	 */
> -	m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
> +	m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
>  	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
> >queue_address >> 8);
>  	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q-
> >queue_address >> 8);
>  	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q-
> >read_ptr);
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> index 85e1b67..2ba7cea 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> @@ -121,7 +121,7 @@ static int __update_mqd(struct mqd_manager *mm,
> void *mqd,
>  	m->cp_hqd_pq_control = 5 <<
> CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
>  			atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT
> |
>  			mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
> -	m->cp_hqd_pq_control |=	ffs(q->queue_size / 4) - 1 - 1;
> +	m->cp_hqd_pq_control |=	order_base_2(q->queue_size / 4) - 1;
>  	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
> 
>  	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
> >queue_address >> 8);
> @@ -151,7 +151,7 @@ static int __update_mqd(struct mqd_manager *mm,
> void *mqd,
>  	 * is safe, giving a maximum field value of 0xA.
>  	 */
>  	m->cp_hqd_eop_control |= min(0xA,
> -		ffs(q->eop_ring_buffer_size / 4) - 1 - 1);
> +		order_base_2(q->eop_ring_buffer_size / 4) - 1);
>  	m->cp_hqd_eop_base_addr_lo =
>  			lower_32_bits(q->eop_ring_buffer_address >> 8);
>  	m->cp_hqd_eop_base_addr_hi =
> @@ -287,7 +287,7 @@ static int update_mqd_sdma(struct mqd_manager
> *mm, void *mqd,
>  	struct vi_sdma_mqd *m;
> 
>  	m = get_sdma_mqd(mqd);
> -	m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1)
> +	m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
>  		<< SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>  		q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
>  		1 <<
> SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
> --
> 2.7.4
> 
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH 2/2] drm/amdkfd: Use order_base_2 to get log2 of buffes sizes

[Oded Gabbay]

Thanks,
Applied to -next

On Tue, Nov 7, 2017 at 12:04 AM, Deucher, Alexander
<Alexander.Deucher@amd.com> wrote:
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
>> Of Felix Kuehling
>> Sent: Monday, November 06, 2017 2:52 PM
>> To: amd-gfx@lists.freedesktop.org; oded.gabbay@gmail.com
>> Cc: Kuehling, Felix
>> Subject: [PATCH 2/2] drm/amdkfd: Use order_base_2 to get log2 of buffes
>> sizes
>>
>> Replace (ffs(size) - 1) with order_base_2(size) as a more straight
>> forward way to get log2 of buffer sizes.
>>
>> Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
>
> Series is:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>> ---
>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 6 +++---
>>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  | 6 +++---
>>  2 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> index efed6ef..7aa57ab 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c
>> @@ -183,7 +183,7 @@ static int update_mqd(struct mqd_manager *mm,
>> void *mqd,
>>        * Calculating queue size which is log base 2 of actual queue size -1
>>        * dwords and another -1 for ffs
>>        */
>> -     m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
>> +     m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
>>       m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
>> >queue_address >> 8);
>>       m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q-
>> >queue_address >> 8);
>>       m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q-
>> >read_ptr);
>> @@ -208,7 +208,7 @@ static int update_mqd_sdma(struct mqd_manager
>> *mm, void *mqd,
>>       struct cik_sdma_rlc_registers *m;
>>
>>       m = get_sdma_mqd(mqd);
>> -     m->sdma_rlc_rb_cntl = (ffs(q->queue_size / 4) - 1)
>> +     m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4)
>>                       << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>>                       q->vmid <<
>> SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
>>                       1 <<
>> SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
>> @@ -349,7 +349,7 @@ static int update_mqd_hiq(struct mqd_manager
>> *mm, void *mqd,
>>        * Calculating queue size which is log base 2 of actual queue
>>        * size -1 dwords
>>        */
>> -     m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
>> +     m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
>>       m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
>> >queue_address >> 8);
>>       m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q-
>> >queue_address >> 8);
>>       m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q-
>> >read_ptr);
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
>> index 85e1b67..2ba7cea 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
>> @@ -121,7 +121,7 @@ static int __update_mqd(struct mqd_manager *mm,
>> void *mqd,
>>       m->cp_hqd_pq_control = 5 <<
>> CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
>>                       atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT
>> |
>>                       mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
>> -     m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1;
>> +     m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
>>       pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
>>
>>       m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q-
>> >queue_address >> 8);
>> @@ -151,7 +151,7 @@ static int __update_mqd(struct mqd_manager *mm,
>> void *mqd,
>>        * is safe, giving a maximum field value of 0xA.
>>        */
>>       m->cp_hqd_eop_control |= min(0xA,
>> -             ffs(q->eop_ring_buffer_size / 4) - 1 - 1);
>> +             order_base_2(q->eop_ring_buffer_size / 4) - 1);
>>       m->cp_hqd_eop_base_addr_lo =
>>                       lower_32_bits(q->eop_ring_buffer_address >> 8);
>>       m->cp_hqd_eop_base_addr_hi =
>> @@ -287,7 +287,7 @@ static int update_mqd_sdma(struct mqd_manager
>> *mm, void *mqd,
>>       struct vi_sdma_mqd *m;
>>
>>       m = get_sdma_mqd(mqd);
>> -     m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1)
>> +     m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
>>               << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
>>               q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
>>               1 <<
>> SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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