[PATCH v2] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too

[PATCH v2] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too

[Valtteri Rantala]

Testing the texture read performance shows that the same tuning for
the SQ credits is needed on GLK as on BXT/APL. This has been also
confirmed by Altug from the HW team.

V2: Rebase

Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index fede62d..e1dcc91 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
 	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
+	/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
+	if (IS_GEN9_LP(dev_priv)) {
+		u32 val = I915_READ(GEN8_L3SQCREG1);
+
+		val &= ~L3_PRIO_CREDITS_MASK;
+		val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
+		I915_WRITE(GEN8_L3SQCREG1, val);
+	}
+
 	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
 	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 				    GEN8_LQSC_FLUSH_COHERENT_LINES));
-- 
2.7.4

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✓ Fi.CI.BAT: success for drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too (rev2)
URL   : https://patchwork.freedesktop.org/series/33772/
State : success

== Summary ==

Series 33772v2 drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too
https://patchwork.freedesktop.org/api/1.0/series/33772/revisions/2/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                incomplete -> PASS       (fi-cfl-s2) k.org#197971

k.org#197971 https://bugzilla.kernel.org/show_bug.cgi?id=197971

fi-bdw-5557u     total:289  pass:268  dwarn:0   dfail:0   fail:0   skip:21  time:449s
fi-bdw-gvtdvm    total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:459s
fi-blb-e6850     total:289  pass:223  dwarn:1   dfail:0   fail:0   skip:65  time:381s
fi-bsw-n3050     total:289  pass:243  dwarn:0   dfail:0   fail:0   skip:46  time:535s
fi-bwr-2160      total:289  pass:183  dwarn:0   dfail:0   fail:0   skip:106 time:281s
fi-bxt-dsi       total:289  pass:259  dwarn:0   dfail:0   fail:0   skip:30  time:506s
fi-bxt-j4205     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:507s
fi-byt-j1900     total:289  pass:254  dwarn:0   dfail:0   fail:0   skip:35  time:502s
fi-byt-n2820     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:491s
fi-cfl-s2        total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:603s
fi-elk-e7500     total:289  pass:229  dwarn:0   dfail:0   fail:0   skip:60  time:425s
fi-gdg-551       total:289  pass:178  dwarn:1   dfail:0   fail:1   skip:109 time:266s
fi-glk-1         total:289  pass:261  dwarn:0   dfail:0   fail:0   skip:28  time:544s
fi-hsw-4770      total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:426s
fi-hsw-4770r     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:445s
fi-ilk-650       total:289  pass:228  dwarn:0   dfail:0   fail:0   skip:61  time:426s
fi-ivb-3520m     total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:484s
fi-ivb-3770      total:289  pass:260  dwarn:0   dfail:0   fail:0   skip:29  time:466s
fi-kbl-7500u     total:289  pass:264  dwarn:1   dfail:0   fail:0   skip:24  time:486s
fi-kbl-7560u     total:289  pass:270  dwarn:0   dfail:0   fail:0   skip:19  time:533s
fi-kbl-7567u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:474s
fi-kbl-r         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:535s
fi-pnv-d510      total:289  pass:222  dwarn:1   dfail:0   fail:0   skip:66  time:577s
fi-skl-6260u     total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:458s
fi-skl-6600u     total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:540s
fi-skl-6700hq    total:289  pass:263  dwarn:0   dfail:0   fail:0   skip:26  time:563s
fi-skl-6700k     total:289  pass:265  dwarn:0   dfail:0   fail:0   skip:24  time:516s
fi-skl-6770hq    total:289  pass:269  dwarn:0   dfail:0   fail:0   skip:20  time:490s
fi-skl-gvtdvm    total:289  pass:266  dwarn:0   dfail:0   fail:0   skip:23  time:470s
fi-snb-2520m     total:289  pass:250  dwarn:0   dfail:0   fail:0   skip:39  time:562s
fi-snb-2600      total:289  pass:249  dwarn:0   dfail:0   fail:0   skip:40  time:421s
Blacklisted hosts:
fi-cnl-y         total:289  pass:262  dwarn:0   dfail:0   fail:0   skip:27  time:547s
fi-glk-dsi       total:22   pass:20   dwarn:1   dfail:0   fail:0   skip:0  

b407e5f38397c0c22b5056a1664753287993b152 drm-tip: 2017y-11m-23d-16h-14m-59s UTC integration manifest
37189718a81f drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7274/
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✗ Fi.CI.IGT: failure for drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too (rev2)
URL   : https://patchwork.freedesktop.org/series/33772/
State : failure

== Summary ==

Test perf:
        Subgroup polling:
                fail       -> PASS       (shard-hsw) fdo#102252
Test kms_setmode:
        Subgroup basic:
                fail       -> PASS       (shard-hsw) fdo#99912
Test drv_module_reload:
        Subgroup basic-no-display:
                pass       -> DMESG-WARN (shard-snb) fdo#102707 +1
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
                pass       -> FAIL       (shard-snb) fdo#101623
Test kms_flip:
        Subgroup modeset-vs-vblank-race:
                pass       -> FAIL       (shard-snb)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hsw        total:2667 pass:1535 dwarn:2   dfail:0   fail:9   skip:1121 time:9542s
shard-snb        total:2667 pass:1310 dwarn:2   dfail:0   fail:14  skip:1341 time:8115s
Blacklisted hosts:
shard-apl        total:2667 pass:1687 dwarn:1   dfail:0   fail:24  skip:954 time:13608s
shard-kbl        total:2667 pass:1771 dwarn:31  dfail:3   fail:23  skip:839 time:10755s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7274/shards.html
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Re: [PATCH v2] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too

[Ville Syrjälä]

On Fri, Nov 24, 2017 at 10:37:12AM +0200, Valtteri Rantala wrote:
> Testing the texture read performance shows that the same tuning for
> the SQ credits is needed on GLK as on BXT/APL. This has been also
> confirmed by Altug from the HW team.
> 
> V2: Rebase
> 
> Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index fede62d..e1dcc91 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>  	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>  
> +	/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> +	if (IS_GEN9_LP(dev_priv)) {
> +		u32 val = I915_READ(GEN8_L3SQCREG1);
> +
> +		val &= ~L3_PRIO_CREDITS_MASK;
> +		val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
> +		I915_WRITE(GEN8_L3SQCREG1, val);
> +	}

We're now doing this twice on bxt aren't we? So pls either remove the
same code from the bxt function, or just add this to the glk function
instead of here.

We might want to actually split gen9_init_workarounds() into big core
and lp variants. IMO there are too many conditional branches in the
current function, which sort of defeats the purpose of having platform
specific init_workarounds() functions in the first place.

> +
>  	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
>  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>  				    GEN8_LQSC_FLUSH_COHERENT_LINES));
> -- 
> 2.7.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v2] drm/i915/glk: Apply WaProgramL3SqcReg1DefaultForPerf for GLK too

[Rantala, Valtteri]

> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> Sent: Friday, November 24, 2017 3:50 PM
> To: Rantala, Valtteri <valtteri.rantala@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/glk: Apply
> WaProgramL3SqcReg1DefaultForPerf for GLK too
> 
> On Fri, Nov 24, 2017 at 10:37:12AM +0200, Valtteri Rantala wrote:
> > Testing the texture read performance shows that the same tuning for
> > the SQ credits is needed on GLK as on BXT/APL. This has been also
> > confirmed by Altug from the HW team.
> >
> > V2: Rebase
> >
> > Signed-off-by: Valtteri Rantala <valtteri.rantala@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c
> > b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index fede62d..e1dcc91 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1067,6 +1067,15 @@ static int gen9_init_workarounds(struct
> intel_engine_cs *engine)
> >  	/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> >  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
> >
> > +	/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
> > +	if (IS_GEN9_LP(dev_priv)) {
> > +		u32 val = I915_READ(GEN8_L3SQCREG1);
> > +
> > +		val &= ~L3_PRIO_CREDITS_MASK;
> > +		val |= L3_GENERAL_PRIO_CREDITS(62) |
> L3_HIGH_PRIO_CREDITS(2);
> > +		I915_WRITE(GEN8_L3SQCREG1, val);
> > +	}
> 
> We're now doing this twice on bxt aren't we? So pls either remove the same
> code from the bxt function, or just add this to the glk function instead of here.
> 
> We might want to actually split gen9_init_workarounds() into big core and lp
> variants. IMO there are too many conditional branches in the current function,
> which sort of defeats the purpose of having platform specific init_workarounds()
> functions in the first place.
Until that split is done I'll remove duplicate code from bxt. Since it is needed for both.

> 
> > +
> >  	/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
> >  	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> >  				    GEN8_LQSC_FLUSH_COHERENT_LINES));
> > --
> > 2.7.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel OTC
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