* [PATCH v13 00/12] Add ARMv8 RAS virtualization support in QEMU
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
From: gengdongjiu <gengdongjiu@huawei.com>
In the ARMv8 platform, the CPU error type are synchronous external
abort(SEA) and SError Interrupt (SEI). If guest happen exception,
sometimes guest itself do the recovery is better, because host
does not know guest's detailed info. For example, if a guest
user-space application happen exception, guest can kill this
application, but host can not do that.
For the ARMv8 SEA/SEI, KVM or host kernel will deliver SIGBUS or
use other interface to notify user space. After user space gets
the notification, it will record the CPER to guest GHES buffer
for guest and inject a exception or IRQ to KVM.
In the current implement, if the SIGBUS is BUS_MCEERR_AR, we will
treat it as synchronous exception, and use ARMv8 SEA notification type
to notify guest after recording CPER for guest; If the SIGBUS is
BUS_MCEERR_AO, we will treat it as asynchronous exception, and use
GPIO-Signal to notify guest after recording CPER for guest.
If KVM wants userspace to do the recovery for the SError, it will return a error
status to Qemu. Then Qemu will specify the guest ESR value and inject a virtual
SError.
This series patches have three parts:
1. Generate APEI/GHES table and record CPER for guest in runtime.
2. Handle the SIGBUS signal, record the CPER and fill into guest memory,
then according to SIGBUS type(BUS_MCEERR_AR or BUS_MCEERR_AO), using
different ACPI notification type to notify guest.
3. Specify guest SError ESR value and inject a virtual SError
Whole solution was suggested by James(james.morse@arm.com); inject RAS SEA abort and specify guest ESR
in user space are suggested by Marc(marc.zyngier@arm.com), APEI part solution is suggested by
Laszlo(lersek@redhat.com). Shown some discussion in [1].
This series patches have already tested on ARM64 platform with RAS feature enabled:
Show the APEI part verification result in [2]
Show the BUS_MCEERR_AR and BUS_MCEERR_AO SIGBUS handling verification result in [3]
Show Qemu set guest ESR and inject virtual SError verification result in [4]
---
Change since v12:
1. Address Paolo's comments to move HWPoisonPage definition to accel/kvm/kvm-all.c
2. Only call kvm_cpu_synchronize_state() when get the BUS_MCEERR_AR signal
3. Only add and enable GPIO-Signal and ARMv8 SEA two hardware error sources
4. Address Michael's comments to not sync SPDX from Linux kernel header file
Change since v11:
Address James's comments(james.morse@arm.com)
1. Check whether KVM has the capability to to set ESR instead of detecting host CPU RAS capability
2. For SIGBUS_MCEERR_AR SIGBUS, use Synchronous-External-Abort(SEA) notification type
for SIGBUS_MCEERR_AO SIGBUS, use GPIO-Signal notification
Address Shannon's comments(for ACPI part):
1. Unify hest_ghes.c and hest_ghes.h license declaration
2. Remove unnecessary including "qmp-commands.h" in hest_ghes.c
3. Unconditionally add guest APEI table based on James's comments(james.morse@arm.com)
4. Add a option to virt machine for migration compatibility. On new virt machine it's on
by default while off for old ones, we enabled it since 2.10
5. Refer to the ACPI spec version which introduces Hardware Error Notification first time
6. Add ACPI_HEST_NOTIFY_RESERVED notification type
Address Igor's comments(for ACPI part):
1. Add doc patch first which will describe how it's supposed to work between QEMU/firmware/guest
OS with expected flows.
2. Move APEI diagrams into doc/spec patch
3. Remove redundant g_malloc in ghes_record_cper()
4. Use build_append_int_noprefix() API to compose whole error status block and whole APEI table,
and try to get rid of most structures in patch 1, as they will be left unused after that
5. Reuse something like https://github.com/imammedo/qemu/commit/3d2fd6d13a3ea298d2ee814835495ce6241d085c
to build GAS
6. Remove much offsetof() in the function
7. Build independent tables first and only then build dependent tables passing to it pointers
to previously build table if necessary.
8. Redefine macro GHES_ACPI_HEST_NOTIFY_RESERVED to ACPI_HEST_ERROR_SOURCE_COUNT to avoid confusion
Address Peter Maydell's comments
1. linux-headers is done as a patch of their own created using scripts/update-linux-headers.sh run against a
mainline kernel tree
2. Tested whether this patchset builds OK on aarch32
3. Abstract Hwpoison page adding code out properly into a cpu-independent source file from target/i386/kvm.c,
such as kvm-all.c
4. Add doc-comment formatted documentation comment for new globally-visible function prototype in a header
---
[1]:
https://lkml.org/lkml/2017/2/27/246
https://patchwork.kernel.org/patch/9633105/
https://patchwork.kernel.org/patch/9925227/
[2]:
Note: the UEFI(QEMU_EFI.fd) is needed if guest want to use ACPI table.
After guest boot up, dump the APEI table, then can see the initialized table
(1) # iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST
(2) # cat HEST.dsl
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20170728 (64-bit version)
* Copyright (c) 2000 - 2017 Intel Corporation
*
* Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016
*
* ACPI Data Table [HEST]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
..................................................................................
[308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2]
[30Ah 0778 2] Source Id : 0008
[30Ch 0780 2] Related Source Id : FFFF
[30Eh 0782 1] Reserved : 00
[30Fh 0783 1] Enabled : 01
[310h 0784 4] Records To Preallocate : 00000001
[314h 0788 4] Max Sections Per Record : 00000001
[318h 0792 4] Max Raw Data Length : 00001000
[31Ch 0796 12] Error Status Address : [Generic Address Structure]
[31Ch 0796 1] Space ID : 00 [SystemMemory]
[31Dh 0797 1] Bit Width : 40
[31Eh 0798 1] Bit Offset : 00
[31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64]
[320h 0800 8] Address : 00000000785D0040
[328h 0808 28] Notify : [Hardware Error Notification Structure]
[328h 0808 1] Notify Type : 08 [SEA]
[329h 0809 1] Notify Length : 1C
[32Ah 0810 2] Configuration Write Enable : 0000
[32Ch 0812 4] PollInterval : 00000000
[330h 0816 4] Vector : 00000000
[334h 0820 4] Polling Threshold Value : 00000000
[338h 0824 4] Polling Threshold Window : 00000000
[33Ch 0828 4] Error Threshold Value : 00000000
[340h 0832 4] Error Threshold Window : 00000000
[344h 0836 4] Error Status Block Length : 00001000
[348h 0840 12] Read Ack Register : [Generic Address Structure]
[348h 0840 1] Space ID : 00 [SystemMemory]
[349h 0841 1] Bit Width : 40
[34Ah 0842 1] Bit Offset : 00
[34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64]
[34Ch 0844 8] Address : 00000000785D0098
[354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE
[35Ch 0860 8] Read Ack Write : 0000000000000001
.....................................................................................
(3) After a synchronous external abort(SEA) happen, Qemu receive a SIGBUS and
filled the CPER into guest GHES memory. For example, according to above table,
the address that contains the physical address of a block of memory that holds
the error status data for this abort is 0x00000000785D0040
(4) the address for SEA notification error source is 0x785d80b0
(qemu) xp /1 0x00000000785D0040
00000000785d0040: 0x785d80b0
(5) check the content of generic error status block and generic error data entry
(qemu) xp /100x 0x785d80b0
00000000785d80b0: 0x00000001 0x00000000 0x00000000 0x00000098
00000000785d80c0: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8
00000000785d80d0: 0xb1837ced 0x00000000 0x00000300 0x00000050
00000000785d80e0: 0x00000000 0x00000000 0x00000000 0x00000000
00000000785d80f0: 0x00000000 0x00000000 0x00000000 0x00000000
00000000785d8100: 0x00000000 0x00000000 0x00000000 0x00004002
(6) check the OSPM's ACK value(for example SEA)
/* Before OSPM acknowledges the error, check the ACK value */
(qemu) xp /1 0x00000000785D0098
00000000785d00f0: 0x00000000
/* After OSPM acknowledges the error, check the ACK value, it change to 1 from 0 */
(qemu) xp /1 0x00000000785D0098
00000000785d00f0: 0x00000001
[2] host memory error hander deliver "BUS_MCEERR_AO" to Qemu, Qemu record the
guest CPER and notify guest by IRQ, then guest do the recovery.
[ 4895.040340] {2}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 7
[ 4895.367779] {2}[Hardware Error]: event severity: recoverable
[ 4896.536868] {2}[Hardware Error]: Error 0, type: recoverable
[ 4896.753032] {2}[Hardware Error]: section_type: memory error
[ 4896.969088] {2}[Hardware Error]: physical_address: 0x0000000040a08000
[ 4897.211532] {2}[Hardware Error]: error_type: 3, multi-bit ECC
[ 4900.666650] Memory failure: 0x40600: already hardware poisoned
[ 4902.744432] Memory failure: 0x40a08: Killing mca-recover:42 due to hardware memory corruption
[ 4903.448544] Memory failure: 0x40a08: recovery action for dirty LRU page: RecoVered
[3] KVM deliver "BUS_MCEERR_AR" to Qemu, Qemu record the guest CPER and inject
synchronous external abort to notify guest, then guest do the recovery.
[ 1552.516170] Synchronous External Abort: synchronous external abort (0x92000410) at 0x000000003751c6b4
[ 1553.074073] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8
[ 1553.081654] {1}[Hardware Error]: event severity: recoverable
[ 1554.034191] {1}[Hardware Error]: Error 0, type: recoverable
[ 1554.037934] {1}[Hardware Error]: section_type: memory error
[ 1554.513261] {1}[Hardware Error]: physical_address: 0x0000000040fa6000
[ 1554.513944] {1}[Hardware Error]: error_type: 3, multi-bit ECC
[ 1555.041451] Memory failure: 0x40fa6: Killing mca-recover:1296 due to hardware memory corruption
[ 1555.373116] Memory failure: 0x40fa6: recovery action for dirty LRU page: Recovered
[4] Qemu set guest ESR and inject virtual SError test result:
KVM return Error status to Qemu, Qemu set the guest ESR and inject virtual SError.
As shown below, the ESR value 0xbe000c11 is set by Qemu
Bad mode in Error handler detected, code 0xbe000c11 -- SError
CPU: 0 PID: 539 Comm: devmem Tainted: G D 4.1.0+ #20
Hardware name: linux,dummy-virt (DT)
task: ffffffc019aad600 ti: ffffffc008134000 task.ti: ffffffc008134000
PC is at 0x405cc0
LR is at 0x40ce80
pc : [<0000000000405cc0>] lr : [<000000000040ce80>] pstate: 60000000
sp : ffffffc008137ff0
x29: 0000007fd9e80790 x28: 0000000000000000
x27: 00000000000000ad x26: 000000000049c000
x25: 000000000048904b x24: 000000000049c000
x23: 0000000040600000 x22: 0000007fd9e808d0
x21: 0000000000000002 x20: 0000000000000000
x19: 0000000000000020 x18: 0000000000000000
x17: 0000000000405cc0 x16: 000000000049c698
x15: 0000000000005798 x14: 0000007f93875f1c
x13: 0000007f93a8ccb0 x12: 0000000000000137
x11: 0000000000000000 x10: 0000000000000000
x9 : 0000000000000000 x8 : 00000000000000de
x7 : 0000000000000000 x6 : 0000000000002000
x5 : 0000000040600000 x4 : 0000000000000003
x3 : 0000000000000001 x2 : 00000000000f123b
x1 : 0000000000000008 x0 : 000000000047a048
Dongjiu Geng (12):
ACPI: add related GHES structures and macros definition
ACPI: Add APEI GHES table generation and CPER record support
docs: APEI GHES generation description
ACPI: enable APEI GHES in the configure file and build it
linux-headers: sync against Linux v4.14-rc8
target-arm: kvm64: detect whether can set vsesr_el2
target-arm: handle SError interrupt exception from the guest OS
target-arm: kvm64: inject synchronous External Abort
Move related hwpoison page function to accel/kvm/ folder
ARM: ACPI: Add _E04 for hardware error device
hw/arm/virt: Add RAS platform version for migration
target-arm: kvm64: handle SIGBUS signal from kernel or KVM
accel/kvm/kvm-all.c | 34 ++++
default-configs/arm-softmmu.mak | 1 +
docs/specs/acpi_hest_ghes.txt | 96 +++++++++++
hw/acpi/Makefile.objs | 1 +
hw/acpi/aml-build.c | 2 +
hw/acpi/hest_ghes.c | 358 ++++++++++++++++++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 43 ++++-
hw/arm/virt.c | 22 +++
include/exec/ram_addr.h | 5 +
include/hw/acpi/acpi-defs.h | 49 ++++++
include/hw/acpi/aml-build.h | 1 +
include/hw/acpi/hest_ghes.h | 83 ++++++++++
include/hw/arm/virt.h | 1 +
include/sysemu/kvm.h | 2 +-
include/sysemu/sysemu.h | 3 +
linux-headers/linux/kvm.h | 3 +
target/arm/internals.h | 4 +
target/arm/kvm.c | 5 +
target/arm/kvm32.c | 6 +
target/arm/kvm64.c | 138 ++++++++++++++++
target/arm/kvm_arm.h | 8 +
target/i386/kvm.c | 33 ----
vl.c | 12 ++
23 files changed, 875 insertions(+), 35 deletions(-)
create mode 100644 docs/specs/acpi_hest_ghes.txt
create mode 100644 hw/acpi/hest_ghes.c
create mode 100644 include/hw/acpi/hest_ghes.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 00/12] Add ARMv8 RAS virtualization support in QEMU
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
From: gengdongjiu <gengdongjiu@huawei.com>
In the ARMv8 platform, the CPU error type are synchronous external
abort(SEA) and SError Interrupt (SEI). If guest happen exception,
sometimes guest itself do the recovery is better, because host
does not know guest's detailed info. For example, if a guest
user-space application happen exception, guest can kill this
application, but host can not do that.
For the ARMv8 SEA/SEI, KVM or host kernel will deliver SIGBUS or
use other interface to notify user space. After user space gets
the notification, it will record the CPER to guest GHES buffer
for guest and inject a exception or IRQ to KVM.
In the current implement, if the SIGBUS is BUS_MCEERR_AR, we will
treat it as synchronous exception, and use ARMv8 SEA notification type
to notify guest after recording CPER for guest; If the SIGBUS is
BUS_MCEERR_AO, we will treat it as asynchronous exception, and use
GPIO-Signal to notify guest after recording CPER for guest.
If KVM wants userspace to do the recovery for the SError, it will return a error
status to Qemu. Then Qemu will specify the guest ESR value and inject a virtual
SError.
This series patches have three parts:
1. Generate APEI/GHES table and record CPER for guest in runtime.
2. Handle the SIGBUS signal, record the CPER and fill into guest memory,
then according to SIGBUS type(BUS_MCEERR_AR or BUS_MCEERR_AO), using
different ACPI notification type to notify guest.
3. Specify guest SError ESR value and inject a virtual SError
Whole solution was suggested by James(james.morse@arm.com); inject RAS SEA abort and specify guest ESR
in user space are suggested by Marc(marc.zyngier@arm.com), APEI part solution is suggested by
Laszlo(lersek@redhat.com). Shown some discussion in [1].
This series patches have already tested on ARM64 platform with RAS feature enabled:
Show the APEI part verification result in [2]
Show the BUS_MCEERR_AR and BUS_MCEERR_AO SIGBUS handling verification result in [3]
Show Qemu set guest ESR and inject virtual SError verification result in [4]
---
Change since v12:
1. Address Paolo's comments to move HWPoisonPage definition to accel/kvm/kvm-all.c
2. Only call kvm_cpu_synchronize_state() when get the BUS_MCEERR_AR signal
3. Only add and enable GPIO-Signal and ARMv8 SEA two hardware error sources
4. Address Michael's comments to not sync SPDX from Linux kernel header file
Change since v11:
Address James's comments(james.morse@arm.com)
1. Check whether KVM has the capability to to set ESR instead of detecting host CPU RAS capability
2. For SIGBUS_MCEERR_AR SIGBUS, use Synchronous-External-Abort(SEA) notification type
for SIGBUS_MCEERR_AO SIGBUS, use GPIO-Signal notification
Address Shannon's comments(for ACPI part):
1. Unify hest_ghes.c and hest_ghes.h license declaration
2. Remove unnecessary including "qmp-commands.h" in hest_ghes.c
3. Unconditionally add guest APEI table based on James's comments(james.morse@arm.com)
4. Add a option to virt machine for migration compatibility. On new virt machine it's on
by default while off for old ones, we enabled it since 2.10
5. Refer to the ACPI spec version which introduces Hardware Error Notification first time
6. Add ACPI_HEST_NOTIFY_RESERVED notification type
Address Igor's comments(for ACPI part):
1. Add doc patch first which will describe how it's supposed to work between QEMU/firmware/guest
OS with expected flows.
2. Move APEI diagrams into doc/spec patch
3. Remove redundant g_malloc in ghes_record_cper()
4. Use build_append_int_noprefix() API to compose whole error status block and whole APEI table,
and try to get rid of most structures in patch 1, as they will be left unused after that
5. Reuse something like https://github.com/imammedo/qemu/commit/3d2fd6d13a3ea298d2ee814835495ce6241d085c
to build GAS
6. Remove much offsetof() in the function
7. Build independent tables first and only then build dependent tables passing to it pointers
to previously build table if necessary.
8. Redefine macro GHES_ACPI_HEST_NOTIFY_RESERVED to ACPI_HEST_ERROR_SOURCE_COUNT to avoid confusion
Address Peter Maydell's comments
1. linux-headers is done as a patch of their own created using scripts/update-linux-headers.sh run against a
mainline kernel tree
2. Tested whether this patchset builds OK on aarch32
3. Abstract Hwpoison page adding code out properly into a cpu-independent source file from target/i386/kvm.c,
such as kvm-all.c
4. Add doc-comment formatted documentation comment for new globally-visible function prototype in a header
---
[1]:
https://lkml.org/lkml/2017/2/27/246
https://patchwork.kernel.org/patch/9633105/
https://patchwork.kernel.org/patch/9925227/
[2]:
Note: the UEFI(QEMU_EFI.fd) is needed if guest want to use ACPI table.
After guest boot up, dump the APEI table, then can see the initialized table
(1) # iasl -p ./HEST -d /sys/firmware/acpi/tables/HEST
(2) # cat HEST.dsl
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20170728 (64-bit version)
* Copyright (c) 2000 - 2017 Intel Corporation
*
* Disassembly of /sys/firmware/acpi/tables/HEST, Mon Sep 5 07:59:17 2016
*
* ACPI Data Table [HEST]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
..................................................................................
[308h 0776 2] Subtable Type : 000A [Generic Hardware Error Source V2]
[30Ah 0778 2] Source Id : 0008
[30Ch 0780 2] Related Source Id : FFFF
[30Eh 0782 1] Reserved : 00
[30Fh 0783 1] Enabled : 01
[310h 0784 4] Records To Preallocate : 00000001
[314h 0788 4] Max Sections Per Record : 00000001
[318h 0792 4] Max Raw Data Length : 00001000
[31Ch 0796 12] Error Status Address : [Generic Address Structure]
[31Ch 0796 1] Space ID : 00 [SystemMemory]
[31Dh 0797 1] Bit Width : 40
[31Eh 0798 1] Bit Offset : 00
[31Fh 0799 1] Encoded Access Width : 04 [QWord Access:64]
[320h 0800 8] Address : 00000000785D0040
[328h 0808 28] Notify : [Hardware Error Notification Structure]
[328h 0808 1] Notify Type : 08 [SEA]
[329h 0809 1] Notify Length : 1C
[32Ah 0810 2] Configuration Write Enable : 0000
[32Ch 0812 4] PollInterval : 00000000
[330h 0816 4] Vector : 00000000
[334h 0820 4] Polling Threshold Value : 00000000
[338h 0824 4] Polling Threshold Window : 00000000
[33Ch 0828 4] Error Threshold Value : 00000000
[340h 0832 4] Error Threshold Window : 00000000
[344h 0836 4] Error Status Block Length : 00001000
[348h 0840 12] Read Ack Register : [Generic Address Structure]
[348h 0840 1] Space ID : 00 [SystemMemory]
[349h 0841 1] Bit Width : 40
[34Ah 0842 1] Bit Offset : 00
[34Bh 0843 1] Encoded Access Width : 04 [QWord Access:64]
[34Ch 0844 8] Address : 00000000785D0098
[354h 0852 8] Read Ack Preserve : 00000000FFFFFFFE
[35Ch 0860 8] Read Ack Write : 0000000000000001
.....................................................................................
(3) After a synchronous external abort(SEA) happen, Qemu receive a SIGBUS and
filled the CPER into guest GHES memory. For example, according to above table,
the address that contains the physical address of a block of memory that holds
the error status data for this abort is 0x00000000785D0040
(4) the address for SEA notification error source is 0x785d80b0
(qemu) xp /1 0x00000000785D0040
00000000785d0040: 0x785d80b0
(5) check the content of generic error status block and generic error data entry
(qemu) xp /100x 0x785d80b0
00000000785d80b0: 0x00000001 0x00000000 0x00000000 0x00000098
00000000785d80c0: 0x00000000 0xa5bc1114 0x4ede6f64 0x833e63b8
00000000785d80d0: 0xb1837ced 0x00000000 0x00000300 0x00000050
00000000785d80e0: 0x00000000 0x00000000 0x00000000 0x00000000
00000000785d80f0: 0x00000000 0x00000000 0x00000000 0x00000000
00000000785d8100: 0x00000000 0x00000000 0x00000000 0x00004002
(6) check the OSPM's ACK value(for example SEA)
/* Before OSPM acknowledges the error, check the ACK value */
(qemu) xp /1 0x00000000785D0098
00000000785d00f0: 0x00000000
/* After OSPM acknowledges the error, check the ACK value, it change to 1 from 0 */
(qemu) xp /1 0x00000000785D0098
00000000785d00f0: 0x00000001
[2] host memory error hander deliver "BUS_MCEERR_AO" to Qemu, Qemu record the
guest CPER and notify guest by IRQ, then guest do the recovery.
[ 4895.040340] {2}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 7
[ 4895.367779] {2}[Hardware Error]: event severity: recoverable
[ 4896.536868] {2}[Hardware Error]: Error 0, type: recoverable
[ 4896.753032] {2}[Hardware Error]: section_type: memory error
[ 4896.969088] {2}[Hardware Error]: physical_address: 0x0000000040a08000
[ 4897.211532] {2}[Hardware Error]: error_type: 3, multi-bit ECC
[ 4900.666650] Memory failure: 0x40600: already hardware poisoned
[ 4902.744432] Memory failure: 0x40a08: Killing mca-recover:42 due to hardware memory corruption
[ 4903.448544] Memory failure: 0x40a08: recovery action for dirty LRU page: RecoVered
[3] KVM deliver "BUS_MCEERR_AR" to Qemu, Qemu record the guest CPER and inject
synchronous external abort to notify guest, then guest do the recovery.
[ 1552.516170] Synchronous External Abort: synchronous external abort (0x92000410) at 0x000000003751c6b4
[ 1553.074073] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 8
[ 1553.081654] {1}[Hardware Error]: event severity: recoverable
[ 1554.034191] {1}[Hardware Error]: Error 0, type: recoverable
[ 1554.037934] {1}[Hardware Error]: section_type: memory error
[ 1554.513261] {1}[Hardware Error]: physical_address: 0x0000000040fa6000
[ 1554.513944] {1}[Hardware Error]: error_type: 3, multi-bit ECC
[ 1555.041451] Memory failure: 0x40fa6: Killing mca-recover:1296 due to hardware memory corruption
[ 1555.373116] Memory failure: 0x40fa6: recovery action for dirty LRU page: Recovered
[4] Qemu set guest ESR and inject virtual SError test result:
KVM return Error status to Qemu, Qemu set the guest ESR and inject virtual SError.
As shown below, the ESR value 0xbe000c11 is set by Qemu
Bad mode in Error handler detected, code 0xbe000c11 -- SError
CPU: 0 PID: 539 Comm: devmem Tainted: G D 4.1.0+ #20
Hardware name: linux,dummy-virt (DT)
task: ffffffc019aad600 ti: ffffffc008134000 task.ti: ffffffc008134000
PC is at 0x405cc0
LR is at 0x40ce80
pc : [<0000000000405cc0>] lr : [<000000000040ce80>] pstate: 60000000
sp : ffffffc008137ff0
x29: 0000007fd9e80790 x28: 0000000000000000
x27: 00000000000000ad x26: 000000000049c000
x25: 000000000048904b x24: 000000000049c000
x23: 0000000040600000 x22: 0000007fd9e808d0
x21: 0000000000000002 x20: 0000000000000000
x19: 0000000000000020 x18: 0000000000000000
x17: 0000000000405cc0 x16: 000000000049c698
x15: 0000000000005798 x14: 0000007f93875f1c
x13: 0000007f93a8ccb0 x12: 0000000000000137
x11: 0000000000000000 x10: 0000000000000000
x9 : 0000000000000000 x8 : 00000000000000de
x7 : 0000000000000000 x6 : 0000000000002000
x5 : 0000000040600000 x4 : 0000000000000003
x3 : 0000000000000001 x2 : 00000000000f123b
x1 : 0000000000000008 x0 : 000000000047a048
Dongjiu Geng (12):
ACPI: add related GHES structures and macros definition
ACPI: Add APEI GHES table generation and CPER record support
docs: APEI GHES generation description
ACPI: enable APEI GHES in the configure file and build it
linux-headers: sync against Linux v4.14-rc8
target-arm: kvm64: detect whether can set vsesr_el2
target-arm: handle SError interrupt exception from the guest OS
target-arm: kvm64: inject synchronous External Abort
Move related hwpoison page function to accel/kvm/ folder
ARM: ACPI: Add _E04 for hardware error device
hw/arm/virt: Add RAS platform version for migration
target-arm: kvm64: handle SIGBUS signal from kernel or KVM
accel/kvm/kvm-all.c | 34 ++++
default-configs/arm-softmmu.mak | 1 +
docs/specs/acpi_hest_ghes.txt | 96 +++++++++++
hw/acpi/Makefile.objs | 1 +
hw/acpi/aml-build.c | 2 +
hw/acpi/hest_ghes.c | 358 ++++++++++++++++++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 43 ++++-
hw/arm/virt.c | 22 +++
include/exec/ram_addr.h | 5 +
include/hw/acpi/acpi-defs.h | 49 ++++++
include/hw/acpi/aml-build.h | 1 +
include/hw/acpi/hest_ghes.h | 83 ++++++++++
include/hw/arm/virt.h | 1 +
include/sysemu/kvm.h | 2 +-
include/sysemu/sysemu.h | 3 +
linux-headers/linux/kvm.h | 3 +
target/arm/internals.h | 4 +
target/arm/kvm.c | 5 +
target/arm/kvm32.c | 6 +
target/arm/kvm64.c | 138 ++++++++++++++++
target/arm/kvm_arm.h | 8 +
target/i386/kvm.c | 33 ----
vl.c | 12 ++
23 files changed, 875 insertions(+), 35 deletions(-)
create mode 100644 docs/specs/acpi_hest_ghes.txt
create mode 100644 hw/acpi/hest_ghes.c
create mode 100644 include/hw/acpi/hest_ghes.h
--
1.8.3.1
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v13 01/12] ACPI: add related GHES structures and macros definition
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add Generic Error Status Block structures and some macros
definition, which refer to the ACPI 4.0 and ACPI 6.1. The
HEST table generation and CPER record will use them.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Igor's comments to to get rid of most structures and use
build_append_int_noprefix() API to compose whole error status block
and APEI table in [1]
[1]: https://lkml.org/lkml/2017/8/29/187
---
include/hw/acpi/acpi-defs.h | 49 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 72be675..f955f1b 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -298,6 +298,25 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
/*
+ * ACPI 4.0 spec, "17.3.2.7 Hardware Error Notification"
+ */
+enum AcpiHestNotifyType {
+ ACPI_HEST_NOTIFY_POLLED = 0,
+ ACPI_HEST_NOTIFY_EXTERNAL = 1,
+ ACPI_HEST_NOTIFY_LOCAL = 2,
+ ACPI_HEST_NOTIFY_SCI = 3,
+ ACPI_HEST_NOTIFY_NMI = 4,
+ ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */
+ ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */
+ ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */
+ ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */
+ ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */
+ ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */
+ ACPI_HEST_NOTIFY_SDEI = 11, /* ACPI 6.2 */
+ ACPI_HEST_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */
+};
+
+/*
* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
*/
#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
@@ -474,6 +493,36 @@ struct AcpiSystemResourceAffinityTable {
} QEMU_PACKED;
typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
+/*
+ * ACPI 4.0, "17.3.2.6.1 Generic Error Data"
+ */
+#define ACPI_GEBS_UNCORRECTABLE (1)
+/*
+ * ACPI 6.1, "18.3.2.8 Generic Hardware Error
+ * Source version 2"
+ */
+#define ACPI_HEST_SOURCE_GENERIC_ERROR_V2 (10)
+/*
+ * Table 17-12 Generic Error Status Block, ACPI 4.0,
+ * "17.3.2.6.1 Generic Error Data"
+ */
+struct AcpiGenericErrorStatus {
+ /* It is a bitmask composed of ACPI_GEBS_xxx macros */
+ uint32_t block_status;
+ uint32_t raw_data_offset;
+ uint32_t raw_data_length;
+ uint32_t data_length;
+ uint32_t error_severity;
+} QEMU_PACKED;
+typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus;
+
+enum AcpiGenericErrorSeverity {
+ ACPI_CPER_SEV_RECOVERABLE,
+ ACPI_CPER_SEV_FATAL,
+ ACPI_CPER_SEV_CORRECTED,
+ ACPI_CPER_SEV_NONE,
+};
+
#define ACPI_SRAT_PROCESSOR_APIC 0
#define ACPI_SRAT_MEMORY 1
#define ACPI_SRAT_PROCESSOR_x2APIC 2
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 01/12] ACPI: add related GHES structures and macros definition
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add Generic Error Status Block structures and some macros
definition, which refer to the ACPI 4.0 and ACPI 6.1. The
HEST table generation and CPER record will use them.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Igor's comments to to get rid of most structures and use
build_append_int_noprefix() API to compose whole error status block
and APEI table in [1]
[1]: https://lkml.org/lkml/2017/8/29/187
---
include/hw/acpi/acpi-defs.h | 49 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 72be675..f955f1b 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -298,6 +298,25 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
#define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */
/*
+ * ACPI 4.0 spec, "17.3.2.7 Hardware Error Notification"
+ */
+enum AcpiHestNotifyType {
+ ACPI_HEST_NOTIFY_POLLED = 0,
+ ACPI_HEST_NOTIFY_EXTERNAL = 1,
+ ACPI_HEST_NOTIFY_LOCAL = 2,
+ ACPI_HEST_NOTIFY_SCI = 3,
+ ACPI_HEST_NOTIFY_NMI = 4,
+ ACPI_HEST_NOTIFY_CMCI = 5, /* ACPI 5.0 */
+ ACPI_HEST_NOTIFY_MCE = 6, /* ACPI 5.0 */
+ ACPI_HEST_NOTIFY_GPIO = 7, /* ACPI 6.0 */
+ ACPI_HEST_NOTIFY_SEA = 8, /* ACPI 6.1 */
+ ACPI_HEST_NOTIFY_SEI = 9, /* ACPI 6.1 */
+ ACPI_HEST_NOTIFY_GSIV = 10, /* ACPI 6.1 */
+ ACPI_HEST_NOTIFY_SDEI = 11, /* ACPI 6.2 */
+ ACPI_HEST_NOTIFY_RESERVED = 12 /* 12 and greater are reserved */
+};
+
+/*
* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
*/
#define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\
@@ -474,6 +493,36 @@ struct AcpiSystemResourceAffinityTable {
} QEMU_PACKED;
typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
+/*
+ * ACPI 4.0, "17.3.2.6.1 Generic Error Data"
+ */
+#define ACPI_GEBS_UNCORRECTABLE (1)
+/*
+ * ACPI 6.1, "18.3.2.8 Generic Hardware Error
+ * Source version 2"
+ */
+#define ACPI_HEST_SOURCE_GENERIC_ERROR_V2 (10)
+/*
+ * Table 17-12 Generic Error Status Block, ACPI 4.0,
+ * "17.3.2.6.1 Generic Error Data"
+ */
+struct AcpiGenericErrorStatus {
+ /* It is a bitmask composed of ACPI_GEBS_xxx macros */
+ uint32_t block_status;
+ uint32_t raw_data_offset;
+ uint32_t raw_data_length;
+ uint32_t data_length;
+ uint32_t error_severity;
+} QEMU_PACKED;
+typedef struct AcpiGenericErrorStatus AcpiGenericErrorStatus;
+
+enum AcpiGenericErrorSeverity {
+ ACPI_CPER_SEV_RECOVERABLE,
+ ACPI_CPER_SEV_FATAL,
+ ACPI_CPER_SEV_CORRECTED,
+ ACPI_CPER_SEV_NONE,
+};
+
#define ACPI_SRAT_PROCESSOR_APIC 0
#define ACPI_SRAT_MEMORY 1
#define ACPI_SRAT_PROCESSOR_x2APIC 2
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 02/12] ACPI: Add APEI GHES table generation and CPER record support
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
This implements APEI GHES Table generation when OS boot and
record CPER in runtime via fw_cfg blobs. After a CPER info is
recorded into guest memory, it need to inject whatever interrupt
(or assert whatever GPIO line) to notify the guest. About the
detailed design or implementation, please see the "hest_ghes.txt"
in the doc folder.
Now we only support three types of GHESv2, which are GPIO-Signal,
ARMv8 SEA and ARMv8 SEI. Afterwards, we can extend the supported
type if needed. For the CPER section type, currently it is memory
section because kernel manly wants userspace to handle the memory
section errors.
For GHESv2 error source, the OSPM must acknowledges the error via
Read Ack register. So user space must check the ack value before
recording a new CPER to avoid read-write race condition.
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
The basic solution is suggested by Laszlo in [1]
[1]: https://lkml.org/lkml/2017/3/29/342
---
hw/acpi/aml-build.c | 2 +
hw/acpi/hest_ghes.c | 360 ++++++++++++++++++++++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 8 +
include/hw/acpi/aml-build.h | 1 +
include/hw/acpi/hest_ghes.h | 83 ++++++++++
5 files changed, 454 insertions(+)
create mode 100644 hw/acpi/hest_ghes.c
create mode 100644 include/hw/acpi/hest_ghes.h
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 36a6cc4..6849e5f 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1561,6 +1561,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables)
tables->table_data = g_array_new(false, true /* clear */, 1);
tables->tcpalog = g_array_new(false, true /* clear */, 1);
tables->vmgenid = g_array_new(false, true /* clear */, 1);
+ tables->hardware_errors = g_array_new(false, true /* clear */, 1);
tables->linker = bios_linker_loader_init();
}
@@ -1571,6 +1572,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
g_array_free(tables->table_data, true);
g_array_free(tables->tcpalog, mfre);
g_array_free(tables->vmgenid, mfre);
+ g_array_free(tables->hardware_errors, mfre);
}
/* Build rsdt table */
diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c
new file mode 100644
index 0000000..08f8bf1
--- /dev/null
+++ b/hw/acpi/hest_ghes.c
@@ -0,0 +1,360 @@
+/* Support for generating APEI tables and passing them to Guests
+ *
+ * Copyright (C) 2017 HuaWei Corporation.
+ *
+ * Author: Dongjiu Geng <gengdongjiu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/aml-build.h"
+#include "hw/acpi/hest_ghes.h"
+#include "hw/nvram/fw_cfg.h"
+#include "sysemu/sysemu.h"
+#include "qemu/error-report.h"
+
+/* Generic Error Status Block
+ * ACPI 4.0: 17.3.2.6.1 Generic Error Data
+ */
+static void build_append_gesb(GArray *table, uint32_t block_status,
+ uint32_t raw_data_offset, uint32_t raw_data_length,
+ uint32_t data_length, uint32_t error_severity)
+{
+ build_append_int_noprefix(table, block_status, 4);
+ build_append_int_noprefix(table, raw_data_offset, 4);
+ build_append_int_noprefix(table, raw_data_length, 4);
+ build_append_int_noprefix(table, data_length, 4);
+ build_append_int_noprefix(table, error_severity, 4);
+}
+
+/* Generic Error Data Entry
+ * ACPI 4.0: 17.3.2.6.1 Generic Error Data
+ */
+static void build_append_gede(GArray *table, const char *section_type,
+ const uint32_t error_severity, const uint16_t revision,
+ const uint32_t error_data_length)
+{
+ int i;
+
+ for (i = 0; i < 16; i++) {
+ build_append_int_noprefix(table, section_type[i], 1);
+ }
+
+ build_append_int_noprefix(table, error_severity, 4);
+ build_append_int_noprefix(table, revision, 2);
+ build_append_int_noprefix(table, 0, 2);
+ build_append_int_noprefix(table, error_data_length, 4);
+ build_append_int_noprefix(table, 0, 44);
+}
+
+/* Generic Address Structure (GAS)
+ * ACPI 2.0/3.0: 5.2.3.1 Generic Address Structure
+ * 2.0 compat note:
+ * @access_width must be 0, see ACPI 2.0:Table 5-1
+ */
+static void build_append_gas(GArray *table, AmlRegionSpace as,
+ uint8_t bit_width, uint8_t bit_offset,
+ uint8_t access_width, uint64_t address)
+{
+ build_append_int_noprefix(table, as, 1);
+ build_append_int_noprefix(table, bit_width, 1);
+ build_append_int_noprefix(table, bit_offset, 1);
+ build_append_int_noprefix(table, access_width, 1);
+ build_append_int_noprefix(table, address, 8);
+}
+
+/* Hardware Error Notification
+ * ACPI 4.0: 17.3.2.7 Hardware Error Notification
+ */
+static void build_append_notify(GArray *table, const uint8_t type,
+ uint8_t length)
+{
+ build_append_int_noprefix(table, type, 1); /* type */
+ build_append_int_noprefix(table, length, 1);
+ build_append_int_noprefix(table, 0, 26);
+}
+
+static int ghes_record_cper(uint64_t error_block_address,
+ uint64_t error_physical_addr)
+{
+ GArray *block;
+ uint64_t current_block_length;
+ uint32_t data_length;
+ /* memory section */
+ char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE,
+ 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C,
+ 0x83, 0xB1};
+
+ block = g_array_new(false, true /* clear */, 1);
+
+ cpu_physical_memory_read(error_block_address +
+ offsetof(AcpiGenericErrorStatus, data_length), &data_length, 4);
+
+ current_block_length = sizeof(AcpiGenericErrorStatus) + data_length;
+
+ data_length += GHES_DATA_LENGTH;
+ data_length += GHES_CPER_LENGTH;
+
+ /* check whether it runs out of the preallocated memory */
+ if ((data_length + sizeof(AcpiGenericErrorStatus)) > GHES_MAX_RAW_DATA_LENGTH) {
+ error_report("Record CPER out of boundary!!!");
+ return GHES_CPER_FAIL;
+ }
+
+ build_append_gesb(block, cpu_to_le32(ACPI_GEBS_UNCORRECTABLE), 0, 0,
+ cpu_to_le32(data_length), cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE));
+
+ /* Write back the Generic Error Status Block to guest memory */
+ cpu_physical_memory_write(error_block_address, block->data,
+ block->len);
+
+ data_length = block->len;
+
+ build_append_gede(block, mem_section_id_le,
+ cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE), cpu_to_le32(0x300),
+ cpu_to_le32(80)/* the total size of Memory Error Record */);
+
+ /*
+ * Memory Error Record
+ */
+ build_append_int_noprefix(block,
+ (1UL << 14) | /* Type Valid */
+ (1UL << 1) /* Physical Address Valid */,
+ 8);
+ /* Memory error status information */
+ build_append_int_noprefix(block, 0, 8);
+ /* The physical address at which the memory error occurred */
+ build_append_int_noprefix(block, error_physical_addr, 8);
+ build_append_int_noprefix(block, 0, 48);
+ /* Hard code to Multi-bit ECC error */
+ build_append_int_noprefix(block, 3 /* Multi-bit ECC */, 1);
+ build_append_int_noprefix(block, 0, 7);
+
+ /* Write back the Generic Error Data Entry to guest memory */
+ cpu_physical_memory_write(error_block_address + current_block_length,
+ block->data + data_length, block->len - data_length);
+
+ g_array_free(block, true);
+
+ return GHES_CPER_OK;
+}
+
+/* Build table for the hardware error fw_cfg blob */
+void build_error_block(GArray *hardware_errors, BIOSLinker *linker)
+{
+ int i;
+
+ build_append_int_noprefix((void *)hardware_errors, 0,
+ GHES_ADDRESS_SIZE * ACPI_HEST_ERROR_SOURCE_COUNT);
+
+ for (i = 0; i < ACPI_HEST_ERROR_SOURCE_COUNT; i++)
+ /* Initialize Read ACK register, so GHES can be
+ * writeable in the first time
+ */
+ build_append_int_noprefix((void *)hardware_errors, 1, GHES_ADDRESS_SIZE);
+ /*
+ * Reserved the total size for ERRORS fw_cfg blob. For one GHES, it occupies
+ * two 64-bit size and one GHES_MAX_RAW_DATA_LENGTH size.
+ */
+ acpi_data_push(hardware_errors, (GHES_ADDRESS_SIZE * 2 +
+ GHES_MAX_RAW_DATA_LENGTH) * ACPI_HEST_ERROR_SOURCE_COUNT);
+
+ /* Allocate guest memory for the hardware error fw_cfg blob */
+ bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_errors,
+ 1, false);
+}
+
+void build_apei_ghes(GArray *table_data, GArray *hardware_errors,
+ BIOSLinker *linker)
+{
+ uint32_t i, block_offset, ghes_start = table_data->len;
+
+ /* Reserve table header size */
+ acpi_data_push(table_data, sizeof(AcpiTableHeader));
+
+ /* Set the error source counts */
+ build_append_int_noprefix(table_data, ACPI_HEST_ERROR_SOURCE_COUNT, 4);
+
+ for (i = 0; i < ACPI_HEST_ERROR_SOURCE_COUNT; i++) {
+ /* Generic Hardware Error Source version 2(GHESv2 - Type 10)
+ */
+ build_append_int_noprefix(table_data,
+ ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */
+ build_append_int_noprefix(table_data, cpu_to_le16(i), 2); /* source id */
+ build_append_int_noprefix(table_data, 0xffff, 2); /* related source id */
+ build_append_int_noprefix(table_data, 0, 1); /* flags */
+
+ build_append_int_noprefix(table_data, 1, 1); /* enabled */
+
+ /* Number of Records To Pre-allocate */
+ build_append_int_noprefix(table_data, 1, 4);
+ /* Max Sections Per Record */
+ build_append_int_noprefix(table_data, 1, 4);
+ /* Max Raw Data Length */
+ build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4);
+
+ /* Build error status address*/
+ build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */, 0);
+ bios_linker_loader_add_pointer(linker,
+ ACPI_BUILD_TABLE_FILE, ERROR_STATUS_ADDRESS_OFFSET(ghes_start, i),
+ GHES_ADDRESS_SIZE, GHES_ERRORS_FW_CFG_FILE, i * GHES_ADDRESS_SIZE);
+
+ /* Hardware Error Notification
+ * Now only enable GPIO-Signal and ARMv8 SEA notification types
+ */
+ if (i == 0) {
+ build_append_notify(table_data, ACPI_HEST_NOTIFY_GPIO, 28);
+ } else if (i == 1) {
+ build_append_notify(table_data, ACPI_HEST_NOTIFY_SEA, 28);
+ }
+
+ /* Error Status Block Length */
+ build_append_int_noprefix(table_data,
+ cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4);
+
+ /* Build Read ACK register */
+ build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */, 0);
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ READ_ACK_REGISTER_ADDRESS_OFFSET(ghes_start, i), GHES_ADDRESS_SIZE,
+ GHES_ERRORS_FW_CFG_FILE,
+ (ACPI_HEST_ERROR_SOURCE_COUNT + i) * GHES_ADDRESS_SIZE);
+
+ /* OSPM will read this value to acknowledge the error.
+ * ACPI 6.1/6.2: 18.3.2.8 Generic Hardware Error Source
+ * version 2 (GHESv2 - Type 10)
+ */
+ build_append_int_noprefix(table_data, cpu_to_le64(ReadAckPreserve), 8);
+ build_append_int_noprefix(table_data, cpu_to_le64(ReadAckWrite), 8);
+ }
+
+ block_offset = GHES_ADDRESS_SIZE * 2 * ACPI_HEST_ERROR_SOURCE_COUNT;
+
+ for (i = 0; i < ACPI_HEST_ERROR_SOURCE_COUNT; i++)
+ /* Patch address of generic error status block into
+ * the address register so OSPM can retrieve and read it.
+ */
+ bios_linker_loader_add_pointer(linker,
+ GHES_ERRORS_FW_CFG_FILE, GHES_ADDRESS_SIZE * i, GHES_ADDRESS_SIZE,
+ GHES_ERRORS_FW_CFG_FILE,
+ block_offset + i * GHES_MAX_RAW_DATA_LENGTH);
+
+ /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob */
+ bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE,
+ 0, GHES_ADDRESS_SIZE, GHES_ERRORS_FW_CFG_FILE, 0);
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + ghes_start), "HEST",
+ table_data->len - ghes_start, 1, NULL, "GHES");
+}
+
+static GhesState ges;
+void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error)
+{
+
+ size_t size = 2 * GHES_ADDRESS_SIZE + GHES_MAX_RAW_DATA_LENGTH;
+ size_t request_block_size = ACPI_HEST_ERROR_SOURCE_COUNT * size;
+
+ /* Create a read-only fw_cfg file for GHES */
+ fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data,
+ request_block_size);
+
+ /* Create a read-write fw_cfg file for Address */
+ fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL,
+ &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false);
+}
+
+bool ghes_update_guest(uint32_t notify, uint64_t physical_address)
+{
+ uint64_t error_block_addr, read_ack_register_addr;
+ int read_ack_register = 0, loop = 0;
+ uint64_t status_addr = le32_to_cpu(ges.ghes_addr_le);
+ bool ret = GHES_CPER_FAIL;
+
+ /* Relationship table between notification type and source id*/
+ const uint8_t error_source_id[] = { 0, 0, 0, 0, 0, 0, 0, 0, 1};
+
+ /*
+ * | +---------------------+ ges.ghes_addr_le
+ * | |error_status_address0|
+ * | +---------------------+
+ * | |error_status_address1|
+ * | +---------------------+ --+--
+ * | | ............. | GHES_ADDRESS_SIZE
+ * | +---------------------+ --+--
+ * | |error_status_addressN|
+ * | +---------------------+
+ * | | read_ack_register0 |
+ * | +---------------------+ --+--
+ * | | read_ack_register1 | GHES_ADDRESS_SIZE
+ * | +---------------------+ --+--
+ * | | ............. |
+ * | +---------------------+
+ * | | read_ack_registerN |
+ * | +---------------------+ --+--
+ * | | CPER | |
+ * | | CPER | |
+ * | | .... | GHES_MAX_RAW_DATA_LENGT
+ * | | CPER | |
+ * | +---------------------+ --+--
+ * | | CPER |
+ * | | CPER |
+ * | | .... |
+ * | | CPER |
+ * | +---------------------+
+ * | | .......... |
+ * | +---------------------+
+ * | | CPER |
+ * | | CPER |
+ * | | .... |
+ * | | CPER |
+ * | +---------------------+
+ */
+ if (physical_address && notify < ACPI_HEST_NOTIFY_RESERVED) {
+ status_addr += error_source_id[notify] * GHES_ADDRESS_SIZE;
+
+ cpu_physical_memory_read(status_addr, &error_block_addr,
+ GHES_ADDRESS_SIZE);
+ read_ack_register_addr = status_addr +
+ ACPI_HEST_ERROR_SOURCE_COUNT * GHES_ADDRESS_SIZE;
+retry:
+ cpu_physical_memory_read(read_ack_register_addr,
+ &read_ack_register, GHES_ADDRESS_SIZE);
+
+ /* zero means OSPM does not acknowledge the error */
+ if (!read_ack_register) {
+ if (loop < 3) {
+ usleep(100 * 1000);
+ loop++;
+ goto retry;
+ } else {
+ error_report("Last time OSPM does not acknowledge the error,"
+ " record CPER failed this time, set the ack value to"
+ " avoid blocking next time CPER record! exit");
+ read_ack_register = 1;
+ cpu_physical_memory_write(read_ack_register_addr,
+ &read_ack_register, GHES_ADDRESS_SIZE);
+ }
+ } else {
+ if (error_block_addr) {
+ read_ack_register = 0;
+ cpu_physical_memory_write(read_ack_register_addr,
+ &read_ack_register, GHES_ADDRESS_SIZE);
+ ret = ghes_record_cper(error_block_addr, physical_address);
+ }
+ }
+ }
+ return ret;
+}
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3d78ff6..7b397c3 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -45,6 +45,7 @@
#include "hw/arm/virt.h"
#include "sysemu/numa.h"
#include "kvm_arm.h"
+#include "hw/acpi/hest_ghes.h"
#define ARM_SPI_BASE 32
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
@@ -771,6 +772,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_spcr(tables_blob, tables->linker, vms);
+ acpi_add_table(table_offsets, tables_blob);
+ build_error_block(tables->hardware_errors, tables->linker);
+ build_apei_ghes(tables_blob, tables->hardware_errors, tables->linker);
+
+
if (nb_numa_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, vms);
@@ -887,6 +893,8 @@ void virt_acpi_setup(VirtMachineState *vms)
fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
acpi_data_len(tables.tcpalog));
+ ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
+
build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
ACPI_BUILD_RSDP_FILE, 0);
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 88d0738..7f7b55c 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -211,6 +211,7 @@ struct AcpiBuildTables {
GArray *rsdp;
GArray *tcpalog;
GArray *vmgenid;
+ GArray *hardware_errors;
BIOSLinker *linker;
} AcpiBuildTables;
diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h
new file mode 100644
index 0000000..e65a665
--- /dev/null
+++ b/include/hw/acpi/hest_ghes.h
@@ -0,0 +1,83 @@
+/* Support for generating APEI tables and passing them to Guests
+ *
+ * Copyright (C) 2017 HuaWei Corporation.
+ *
+ * Author: Dongjiu Geng <gengdongjiu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef ACPI_GHES_H
+#define ACPI_GHES_H
+
+#include "hw/acpi/bios-linker-loader.h"
+
+#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors"
+#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr"
+
+#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20
+#define GHES_NOTIFICATION_STRUCTURE 32
+
+#define GHES_CPER_OK 1
+#define GHES_CPER_FAIL 0
+
+/* The max size in bytes for one error block */
+#define GHES_MAX_RAW_DATA_LENGTH 0x1000
+
+/* Now only have GPIO-Signal and ARMv8 SEA notification types error source
+ */
+#define ACPI_HEST_ERROR_SOURCE_COUNT 2
+
+/* The Address field is 64-bit size, ACPI 2.0/3.0: 5.2.3.1 Generic Address
+ * Structure
+ */
+#define GHES_ADDRESS_SIZE 8
+
+#define GHES_DATA_LENGTH 72
+#define GHES_CPER_LENGTH 80
+
+#define ReadAckPreserve 0xfffffffe
+#define ReadAckWrite 0x1
+
+/*
+ * | +--------------------------+ 0
+ * | | Header |
+ * | +--------------------------+ 40---+-
+ * | | ................. | |
+ * | | error_status_address-----+ 60 |
+ * | | ................. | |
+ * | | read_ack_register--------+ 104 92
+ * | | read_ack_preserve | |
+ * | | read_ack_write | |
+ * + +--------------------------+ 132--+-
+ *
+ * From above HEST and GHES definition, the error status address offset is 60;
+ * the Read ack register offset is 104, the whole size of GHESv2 is 92
+ */
+#define ERROR_STATUS_ADDRESS_OFFSET(start_addr, i) (start_addr + 60 + \
+ offsetof(struct AcpiGenericAddress, address) + i * 92)
+
+#define READ_ACK_REGISTER_ADDRESS_OFFSET(start_addr, i) (start_addr + 104 + \
+ offsetof(struct AcpiGenericAddress, address) + i * 92)
+
+typedef struct GhesState {
+ uint64_t ghes_addr_le;
+} GhesState;
+
+void build_apei_ghes(GArray *table_data, GArray *hardware_error,
+ BIOSLinker *linker);
+void build_error_block(GArray *hardware_errors, BIOSLinker *linker);
+void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors);
+bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr);
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 02/12] ACPI: Add APEI GHES table generation and CPER record support
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
This implements APEI GHES Table generation when OS boot and
record CPER in runtime via fw_cfg blobs. After a CPER info is
recorded into guest memory, it need to inject whatever interrupt
(or assert whatever GPIO line) to notify the guest. About the
detailed design or implementation, please see the "hest_ghes.txt"
in the doc folder.
Now we only support three types of GHESv2, which are GPIO-Signal,
ARMv8 SEA and ARMv8 SEI. Afterwards, we can extend the supported
type if needed. For the CPER section type, currently it is memory
section because kernel manly wants userspace to handle the memory
section errors.
For GHESv2 error source, the OSPM must acknowledges the error via
Read Ack register. So user space must check the ack value before
recording a new CPER to avoid read-write race condition.
Suggested-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
The basic solution is suggested by Laszlo in [1]
[1]: https://lkml.org/lkml/2017/3/29/342
---
hw/acpi/aml-build.c | 2 +
hw/acpi/hest_ghes.c | 360 ++++++++++++++++++++++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 8 +
include/hw/acpi/aml-build.h | 1 +
include/hw/acpi/hest_ghes.h | 83 ++++++++++
5 files changed, 454 insertions(+)
create mode 100644 hw/acpi/hest_ghes.c
create mode 100644 include/hw/acpi/hest_ghes.h
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 36a6cc4..6849e5f 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1561,6 +1561,7 @@ void acpi_build_tables_init(AcpiBuildTables *tables)
tables->table_data = g_array_new(false, true /* clear */, 1);
tables->tcpalog = g_array_new(false, true /* clear */, 1);
tables->vmgenid = g_array_new(false, true /* clear */, 1);
+ tables->hardware_errors = g_array_new(false, true /* clear */, 1);
tables->linker = bios_linker_loader_init();
}
@@ -1571,6 +1572,7 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
g_array_free(tables->table_data, true);
g_array_free(tables->tcpalog, mfre);
g_array_free(tables->vmgenid, mfre);
+ g_array_free(tables->hardware_errors, mfre);
}
/* Build rsdt table */
diff --git a/hw/acpi/hest_ghes.c b/hw/acpi/hest_ghes.c
new file mode 100644
index 0000000..08f8bf1
--- /dev/null
+++ b/hw/acpi/hest_ghes.c
@@ -0,0 +1,360 @@
+/* Support for generating APEI tables and passing them to Guests
+ *
+ * Copyright (C) 2017 HuaWei Corporation.
+ *
+ * Author: Dongjiu Geng <gengdongjiu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/aml-build.h"
+#include "hw/acpi/hest_ghes.h"
+#include "hw/nvram/fw_cfg.h"
+#include "sysemu/sysemu.h"
+#include "qemu/error-report.h"
+
+/* Generic Error Status Block
+ * ACPI 4.0: 17.3.2.6.1 Generic Error Data
+ */
+static void build_append_gesb(GArray *table, uint32_t block_status,
+ uint32_t raw_data_offset, uint32_t raw_data_length,
+ uint32_t data_length, uint32_t error_severity)
+{
+ build_append_int_noprefix(table, block_status, 4);
+ build_append_int_noprefix(table, raw_data_offset, 4);
+ build_append_int_noprefix(table, raw_data_length, 4);
+ build_append_int_noprefix(table, data_length, 4);
+ build_append_int_noprefix(table, error_severity, 4);
+}
+
+/* Generic Error Data Entry
+ * ACPI 4.0: 17.3.2.6.1 Generic Error Data
+ */
+static void build_append_gede(GArray *table, const char *section_type,
+ const uint32_t error_severity, const uint16_t revision,
+ const uint32_t error_data_length)
+{
+ int i;
+
+ for (i = 0; i < 16; i++) {
+ build_append_int_noprefix(table, section_type[i], 1);
+ }
+
+ build_append_int_noprefix(table, error_severity, 4);
+ build_append_int_noprefix(table, revision, 2);
+ build_append_int_noprefix(table, 0, 2);
+ build_append_int_noprefix(table, error_data_length, 4);
+ build_append_int_noprefix(table, 0, 44);
+}
+
+/* Generic Address Structure (GAS)
+ * ACPI 2.0/3.0: 5.2.3.1 Generic Address Structure
+ * 2.0 compat note:
+ * @access_width must be 0, see ACPI 2.0:Table 5-1
+ */
+static void build_append_gas(GArray *table, AmlRegionSpace as,
+ uint8_t bit_width, uint8_t bit_offset,
+ uint8_t access_width, uint64_t address)
+{
+ build_append_int_noprefix(table, as, 1);
+ build_append_int_noprefix(table, bit_width, 1);
+ build_append_int_noprefix(table, bit_offset, 1);
+ build_append_int_noprefix(table, access_width, 1);
+ build_append_int_noprefix(table, address, 8);
+}
+
+/* Hardware Error Notification
+ * ACPI 4.0: 17.3.2.7 Hardware Error Notification
+ */
+static void build_append_notify(GArray *table, const uint8_t type,
+ uint8_t length)
+{
+ build_append_int_noprefix(table, type, 1); /* type */
+ build_append_int_noprefix(table, length, 1);
+ build_append_int_noprefix(table, 0, 26);
+}
+
+static int ghes_record_cper(uint64_t error_block_address,
+ uint64_t error_physical_addr)
+{
+ GArray *block;
+ uint64_t current_block_length;
+ uint32_t data_length;
+ /* memory section */
+ char mem_section_id_le[] = {0x14, 0x11, 0xBC, 0xA5, 0x64, 0x6F, 0xDE,
+ 0x4E, 0xB8, 0x63, 0x3E, 0x83, 0xED, 0x7C,
+ 0x83, 0xB1};
+
+ block = g_array_new(false, true /* clear */, 1);
+
+ cpu_physical_memory_read(error_block_address +
+ offsetof(AcpiGenericErrorStatus, data_length), &data_length, 4);
+
+ current_block_length = sizeof(AcpiGenericErrorStatus) + data_length;
+
+ data_length += GHES_DATA_LENGTH;
+ data_length += GHES_CPER_LENGTH;
+
+ /* check whether it runs out of the preallocated memory */
+ if ((data_length + sizeof(AcpiGenericErrorStatus)) > GHES_MAX_RAW_DATA_LENGTH) {
+ error_report("Record CPER out of boundary!!!");
+ return GHES_CPER_FAIL;
+ }
+
+ build_append_gesb(block, cpu_to_le32(ACPI_GEBS_UNCORRECTABLE), 0, 0,
+ cpu_to_le32(data_length), cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE));
+
+ /* Write back the Generic Error Status Block to guest memory */
+ cpu_physical_memory_write(error_block_address, block->data,
+ block->len);
+
+ data_length = block->len;
+
+ build_append_gede(block, mem_section_id_le,
+ cpu_to_le32(ACPI_CPER_SEV_RECOVERABLE), cpu_to_le32(0x300),
+ cpu_to_le32(80)/* the total size of Memory Error Record */);
+
+ /*
+ * Memory Error Record
+ */
+ build_append_int_noprefix(block,
+ (1UL << 14) | /* Type Valid */
+ (1UL << 1) /* Physical Address Valid */,
+ 8);
+ /* Memory error status information */
+ build_append_int_noprefix(block, 0, 8);
+ /* The physical address at which the memory error occurred */
+ build_append_int_noprefix(block, error_physical_addr, 8);
+ build_append_int_noprefix(block, 0, 48);
+ /* Hard code to Multi-bit ECC error */
+ build_append_int_noprefix(block, 3 /* Multi-bit ECC */, 1);
+ build_append_int_noprefix(block, 0, 7);
+
+ /* Write back the Generic Error Data Entry to guest memory */
+ cpu_physical_memory_write(error_block_address + current_block_length,
+ block->data + data_length, block->len - data_length);
+
+ g_array_free(block, true);
+
+ return GHES_CPER_OK;
+}
+
+/* Build table for the hardware error fw_cfg blob */
+void build_error_block(GArray *hardware_errors, BIOSLinker *linker)
+{
+ int i;
+
+ build_append_int_noprefix((void *)hardware_errors, 0,
+ GHES_ADDRESS_SIZE * ACPI_HEST_ERROR_SOURCE_COUNT);
+
+ for (i = 0; i < ACPI_HEST_ERROR_SOURCE_COUNT; i++)
+ /* Initialize Read ACK register, so GHES can be
+ * writeable in the first time
+ */
+ build_append_int_noprefix((void *)hardware_errors, 1, GHES_ADDRESS_SIZE);
+ /*
+ * Reserved the total size for ERRORS fw_cfg blob. For one GHES, it occupies
+ * two 64-bit size and one GHES_MAX_RAW_DATA_LENGTH size.
+ */
+ acpi_data_push(hardware_errors, (GHES_ADDRESS_SIZE * 2 +
+ GHES_MAX_RAW_DATA_LENGTH) * ACPI_HEST_ERROR_SOURCE_COUNT);
+
+ /* Allocate guest memory for the hardware error fw_cfg blob */
+ bios_linker_loader_alloc(linker, GHES_ERRORS_FW_CFG_FILE, hardware_errors,
+ 1, false);
+}
+
+void build_apei_ghes(GArray *table_data, GArray *hardware_errors,
+ BIOSLinker *linker)
+{
+ uint32_t i, block_offset, ghes_start = table_data->len;
+
+ /* Reserve table header size */
+ acpi_data_push(table_data, sizeof(AcpiTableHeader));
+
+ /* Set the error source counts */
+ build_append_int_noprefix(table_data, ACPI_HEST_ERROR_SOURCE_COUNT, 4);
+
+ for (i = 0; i < ACPI_HEST_ERROR_SOURCE_COUNT; i++) {
+ /* Generic Hardware Error Source version 2(GHESv2 - Type 10)
+ */
+ build_append_int_noprefix(table_data,
+ ACPI_HEST_SOURCE_GENERIC_ERROR_V2, 2); /* type */
+ build_append_int_noprefix(table_data, cpu_to_le16(i), 2); /* source id */
+ build_append_int_noprefix(table_data, 0xffff, 2); /* related source id */
+ build_append_int_noprefix(table_data, 0, 1); /* flags */
+
+ build_append_int_noprefix(table_data, 1, 1); /* enabled */
+
+ /* Number of Records To Pre-allocate */
+ build_append_int_noprefix(table_data, 1, 4);
+ /* Max Sections Per Record */
+ build_append_int_noprefix(table_data, 1, 4);
+ /* Max Raw Data Length */
+ build_append_int_noprefix(table_data, GHES_MAX_RAW_DATA_LENGTH, 4);
+
+ /* Build error status address*/
+ build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */, 0);
+ bios_linker_loader_add_pointer(linker,
+ ACPI_BUILD_TABLE_FILE, ERROR_STATUS_ADDRESS_OFFSET(ghes_start, i),
+ GHES_ADDRESS_SIZE, GHES_ERRORS_FW_CFG_FILE, i * GHES_ADDRESS_SIZE);
+
+ /* Hardware Error Notification
+ * Now only enable GPIO-Signal and ARMv8 SEA notification types
+ */
+ if (i == 0) {
+ build_append_notify(table_data, ACPI_HEST_NOTIFY_GPIO, 28);
+ } else if (i == 1) {
+ build_append_notify(table_data, ACPI_HEST_NOTIFY_SEA, 28);
+ }
+
+ /* Error Status Block Length */
+ build_append_int_noprefix(table_data,
+ cpu_to_le32(GHES_MAX_RAW_DATA_LENGTH), 4);
+
+ /* Build Read ACK register */
+ build_append_gas(table_data, AML_SYSTEM_MEMORY, 0x40, 0, 4 /* QWord access */, 0);
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ READ_ACK_REGISTER_ADDRESS_OFFSET(ghes_start, i), GHES_ADDRESS_SIZE,
+ GHES_ERRORS_FW_CFG_FILE,
+ (ACPI_HEST_ERROR_SOURCE_COUNT + i) * GHES_ADDRESS_SIZE);
+
+ /* OSPM will read this value to acknowledge the error.
+ * ACPI 6.1/6.2: 18.3.2.8 Generic Hardware Error Source
+ * version 2 (GHESv2 - Type 10)
+ */
+ build_append_int_noprefix(table_data, cpu_to_le64(ReadAckPreserve), 8);
+ build_append_int_noprefix(table_data, cpu_to_le64(ReadAckWrite), 8);
+ }
+
+ block_offset = GHES_ADDRESS_SIZE * 2 * ACPI_HEST_ERROR_SOURCE_COUNT;
+
+ for (i = 0; i < ACPI_HEST_ERROR_SOURCE_COUNT; i++)
+ /* Patch address of generic error status block into
+ * the address register so OSPM can retrieve and read it.
+ */
+ bios_linker_loader_add_pointer(linker,
+ GHES_ERRORS_FW_CFG_FILE, GHES_ADDRESS_SIZE * i, GHES_ADDRESS_SIZE,
+ GHES_ERRORS_FW_CFG_FILE,
+ block_offset + i * GHES_MAX_RAW_DATA_LENGTH);
+
+ /* Patch address of ERRORS fw_cfg blob into the ADDR fw_cfg blob */
+ bios_linker_loader_write_pointer(linker, GHES_DATA_ADDR_FW_CFG_FILE,
+ 0, GHES_ADDRESS_SIZE, GHES_ERRORS_FW_CFG_FILE, 0);
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + ghes_start), "HEST",
+ table_data->len - ghes_start, 1, NULL, "GHES");
+}
+
+static GhesState ges;
+void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_error)
+{
+
+ size_t size = 2 * GHES_ADDRESS_SIZE + GHES_MAX_RAW_DATA_LENGTH;
+ size_t request_block_size = ACPI_HEST_ERROR_SOURCE_COUNT * size;
+
+ /* Create a read-only fw_cfg file for GHES */
+ fw_cfg_add_file(s, GHES_ERRORS_FW_CFG_FILE, hardware_error->data,
+ request_block_size);
+
+ /* Create a read-write fw_cfg file for Address */
+ fw_cfg_add_file_callback(s, GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL,
+ &ges.ghes_addr_le, sizeof(ges.ghes_addr_le), false);
+}
+
+bool ghes_update_guest(uint32_t notify, uint64_t physical_address)
+{
+ uint64_t error_block_addr, read_ack_register_addr;
+ int read_ack_register = 0, loop = 0;
+ uint64_t status_addr = le32_to_cpu(ges.ghes_addr_le);
+ bool ret = GHES_CPER_FAIL;
+
+ /* Relationship table between notification type and source id*/
+ const uint8_t error_source_id[] = { 0, 0, 0, 0, 0, 0, 0, 0, 1};
+
+ /*
+ * | +---------------------+ ges.ghes_addr_le
+ * | |error_status_address0|
+ * | +---------------------+
+ * | |error_status_address1|
+ * | +---------------------+ --+--
+ * | | ............. | GHES_ADDRESS_SIZE
+ * | +---------------------+ --+--
+ * | |error_status_addressN|
+ * | +---------------------+
+ * | | read_ack_register0 |
+ * | +---------------------+ --+--
+ * | | read_ack_register1 | GHES_ADDRESS_SIZE
+ * | +---------------------+ --+--
+ * | | ............. |
+ * | +---------------------+
+ * | | read_ack_registerN |
+ * | +---------------------+ --+--
+ * | | CPER | |
+ * | | CPER | |
+ * | | .... | GHES_MAX_RAW_DATA_LENGT
+ * | | CPER | |
+ * | +---------------------+ --+--
+ * | | CPER |
+ * | | CPER |
+ * | | .... |
+ * | | CPER |
+ * | +---------------------+
+ * | | .......... |
+ * | +---------------------+
+ * | | CPER |
+ * | | CPER |
+ * | | .... |
+ * | | CPER |
+ * | +---------------------+
+ */
+ if (physical_address && notify < ACPI_HEST_NOTIFY_RESERVED) {
+ status_addr += error_source_id[notify] * GHES_ADDRESS_SIZE;
+
+ cpu_physical_memory_read(status_addr, &error_block_addr,
+ GHES_ADDRESS_SIZE);
+ read_ack_register_addr = status_addr +
+ ACPI_HEST_ERROR_SOURCE_COUNT * GHES_ADDRESS_SIZE;
+retry:
+ cpu_physical_memory_read(read_ack_register_addr,
+ &read_ack_register, GHES_ADDRESS_SIZE);
+
+ /* zero means OSPM does not acknowledge the error */
+ if (!read_ack_register) {
+ if (loop < 3) {
+ usleep(100 * 1000);
+ loop++;
+ goto retry;
+ } else {
+ error_report("Last time OSPM does not acknowledge the error,"
+ " record CPER failed this time, set the ack value to"
+ " avoid blocking next time CPER record! exit");
+ read_ack_register = 1;
+ cpu_physical_memory_write(read_ack_register_addr,
+ &read_ack_register, GHES_ADDRESS_SIZE);
+ }
+ } else {
+ if (error_block_addr) {
+ read_ack_register = 0;
+ cpu_physical_memory_write(read_ack_register_addr,
+ &read_ack_register, GHES_ADDRESS_SIZE);
+ ret = ghes_record_cper(error_block_addr, physical_address);
+ }
+ }
+ }
+ return ret;
+}
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3d78ff6..7b397c3 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -45,6 +45,7 @@
#include "hw/arm/virt.h"
#include "sysemu/numa.h"
#include "kvm_arm.h"
+#include "hw/acpi/hest_ghes.h"
#define ARM_SPI_BASE 32
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
@@ -771,6 +772,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_spcr(tables_blob, tables->linker, vms);
+ acpi_add_table(table_offsets, tables_blob);
+ build_error_block(tables->hardware_errors, tables->linker);
+ build_apei_ghes(tables_blob, tables->hardware_errors, tables->linker);
+
+
if (nb_numa_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
build_srat(tables_blob, tables->linker, vms);
@@ -887,6 +893,8 @@ void virt_acpi_setup(VirtMachineState *vms)
fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
acpi_data_len(tables.tcpalog));
+ ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
+
build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
ACPI_BUILD_RSDP_FILE, 0);
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 88d0738..7f7b55c 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -211,6 +211,7 @@ struct AcpiBuildTables {
GArray *rsdp;
GArray *tcpalog;
GArray *vmgenid;
+ GArray *hardware_errors;
BIOSLinker *linker;
} AcpiBuildTables;
diff --git a/include/hw/acpi/hest_ghes.h b/include/hw/acpi/hest_ghes.h
new file mode 100644
index 0000000..e65a665
--- /dev/null
+++ b/include/hw/acpi/hest_ghes.h
@@ -0,0 +1,83 @@
+/* Support for generating APEI tables and passing them to Guests
+ *
+ * Copyright (C) 2017 HuaWei Corporation.
+ *
+ * Author: Dongjiu Geng <gengdongjiu@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef ACPI_GHES_H
+#define ACPI_GHES_H
+
+#include "hw/acpi/bios-linker-loader.h"
+
+#define GHES_ERRORS_FW_CFG_FILE "etc/hardware_errors"
+#define GHES_DATA_ADDR_FW_CFG_FILE "etc/hardware_errors_addr"
+
+#define GHES_ERROR_STATUS_ADDRESS_OFFSET 20
+#define GHES_NOTIFICATION_STRUCTURE 32
+
+#define GHES_CPER_OK 1
+#define GHES_CPER_FAIL 0
+
+/* The max size in bytes for one error block */
+#define GHES_MAX_RAW_DATA_LENGTH 0x1000
+
+/* Now only have GPIO-Signal and ARMv8 SEA notification types error source
+ */
+#define ACPI_HEST_ERROR_SOURCE_COUNT 2
+
+/* The Address field is 64-bit size, ACPI 2.0/3.0: 5.2.3.1 Generic Address
+ * Structure
+ */
+#define GHES_ADDRESS_SIZE 8
+
+#define GHES_DATA_LENGTH 72
+#define GHES_CPER_LENGTH 80
+
+#define ReadAckPreserve 0xfffffffe
+#define ReadAckWrite 0x1
+
+/*
+ * | +--------------------------+ 0
+ * | | Header |
+ * | +--------------------------+ 40---+-
+ * | | ................. | |
+ * | | error_status_address-----+ 60 |
+ * | | ................. | |
+ * | | read_ack_register--------+ 104 92
+ * | | read_ack_preserve | |
+ * | | read_ack_write | |
+ * + +--------------------------+ 132--+-
+ *
+ * From above HEST and GHES definition, the error status address offset is 60;
+ * the Read ack register offset is 104, the whole size of GHESv2 is 92
+ */
+#define ERROR_STATUS_ADDRESS_OFFSET(start_addr, i) (start_addr + 60 + \
+ offsetof(struct AcpiGenericAddress, address) + i * 92)
+
+#define READ_ACK_REGISTER_ADDRESS_OFFSET(start_addr, i) (start_addr + 104 + \
+ offsetof(struct AcpiGenericAddress, address) + i * 92)
+
+typedef struct GhesState {
+ uint64_t ghes_addr_le;
+} GhesState;
+
+void build_apei_ghes(GArray *table_data, GArray *hardware_error,
+ BIOSLinker *linker);
+void build_error_block(GArray *hardware_errors, BIOSLinker *linker);
+void ghes_add_fw_cfg(FWCfgState *s, GArray *hardware_errors);
+bool ghes_update_guest(uint32_t notify, uint64_t error_physical_addr);
+#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 03/12] docs: APEI GHES generation description
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add APEI/GHES description document
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Igor's comments to add a doc
---
docs/specs/acpi_hest_ghes.txt | 96 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 docs/specs/acpi_hest_ghes.txt
diff --git a/docs/specs/acpi_hest_ghes.txt b/docs/specs/acpi_hest_ghes.txt
new file mode 100644
index 0000000..df28757
--- /dev/null
+++ b/docs/specs/acpi_hest_ghes.txt
@@ -0,0 +1,96 @@
+Generating APEI tables and record CPER
+=============================
+
+Copyright (C) 2017 HuaWei Corporation.
+
+Design Details:
+-------------------
+
+ etc/acpi/tables etc/hardware_errors
+ ==================== ==========================================
++ +--------------------------+ +------------------+
+| | HEST | | address | +--------------+
+| +--------------------------+ | registers | | Error Status |
+| | GHES1 | | +----------------+ | Data Block 1 |
+| +--------------------------+ +--------->| |status_address1 |------------->| +------------+
+| | ................. | | | +----------------+ | | CPER |
+| | error_status_address-----+-+ +------->| |status_address2 |----------+ | | CPER |
+| | ................. | | | +----------------+ | | | .... |
+| | read_ack_register--------+-+ | | ............. | | | | CPER |
+| | read_ack_preserve | | | +------------------+ | | +------------+
+| | read_ack_write | | | +----->| |status_addressN |--------+ | | Error Status |
++ +--------------------------+ | | | | +----------------+ | | | Data Block 2 |
+| | GHES2 | +-+-+----->| | ack_value1 | | +-->| +------------+
++ +--------------------------+ | | | +----------------+ | | | CPER |
+| | ................. | | | +--->| | ack_value2 | | | | CPER |
+| | error_status_address-----+---+ | | | +----------------+ | | | .... |
+| | ................. | | | | | ............. | | | | CPER |
+| | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+
+| | read_ack_preserve | | +->| | ack_valueN | | | |.......... |
+| | read_ack_write | | | | +----------------+ | | +------------+
++ +--------------------------| | | | | Error Status |
+| | ............... | | | | | Data Block N |
++ +--------------------------+ | | +---->| +------------+
+| | GHESN | | | | | CPER |
++ +--------------------------+ | | | | CPER |
+| | ................. | | | | | .... |
+| | error_status_address-----+-----+ | | | CPER |
+| | ................. | | +-+------------+
+| | read_ack_register--------+---------+
+| | read_ack_preserve |
+| | read_ack_write |
++ +--------------------------+
+
+(1) QEMU generates the ACPI HEST table. This table goes in the current
+ "etc/acpi/tables" fw_cfg blob. Each error source has different
+ notification type.
+
+(2) A new fw_cfg blob called "etc/hardware_errors" is introduced. QEMU
+ also need to populate this blob. The "etc/hardwre_errors" fw_cfg blob contains
+ one address registers table and one Error Status Data Block table, all
+ of which are pre-allocated.
+
+(3) The address registers table contains N Error Status Address entries
+ and N Read Ack Address entries, the size for each entry is 8-byte. The
+ Error Status Data Block table contains N Error Status Data Block entry,
+ the size for each entry is 0x1000(4096) bytes. The total size for
+ "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) bytes
+
+(4) QEMU generates the ACPI linker/loader script for the firmware
+
+(4a) The HEST table is part of "etc/acpi/tables", which the firmware
+ already allocates memory for it and downloads, because QEMU already
+ generates an ALLOCATE linker/loader command for it.
+
+(4b) QEMU creates another ALLOCATE command for the "etc/hardware_errors"
+ blob. The firmware allocates memory for this blob,
+ and downloads it.
+
+(5) QEMU generates, N ADD_POINTER commands, which patch address in the
+ "Error Status Address" fields of the HEST table with a pointer to the
+ corresponding address registers in the downloaded "etc/hardware_errors" blob.
+
+(6) QEMU generates N ADD_POINTER commands for the firmware, pointing the
+ address registers (located in guest memory, in the downloaded
+ "etc/hardware_errors" blob) to the respective Error Status Data Blocks.
+
+(7) QEMU Defines a third, write-only fw_cfg blob, called "etc/hardware_errors_addr".
+ Through that blob, the firmware can send back the guest-side allocation addresses
+ to QEMU. The "etc/hardware_errors_addr" blob contains a 8-byte entry. QEMU generates
+ a single WRITE_POINTER commands for the firmware, the firmware will write the start
+ address of status address register back to fw_cfg file "etc/hardware_errors_addr".
+ Then Qemu will know the Error Status Data Block for every error source. Each of Error
+ Status Data Block has fixed size which is 0x1000.
+
+(8) When QEMU gets SIGBUS from the kernel, QEMU format the CPER right into guest
+ memory, and then inject whatever interrupt (or assert whatever GPIO line) which is
+ necessary for notifying the guest.
+
+(9) This notification (in virtual hardware) can either be handled by the
+ guest kernel stand-alone, or else the guest kernel can invoke an ACPI
+ event handler method with it. The ACPI event handler method could
+ invoke the specific guest kernel driver for error handling via a
+ Notify() operation.
+
+For the above design, it would leave the firmware alone after OS boot and firmware no need
+to care about HEST, GHES, CPER.
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 03/12] docs: APEI GHES generation description
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add APEI/GHES description document
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Igor's comments to add a doc
---
docs/specs/acpi_hest_ghes.txt | 96 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 docs/specs/acpi_hest_ghes.txt
diff --git a/docs/specs/acpi_hest_ghes.txt b/docs/specs/acpi_hest_ghes.txt
new file mode 100644
index 0000000..df28757
--- /dev/null
+++ b/docs/specs/acpi_hest_ghes.txt
@@ -0,0 +1,96 @@
+Generating APEI tables and record CPER
+=============================
+
+Copyright (C) 2017 HuaWei Corporation.
+
+Design Details:
+-------------------
+
+ etc/acpi/tables etc/hardware_errors
+ ==================== ==========================================
++ +--------------------------+ +------------------+
+| | HEST | | address | +--------------+
+| +--------------------------+ | registers | | Error Status |
+| | GHES1 | | +----------------+ | Data Block 1 |
+| +--------------------------+ +--------->| |status_address1 |------------->| +------------+
+| | ................. | | | +----------------+ | | CPER |
+| | error_status_address-----+-+ +------->| |status_address2 |----------+ | | CPER |
+| | ................. | | | +----------------+ | | | .... |
+| | read_ack_register--------+-+ | | ............. | | | | CPER |
+| | read_ack_preserve | | | +------------------+ | | +------------+
+| | read_ack_write | | | +----->| |status_addressN |--------+ | | Error Status |
++ +--------------------------+ | | | | +----------------+ | | | Data Block 2 |
+| | GHES2 | +-+-+----->| | ack_value1 | | +-->| +------------+
++ +--------------------------+ | | | +----------------+ | | | CPER |
+| | ................. | | | +--->| | ack_value2 | | | | CPER |
+| | error_status_address-----+---+ | | | +----------------+ | | | .... |
+| | ................. | | | | | ............. | | | | CPER |
+| | read_ack_register--------+-----+-+ | +----------------+ | +-+------------+
+| | read_ack_preserve | | +->| | ack_valueN | | | |.......... |
+| | read_ack_write | | | | +----------------+ | | +------------+
++ +--------------------------| | | | | Error Status |
+| | ............... | | | | | Data Block N |
++ +--------------------------+ | | +---->| +------------+
+| | GHESN | | | | | CPER |
++ +--------------------------+ | | | | CPER |
+| | ................. | | | | | .... |
+| | error_status_address-----+-----+ | | | CPER |
+| | ................. | | +-+------------+
+| | read_ack_register--------+---------+
+| | read_ack_preserve |
+| | read_ack_write |
++ +--------------------------+
+
+(1) QEMU generates the ACPI HEST table. This table goes in the current
+ "etc/acpi/tables" fw_cfg blob. Each error source has different
+ notification type.
+
+(2) A new fw_cfg blob called "etc/hardware_errors" is introduced. QEMU
+ also need to populate this blob. The "etc/hardwre_errors" fw_cfg blob contains
+ one address registers table and one Error Status Data Block table, all
+ of which are pre-allocated.
+
+(3) The address registers table contains N Error Status Address entries
+ and N Read Ack Address entries, the size for each entry is 8-byte. The
+ Error Status Data Block table contains N Error Status Data Block entry,
+ the size for each entry is 0x1000(4096) bytes. The total size for
+ "etc/hardware_errors" fw_cfg blob is (N * 8 * 2 + N * 4096) bytes
+
+(4) QEMU generates the ACPI linker/loader script for the firmware
+
+(4a) The HEST table is part of "etc/acpi/tables", which the firmware
+ already allocates memory for it and downloads, because QEMU already
+ generates an ALLOCATE linker/loader command for it.
+
+(4b) QEMU creates another ALLOCATE command for the "etc/hardware_errors"
+ blob. The firmware allocates memory for this blob,
+ and downloads it.
+
+(5) QEMU generates, N ADD_POINTER commands, which patch address in the
+ "Error Status Address" fields of the HEST table with a pointer to the
+ corresponding address registers in the downloaded "etc/hardware_errors" blob.
+
+(6) QEMU generates N ADD_POINTER commands for the firmware, pointing the
+ address registers (located in guest memory, in the downloaded
+ "etc/hardware_errors" blob) to the respective Error Status Data Blocks.
+
+(7) QEMU Defines a third, write-only fw_cfg blob, called "etc/hardware_errors_addr".
+ Through that blob, the firmware can send back the guest-side allocation addresses
+ to QEMU. The "etc/hardware_errors_addr" blob contains a 8-byte entry. QEMU generates
+ a single WRITE_POINTER commands for the firmware, the firmware will write the start
+ address of status address register back to fw_cfg file "etc/hardware_errors_addr".
+ Then Qemu will know the Error Status Data Block for every error source. Each of Error
+ Status Data Block has fixed size which is 0x1000.
+
+(8) When QEMU gets SIGBUS from the kernel, QEMU format the CPER right into guest
+ memory, and then inject whatever interrupt (or assert whatever GPIO line) which is
+ necessary for notifying the guest.
+
+(9) This notification (in virtual hardware) can either be handled by the
+ guest kernel stand-alone, or else the guest kernel can invoke an ACPI
+ event handler method with it. The ACPI event handler method could
+ invoke the specific guest kernel driver for error handling via a
+ Notify() operation.
+
+For the above design, it would leave the firmware alone after OS boot and firmware no need
+to care about HEST, GHES, CPER.
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 04/12] ACPI: enable APEI GHES in the configure file and build it
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add CONFIG_ACPI_APEI configuration in the arm-softmmu.mak
and add build choice in the Makefile.objs.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/acpi/Makefile.objs | 1 +
2 files changed, 2 insertions(+)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index bbdd3c1..c362113 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -129,3 +129,4 @@ CONFIG_ACPI=y
CONFIG_SMBIOS=y
CONFIG_ASPEED_SOC=y
CONFIG_GPIO_KEY=y
+CONFIG_ACPI_APEI=y
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index 11c35bc..bafb148 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o
common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o
common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o
+common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o
common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o
common-obj-y += acpi_interface.o
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 04/12] ACPI: enable APEI GHES in the configure file and build it
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add CONFIG_ACPI_APEI configuration in the arm-softmmu.mak
and add build choice in the Makefile.objs.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/acpi/Makefile.objs | 1 +
2 files changed, 2 insertions(+)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index bbdd3c1..c362113 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -129,3 +129,4 @@ CONFIG_ACPI=y
CONFIG_SMBIOS=y
CONFIG_ASPEED_SOC=y
CONFIG_GPIO_KEY=y
+CONFIG_ACPI_APEI=y
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index 11c35bc..bafb148 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -6,6 +6,7 @@ common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu.o
common-obj-$(CONFIG_ACPI_NVDIMM) += nvdimm.o
common-obj-$(CONFIG_ACPI_VMGENID) += vmgenid.o
+common-obj-$(CONFIG_ACPI_APEI) += hest_ghes.o
common-obj-$(call lnot,$(CONFIG_ACPI_X86)) += acpi-stub.o
common-obj-y += acpi_interface.o
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 05/12] linux-headers: sync against Linux v4.14-rc8
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Peter's comments to sync mainline Linux header file in [1]
Address Michael's comments to not sync SPDX from Linux kernel header file
[1]: https://lkml.org/lkml/2017/9/5/575
---
| 3 +++
1 file changed, 3 insertions(+)
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 7971a4f..06a217f 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -929,6 +929,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_PPC_SMT_POSSIBLE 147
#define KVM_CAP_HYPERV_SYNIC2 148
#define KVM_CAP_HYPERV_VP_INDEX 149
+#define KVM_CAP_ARM_INJECT_SERROR_ESR 150
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1355,6 +1356,8 @@ struct kvm_s390_ucas_mapping {
/* Available with KVM_CAP_S390_CMMA_MIGRATION */
#define KVM_S390_GET_CMMA_BITS _IOWR(KVMIO, 0xb8, struct kvm_s390_cmma_log)
#define KVM_S390_SET_CMMA_BITS _IOW(KVMIO, 0xb9, struct kvm_s390_cmma_log)
+/* Available with KVM_CAP_ARM_INJECT_SERROR_ESR */
+#define KVM_ARM_INJECT_SERROR_ESR _IOW(KVMIO, 0xba, __u32)
#define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0)
#define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 05/12] linux-headers: sync against Linux v4.14-rc8
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Peter's comments to sync mainline Linux header file in [1]
Address Michael's comments to not sync SPDX from Linux kernel header file
[1]: https://lkml.org/lkml/2017/9/5/575
---
| 3 +++
1 file changed, 3 insertions(+)
--git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index 7971a4f..06a217f 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -929,6 +929,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_PPC_SMT_POSSIBLE 147
#define KVM_CAP_HYPERV_SYNIC2 148
#define KVM_CAP_HYPERV_VP_INDEX 149
+#define KVM_CAP_ARM_INJECT_SERROR_ESR 150
#ifdef KVM_CAP_IRQ_ROUTING
@@ -1355,6 +1356,8 @@ struct kvm_s390_ucas_mapping {
/* Available with KVM_CAP_S390_CMMA_MIGRATION */
#define KVM_S390_GET_CMMA_BITS _IOWR(KVMIO, 0xb8, struct kvm_s390_cmma_log)
#define KVM_S390_SET_CMMA_BITS _IOW(KVMIO, 0xb9, struct kvm_s390_cmma_log)
+/* Available with KVM_CAP_ARM_INJECT_SERROR_ESR */
+#define KVM_ARM_INJECT_SERROR_ESR _IOW(KVMIO, 0xba, __u32)
#define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0)
#define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 06/12] target-arm: kvm64: detect whether can set vsesr_el2
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Check if kvm can support to set vsesr_el2 value for vcpu. When
guest takes a virtual SError interrupt exception, this value
will provides syndrome value reported into ESR_EL1 ISS filed.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Quanming Wu <wuquanming@huawei.com>
---
Address James's(james.morse@arm.com) comments to detect whether KVM has the capability to set ESR
instead of detecting CPU RAS capability in [1]
[1]
https://www.spinics.net/lists/kvm-arm/msg27150.html
https://www.spinics.net/lists/arm-kernel/msg604440.html
---
target/arm/kvm64.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index a16abc8..af8ebc9 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -980,3 +980,9 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
return false;
}
+
+static bool kvm_can_set_vcpu_esr(struct KVMState *state)
+{
+ int ret = kvm_check_extension(state, KVM_CAP_ARM_INJECT_SERROR_ESR);
+ return (ret) ? true : false;
+}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 06/12] target-arm: kvm64: detect whether can set vsesr_el2
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Check if kvm can support to set vsesr_el2 value for vcpu. When
guest takes a virtual SError interrupt exception, this value
will provides syndrome value reported into ESR_EL1 ISS filed.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Quanming Wu <wuquanming@huawei.com>
---
Address James's(james.morse@arm.com) comments to detect whether KVM has the capability to set ESR
instead of detecting CPU RAS capability in [1]
[1]
https://www.spinics.net/lists/kvm-arm/msg27150.html
https://www.spinics.net/lists/arm-kernel/msg604440.html
---
target/arm/kvm64.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index a16abc8..af8ebc9 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -980,3 +980,9 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
return false;
}
+
+static bool kvm_can_set_vcpu_esr(struct KVMState *state)
+{
+ int ret = kvm_check_extension(state, KVM_CAP_ARM_INJECT_SERROR_ESR);
+ return (ret) ? true : false;
+}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 07/12] target-arm: handle SError interrupt exception from the guest OS
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
When guest OS happens SError interrupt(SEI), it will trap to
host. Host check the Asynchronous Error Type(ESR_ELx.AET). If
it the error has not been propagated and has not (yet) been
architecturally consumed by the PE, it will return to use space
with error code KVM_SEI_SEV_RECOVERABLE.
Qemu receive this exception exit, check whether KVM support to
set ESR(exception syndrome registers) value. If support, it sets
the ESR value using a new IOCTL.
This handling is only supported in AArch64 platform, not supported
in AArch32 platform.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Quanming Wu <wuquanming@huawei.com>
---
Address James and Marc's comments to set ESR and inject SEI by user space
in [1]
[1]:
https://lkml.org/lkml/2017/3/20/441
https://lkml.org/lkml/2017/3/20/516
Below is the log that Qemu inject SError with specify ESR and guest happen exception:
Bad mode in Error handler detected, code 0xbe000c11 -- SError
CPU: 0 PID: 539 Comm: devmem Tainted: G D 4.1.0+ #20
Hardware name: linux,dummy-virt (DT)
task: ffffffc019aad600 ti: ffffffc008134000 task.ti: ffffffc008134000
PC is at 0x405cc0
LR is at 0x40ce80
pc : [<0000000000405cc0>] lr : [<000000000040ce80>] pstate: 60000000
sp : ffffffc008137ff0
x29: 0000007fd9e80790 x28: 0000000000000000
x27: 00000000000000ad x26: 000000000049c000
x25: 000000000048904b x24: 000000000049c000
x23: 0000000040600000 x22: 0000007fd9e808d0
x21: 0000000000000002 x20: 0000000000000000
x19: 0000000000000020 x18: 0000000000000000
x17: 0000000000405cc0 x16: 000000000049c698
x15: 0000000000005798 x14: 0000007f93875f1c
x13: 0000007f93a8ccb0 x12: 0000000000000137
x11: 0000000000000000 x10: 0000000000000000
x9 : 0000000000000000 x8 : 00000000000000de
x7 : 0000000000000000 x6 : 0000000000002000
x5 : 0000000040600000 x4 : 0000000000000003
x3 : 0000000000000001 x2 : 00000000000f123b
x1 : 0000000000000008 x0 : 000000000047a048
---
target/arm/internals.h | 4 ++++
target/arm/kvm.c | 3 +++
target/arm/kvm32.c | 6 ++++++
target/arm/kvm64.c | 34 ++++++++++++++++++++++++++++++++++
target/arm/kvm_arm.h | 8 ++++++++
5 files changed, 55 insertions(+)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1f6efef..cd26a9d 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -233,9 +233,13 @@ enum arm_exception_class {
#define ARM_EL_EC_SHIFT 26
#define ARM_EL_IL_SHIFT 25
#define ARM_EL_ISV_SHIFT 24
+#define ARM_EL_AET_SHIFT 10
#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
+/* Asynchronous Error Type */
+#define KVM_SEI_SEV_RECOVERABLE 1
+
/* Utility functions for constructing various kinds of syndrome value.
* Note that in general we follow the AArch64 syndrome values; in a
* few cases the value in HSR for exceptions taken to AArch32 Hyp
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 7c17f0d..d85e36a 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -593,6 +593,9 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
ret = EXCP_DEBUG;
} /* otherwise return to guest */
break;
+ case KVM_EXIT_EXCEPTION:
+ kvm_arm_handle_exception(cs, run);
+ break;
default:
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
__func__, run->exit_reason);
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index 069da0c..8ce56fd 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -493,6 +493,12 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
return false;
}
+bool kvm_arm_handle_exception(CPUState *cs, struct kvm_run *run)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
+ return false;
+}
+
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
target_ulong len, int type)
{
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index af8ebc9..2d0eb32 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -986,3 +986,37 @@ static bool kvm_can_set_vcpu_esr(struct KVMState *state)
int ret = kvm_check_extension(state, KVM_CAP_ARM_INJECT_SERROR_ESR);
return (ret) ? true : false;
}
+
+static bool kvm_inject_arm_sei(CPUState *cs, unsigned int error_code)
+{
+ int ret;
+ /* IMPLEMENTATION DEFINED syndrome by default */
+ uint32_t syndrome = ARM_EL_ISV;
+
+ if (kvm_can_set_vcpu_esr(cs->kvm_state)) {
+ if (error_code == KVM_SEI_SEV_RECOVERABLE) {
+ /* Set Recoverable Asynchronous SError interrupt Type */
+ syndrome = (3 << ARM_EL_AET_SHIFT) | 0x11;
+ }
+ ret = kvm_vcpu_ioctl(cs, KVM_ARM_INJECT_SERROR_ESR, &syndrome);
+ if (ret < 0) {
+ fprintf(stderr, "KVM_ARM_SET_SERROR_ESR failed: %s\n",
+ strerror(-ret));
+ abort();
+ }
+
+ return true;
+ }
+
+ return false;
+}
+
+bool kvm_arm_handle_exception(CPUState *cs, struct kvm_run *run)
+{
+ int exception = run->ex.exception;
+ unsigned int error_code = run->ex.error_code;
+ if (exception == EC_SERROR) {
+ return kvm_inject_arm_sei(cs, error_code);
+ }
+ return false;
+}
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 633d088..b2a7933 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -288,4 +288,12 @@ static inline const char *its_class_name(void)
}
}
+/**
+ * kvm_arm_handle_exception:
+ * @cs: CPUState
+ * @run: KVM RUN structure
+ *
+ * Returns: TRUE if the SError exception was successfully handled
+ */
+bool kvm_arm_handle_exception(CPUState *cs, struct kvm_run *run);
#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 07/12] target-arm: handle SError interrupt exception from the guest OS
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
When guest OS happens SError interrupt(SEI), it will trap to
host. Host check the Asynchronous Error Type(ESR_ELx.AET). If
it the error has not been propagated and has not (yet) been
architecturally consumed by the PE, it will return to use space
with error code KVM_SEI_SEV_RECOVERABLE.
Qemu receive this exception exit, check whether KVM support to
set ESR(exception syndrome registers) value. If support, it sets
the ESR value using a new IOCTL.
This handling is only supported in AArch64 platform, not supported
in AArch32 platform.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Quanming Wu <wuquanming@huawei.com>
---
Address James and Marc's comments to set ESR and inject SEI by user space
in [1]
[1]:
https://lkml.org/lkml/2017/3/20/441
https://lkml.org/lkml/2017/3/20/516
Below is the log that Qemu inject SError with specify ESR and guest happen exception:
Bad mode in Error handler detected, code 0xbe000c11 -- SError
CPU: 0 PID: 539 Comm: devmem Tainted: G D 4.1.0+ #20
Hardware name: linux,dummy-virt (DT)
task: ffffffc019aad600 ti: ffffffc008134000 task.ti: ffffffc008134000
PC is at 0x405cc0
LR is at 0x40ce80
pc : [<0000000000405cc0>] lr : [<000000000040ce80>] pstate: 60000000
sp : ffffffc008137ff0
x29: 0000007fd9e80790 x28: 0000000000000000
x27: 00000000000000ad x26: 000000000049c000
x25: 000000000048904b x24: 000000000049c000
x23: 0000000040600000 x22: 0000007fd9e808d0
x21: 0000000000000002 x20: 0000000000000000
x19: 0000000000000020 x18: 0000000000000000
x17: 0000000000405cc0 x16: 000000000049c698
x15: 0000000000005798 x14: 0000007f93875f1c
x13: 0000007f93a8ccb0 x12: 0000000000000137
x11: 0000000000000000 x10: 0000000000000000
x9 : 0000000000000000 x8 : 00000000000000de
x7 : 0000000000000000 x6 : 0000000000002000
x5 : 0000000040600000 x4 : 0000000000000003
x3 : 0000000000000001 x2 : 00000000000f123b
x1 : 0000000000000008 x0 : 000000000047a048
---
target/arm/internals.h | 4 ++++
target/arm/kvm.c | 3 +++
target/arm/kvm32.c | 6 ++++++
target/arm/kvm64.c | 34 ++++++++++++++++++++++++++++++++++
target/arm/kvm_arm.h | 8 ++++++++
5 files changed, 55 insertions(+)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 1f6efef..cd26a9d 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -233,9 +233,13 @@ enum arm_exception_class {
#define ARM_EL_EC_SHIFT 26
#define ARM_EL_IL_SHIFT 25
#define ARM_EL_ISV_SHIFT 24
+#define ARM_EL_AET_SHIFT 10
#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
+/* Asynchronous Error Type */
+#define KVM_SEI_SEV_RECOVERABLE 1
+
/* Utility functions for constructing various kinds of syndrome value.
* Note that in general we follow the AArch64 syndrome values; in a
* few cases the value in HSR for exceptions taken to AArch32 Hyp
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 7c17f0d..d85e36a 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -593,6 +593,9 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
ret = EXCP_DEBUG;
} /* otherwise return to guest */
break;
+ case KVM_EXIT_EXCEPTION:
+ kvm_arm_handle_exception(cs, run);
+ break;
default:
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
__func__, run->exit_reason);
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index 069da0c..8ce56fd 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -493,6 +493,12 @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
return false;
}
+bool kvm_arm_handle_exception(CPUState *cs, struct kvm_run *run)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
+ return false;
+}
+
int kvm_arch_insert_hw_breakpoint(target_ulong addr,
target_ulong len, int type)
{
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index af8ebc9..2d0eb32 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -986,3 +986,37 @@ static bool kvm_can_set_vcpu_esr(struct KVMState *state)
int ret = kvm_check_extension(state, KVM_CAP_ARM_INJECT_SERROR_ESR);
return (ret) ? true : false;
}
+
+static bool kvm_inject_arm_sei(CPUState *cs, unsigned int error_code)
+{
+ int ret;
+ /* IMPLEMENTATION DEFINED syndrome by default */
+ uint32_t syndrome = ARM_EL_ISV;
+
+ if (kvm_can_set_vcpu_esr(cs->kvm_state)) {
+ if (error_code == KVM_SEI_SEV_RECOVERABLE) {
+ /* Set Recoverable Asynchronous SError interrupt Type */
+ syndrome = (3 << ARM_EL_AET_SHIFT) | 0x11;
+ }
+ ret = kvm_vcpu_ioctl(cs, KVM_ARM_INJECT_SERROR_ESR, &syndrome);
+ if (ret < 0) {
+ fprintf(stderr, "KVM_ARM_SET_SERROR_ESR failed: %s\n",
+ strerror(-ret));
+ abort();
+ }
+
+ return true;
+ }
+
+ return false;
+}
+
+bool kvm_arm_handle_exception(CPUState *cs, struct kvm_run *run)
+{
+ int exception = run->ex.exception;
+ unsigned int error_code = run->ex.error_code;
+ if (exception == EC_SERROR) {
+ return kvm_inject_arm_sei(cs, error_code);
+ }
+ return false;
+}
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index 633d088..b2a7933 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -288,4 +288,12 @@ static inline const char *its_class_name(void)
}
}
+/**
+ * kvm_arm_handle_exception:
+ * @cs: CPUState
+ * @run: KVM RUN structure
+ *
+ * Returns: TRUE if the SError exception was successfully handled
+ */
+bool kvm_arm_handle_exception(CPUState *cs, struct kvm_run *run);
#endif
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 08/12] target-arm: kvm64: inject synchronous External Abort
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add synchronous external abort injection logic, setup
spsr_elx, esr_elx, PSTATE, elr_elx etc, when switch to
guest, guest will jump to the synchronous external abort
vector table entry.
The ESR_ELx.DFSC is set to Synchronous external abort(0x10),
and ESR_ELx.FnV is set to not valid(0x1), which will tell
guest that FAR is not valid and holds an UNKNOWN value.
These value will be set to KVM related structure through
KVM_SET_ONE_REG IOCTL.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Quanming Wu <wuquanming@huawei.com>
---
Marc is against that KVM inject the synchronous external abort(SEA) in [1],
so user space how to inject it. The test result that injection SEA to guest by Qemu
is shown in [2].
[1]: https://lkml.org/lkml/2017/3/2/110
[2]:
Taking exception 4 [Data Abort]
...from EL0 to EL1
...with ESR 0x24/0x92000410
...with FAR 0x0
...with ELR 0x40cf04
...to EL1 PC 0xffffffc000084c00 PSTATE 0x3c5
after kvm_inject_arm_sea
Unhandled fault: synchronous external abort (0x92000410) at 0x0000007fa234c12c
CPU: 0 PID: 536 Comm: devmem Not tainted 4.1.0+ #20
Hardware name: linux,dummy-virt (DT)
task: ffffffc019ab2b00 ti: ffffffc008134000 task.ti: ffffffc008134000
PC is at 0x40cf04
LR is at 0x40cdec
pc : [<000000000040cf04>] lr : [<000000000040cdec>] pstate: 60000000
sp : 0000007ff7b24130
x29: 0000007ff7b24260 x28: 0000000000000000
x27: 00000000000000ad x26: 000000000049c000
x25: 000000000048904b x24: 000000000049c000
x23: 0000000040600000 x22: 0000007ff7b243a0
x21: 0000000000000002 x20: 0000000000000000
x19: 0000000000000020 x18: 0000000000000000
x17: 000000000049c6d0 x16: 0000007fa22c85c0
x15: 0000000000005798 x14: 0000007fa2205f1c
x13: 0000007fa241ccb0 x12: 0000000000000137
x11: 0000000000000000 x10: 0000000000000000
x9 : 0000000000000000 x8 : 00000000000000de
x7 : 0000000000000000 x6 : 0000000000002000
x5 : 0000000040600000 x4 : 0000000000000003
x3 : 0000000000000001 x2 : 0000000000000000
x1 : 0000000000000000 x0 : 0000007fa2418000
---
target/arm/kvm64.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 2d0eb32..7f662e9 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -582,6 +582,70 @@ int kvm_arm_cpreg_level(uint64_t regidx)
return KVM_PUT_RUNTIME_STATE;
}
+static int kvm_arm_cpreg_value(ARMCPU *cpu, ptrdiff_t fieldoffset)
+{
+ int i;
+
+ for (i = 0; i < cpu->cpreg_array_len; i++) {
+ uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
+ const ARMCPRegInfo *ri;
+ ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+ if (!ri) {
+ continue;
+ }
+
+ if (ri->type & ARM_CP_NO_RAW) {
+ continue;
+ }
+
+ if (ri->fieldoffset == fieldoffset) {
+ cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+/* Inject synchronous external abort */
+static void kvm_inject_arm_sea(CPUState *c)
+{
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+ unsigned long cpsr = pstate_read(env);
+ uint32_t esr, ret;
+
+ c->exception_index = EXCP_DATA_ABORT;
+ /* Inject the exception to El1 */
+ env->exception.target_el = 1;
+ CPUClass *cc = CPU_GET_CLASS(c);
+
+ /* Set the DFSC to Synchronous external abort and FnV to not valid,
+ * this will tell guest the FAR_EL1 is UNKNOWN.
+ */
+ esr = (0x10 | (1 << 10));
+
+ /* This exception is EL0 or EL1 fault. */
+ if ((cpsr & 0xf) == PSTATE_MODE_EL0t) {
+ esr |= (EC_DATAABORT << ARM_EL_EC_SHIFT);
+ } else {
+ esr |= (EC_DATAABORT_SAME_EL << ARM_EL_EC_SHIFT);
+ }
+
+ /* In the aarch64, there is only 32-bit instruction*/
+ esr |= ARM_EL_IL;
+ env->exception.syndrome = esr;
+
+ cc->do_interrupt(c);
+
+ /* set ESR_EL1 */
+ ret = kvm_arm_cpreg_value(cpu, offsetof(CPUARMState, cp15.esr_el[1]));
+
+ if (ret) {
+ fprintf(stderr, "<%s> failed to set esr_el1\n", __func__);
+ abort();
+ }
+}
+
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 08/12] target-arm: kvm64: inject synchronous External Abort
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add synchronous external abort injection logic, setup
spsr_elx, esr_elx, PSTATE, elr_elx etc, when switch to
guest, guest will jump to the synchronous external abort
vector table entry.
The ESR_ELx.DFSC is set to Synchronous external abort(0x10),
and ESR_ELx.FnV is set to not valid(0x1), which will tell
guest that FAR is not valid and holds an UNKNOWN value.
These value will be set to KVM related structure through
KVM_SET_ONE_REG IOCTL.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Quanming Wu <wuquanming@huawei.com>
---
Marc is against that KVM inject the synchronous external abort(SEA) in [1],
so user space how to inject it. The test result that injection SEA to guest by Qemu
is shown in [2].
[1]: https://lkml.org/lkml/2017/3/2/110
[2]:
Taking exception 4 [Data Abort]
...from EL0 to EL1
...with ESR 0x24/0x92000410
...with FAR 0x0
...with ELR 0x40cf04
...to EL1 PC 0xffffffc000084c00 PSTATE 0x3c5
after kvm_inject_arm_sea
Unhandled fault: synchronous external abort (0x92000410) at 0x0000007fa234c12c
CPU: 0 PID: 536 Comm: devmem Not tainted 4.1.0+ #20
Hardware name: linux,dummy-virt (DT)
task: ffffffc019ab2b00 ti: ffffffc008134000 task.ti: ffffffc008134000
PC is at 0x40cf04
LR is at 0x40cdec
pc : [<000000000040cf04>] lr : [<000000000040cdec>] pstate: 60000000
sp : 0000007ff7b24130
x29: 0000007ff7b24260 x28: 0000000000000000
x27: 00000000000000ad x26: 000000000049c000
x25: 000000000048904b x24: 000000000049c000
x23: 0000000040600000 x22: 0000007ff7b243a0
x21: 0000000000000002 x20: 0000000000000000
x19: 0000000000000020 x18: 0000000000000000
x17: 000000000049c6d0 x16: 0000007fa22c85c0
x15: 0000000000005798 x14: 0000007fa2205f1c
x13: 0000007fa241ccb0 x12: 0000000000000137
x11: 0000000000000000 x10: 0000000000000000
x9 : 0000000000000000 x8 : 00000000000000de
x7 : 0000000000000000 x6 : 0000000000002000
x5 : 0000000040600000 x4 : 0000000000000003
x3 : 0000000000000001 x2 : 0000000000000000
x1 : 0000000000000000 x0 : 0000007fa2418000
---
target/arm/kvm64.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 2d0eb32..7f662e9 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -582,6 +582,70 @@ int kvm_arm_cpreg_level(uint64_t regidx)
return KVM_PUT_RUNTIME_STATE;
}
+static int kvm_arm_cpreg_value(ARMCPU *cpu, ptrdiff_t fieldoffset)
+{
+ int i;
+
+ for (i = 0; i < cpu->cpreg_array_len; i++) {
+ uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
+ const ARMCPRegInfo *ri;
+ ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
+ if (!ri) {
+ continue;
+ }
+
+ if (ri->type & ARM_CP_NO_RAW) {
+ continue;
+ }
+
+ if (ri->fieldoffset == fieldoffset) {
+ cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+/* Inject synchronous external abort */
+static void kvm_inject_arm_sea(CPUState *c)
+{
+ ARMCPU *cpu = ARM_CPU(c);
+ CPUARMState *env = &cpu->env;
+ unsigned long cpsr = pstate_read(env);
+ uint32_t esr, ret;
+
+ c->exception_index = EXCP_DATA_ABORT;
+ /* Inject the exception to El1 */
+ env->exception.target_el = 1;
+ CPUClass *cc = CPU_GET_CLASS(c);
+
+ /* Set the DFSC to Synchronous external abort and FnV to not valid,
+ * this will tell guest the FAR_EL1 is UNKNOWN.
+ */
+ esr = (0x10 | (1 << 10));
+
+ /* This exception is EL0 or EL1 fault. */
+ if ((cpsr & 0xf) == PSTATE_MODE_EL0t) {
+ esr |= (EC_DATAABORT << ARM_EL_EC_SHIFT);
+ } else {
+ esr |= (EC_DATAABORT_SAME_EL << ARM_EL_EC_SHIFT);
+ }
+
+ /* In the aarch64, there is only 32-bit instruction*/
+ esr |= ARM_EL_IL;
+ env->exception.syndrome = esr;
+
+ cc->do_interrupt(c);
+
+ /* set ESR_EL1 */
+ ret = kvm_arm_cpreg_value(cpu, offsetof(CPUARMState, cp15.esr_el[1]));
+
+ if (ret) {
+ fprintf(stderr, "<%s> failed to set esr_el1\n", __func__);
+ abort();
+ }
+}
+
#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 09/12] Move related hwpoison page function to accel/kvm/ folder
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
kvm_hwpoison_page_add() and kvm_unpoison_all() will be used
by both X86 and ARM platforms, so move them to a common accel/kvm/
folder to avoid duplicate code.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Peter's comments to move related hwpoison page function to accel/kvm folder in [1]
Address Paolo's comments to move HWPoisonPage definition back to accel/kvm/kvm-all.c
[1]:
https://lists.gnu.org/archive/html/qemu-arm/2017-09/msg00077.html
https://lists.gnu.org/archive/html/qemu-arm/2017-09/msg00152.html
---
accel/kvm/kvm-all.c | 34 ++++++++++++++++++++++++++++++++++
include/exec/ram_addr.h | 5 +++++
target/i386/kvm.c | 33 ---------------------------------
3 files changed, 39 insertions(+), 33 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 46ce479..98ac06c 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -564,6 +564,39 @@ int kvm_vm_check_extension(KVMState *s, unsigned int extension)
return ret;
}
+typedef struct HWPoisonPage {
+ ram_addr_t ram_addr;
+ QLIST_ENTRY(HWPoisonPage) list;
+} HWPoisonPage;
+
+static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
+ QLIST_HEAD_INITIALIZER(hwpoison_page_list);
+
+void kvm_unpoison_all(void *param)
+{
+ HWPoisonPage *page, *next_page;
+
+ QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
+ QLIST_REMOVE(page, list);
+ qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
+ g_free(page);
+ }
+}
+
+void kvm_hwpoison_page_add(ram_addr_t ram_addr)
+{
+ HWPoisonPage *page;
+
+ QLIST_FOREACH(page, &hwpoison_page_list, list) {
+ if (page->ram_addr == ram_addr) {
+ return;
+ }
+ }
+ page = g_new(HWPoisonPage, 1);
+ page->ram_addr = ram_addr;
+ QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
+}
+
static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size)
{
#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
@@ -2279,6 +2312,7 @@ bool kvm_arm_supports_user_irq(void)
return kvm_check_extension(kvm_state, KVM_CAP_ARM_USER_IRQ);
}
+
#ifdef KVM_CAP_SET_GUEST_DEBUG
struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *cpu,
target_ulong pc)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index d017639..2a25315 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -80,6 +80,11 @@ void qemu_ram_free(RAMBlock *block);
int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp);
+/* Free and remove all the poisoned pages in the list */
+void kvm_unpoison_all(void *param);
+/* Add a poisoned page to the list */
+void kvm_hwpoison_page_add(ram_addr_t ram_addr);
+
#define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1)
#define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE))
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 6db7783..3e1afb6 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -390,39 +390,6 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
return ret;
}
-typedef struct HWPoisonPage {
- ram_addr_t ram_addr;
- QLIST_ENTRY(HWPoisonPage) list;
-} HWPoisonPage;
-
-static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
- QLIST_HEAD_INITIALIZER(hwpoison_page_list);
-
-static void kvm_unpoison_all(void *param)
-{
- HWPoisonPage *page, *next_page;
-
- QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
- QLIST_REMOVE(page, list);
- qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
- g_free(page);
- }
-}
-
-static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
-{
- HWPoisonPage *page;
-
- QLIST_FOREACH(page, &hwpoison_page_list, list) {
- if (page->ram_addr == ram_addr) {
- return;
- }
- }
- page = g_new(HWPoisonPage, 1);
- page->ram_addr = ram_addr;
- QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
-}
-
static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
int *max_banks)
{
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 09/12] Move related hwpoison page function to accel/kvm/ folder
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
kvm_hwpoison_page_add() and kvm_unpoison_all() will be used
by both X86 and ARM platforms, so move them to a common accel/kvm/
folder to avoid duplicate code.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Peter's comments to move related hwpoison page function to accel/kvm folder in [1]
Address Paolo's comments to move HWPoisonPage definition back to accel/kvm/kvm-all.c
[1]:
https://lists.gnu.org/archive/html/qemu-arm/2017-09/msg00077.html
https://lists.gnu.org/archive/html/qemu-arm/2017-09/msg00152.html
---
accel/kvm/kvm-all.c | 34 ++++++++++++++++++++++++++++++++++
include/exec/ram_addr.h | 5 +++++
target/i386/kvm.c | 33 ---------------------------------
3 files changed, 39 insertions(+), 33 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index 46ce479..98ac06c 100644
--- a/accel/kvm/kvm-all.c
+++ b/accel/kvm/kvm-all.c
@@ -564,6 +564,39 @@ int kvm_vm_check_extension(KVMState *s, unsigned int extension)
return ret;
}
+typedef struct HWPoisonPage {
+ ram_addr_t ram_addr;
+ QLIST_ENTRY(HWPoisonPage) list;
+} HWPoisonPage;
+
+static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
+ QLIST_HEAD_INITIALIZER(hwpoison_page_list);
+
+void kvm_unpoison_all(void *param)
+{
+ HWPoisonPage *page, *next_page;
+
+ QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
+ QLIST_REMOVE(page, list);
+ qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
+ g_free(page);
+ }
+}
+
+void kvm_hwpoison_page_add(ram_addr_t ram_addr)
+{
+ HWPoisonPage *page;
+
+ QLIST_FOREACH(page, &hwpoison_page_list, list) {
+ if (page->ram_addr == ram_addr) {
+ return;
+ }
+ }
+ page = g_new(HWPoisonPage, 1);
+ page->ram_addr = ram_addr;
+ QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
+}
+
static uint32_t adjust_ioeventfd_endianness(uint32_t val, uint32_t size)
{
#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
@@ -2279,6 +2312,7 @@ bool kvm_arm_supports_user_irq(void)
return kvm_check_extension(kvm_state, KVM_CAP_ARM_USER_IRQ);
}
+
#ifdef KVM_CAP_SET_GUEST_DEBUG
struct kvm_sw_breakpoint *kvm_find_sw_breakpoint(CPUState *cpu,
target_ulong pc)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index d017639..2a25315 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -80,6 +80,11 @@ void qemu_ram_free(RAMBlock *block);
int qemu_ram_resize(RAMBlock *block, ram_addr_t newsize, Error **errp);
+/* Free and remove all the poisoned pages in the list */
+void kvm_unpoison_all(void *param);
+/* Add a poisoned page to the list */
+void kvm_hwpoison_page_add(ram_addr_t ram_addr);
+
#define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1)
#define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_CODE))
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 6db7783..3e1afb6 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -390,39 +390,6 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
return ret;
}
-typedef struct HWPoisonPage {
- ram_addr_t ram_addr;
- QLIST_ENTRY(HWPoisonPage) list;
-} HWPoisonPage;
-
-static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
- QLIST_HEAD_INITIALIZER(hwpoison_page_list);
-
-static void kvm_unpoison_all(void *param)
-{
- HWPoisonPage *page, *next_page;
-
- QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
- QLIST_REMOVE(page, list);
- qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
- g_free(page);
- }
-}
-
-static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
-{
- HWPoisonPage *page;
-
- QLIST_FOREACH(page, &hwpoison_page_list, list) {
- if (page->ram_addr == ram_addr) {
- return;
- }
- }
- page = g_new(HWPoisonPage, 1);
- page->ram_addr = ram_addr;
- QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
-}
-
static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
int *max_banks)
{
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 10/12] ARM: ACPI: Add _E04 for hardware error device
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
In ARM platform we implements a notification of error
events via a GPIO pin. In this case of GPIO-signaled
events, an _AEI object lists the appropriate GPIO pin.
GPIO pin 4 is used for hardware error device (PNP0C33),
so add _E04 in ACPI DSDT table. When GPIO-pin 4 signaled
a events, the guest ACPI driver will receive this
notification and handing the error.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
1. Address discussion result about guest APEI notification type for SIGBUS_MCEERR_AO SIGBUS in [1],
the discussion conclusion is using GPIO-Signal
[1]:
https://lists.gnu.org/archive/html/qemu-devel/2017-10/msg03397.html
https://lists.gnu.org/archive/html/qemu-devel/2017-10/msg03467.html
https://lists.gnu.org/archive/html/qemu-devel/2017-10/msg03601.html
https://lists.gnu.org/archive/html/qemu-devel/2017-10/msg03775.html
2. The ASL dump for the GPIO and hardware error device
................
Device (GPO0)
{
Name (_AEI, ResourceTemplate () // _AEI: ACPI Event Interrupts
{
.............
GpioInt (Edge, ActiveHigh, Exclusive, PullUp, 0x0000,
"GPO0", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0004
}
})
Method (_E04, 0, NotSerialized) // _Exx: Edge-Triggered GPE
{
Notify (ERRD, 0x80) // Status Change
}
}
Device (ERRD)
{
Name (_HID, EisaId ("PNP0C33") /* Error Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
3. Below is the guest log when Qemu notifies guest using GPIO-signal after record a CPER
[ 504.164899] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 7
[ 504.166970] {1}[Hardware Error]: event severity: recoverable
[ 504.251650] {1}[Hardware Error]: Error 0, type: recoverable
[ 504.252974] {1}[Hardware Error]: section_type: memory error
[ 504.254380] {1}[Hardware Error]: physical_address: 0x00000000000003ec
[ 504.255879] {1}[Hardware Error]: error_type: 3, multi-bit ECC
---
hw/arm/virt-acpi-build.c | 31 ++++++++++++++++++++++++++++++-
hw/arm/virt.c | 18 ++++++++++++++++++
include/sysemu/sysemu.h | 3 +++
vl.c | 12 ++++++++++++
4 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 7b397c3..92c8c38 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -49,6 +49,7 @@
#define ARM_SPI_BASE 32
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
+#define ACPI_HARDWARE_ERROR_DEVICE "ERRD"
static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
{
@@ -340,7 +341,13 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
Aml *aei = aml_resource_template();
/* Pin 3 for power button */
- const uint32_t pin_list[1] = {3};
+ uint32_t pin_list[1] = {3};
+ aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
+ "GPO0", NULL, 0));
+
+ /* Pin 4 for hardware error device */
+ pin_list[0] = 4;
aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
"GPO0", NULL, 0));
@@ -351,6 +358,13 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
aml_int(0x80)));
aml_append(dev, method);
+
+ /* _E04 is handle for hardware error */
+ method = aml_method("_E04", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_notify(aml_name(ACPI_HARDWARE_ERROR_DEVICE),
+ aml_int(0x80)));
+ aml_append(dev, method);
+
aml_append(scope, dev);
}
@@ -363,6 +377,20 @@ static void acpi_dsdt_add_power_button(Aml *scope)
aml_append(scope, dev);
}
+static void acpi_dsdt_add_error_device(Aml *scope)
+{
+ Aml *dev = aml_device(ACPI_HARDWARE_ERROR_DEVICE);
+ Aml *method;
+
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C33")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(0x0f)));
+ aml_append(dev, method);
+ aml_append(scope, dev);
+}
+
/* RSDP */
static GArray *
build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned xsdt_tbl_offset)
@@ -716,6 +744,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
(irqmap[VIRT_GPIO] + ARM_SPI_BASE));
acpi_dsdt_add_power_button(scope);
+ acpi_dsdt_add_error_device(scope);
aml_append(dsdt, scope);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 6b7a0fe..68495c2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -701,16 +701,27 @@ static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
}
static DeviceState *gpio_key_dev;
+static DeviceState *gpio_err_dev;
static void virt_powerdown_req(Notifier *n, void *opaque)
{
/* use gpio Pin 3 for power button event */
qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
}
+static void virt_error_notify_req(Notifier *n, void *opaque)
+{
+ /* use gpio Pin 4 for hardware error event */
+ qemu_set_irq(qdev_get_gpio_in(gpio_err_dev, 0), 1);
+}
+
static Notifier virt_system_powerdown_notifier = {
.notify = virt_powerdown_req
};
+static Notifier virt_hardware_error_notifier = {
+ .notify = virt_error_notify_req
+};
+
static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
{
char *nodename;
@@ -739,6 +750,10 @@ static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
gpio_key_dev = sysbus_create_simple("gpio-key", -1,
qdev_get_gpio_in(pl061_dev, 3));
+
+ gpio_err_dev = sysbus_create_simple("gpio-key", -1,
+ qdev_get_gpio_in(pl061_dev, 4));
+
qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
@@ -755,6 +770,9 @@ static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
/* connect powerdown request */
qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
+ /* connect hardware error notify request */
+ qemu_register_hardware_error_notifier(&virt_hardware_error_notifier);
+
g_free(nodename);
}
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index b213696..86931cf 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -75,6 +75,7 @@ void qemu_register_wakeup_notifier(Notifier *notifier);
void qemu_system_shutdown_request(ShutdownCause reason);
void qemu_system_powerdown_request(void);
void qemu_register_powerdown_notifier(Notifier *notifier);
+void qemu_register_hardware_error_notifier(Notifier *notifier);
void qemu_system_debug_request(void);
void qemu_system_vmstop_request(RunState reason);
void qemu_system_vmstop_request_prepare(void);
@@ -93,6 +94,8 @@ void qemu_remove_machine_init_done_notifier(Notifier *notify);
void qemu_announce_self(void);
+void qemu_hardware_error_notify(void);
+
extern int autostart;
typedef enum {
diff --git a/vl.c b/vl.c
index d632693..3552f7d 100644
--- a/vl.c
+++ b/vl.c
@@ -1614,6 +1614,8 @@ static int suspend_requested;
static WakeupReason wakeup_reason;
static NotifierList powerdown_notifiers =
NOTIFIER_LIST_INITIALIZER(powerdown_notifiers);
+static NotifierList hardware_error_notifiers =
+ NOTIFIER_LIST_INITIALIZER(hardware_error_notifiers);
static NotifierList suspend_notifiers =
NOTIFIER_LIST_INITIALIZER(suspend_notifiers);
static NotifierList wakeup_notifiers =
@@ -1850,12 +1852,22 @@ void qemu_register_powerdown_notifier(Notifier *notifier)
notifier_list_add(&powerdown_notifiers, notifier);
}
+void qemu_register_hardware_error_notifier(Notifier *notifier)
+{
+ notifier_list_add(&hardware_error_notifiers, notifier);
+}
+
void qemu_system_debug_request(void)
{
debug_requested = 1;
qemu_notify_event();
}
+void qemu_hardware_error_notify(void)
+{
+ notifier_list_notify(&hardware_error_notifiers, NULL);
+}
+
static bool main_loop_should_exit(void)
{
RunState r;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 10/12] ARM: ACPI: Add _E04 for hardware error device
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
In ARM platform we implements a notification of error
events via a GPIO pin. In this case of GPIO-signaled
events, an _AEI object lists the appropriate GPIO pin.
GPIO pin 4 is used for hardware error device (PNP0C33),
so add _E04 in ACPI DSDT table. When GPIO-pin 4 signaled
a events, the guest ACPI driver will receive this
notification and handing the error.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
1. Address discussion result about guest APEI notification type for SIGBUS_MCEERR_AO SIGBUS in [1],
the discussion conclusion is using GPIO-Signal
[1]:
https://lists.gnu.org/archive/html/qemu-devel/2017-10/msg03397.html
https://lists.gnu.org/archive/html/qemu-devel/2017-10/msg03467.html
https://lists.gnu.org/archive/html/qemu-devel/2017-10/msg03601.html
https://lists.gnu.org/archive/html/qemu-devel/2017-10/msg03775.html
2. The ASL dump for the GPIO and hardware error device
................
Device (GPO0)
{
Name (_AEI, ResourceTemplate () // _AEI: ACPI Event Interrupts
{
.............
GpioInt (Edge, ActiveHigh, Exclusive, PullUp, 0x0000,
"GPO0", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0004
}
})
Method (_E04, 0, NotSerialized) // _Exx: Edge-Triggered GPE
{
Notify (ERRD, 0x80) // Status Change
}
}
Device (ERRD)
{
Name (_HID, EisaId ("PNP0C33") /* Error Device */) // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
}
3. Below is the guest log when Qemu notifies guest using GPIO-signal after record a CPER
[ 504.164899] {1}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 7
[ 504.166970] {1}[Hardware Error]: event severity: recoverable
[ 504.251650] {1}[Hardware Error]: Error 0, type: recoverable
[ 504.252974] {1}[Hardware Error]: section_type: memory error
[ 504.254380] {1}[Hardware Error]: physical_address: 0x00000000000003ec
[ 504.255879] {1}[Hardware Error]: error_type: 3, multi-bit ECC
---
hw/arm/virt-acpi-build.c | 31 ++++++++++++++++++++++++++++++-
hw/arm/virt.c | 18 ++++++++++++++++++
include/sysemu/sysemu.h | 3 +++
vl.c | 12 ++++++++++++
4 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 7b397c3..92c8c38 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -49,6 +49,7 @@
#define ARM_SPI_BASE 32
#define ACPI_POWER_BUTTON_DEVICE "PWRB"
+#define ACPI_HARDWARE_ERROR_DEVICE "ERRD"
static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
{
@@ -340,7 +341,13 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
Aml *aei = aml_resource_template();
/* Pin 3 for power button */
- const uint32_t pin_list[1] = {3};
+ uint32_t pin_list[1] = {3};
+ aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
+ "GPO0", NULL, 0));
+
+ /* Pin 4 for hardware error device */
+ pin_list[0] = 4;
aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
"GPO0", NULL, 0));
@@ -351,6 +358,13 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
aml_int(0x80)));
aml_append(dev, method);
+
+ /* _E04 is handle for hardware error */
+ method = aml_method("_E04", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_notify(aml_name(ACPI_HARDWARE_ERROR_DEVICE),
+ aml_int(0x80)));
+ aml_append(dev, method);
+
aml_append(scope, dev);
}
@@ -363,6 +377,20 @@ static void acpi_dsdt_add_power_button(Aml *scope)
aml_append(scope, dev);
}
+static void acpi_dsdt_add_error_device(Aml *scope)
+{
+ Aml *dev = aml_device(ACPI_HARDWARE_ERROR_DEVICE);
+ Aml *method;
+
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C33")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ method = aml_method("_STA", 0, AML_NOTSERIALIZED);
+ aml_append(method, aml_return(aml_int(0x0f)));
+ aml_append(dev, method);
+ aml_append(scope, dev);
+}
+
/* RSDP */
static GArray *
build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned xsdt_tbl_offset)
@@ -716,6 +744,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
(irqmap[VIRT_GPIO] + ARM_SPI_BASE));
acpi_dsdt_add_power_button(scope);
+ acpi_dsdt_add_error_device(scope);
aml_append(dsdt, scope);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 6b7a0fe..68495c2 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -701,16 +701,27 @@ static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
}
static DeviceState *gpio_key_dev;
+static DeviceState *gpio_err_dev;
static void virt_powerdown_req(Notifier *n, void *opaque)
{
/* use gpio Pin 3 for power button event */
qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
}
+static void virt_error_notify_req(Notifier *n, void *opaque)
+{
+ /* use gpio Pin 4 for hardware error event */
+ qemu_set_irq(qdev_get_gpio_in(gpio_err_dev, 0), 1);
+}
+
static Notifier virt_system_powerdown_notifier = {
.notify = virt_powerdown_req
};
+static Notifier virt_hardware_error_notifier = {
+ .notify = virt_error_notify_req
+};
+
static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
{
char *nodename;
@@ -739,6 +750,10 @@ static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
gpio_key_dev = sysbus_create_simple("gpio-key", -1,
qdev_get_gpio_in(pl061_dev, 3));
+
+ gpio_err_dev = sysbus_create_simple("gpio-key", -1,
+ qdev_get_gpio_in(pl061_dev, 4));
+
qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
@@ -755,6 +770,9 @@ static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
/* connect powerdown request */
qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
+ /* connect hardware error notify request */
+ qemu_register_hardware_error_notifier(&virt_hardware_error_notifier);
+
g_free(nodename);
}
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index b213696..86931cf 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -75,6 +75,7 @@ void qemu_register_wakeup_notifier(Notifier *notifier);
void qemu_system_shutdown_request(ShutdownCause reason);
void qemu_system_powerdown_request(void);
void qemu_register_powerdown_notifier(Notifier *notifier);
+void qemu_register_hardware_error_notifier(Notifier *notifier);
void qemu_system_debug_request(void);
void qemu_system_vmstop_request(RunState reason);
void qemu_system_vmstop_request_prepare(void);
@@ -93,6 +94,8 @@ void qemu_remove_machine_init_done_notifier(Notifier *notify);
void qemu_announce_self(void);
+void qemu_hardware_error_notify(void);
+
extern int autostart;
typedef enum {
diff --git a/vl.c b/vl.c
index d632693..3552f7d 100644
--- a/vl.c
+++ b/vl.c
@@ -1614,6 +1614,8 @@ static int suspend_requested;
static WakeupReason wakeup_reason;
static NotifierList powerdown_notifiers =
NOTIFIER_LIST_INITIALIZER(powerdown_notifiers);
+static NotifierList hardware_error_notifiers =
+ NOTIFIER_LIST_INITIALIZER(hardware_error_notifiers);
static NotifierList suspend_notifiers =
NOTIFIER_LIST_INITIALIZER(suspend_notifiers);
static NotifierList wakeup_notifiers =
@@ -1850,12 +1852,22 @@ void qemu_register_powerdown_notifier(Notifier *notifier)
notifier_list_add(&powerdown_notifiers, notifier);
}
+void qemu_register_hardware_error_notifier(Notifier *notifier)
+{
+ notifier_list_add(&hardware_error_notifiers, notifier);
+}
+
void qemu_system_debug_request(void)
{
debug_requested = 1;
qemu_notify_event();
}
+void qemu_hardware_error_notify(void)
+{
+ notifier_list_notify(&hardware_error_notifiers, NULL);
+}
+
static bool main_loop_should_exit(void)
{
RunState r;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 11/12] hw/arm/virt: Add RAS platform version for migration
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Support this feature since version 2.10, disable it by
default in the old version.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Shannon's comments to add platform version in [1].
[1]: https://lkml.org/lkml/2017/8/25/821
---
hw/arm/virt-acpi-build.c | 14 +++++++++-----
hw/arm/virt.c | 4 ++++
include/hw/arm/virt.h | 1 +
3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 92c8c38..961b67d 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -801,10 +801,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_spcr(tables_blob, tables->linker, vms);
- acpi_add_table(table_offsets, tables_blob);
- build_error_block(tables->hardware_errors, tables->linker);
- build_apei_ghes(tables_blob, tables->hardware_errors, tables->linker);
-
+ if (!vmc->no_ras) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_error_block(tables->hardware_errors, tables->linker);
+ build_apei_ghes(tables_blob, tables->hardware_errors, tables->linker);
+ }
if (nb_numa_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
@@ -891,6 +892,7 @@ static const VMStateDescription vmstate_virt_acpi_build = {
void virt_acpi_setup(VirtMachineState *vms)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
AcpiBuildTables tables;
AcpiBuildState *build_state;
@@ -922,7 +924,9 @@ void virt_acpi_setup(VirtMachineState *vms)
fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
acpi_data_len(tables.tcpalog));
- ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
+ if (!vmc->no_ras) {
+ ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
+ }
build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
ACPI_BUILD_RSDP_FILE, 0);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 68495c2..ab79988 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1732,8 +1732,12 @@ static void virt_2_9_instance_init(Object *obj)
static void virt_machine_2_9_options(MachineClass *mc)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_2_10_options(mc);
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9);
+ /* memory recovery feature was introduced with 2.10 */
+ vmc->no_ras = true;
}
DEFINE_VIRT_MACHINE(2, 9)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 33b0ff3..8fbd664 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -84,6 +84,7 @@ typedef struct {
bool disallow_affinity_adjustment;
bool no_its;
bool no_pmu;
+ bool no_ras;
bool claim_edge_triggered_timers;
} VirtMachineClass;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 11/12] hw/arm/virt: Add RAS platform version for migration
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Support this feature since version 2.10, disable it by
default in the old version.
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
---
Address Shannon's comments to add platform version in [1].
[1]: https://lkml.org/lkml/2017/8/25/821
---
hw/arm/virt-acpi-build.c | 14 +++++++++-----
hw/arm/virt.c | 4 ++++
include/hw/arm/virt.h | 1 +
3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 92c8c38..961b67d 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -801,10 +801,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_spcr(tables_blob, tables->linker, vms);
- acpi_add_table(table_offsets, tables_blob);
- build_error_block(tables->hardware_errors, tables->linker);
- build_apei_ghes(tables_blob, tables->hardware_errors, tables->linker);
-
+ if (!vmc->no_ras) {
+ acpi_add_table(table_offsets, tables_blob);
+ build_error_block(tables->hardware_errors, tables->linker);
+ build_apei_ghes(tables_blob, tables->hardware_errors, tables->linker);
+ }
if (nb_numa_nodes > 0) {
acpi_add_table(table_offsets, tables_blob);
@@ -891,6 +892,7 @@ static const VMStateDescription vmstate_virt_acpi_build = {
void virt_acpi_setup(VirtMachineState *vms)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
AcpiBuildTables tables;
AcpiBuildState *build_state;
@@ -922,7 +924,9 @@ void virt_acpi_setup(VirtMachineState *vms)
fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
acpi_data_len(tables.tcpalog));
- ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
+ if (!vmc->no_ras) {
+ ghes_add_fw_cfg(vms->fw_cfg, tables.hardware_errors);
+ }
build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
ACPI_BUILD_RSDP_FILE, 0);
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 68495c2..ab79988 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1732,8 +1732,12 @@ static void virt_2_9_instance_init(Object *obj)
static void virt_machine_2_9_options(MachineClass *mc)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_2_10_options(mc);
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_9);
+ /* memory recovery feature was introduced with 2.10 */
+ vmc->no_ras = true;
}
DEFINE_VIRT_MACHINE(2, 9)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 33b0ff3..8fbd664 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -84,6 +84,7 @@ typedef struct {
bool disallow_affinity_adjustment;
bool no_its;
bool no_pmu;
+ bool no_ras;
bool claim_edge_triggered_timers;
} VirtMachineClass;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v13 12/12] target-arm: kvm64: handle SIGBUS signal from kernel or KVM
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
@ 2017-11-27 18:49 ` Dongjiu Geng
-1 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translate the host VA which is delivered by host to guest PA, then fill
this PA to CPER and fill the CPER to guest APEI GHES memory, finally
notify guest according the SIGBUS type. There are two kinds of SIGBUS
that QEMU need to handle, which are BUS_MCEERR_AO and BUS_MCEERR_AR.
Guest access device type poisoned memory, generate SError interrupt,
so it reports it to host firmware. Host kernel gets an APEI notification
and memory_failure() causes the affected page to be unmapped from the
guest's stage2, and SIGBUS_MCEERR_AO is sent to user-space. Here Qemu
will create a new CPER and add it to guest APEI GHES memory, and notify the
guest with a GPIO-Signal notification.
When guest hit a PG_hwpoison page, it will trap to KVM as stage2 fault,
here a SIGBUS_MCEERR_AR synchronous signal is delivered to user-space,
Qemu record this error into guest APEI GHES memory and notify guest using
Synchronous-External-Abort(SEA).
Suggested-by: James Morse <james.morse@arm.com>
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Quanming Wu <wuquanming@huawei.com>
---
Address James's comments to record CPER and notify guest for SIGBUS signal handling.
Shown some discussion in [1].
[1]:
https://lkml.org/lkml/2017/2/27/246
https://lkml.org/lkml/2017/9/14/241
https://lkml.org/lkml/2017/9/22/499
---
include/sysemu/kvm.h | 2 +-
target/arm/kvm.c | 2 ++
target/arm/kvm64.c | 34 ++++++++++++++++++++++++++++++++++
3 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 3a458f5..90c1605 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -361,7 +361,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id);
/* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */
unsigned long kvm_arch_vcpu_id(CPUState *cpu);
-#ifdef TARGET_I386
+#if defined(TARGET_I386) || defined(TARGET_AARCH64)
#define KVM_HAVE_MCE_INJECTION 1
void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
#endif
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index d85e36a..8523158 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -26,6 +26,7 @@
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "qemu/log.h"
+#include "exec/ram_addr.h"
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
@@ -182,6 +183,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
+ qemu_register_reset(kvm_unpoison_all, NULL);
type_register_static(&host_arm_cpu_type_info);
return 0;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 7f662e9..d83863d 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -27,6 +27,9 @@
#include "kvm_arm.h"
#include "internals.h"
#include "hw/arm/arm.h"
+#include "exec/ram_addr.h"
+#include "hw/acpi/acpi-defs.h"
+#include "hw/acpi/hest_ghes.h"
static bool have_guest_debug;
@@ -943,6 +946,37 @@ int kvm_arch_get_registers(CPUState *cs)
return ret;
}
+void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
+{
+ ram_addr_t ram_addr;
+ hwaddr paddr;
+
+ assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
+ if (addr) {
+ ram_addr = qemu_ram_addr_from_host(addr);
+ if (ram_addr != RAM_ADDR_INVALID &&
+ kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
+ kvm_hwpoison_page_add(ram_addr);
+ if (code == BUS_MCEERR_AR) {
+ kvm_cpu_synchronize_state(c);
+ ghes_update_guest(ACPI_HEST_NOTIFY_SEA, paddr);
+ kvm_inject_arm_sea(c);
+ } else if (code == BUS_MCEERR_AO) {
+ ghes_update_guest(ACPI_HEST_NOTIFY_GPIO, paddr);
+ qemu_hardware_error_notify();
+ }
+ return;
+ }
+ fprintf(stderr, "Hardware memory error for memory used by "
+ "QEMU itself instead of guest system!\n");
+ }
+
+ if (code == BUS_MCEERR_AR) {
+ fprintf(stderr, "Hardware memory error!\n");
+ exit(1);
+ }
+}
+
/* C6.6.29 BRK instruction */
static const uint32_t brk_insn = 0xd4200000;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH v13 12/12] target-arm: kvm64: handle SIGBUS signal from kernel or KVM
@ 2017-11-27 18:49 ` Dongjiu Geng
0 siblings, 0 replies; 26+ messages in thread
From: Dongjiu Geng @ 2017-11-27 18:49 UTC (permalink / raw)
To: pbonzini, mst, imammedo, zhaoshenglong, peter.maydell, mtosatti,
james.morse, lersek, marc.zyngier, christoffer.dall, rth,
ehabkost, kvm, guohanjun, lijinyue, huangshaoyu, wuquanming,
zhengqiang10, linuxarm, qemu-devel, qemu-arm
Add SIGBUS signal handler. In this handler, it checks the SIGBUS type,
translate the host VA which is delivered by host to guest PA, then fill
this PA to CPER and fill the CPER to guest APEI GHES memory, finally
notify guest according the SIGBUS type. There are two kinds of SIGBUS
that QEMU need to handle, which are BUS_MCEERR_AO and BUS_MCEERR_AR.
Guest access device type poisoned memory, generate SError interrupt,
so it reports it to host firmware. Host kernel gets an APEI notification
and memory_failure() causes the affected page to be unmapped from the
guest's stage2, and SIGBUS_MCEERR_AO is sent to user-space. Here Qemu
will create a new CPER and add it to guest APEI GHES memory, and notify the
guest with a GPIO-Signal notification.
When guest hit a PG_hwpoison page, it will trap to KVM as stage2 fault,
here a SIGBUS_MCEERR_AR synchronous signal is delivered to user-space,
Qemu record this error into guest APEI GHES memory and notify guest using
Synchronous-External-Abort(SEA).
Suggested-by: James Morse <james.morse@arm.com>
Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
Signed-off-by: Quanming Wu <wuquanming@huawei.com>
---
Address James's comments to record CPER and notify guest for SIGBUS signal handling.
Shown some discussion in [1].
[1]:
https://lkml.org/lkml/2017/2/27/246
https://lkml.org/lkml/2017/9/14/241
https://lkml.org/lkml/2017/9/22/499
---
include/sysemu/kvm.h | 2 +-
target/arm/kvm.c | 2 ++
target/arm/kvm64.c | 34 ++++++++++++++++++++++++++++++++++
3 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 3a458f5..90c1605 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -361,7 +361,7 @@ bool kvm_vcpu_id_is_valid(int vcpu_id);
/* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */
unsigned long kvm_arch_vcpu_id(CPUState *cpu);
-#ifdef TARGET_I386
+#if defined(TARGET_I386) || defined(TARGET_AARCH64)
#define KVM_HAVE_MCE_INJECTION 1
void kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr);
#endif
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index d85e36a..8523158 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -26,6 +26,7 @@
#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "qemu/log.h"
+#include "exec/ram_addr.h"
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
@@ -182,6 +183,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
cap_has_mp_state = kvm_check_extension(s, KVM_CAP_MP_STATE);
+ qemu_register_reset(kvm_unpoison_all, NULL);
type_register_static(&host_arm_cpu_type_info);
return 0;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 7f662e9..d83863d 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -27,6 +27,9 @@
#include "kvm_arm.h"
#include "internals.h"
#include "hw/arm/arm.h"
+#include "exec/ram_addr.h"
+#include "hw/acpi/acpi-defs.h"
+#include "hw/acpi/hest_ghes.h"
static bool have_guest_debug;
@@ -943,6 +946,37 @@ int kvm_arch_get_registers(CPUState *cs)
return ret;
}
+void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
+{
+ ram_addr_t ram_addr;
+ hwaddr paddr;
+
+ assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
+ if (addr) {
+ ram_addr = qemu_ram_addr_from_host(addr);
+ if (ram_addr != RAM_ADDR_INVALID &&
+ kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
+ kvm_hwpoison_page_add(ram_addr);
+ if (code == BUS_MCEERR_AR) {
+ kvm_cpu_synchronize_state(c);
+ ghes_update_guest(ACPI_HEST_NOTIFY_SEA, paddr);
+ kvm_inject_arm_sea(c);
+ } else if (code == BUS_MCEERR_AO) {
+ ghes_update_guest(ACPI_HEST_NOTIFY_GPIO, paddr);
+ qemu_hardware_error_notify();
+ }
+ return;
+ }
+ fprintf(stderr, "Hardware memory error for memory used by "
+ "QEMU itself instead of guest system!\n");
+ }
+
+ if (code == BUS_MCEERR_AR) {
+ fprintf(stderr, "Hardware memory error!\n");
+ exit(1);
+ }
+}
+
/* C6.6.29 BRK instruction */
static const uint32_t brk_insn = 0xd4200000;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
end of thread, other threads:[~2017-11-27 10:48 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-27 18:49 [PATCH v13 00/12] Add ARMv8 RAS virtualization support in QEMU Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 01/12] ACPI: add related GHES structures and macros definition Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 02/12] ACPI: Add APEI GHES table generation and CPER record support Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 03/12] docs: APEI GHES generation description Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 04/12] ACPI: enable APEI GHES in the configure file and build it Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 05/12] linux-headers: sync against Linux v4.14-rc8 Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 06/12] target-arm: kvm64: detect whether can set vsesr_el2 Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 07/12] target-arm: handle SError interrupt exception from the guest OS Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 08/12] target-arm: kvm64: inject synchronous External Abort Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 09/12] Move related hwpoison page function to accel/kvm/ folder Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 10/12] ARM: ACPI: Add _E04 for hardware error device Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 11/12] hw/arm/virt: Add RAS platform version for migration Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
2017-11-27 18:49 ` [PATCH v13 12/12] target-arm: kvm64: handle SIGBUS signal from kernel or KVM Dongjiu Geng
2017-11-27 18:49 ` [Qemu-devel] " Dongjiu Geng
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