* [U-Boot] [PATCH v2 1/3] rockchip: rk3036: fix pll config for correct frequency
@ 2017-11-30 8:51 Kever Yang
2017-11-30 8:51 ` [U-Boot] [PATCH v2 2/3] rockchip: rk3036: update clock driver for ddr Kever Yang
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Kever Yang @ 2017-11-30 8:51 UTC (permalink / raw)
To: u-boot
There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
so we need to double to pll output and then ddr can work
in correct frequency.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v2:
- update comment for code change
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 460dd60..1d3fc1a 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -34,10 +34,11 @@ struct rk3036_sdram_priv {
struct rk3036_ddr_config ddr_config;
};
-/* use integer mode, 396MHz dpll setting
+/*
+ * use integer mode, dpll output 792MHz and ddr get 396MHz
* refdiv, fbdiv, postdiv1, postdiv2
*/
-const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
+const struct pll_div dpll_init_cfg = {1, 66, 2, 1};
/* 396Mhz ddr timing */
const struct rk3036_ddr_timing ddr_timing = {0x18c,
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v2 2/3] rockchip: rk3036: update clock driver for ddr
2017-11-30 8:51 [U-Boot] [PATCH v2 1/3] rockchip: rk3036: fix pll config for correct frequency Kever Yang
@ 2017-11-30 8:51 ` Kever Yang
2017-11-30 10:26 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-30 8:51 ` [U-Boot] [PATCH v2 3/3] rockchip: rk3036: sdram: correct setting for pll integer mode Kever Yang
2017-11-30 10:26 ` [U-Boot] [U-Boot, v2, 1/3] rockchip: rk3036: fix pll config for correct frequency Philipp Tomsich
2 siblings, 1 reply; 6+ messages in thread
From: Kever Yang @ 2017-11-30 8:51 UTC (permalink / raw)
To: u-boot
After the MASK MACRO update, we need to update the driver at the same time.
This is a fix to:
37943aa rockchip: rk3036: clean mask definition for cru reg
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v2: None
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 1d3fc1a..a06ef7b 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -330,29 +330,26 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
struct rk3036_pll *pll = &priv->cru->pll[1];
/* pll enter slow-mode */
- rk_clrsetreg(&priv->cru->cru_mode_con,
- DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
/* use integer mode */
rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_clrsetreg(&pll->con0,
- PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
+ PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
(dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
dpll_init_cfg.fbdiv);
- rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
- PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
- (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
- dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
+ rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+ (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
+ dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
/* waiting for pll lock */
while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
rockchip_udelay(1);
/* PLL enter normal-mode */
- rk_clrsetreg(&priv->cru->cru_mode_con,
- DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+ rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
DPLL_MODE_NORM << DPLL_MODE_SHIFT);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v2 3/3] rockchip: rk3036: sdram: correct setting for pll integer mode
2017-11-30 8:51 [U-Boot] [PATCH v2 1/3] rockchip: rk3036: fix pll config for correct frequency Kever Yang
2017-11-30 8:51 ` [U-Boot] [PATCH v2 2/3] rockchip: rk3036: update clock driver for ddr Kever Yang
@ 2017-11-30 8:51 ` Kever Yang
2017-11-30 10:26 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-30 10:26 ` [U-Boot] [U-Boot, v2, 1/3] rockchip: rk3036: fix pll config for correct frequency Philipp Tomsich
2 siblings, 1 reply; 6+ messages in thread
From: Kever Yang @ 2017-11-30 8:51 UTC (permalink / raw)
To: u-boot
According to rk3036 TRM, should be set to '1' for the pll
integer mode, while the '0' means the frac mode.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
---
Changes in v2: None
arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index a06ef7b..e5393ec 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -334,7 +334,7 @@ static void rkdclk_init(struct rk3036_sdram_priv *priv)
DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
/* use integer mode */
- rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+ rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
rk_clrsetreg(&pll->con0,
PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [U-Boot, v2, 3/3] rockchip: rk3036: sdram: correct setting for pll integer mode
2017-11-30 8:51 ` [U-Boot] [PATCH v2 3/3] rockchip: rk3036: sdram: correct setting for pll integer mode Kever Yang
@ 2017-11-30 10:26 ` Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2017-11-30 10:26 UTC (permalink / raw)
To: u-boot
> According to rk3036 TRM, should be set to '1' for the pll
> integer mode, while the '0' means the frac mode.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
> arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [U-Boot, v2, 1/3] rockchip: rk3036: fix pll config for correct frequency
2017-11-30 8:51 [U-Boot] [PATCH v2 1/3] rockchip: rk3036: fix pll config for correct frequency Kever Yang
2017-11-30 8:51 ` [U-Boot] [PATCH v2 2/3] rockchip: rk3036: update clock driver for ddr Kever Yang
2017-11-30 8:51 ` [U-Boot] [PATCH v2 3/3] rockchip: rk3036: sdram: correct setting for pll integer mode Kever Yang
@ 2017-11-30 10:26 ` Philipp Tomsich
2 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2017-11-30 10:26 UTC (permalink / raw)
To: u-boot
> There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy,
> so we need to double to pll output and then ddr can work
> in correct frequency.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2:
> - update comment for code change
>
> arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [U-Boot, v2, 2/3] rockchip: rk3036: update clock driver for ddr
2017-11-30 8:51 ` [U-Boot] [PATCH v2 2/3] rockchip: rk3036: update clock driver for ddr Kever Yang
@ 2017-11-30 10:26 ` Philipp Tomsich
0 siblings, 0 replies; 6+ messages in thread
From: Philipp Tomsich @ 2017-11-30 10:26 UTC (permalink / raw)
To: u-boot
> After the MASK MACRO update, we need to update the driver at the same time.
> This is a fix to:
> 37943aa rockchip: rk3036: clean mask definition for cru reg
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
> arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
Applied to u-boot-rockchip, thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-11-30 10:26 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-30 8:51 [U-Boot] [PATCH v2 1/3] rockchip: rk3036: fix pll config for correct frequency Kever Yang
2017-11-30 8:51 ` [U-Boot] [PATCH v2 2/3] rockchip: rk3036: update clock driver for ddr Kever Yang
2017-11-30 10:26 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-30 8:51 ` [U-Boot] [PATCH v2 3/3] rockchip: rk3036: sdram: correct setting for pll integer mode Kever Yang
2017-11-30 10:26 ` [U-Boot] [U-Boot, v2, " Philipp Tomsich
2017-11-30 10:26 ` [U-Boot] [U-Boot, v2, 1/3] rockchip: rk3036: fix pll config for correct frequency Philipp Tomsich
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.