From: Vidya Sagar <vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> To: treding-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, kthota-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Subject: [PATCH V3 0/2] Tegra PCIe end point config space map code refactoring Date: Mon, 4 Dec 2017 23:23:48 +0530 [thread overview] Message-ID: <1512410030-21038-1-git-send-email-vidyas@nvidia.com> (raw) PCIe host controller in Tegra SoCs has 1GB of aperture available for mapping end points config space, IO and BARs. In that, currently 256MB is being reserved for mapping end points configuration space which leaves less memory space available for mapping end points BARs on some of the platforms. This patch series attempts to map only 4K space from 1GB aperture to access end points configuration space. Currently, this change can benefit T20 and T186 in saving (i.e. repurposed to use for BAR mapping) physical space as well as kernel virtual mapping space, it saves only kernel virtual address space in T30, T124, T132 and T210. NOTE: Since T186 PCIe DT entry is not yet present in main line (it is currently merged to 'for-4.15/arm64/dt' branch), nothing gets broken with this change for T186. For older platforms (T20, T30, T124, T132, T210), this change works fine without any DT modifications Testing Done on T124, T210 & T186: Enumeration and basic functionality of immediate devices Enumeration of devices behind a PCIe switch Complete 4K configuration space access Vidya Sagar (2): PCI: tegra: refactor config space mapping code ARM64: tegra: limit PCIe config space mapping to 4K for T186 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +- drivers/pci/host/pci-tegra.c | 125 ++++++++++--------------------- 2 files changed, 44 insertions(+), 89 deletions(-) -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com> To: <treding@nvidia.com>, <bhelgaas@google.com> Cc: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>, <kthota@nvidia.com>, <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <robh+dt@kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH V3 0/2] Tegra PCIe end point config space map code refactoring Date: Mon, 4 Dec 2017 23:23:48 +0530 [thread overview] Message-ID: <1512410030-21038-1-git-send-email-vidyas@nvidia.com> (raw) PCIe host controller in Tegra SoCs has 1GB of aperture available for mapping end points config space, IO and BARs. In that, currently 256MB is being reserved for mapping end points configuration space which leaves less memory space available for mapping end points BARs on some of the platforms. This patch series attempts to map only 4K space from 1GB aperture to access end points configuration space. Currently, this change can benefit T20 and T186 in saving (i.e. repurposed to use for BAR mapping) physical space as well as kernel virtual mapping space, it saves only kernel virtual address space in T30, T124, T132 and T210. NOTE: Since T186 PCIe DT entry is not yet present in main line (it is currently merged to 'for-4.15/arm64/dt' branch), nothing gets broken with this change for T186. For older platforms (T20, T30, T124, T132, T210), this change works fine without any DT modifications Testing Done on T124, T210 & T186: Enumeration and basic functionality of immediate devices Enumeration of devices behind a PCIe switch Complete 4K configuration space access Vidya Sagar (2): PCI: tegra: refactor config space mapping code ARM64: tegra: limit PCIe config space mapping to 4K for T186 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +- drivers/pci/host/pci-tegra.c | 125 ++++++++++--------------------- 2 files changed, 44 insertions(+), 89 deletions(-) -- 2.7.4
next reply other threads:[~2017-12-04 17:53 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-12-04 17:53 Vidya Sagar [this message] 2017-12-04 17:53 ` [PATCH V3 0/2] Tegra PCIe end point config space map code refactoring Vidya Sagar [not found] ` <1512410030-21038-1-git-send-email-vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-12-04 17:53 ` [PATCH V3 1/2] PCI: tegra: refactor config space mapping code Vidya Sagar 2017-12-04 17:53 ` Vidya Sagar 2017-12-04 17:53 ` [PATCH V3 2/2] ARM64: tegra: limit PCIe config space mapping to 4K for T186 Vidya Sagar 2017-12-04 17:53 ` Vidya Sagar 2017-12-11 10:54 ` [PATCH V3 0/2] Tegra PCIe end point config space map code refactoring Thierry Reding 2017-12-11 10:54 ` Thierry Reding 2017-12-11 17:54 ` Bjorn Helgaas [not found] ` <20171211175452.GC16032-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org> 2017-12-12 11:01 ` Lorenzo Pieralisi 2017-12-12 11:01 ` Lorenzo Pieralisi [not found] ` <20171212110158.GA30601-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> 2017-12-12 12:22 ` Thierry Reding 2017-12-12 12:22 ` Thierry Reding 2017-12-14 10:37 ` Lorenzo Pieralisi 2017-12-14 10:37 ` Lorenzo Pieralisi [not found] ` <20171214103722.GC697-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> 2017-12-14 14:01 ` Thierry Reding 2017-12-14 14:01 ` Thierry Reding -- strict thread matches above, loose matches on Subject: below -- 2017-10-24 6:44 Vidya Sagar 2017-10-24 6:44 ` Vidya Sagar [not found] ` <1508827489-10842-1-git-send-email-vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-10-24 20:15 ` Bjorn Helgaas 2017-10-24 20:15 ` Bjorn Helgaas 2017-11-06 19:51 ` Bjorn Helgaas [not found] ` <20171106195123.GG31930-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org> 2017-11-20 10:27 ` Vidya Sagar 2017-11-20 10:27 ` Vidya Sagar
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