* [RFC i-g-t] tests/perf_pmu: Verify engine busyness accuracy
@ 2017-12-12 14:53 Tvrtko Ursulin
2017-12-12 15:05 ` Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Tvrtko Ursulin @ 2017-12-12 14:53 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
A subtest to verify that the engine busyness is reported with expected
accuracy on platforms where the feature is available.
We test three patterns: 2%, 50% and 98% load per engine.
Problematic part is we also rely on scheduling latencies and the no-op
batch calibration accuracy. For these reasons we use a large-ish tolerance
and also set the load emitting process to SCHED_FIFO.
Load calibration is also moved to a subtest group fixture so the set-up
time is shared between all subtests which use it.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
tests/perf_pmu.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 115 insertions(+), 10 deletions(-)
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index db7696115a7b..ec6b0ee1cb86 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -35,6 +35,7 @@
#include <dirent.h>
#include <time.h>
#include <poll.h>
+#include <sched.h>
#include "igt.h"
#include "igt_core.h"
@@ -79,6 +80,17 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
close(fd);
}
+static uint64_t __pmu_read_single(int fd, uint64_t *ts)
+{
+ uint64_t data[2];
+
+ igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
+
+ *ts = data[1];
+
+ return data[0];
+}
+
static uint64_t pmu_read_single(int fd)
{
uint64_t data[2];
@@ -665,6 +677,77 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
assert_within_epsilon(val[1], slept, tolerance);
}
+static void
+accuracy(int gem_fd, const struct intel_execution_engine2 *e,
+ unsigned long cal_ms_sz, unsigned long target_busy_pct)
+{
+ const unsigned long busy_us = 2500;
+ const unsigned long idle_us = 100 * (busy_us - target_busy_pct *
+ busy_us / 100) / target_busy_pct;
+ const unsigned int test_us = 1e6;
+ double busy_r;
+ uint64_t val[2];
+ uint64_t ts[2];
+ int fd;
+
+ igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
+
+ assert_within_epsilon((double)busy_us / (busy_us + idle_us),
+ (double)target_busy_pct / 100.0, tolerance);
+
+ /* Emit PWM pattern on the engine from a child. */
+ igt_fork(child, 1) {
+ struct sched_param rt = { .sched_priority = 99 };
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ const unsigned long loops = test_us / (busy_us + idle_us);
+ const unsigned long sz = ALIGN(busy_us * cal_ms_sz / 1000,
+ sizeof(uint32_t));
+ struct drm_i915_gem_exec_object2 obj = { };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffers_ptr = to_user_pointer(&obj),
+ .buffer_count = 1,
+ .flags = e2ring(gem_fd, e)
+ };
+ unsigned long i;
+
+ /* We need the best sleep accuracy we can get. */
+ igt_require(sched_setscheduler(0,
+ SCHED_FIFO | SCHED_RESET_ON_FORK,
+ &rt) == 0);
+
+ obj.handle = gem_create(gem_fd, sz);
+ gem_write(gem_fd, obj.handle, sz - sizeof(bbe), &bbe,
+ sizeof(bbe));
+
+ for (i = 0; i < loops; i++) {
+ gem_execbuf(gem_fd, &eb);
+ gem_sync(gem_fd, obj.handle);
+ usleep(idle_us);
+ }
+
+ gem_close(gem_fd, obj.handle);
+ }
+
+ /* Let child run. */
+ usleep(test_us / 4);
+
+ /* Collect engine busyness for a subset of child runtime. */
+ fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ val[0] = __pmu_read_single(fd, &ts[0]);
+ usleep(test_us / 2);
+ val[1] = __pmu_read_single(fd, &ts[1]);
+ close(fd);
+
+ igt_waitchildren();
+
+ busy_r = (double)(val[1] - val[0]) / (ts[1] - ts[0]);
+
+ igt_info("error=%.2f%%\n",
+ 100.0 - 100.0 * (busy_r / ((double)target_busy_pct / 100.0)));
+
+ assert_within_epsilon(busy_r, (double)target_busy_pct / 100.0, 0.2);
+}
+
/**
* Tests that i915 PMU corectly errors out in invalid initialization.
* i915 PMU is uncore PMU, thus:
@@ -801,7 +884,7 @@ static void cpu_hotplug(int gem_fd)
static unsigned long calibrate_nop(int fd, const uint64_t calibration_us)
{
- const uint64_t cal_min_us = calibration_us * 3;
+ const uint64_t cal_min_us = 2e6;
const unsigned int tolerance_pct = 10;
const uint32_t bbe = MI_BATCH_BUFFER_END;
const unsigned int loops = 17;
@@ -844,7 +927,7 @@ static unsigned long calibrate_nop(int fd, const uint64_t calibration_us)
}
static void
-test_interrupts(int gem_fd)
+test_interrupts(int gem_fd, unsigned long cal_ms_sz)
{
const uint32_t bbe = MI_BATCH_BUFFER_END;
const unsigned int test_duration_ms = 1000;
@@ -854,14 +937,14 @@ test_interrupts(int gem_fd)
.buffer_count = 1,
.flags = I915_EXEC_FENCE_OUT,
};
- unsigned long sz;
- igt_spin_t *spin;
const int target = 30;
+ const unsigned long sz = ALIGN(test_duration_ms * cal_ms_sz / target,
+ sizeof(uint32_t));
+ igt_spin_t *spin;
struct pollfd pfd;
uint64_t idle, busy;
int fd;
- sz = calibrate_nop(gem_fd, test_duration_ms * 1000 / target);
gem_quiescent_gpu(gem_fd);
fd = open_pmu(I915_PMU_INTERRUPTS);
@@ -1178,11 +1261,33 @@ igt_main
igt_subtest("frequency")
test_frequency(fd);
- /**
- * Test interrupt count reporting.
- */
- igt_subtest("interrupts")
- test_interrupts(fd);
+ igt_subtest_group {
+ unsigned long cal_ms_sz;
+
+ igt_fixture {
+ cal_ms_sz = calibrate_nop(fd, 1e3);
+ igt_debug("%lu nops for a 1ms batch\n", cal_ms_sz / 4);
+ }
+
+ /**
+ * Test interrupt count reporting.
+ */
+ igt_subtest("interrupts")
+ test_interrupts(fd, cal_ms_sz);
+
+ for_each_engine_class_instance(fd, e) {
+ unsigned int pct[] = { 2, 50, 98 };
+
+ /**
+ * Check engine busyness accuracy is as expected.
+ */
+ for (i = 0; i < ARRAY_SIZE(pct); i++) {
+ igt_subtest_f("busy-accuracy-%u-%s", pct[i],
+ e->name)
+ accuracy(fd, e, cal_ms_sz, pct[i]);
+ }
+ }
+ }
/**
* Test RC6 residency reporting.
--
2.14.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [RFC i-g-t] tests/perf_pmu: Verify engine busyness accuracy
2017-12-12 14:53 [RFC i-g-t] tests/perf_pmu: Verify engine busyness accuracy Tvrtko Ursulin
@ 2017-12-12 15:05 ` Chris Wilson
2017-12-12 15:21 ` Tvrtko Ursulin
2017-12-12 15:29 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-12-12 17:49 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2017-12-12 15:05 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx
Quoting Tvrtko Ursulin (2017-12-12 14:53:00)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> A subtest to verify that the engine busyness is reported with expected
> accuracy on platforms where the feature is available.
>
> We test three patterns: 2%, 50% and 98% load per engine.
>
> Problematic part is we also rely on scheduling latencies and the no-op
> batch calibration accuracy. For these reasons we use a large-ish tolerance
> and also set the load emitting process to SCHED_FIFO.
>
> Load calibration is also moved to a subtest group fixture so the set-up
> time is shared between all subtests which use it.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> tests/perf_pmu.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 115 insertions(+), 10 deletions(-)
>
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index db7696115a7b..ec6b0ee1cb86 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -35,6 +35,7 @@
> #include <dirent.h>
> #include <time.h>
> #include <poll.h>
> +#include <sched.h>
>
> #include "igt.h"
> #include "igt_core.h"
> @@ -79,6 +80,17 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
> close(fd);
> }
>
> +static uint64_t __pmu_read_single(int fd, uint64_t *ts)
> +{
> + uint64_t data[2];
> +
> + igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
> +
> + *ts = data[1];
> +
> + return data[0];
> +}
> +
> static uint64_t pmu_read_single(int fd)
> {
> uint64_t data[2];
> @@ -665,6 +677,77 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
> assert_within_epsilon(val[1], slept, tolerance);
> }
>
> +static void
> +accuracy(int gem_fd, const struct intel_execution_engine2 *e,
> + unsigned long cal_ms_sz, unsigned long target_busy_pct)
> +{
> + const unsigned long busy_us = 2500;
> + const unsigned long idle_us = 100 * (busy_us - target_busy_pct *
> + busy_us / 100) / target_busy_pct;
> + const unsigned int test_us = 1e6;
> + double busy_r;
> + uint64_t val[2];
> + uint64_t ts[2];
> + int fd;
> +
> + igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
> +
> + assert_within_epsilon((double)busy_us / (busy_us + idle_us),
> + (double)target_busy_pct / 100.0, tolerance);
> +
> + /* Emit PWM pattern on the engine from a child. */
> + igt_fork(child, 1) {
> + struct sched_param rt = { .sched_priority = 99 };
> + const uint32_t bbe = MI_BATCH_BUFFER_END;
> + const unsigned long loops = test_us / (busy_us + idle_us);
> + const unsigned long sz = ALIGN(busy_us * cal_ms_sz / 1000,
> + sizeof(uint32_t));
> + struct drm_i915_gem_exec_object2 obj = { };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffers_ptr = to_user_pointer(&obj),
> + .buffer_count = 1,
> + .flags = e2ring(gem_fd, e)
> + };
> + unsigned long i;
> +
> + /* We need the best sleep accuracy we can get. */
> + igt_require(sched_setscheduler(0,
> + SCHED_FIFO | SCHED_RESET_ON_FORK,
> + &rt) == 0);
> +
> + obj.handle = gem_create(gem_fd, sz);
> + gem_write(gem_fd, obj.handle, sz - sizeof(bbe), &bbe,
> + sizeof(bbe));
> +
> + for (i = 0; i < loops; i++) {
> + gem_execbuf(gem_fd, &eb);
> + gem_sync(gem_fd, obj.handle);
> + usleep(idle_us);
> + }
> +
> + gem_close(gem_fd, obj.handle);
> + }
Wouldn't using a signaling thread and a igt_spin_t give you better
accuracy, with the bonus of not requiring calibration?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC i-g-t] tests/perf_pmu: Verify engine busyness accuracy
2017-12-12 15:05 ` Chris Wilson
@ 2017-12-12 15:21 ` Tvrtko Ursulin
2017-12-12 15:24 ` Chris Wilson
0 siblings, 1 reply; 6+ messages in thread
From: Tvrtko Ursulin @ 2017-12-12 15:21 UTC (permalink / raw)
To: Chris Wilson, Tvrtko Ursulin, Intel-gfx
On 12/12/2017 15:05, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2017-12-12 14:53:00)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> A subtest to verify that the engine busyness is reported with expected
>> accuracy on platforms where the feature is available.
>>
>> We test three patterns: 2%, 50% and 98% load per engine.
>>
>> Problematic part is we also rely on scheduling latencies and the no-op
>> batch calibration accuracy. For these reasons we use a large-ish tolerance
>> and also set the load emitting process to SCHED_FIFO.
>>
>> Load calibration is also moved to a subtest group fixture so the set-up
>> time is shared between all subtests which use it.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>> tests/perf_pmu.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
>> 1 file changed, 115 insertions(+), 10 deletions(-)
>>
>> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
>> index db7696115a7b..ec6b0ee1cb86 100644
>> --- a/tests/perf_pmu.c
>> +++ b/tests/perf_pmu.c
>> @@ -35,6 +35,7 @@
>> #include <dirent.h>
>> #include <time.h>
>> #include <poll.h>
>> +#include <sched.h>
>>
>> #include "igt.h"
>> #include "igt_core.h"
>> @@ -79,6 +80,17 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
>> close(fd);
>> }
>>
>> +static uint64_t __pmu_read_single(int fd, uint64_t *ts)
>> +{
>> + uint64_t data[2];
>> +
>> + igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
>> +
>> + *ts = data[1];
>> +
>> + return data[0];
>> +}
>> +
>> static uint64_t pmu_read_single(int fd)
>> {
>> uint64_t data[2];
>> @@ -665,6 +677,77 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
>> assert_within_epsilon(val[1], slept, tolerance);
>> }
>>
>> +static void
>> +accuracy(int gem_fd, const struct intel_execution_engine2 *e,
>> + unsigned long cal_ms_sz, unsigned long target_busy_pct)
>> +{
>> + const unsigned long busy_us = 2500;
>> + const unsigned long idle_us = 100 * (busy_us - target_busy_pct *
>> + busy_us / 100) / target_busy_pct;
>> + const unsigned int test_us = 1e6;
>> + double busy_r;
>> + uint64_t val[2];
>> + uint64_t ts[2];
>> + int fd;
>> +
>> + igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
>> +
>> + assert_within_epsilon((double)busy_us / (busy_us + idle_us),
>> + (double)target_busy_pct / 100.0, tolerance);
>> +
>> + /* Emit PWM pattern on the engine from a child. */
>> + igt_fork(child, 1) {
>> + struct sched_param rt = { .sched_priority = 99 };
>> + const uint32_t bbe = MI_BATCH_BUFFER_END;
>> + const unsigned long loops = test_us / (busy_us + idle_us);
>> + const unsigned long sz = ALIGN(busy_us * cal_ms_sz / 1000,
>> + sizeof(uint32_t));
>> + struct drm_i915_gem_exec_object2 obj = { };
>> + struct drm_i915_gem_execbuffer2 eb = {
>> + .buffers_ptr = to_user_pointer(&obj),
>> + .buffer_count = 1,
>> + .flags = e2ring(gem_fd, e)
>> + };
>> + unsigned long i;
>> +
>> + /* We need the best sleep accuracy we can get. */
>> + igt_require(sched_setscheduler(0,
>> + SCHED_FIFO | SCHED_RESET_ON_FORK,
>> + &rt) == 0);
>> +
>> + obj.handle = gem_create(gem_fd, sz);
>> + gem_write(gem_fd, obj.handle, sz - sizeof(bbe), &bbe,
>> + sizeof(bbe));
>> +
>> + for (i = 0; i < loops; i++) {
>> + gem_execbuf(gem_fd, &eb);
>> + gem_sync(gem_fd, obj.handle);
>> + usleep(idle_us);
>> + }
>> +
>> + gem_close(gem_fd, obj.handle);
>> + }
>
> Wouldn't using a signaling thread and a igt_spin_t give you better
> accuracy, with the bonus of not requiring calibration?
Sounds like it could be better if main source of error is calibration
and not the scheduler. I have no idea at the moment which one it is so
I'll give it a try.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [RFC i-g-t] tests/perf_pmu: Verify engine busyness accuracy
2017-12-12 15:21 ` Tvrtko Ursulin
@ 2017-12-12 15:24 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2017-12-12 15:24 UTC (permalink / raw)
To: Tvrtko Ursulin, Tvrtko Ursulin, Intel-gfx
Quoting Tvrtko Ursulin (2017-12-12 15:21:32)
>
> On 12/12/2017 15:05, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2017-12-12 14:53:00)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> A subtest to verify that the engine busyness is reported with expected
> >> accuracy on platforms where the feature is available.
> >>
> >> We test three patterns: 2%, 50% and 98% load per engine.
> >>
> >> Problematic part is we also rely on scheduling latencies and the no-op
> >> batch calibration accuracy. For these reasons we use a large-ish tolerance
> >> and also set the load emitting process to SCHED_FIFO.
> >>
> >> Load calibration is also moved to a subtest group fixture so the set-up
> >> time is shared between all subtests which use it.
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> ---
> >> tests/perf_pmu.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
> >> 1 file changed, 115 insertions(+), 10 deletions(-)
> >>
> >> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> >> index db7696115a7b..ec6b0ee1cb86 100644
> >> --- a/tests/perf_pmu.c
> >> +++ b/tests/perf_pmu.c
> >> @@ -35,6 +35,7 @@
> >> #include <dirent.h>
> >> #include <time.h>
> >> #include <poll.h>
> >> +#include <sched.h>
> >>
> >> #include "igt.h"
> >> #include "igt_core.h"
> >> @@ -79,6 +80,17 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
> >> close(fd);
> >> }
> >>
> >> +static uint64_t __pmu_read_single(int fd, uint64_t *ts)
> >> +{
> >> + uint64_t data[2];
> >> +
> >> + igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
> >> +
> >> + *ts = data[1];
> >> +
> >> + return data[0];
> >> +}
> >> +
> >> static uint64_t pmu_read_single(int fd)
> >> {
> >> uint64_t data[2];
> >> @@ -665,6 +677,77 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
> >> assert_within_epsilon(val[1], slept, tolerance);
> >> }
> >>
> >> +static void
> >> +accuracy(int gem_fd, const struct intel_execution_engine2 *e,
> >> + unsigned long cal_ms_sz, unsigned long target_busy_pct)
> >> +{
> >> + const unsigned long busy_us = 2500;
> >> + const unsigned long idle_us = 100 * (busy_us - target_busy_pct *
> >> + busy_us / 100) / target_busy_pct;
> >> + const unsigned int test_us = 1e6;
> >> + double busy_r;
> >> + uint64_t val[2];
> >> + uint64_t ts[2];
> >> + int fd;
> >> +
> >> + igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
> >> +
> >> + assert_within_epsilon((double)busy_us / (busy_us + idle_us),
> >> + (double)target_busy_pct / 100.0, tolerance);
> >> +
> >> + /* Emit PWM pattern on the engine from a child. */
> >> + igt_fork(child, 1) {
> >> + struct sched_param rt = { .sched_priority = 99 };
> >> + const uint32_t bbe = MI_BATCH_BUFFER_END;
> >> + const unsigned long loops = test_us / (busy_us + idle_us);
> >> + const unsigned long sz = ALIGN(busy_us * cal_ms_sz / 1000,
> >> + sizeof(uint32_t));
> >> + struct drm_i915_gem_exec_object2 obj = { };
> >> + struct drm_i915_gem_execbuffer2 eb = {
> >> + .buffers_ptr = to_user_pointer(&obj),
> >> + .buffer_count = 1,
> >> + .flags = e2ring(gem_fd, e)
> >> + };
> >> + unsigned long i;
> >> +
> >> + /* We need the best sleep accuracy we can get. */
> >> + igt_require(sched_setscheduler(0,
> >> + SCHED_FIFO | SCHED_RESET_ON_FORK,
> >> + &rt) == 0);
> >> +
> >> + obj.handle = gem_create(gem_fd, sz);
> >> + gem_write(gem_fd, obj.handle, sz - sizeof(bbe), &bbe,
> >> + sizeof(bbe));
> >> +
> >> + for (i = 0; i < loops; i++) {
> >> + gem_execbuf(gem_fd, &eb);
> >> + gem_sync(gem_fd, obj.handle);
> >> + usleep(idle_us);
> >> + }
> >> +
> >> + gem_close(gem_fd, obj.handle);
> >> + }
> >
> > Wouldn't using a signaling thread and a igt_spin_t give you better
> > accuracy, with the bonus of not requiring calibration?
>
> Sounds like it could be better if main source of error is calibration
> and not the scheduler. I have no idea at the moment which one it is so
> I'll give it a try.
I think you'll still need a RT-99 thread, but it's worth a shot. :)
-Chris
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for tests/perf_pmu: Verify engine busyness accuracy
2017-12-12 14:53 [RFC i-g-t] tests/perf_pmu: Verify engine busyness accuracy Tvrtko Ursulin
2017-12-12 15:05 ` Chris Wilson
@ 2017-12-12 15:29 ` Patchwork
2017-12-12 17:49 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-12-12 15:29 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: tests/perf_pmu: Verify engine busyness accuracy
URL : https://patchwork.freedesktop.org/series/35232/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
74407418720ff7a9de7caabec05d4c3afe9a5c51 igt/kms_flip: Allow very large bo to fail pageflips with E2BIG
with latest DRM-Tip kernel build CI_DRM_3501
f49a92217adc drm-tip: 2017y-12m-12d-12h-12m-26s UTC integration manifest
Testlist changes:
+igt@perf_pmu@busy-accuracy-2-bcs0
+igt@perf_pmu@busy-accuracy-2-rcs0
+igt@perf_pmu@busy-accuracy-2-vcs0
+igt@perf_pmu@busy-accuracy-2-vcs1
+igt@perf_pmu@busy-accuracy-2-vecs0
+igt@perf_pmu@busy-accuracy-50-bcs0
+igt@perf_pmu@busy-accuracy-50-rcs0
+igt@perf_pmu@busy-accuracy-50-vcs0
+igt@perf_pmu@busy-accuracy-50-vcs1
+igt@perf_pmu@busy-accuracy-50-vecs0
+igt@perf_pmu@busy-accuracy-98-bcs0
+igt@perf_pmu@busy-accuracy-98-rcs0
+igt@perf_pmu@busy-accuracy-98-vcs0
+igt@perf_pmu@busy-accuracy-98-vcs1
+igt@perf_pmu@busy-accuracy-98-vecs0
Test debugfs_test:
Subgroup read_all_entries:
dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test gem_exec_suspend:
Subgroup basic-s3:
incomplete -> PASS (fi-glk-1) fdo#103326
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#103326 https://bugs.freedesktop.org/show_bug.cgi?id=103326
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:447s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:443s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:390s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:516s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:510s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:506s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:488s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:473s
fi-elk-e7500 total:224 pass:163 dwarn:14 dfail:1 fail:0 skip:45
fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:268s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:548s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:371s
fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:262s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:393s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:478s
fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:448s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:487s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:525s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:478s
fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:531s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:589s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:536s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:565s
fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:514s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:496s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:452s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:424s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:593s
fi-cnl-y total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:618s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_656/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.IGT: success for tests/perf_pmu: Verify engine busyness accuracy
2017-12-12 14:53 [RFC i-g-t] tests/perf_pmu: Verify engine busyness accuracy Tvrtko Ursulin
2017-12-12 15:05 ` Chris Wilson
2017-12-12 15:29 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-12-12 17:49 ` Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2017-12-12 17:49 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: tests/perf_pmu: Verify engine busyness accuracy
URL : https://patchwork.freedesktop.org/series/35232/
State : success
== Summary ==
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test kms_flip:
Subgroup wf_vblank-vs-modeset:
pass -> DMESG-WARN (shard-hsw) fdo#102614
Subgroup dpms-vs-vblank-race:
pass -> FAIL (shard-hsw) fdo#103060
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
pass -> FAIL (shard-snb) fdo#101623
Test gem_tiled_swapping:
Subgroup non-threaded:
incomplete -> PASS (shard-snb) fdo#104009
pass -> INCOMPLETE (shard-hsw) fdo#104218
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#104009 https://bugs.freedesktop.org/show_bug.cgi?id=104009
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
shard-hsw total:2687 pass:1509 dwarn:2 dfail:0 fail:10 skip:1165 time:9448s
shard-snb total:2727 pass:1309 dwarn:1 dfail:0 fail:12 skip:1405 time:8291s
Blacklisted hosts:
shard-apl total:2659 pass:1642 dwarn:1 dfail:0 fail:22 skip:992 time:13025s
shard-kbl total:2727 pass:1821 dwarn:1 dfail:0 fail:24 skip:881 time:11269s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_656/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-12-12 17:49 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-12 14:53 [RFC i-g-t] tests/perf_pmu: Verify engine busyness accuracy Tvrtko Ursulin
2017-12-12 15:05 ` Chris Wilson
2017-12-12 15:21 ` Tvrtko Ursulin
2017-12-12 15:24 ` Chris Wilson
2017-12-12 15:29 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-12-12 17:49 ` ✓ Fi.CI.IGT: " Patchwork
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