Re: [PATCH 2/3] drm/i915: Show IPEIR and IPEHR in the engine dump

From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/3] drm/i915: Show IPEIR and IPEHR in the engine dump
Date: Mon, 18 Dec 2017 11:14:35 +0000	[thread overview]
Message-ID: <151359567537.29397.9083721026446750275@mail.alporthouse.com> (raw)
In-Reply-To: <20171217132852.30642-2-chris@chris-wilson.co.uk>

Quoting Chris Wilson (2017-12-17 13:28:51)
> A useful bit of information for inspecting GPU stalls from
> intel_engine_dump() are the error registers, IPEIR and IPEHR.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_engine_cs.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 510e0bc3a377..05bd9e17452c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1757,6 +1757,13 @@ void intel_engine_dump(struct intel_engine_cs *engine,
>         addr = intel_engine_get_last_batch_head(engine);
>         drm_printf(m, "    BBADDR: 0x%08x_%08x\n",
>                    upper_32_bits(addr), lower_32_bits(addr));
> +       addr = I915_READ(RING_DMA_FADD(engine->mmio_base));

if (GEN >= 8)
	addr |= (u64)I915_READ(RING_DMA_FADD_UDW) << 32;
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx