* [PATCH 1/4] drm/amd/pp: move smu_version out vega to hwmgr
@ 2017-12-19 8:11 Rex Zhu
[not found] ` <1513671094-5078-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Rex Zhu @ 2017-12-19 8:11 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Ie8c32663aa0d61a1dfdd8e019509cb551f137aa0
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 8 ++++----
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 -
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index f0295fa..2d55dab 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -426,9 +426,9 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
data->smu_features[GNLD_VR0HOT].supported = true;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
- vega10_read_arg_from_smc(hwmgr, &(data->smu_version));
+ vega10_read_arg_from_smc(hwmgr, &(hwmgr->smu_version));
/* ACG firmware has major version 5 */
- if ((data->smu_version & 0xff000000) == 0x5000000)
+ if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
data->smu_features[GNLD_ACG].supported = true;
if (data->registry_data.didt_support)
@@ -2879,8 +2879,8 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
"DPM is already running right , skipping re-enablement!",
return 0);
- if ((data->smu_version == 0x001c2c00) ||
- (data->smu_version == 0x001c2d00)) {
+ if ((hwmgr->smu_version == 0x001c2c00) ||
+ (hwmgr->smu_version == 0x001c2d00)) {
tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
PP_ASSERT_WITH_CODE(!tmp_result,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index 8f7358c..e8507ff 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -387,7 +387,6 @@ struct vega10_hwmgr {
struct vega10_smc_state_table smc_state_table;
uint32_t config_telemetry;
- uint32_t smu_version;
uint32_t acg_loop_state;
uint32_t mem_channels;
};
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 39eedbc..565fe08 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -692,6 +692,7 @@ enum PP_TABLE_VERSION {
struct pp_hwmgr {
uint32_t chip_family;
uint32_t chip_id;
+ uint32_t smu_version;
uint32_t pp_table_version;
void *device;
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/4] drm/amd/pp: update smu_version value for CI/VI
[not found] ` <1513671094-5078-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-12-19 8:11 ` Rex Zhu
[not found] ` <1513671094-5078-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 8:11 ` [PATCH 3/4] drm/amd/pp: get Rv smu_version and notify amdgpu Rex Zhu
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Rex Zhu @ 2017-12-19 8:11 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Ia55a0bc2cde45cb995d92ff054e57b07ed548f08
---
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 1 +
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 +-
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index c6c741a..0b4a556 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -2316,6 +2316,7 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
hwmgr->is_kicker = info.is_kicker;
+ hwmgr->smu_version = info.version;
byte_count = info.image_size;
src = (uint8_t *)info.kptr;
start_addr = info.ucode_start_address;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index d75bb99..1253126 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -204,7 +204,7 @@ static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
return -EINVAL;
}
-
+ hwmgr->smu_version = info.version;
/* wait for smc boot up */
PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
RCU_UC_EVENTS, boot_seq_done, 0);
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 7f5359a..cb95e88 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -535,7 +535,7 @@ int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
hwmgr->is_kicker = info.is_kicker;
-
+ hwmgr->smu_version = info.version;
result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
return result;
--
1.9.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/4] drm/amd/pp: get Rv smu_version and notify amdgpu
[not found] ` <1513671094-5078-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 8:11 ` [PATCH 2/4] drm/amd/pp: update smu_version value for CI/VI Rex Zhu
@ 2017-12-19 8:11 ` Rex Zhu
[not found] ` <1513671094-5078-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 8:11 ` [PATCH 4/4] drm/amd/pp: implement force_dpm_level on rv Rex Zhu
2017-12-19 14:28 ` [PATCH 1/4] drm/amd/pp: move smu_version out vega to hwmgr Alex Deucher
3 siblings, 1 reply; 8+ messages in thread
From: Rex Zhu @ 2017-12-19 8:11 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 3 +++
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 8 ++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 85d2149..13607e2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -801,6 +801,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
else
strcpy(fw_name, "amdgpu/vega10_smc.bin");
break;
+ case CHIP_RAVEN:
+ adev->pm.fw_version = info->version;
+ return 0;
default:
DRM_ERROR("SMC firmware not supported\n");
return -EINVAL;
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index b98ade6..2d662b4 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -305,6 +305,14 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr)
static int rv_start_smu(struct pp_hwmgr *hwmgr)
{
+ struct cgs_firmware_info info = {0};
+
+ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
+ rv_read_arg_from_smc(hwmgr, &hwmgr->smu_version);
+ info.version = hwmgr->smu_version >> 8;
+
+ cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
+
if (rv_verify_smc_interface(hwmgr))
return -EINVAL;
if (rv_smc_enable_sdma(hwmgr))
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] drm/amd/pp: implement force_dpm_level on rv
[not found] ` <1513671094-5078-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 8:11 ` [PATCH 2/4] drm/amd/pp: update smu_version value for CI/VI Rex Zhu
2017-12-19 8:11 ` [PATCH 3/4] drm/amd/pp: get Rv smu_version and notify amdgpu Rex Zhu
@ 2017-12-19 8:11 ` Rex Zhu
[not found] ` <1513671094-5078-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 14:28 ` [PATCH 1/4] drm/amd/pp: move smu_version out vega to hwmgr Alex Deucher
3 siblings, 1 reply; 8+ messages in thread
From: Rex Zhu @ 2017-12-19 8:11 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
user can change engine/mclk/soc/vcn clocks on Rv
v3: add smu version check
v2: fix no return statement
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 123 +++++++++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 15 +++
2 files changed, 138 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index ae11a85..569073e 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -484,6 +484,129 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level)
{
+ if (hwmgr->smu_version < 0x1E3700) {
+ pr_info("smu firmware version too old, can not set dpm level\n");
+ return 0;
+ }
+
+ switch (level) {
+ case AMD_DPM_FORCED_LEVEL_HIGH:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinSocclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinVcn,
+ RAVEN_UMD_PSTATE_VCE);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxSocclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxVcn,
+ RAVEN_UMD_PSTATE_VCE);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ break;
+ case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinSocclkByFreq,
+ RAVEN_UMD_PSTATE_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinVcn,
+ RAVEN_UMD_PSTATE_VCE);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxSocclkByFreq,
+ RAVEN_UMD_PSTATE_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxVcn,
+ RAVEN_UMD_PSTATE_VCE);
+ break;
+ case AMD_DPM_FORCED_LEVEL_AUTO:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinSocclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinVcn,
+ RAVEN_UMD_PSTATE_MIN_VCE);
+
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxSocclkByFreq,
+ RAVEN_UMD_PSTATE_PEAK_SOCCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxVcn,
+ RAVEN_UMD_PSTATE_VCE);
+ break;
+ case AMD_DPM_FORCED_LEVEL_LOW:
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxGfxClk,
+ RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetHardMinFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_SetSoftMaxFclkByFreq,
+ RAVEN_UMD_PSTATE_MIN_FCLK);
+ break;
+ case AMD_DPM_FORCED_LEVEL_MANUAL:
+ case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
+ default:
+ break;
+ }
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index 9dc5030..c3bc311 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -304,4 +304,19 @@ struct rv_hwmgr {
int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
+/* UMD PState Raven Msg Parameters in MHz */
+#define RAVEN_UMD_PSTATE_GFXCLK 700
+#define RAVEN_UMD_PSTATE_SOCCLK 626
+#define RAVEN_UMD_PSTATE_FCLK 933
+#define RAVEN_UMD_PSTATE_VCE 0x03C00320
+
+#define RAVEN_UMD_PSTATE_PEAK_GFXCLK 1100
+#define RAVEN_UMD_PSTATE_PEAK_SOCCLK 757
+#define RAVEN_UMD_PSTATE_PEAK_FCLK 1200
+
+#define RAVEN_UMD_PSTATE_MIN_GFXCLK 200
+#define RAVEN_UMD_PSTATE_MIN_FCLK 400
+#define RAVEN_UMD_PSTATE_MIN_SOCCLK 200
+#define RAVEN_UMD_PSTATE_MIN_VCE 0x0190012C
+
#endif
--
1.9.1
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] drm/amd/pp: move smu_version out vega to hwmgr
[not found] ` <1513671094-5078-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-12-19 8:11 ` [PATCH 4/4] drm/amd/pp: implement force_dpm_level on rv Rex Zhu
@ 2017-12-19 14:28 ` Alex Deucher
3 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2017-12-19 14:28 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Dec 19, 2017 at 3:11 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
Please include a better patch description. Something like:
Move the smu_version to common code so it can be shared by other asics.
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> Change-Id: Ie8c32663aa0d61a1dfdd8e019509cb551f137aa0
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 8 ++++----
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 -
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
> 3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index f0295fa..2d55dab 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -426,9 +426,9 @@ static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
> data->smu_features[GNLD_VR0HOT].supported = true;
>
> smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
> - vega10_read_arg_from_smc(hwmgr, &(data->smu_version));
> + vega10_read_arg_from_smc(hwmgr, &(hwmgr->smu_version));
> /* ACG firmware has major version 5 */
> - if ((data->smu_version & 0xff000000) == 0x5000000)
> + if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
> data->smu_features[GNLD_ACG].supported = true;
>
> if (data->registry_data.didt_support)
> @@ -2879,8 +2879,8 @@ static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> "DPM is already running right , skipping re-enablement!",
> return 0);
>
> - if ((data->smu_version == 0x001c2c00) ||
> - (data->smu_version == 0x001c2d00)) {
> + if ((hwmgr->smu_version == 0x001c2c00) ||
> + (hwmgr->smu_version == 0x001c2d00)) {
> tmp_result = smum_send_msg_to_smc_with_parameter(hwmgr,
> PPSMC_MSG_UpdatePkgPwrPidAlpha, 1);
> PP_ASSERT_WITH_CODE(!tmp_result,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> index 8f7358c..e8507ff 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> @@ -387,7 +387,6 @@ struct vega10_hwmgr {
> struct vega10_smc_state_table smc_state_table;
>
> uint32_t config_telemetry;
> - uint32_t smu_version;
> uint32_t acg_loop_state;
> uint32_t mem_channels;
> };
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 39eedbc..565fe08 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -692,6 +692,7 @@ enum PP_TABLE_VERSION {
> struct pp_hwmgr {
> uint32_t chip_family;
> uint32_t chip_id;
> + uint32_t smu_version;
>
> uint32_t pp_table_version;
> void *device;
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/4] drm/amd/pp: update smu_version value for CI/VI
[not found] ` <1513671094-5078-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-12-19 14:29 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2017-12-19 14:29 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Dec 19, 2017 at 3:11 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: Ia55a0bc2cde45cb995d92ff054e57b07ed548f08
Missing your signed-off-by. Please also include a patch description. E.g.,
Set the new common smu firmware version for smu7 parts (CI and VI).
With those things fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 1 +
> drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 2 +-
> drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 +-
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> index c6c741a..0b4a556 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> @@ -2316,6 +2316,7 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
> cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
>
> hwmgr->is_kicker = info.is_kicker;
> + hwmgr->smu_version = info.version;
> byte_count = info.image_size;
> src = (uint8_t *)info.kptr;
> start_addr = info.ucode_start_address;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> index d75bb99..1253126 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> @@ -204,7 +204,7 @@ static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
> pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
> return -EINVAL;
> }
> -
> + hwmgr->smu_version = info.version;
> /* wait for smc boot up */
> PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
> RCU_UC_EVENTS, boot_seq_done, 0);
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> index 7f5359a..cb95e88 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
> @@ -535,7 +535,7 @@ int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
> smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
>
> hwmgr->is_kicker = info.is_kicker;
> -
> + hwmgr->smu_version = info.version;
> result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
>
> return result;
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/4] drm/amd/pp: get Rv smu_version and notify amdgpu
[not found] ` <1513671094-5078-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-12-19 14:35 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2017-12-19 14:35 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Dec 19, 2017 at 3:11 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
Please include a patch description. E.g.,
The smu firmware is loaded by the sbios on APUs, so query it from the
smu and update the
smu fw version info that is reported to userspace.
With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Can you update CZ/ST as well if you get a chance?
Thanks,
Alex
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 3 +++
> drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c | 8 ++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index 85d2149..13607e2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -801,6 +801,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
> else
> strcpy(fw_name, "amdgpu/vega10_smc.bin");
> break;
> + case CHIP_RAVEN:
> + adev->pm.fw_version = info->version;
> + return 0;
> default:
> DRM_ERROR("SMC firmware not supported\n");
> return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> index b98ade6..2d662b4 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
> @@ -305,6 +305,14 @@ static int rv_smu_fini(struct pp_hwmgr *hwmgr)
>
> static int rv_start_smu(struct pp_hwmgr *hwmgr)
> {
> + struct cgs_firmware_info info = {0};
> +
> + smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
> + rv_read_arg_from_smc(hwmgr, &hwmgr->smu_version);
> + info.version = hwmgr->smu_version >> 8;
> +
> + cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
> +
> if (rv_verify_smc_interface(hwmgr))
> return -EINVAL;
> if (rv_smc_enable_sdma(hwmgr))
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4/4] drm/amd/pp: implement force_dpm_level on rv
[not found] ` <1513671094-5078-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-12-19 14:39 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2017-12-19 14:39 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Tue, Dec 19, 2017 at 3:11 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> user can change engine/mclk/soc/vcn clocks on Rv
>
> v3: add smu version check
> v2: fix no return statement
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 123 +++++++++++++++++++++++++
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 15 +++
> 2 files changed, 138 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index ae11a85..569073e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -484,6 +484,129 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
> static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
> enum amd_dpm_forced_level level)
> {
> + if (hwmgr->smu_version < 0x1E3700) {
> + pr_info("smu firmware version too old, can not set dpm level\n");
> + return 0;
> + }
> +
> + switch (level) {
> + case AMD_DPM_FORCED_LEVEL_HIGH:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinSocclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinVcn,
> + RAVEN_UMD_PSTATE_VCE);
> +
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxSocclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxVcn,
> + RAVEN_UMD_PSTATE_VCE);
> + break;
> + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + break;
> + case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + break;
> + case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinSocclkByFreq,
> + RAVEN_UMD_PSTATE_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinVcn,
> + RAVEN_UMD_PSTATE_VCE);
> +
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxSocclkByFreq,
> + RAVEN_UMD_PSTATE_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxVcn,
> + RAVEN_UMD_PSTATE_VCE);
> + break;
> + case AMD_DPM_FORCED_LEVEL_AUTO:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinSocclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinVcn,
> + RAVEN_UMD_PSTATE_MIN_VCE);
> +
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_PEAK_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxSocclkByFreq,
> + RAVEN_UMD_PSTATE_PEAK_SOCCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxVcn,
> + RAVEN_UMD_PSTATE_VCE);
> + break;
> + case AMD_DPM_FORCED_LEVEL_LOW:
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxGfxClk,
> + RAVEN_UMD_PSTATE_MIN_GFXCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetHardMinFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxFclkByFreq,
> + RAVEN_UMD_PSTATE_MIN_FCLK);
> + break;
> + case AMD_DPM_FORCED_LEVEL_MANUAL:
> + case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
> + default:
> + break;
> + }
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> index 9dc5030..c3bc311 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
> @@ -304,4 +304,19 @@ struct rv_hwmgr {
>
> int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
>
> +/* UMD PState Raven Msg Parameters in MHz */
> +#define RAVEN_UMD_PSTATE_GFXCLK 700
> +#define RAVEN_UMD_PSTATE_SOCCLK 626
> +#define RAVEN_UMD_PSTATE_FCLK 933
> +#define RAVEN_UMD_PSTATE_VCE 0x03C00320
> +
> +#define RAVEN_UMD_PSTATE_PEAK_GFXCLK 1100
> +#define RAVEN_UMD_PSTATE_PEAK_SOCCLK 757
> +#define RAVEN_UMD_PSTATE_PEAK_FCLK 1200
> +
> +#define RAVEN_UMD_PSTATE_MIN_GFXCLK 200
> +#define RAVEN_UMD_PSTATE_MIN_FCLK 400
> +#define RAVEN_UMD_PSTATE_MIN_SOCCLK 200
> +#define RAVEN_UMD_PSTATE_MIN_VCE 0x0190012C
> +
> #endif
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-12-19 14:39 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-19 8:11 [PATCH 1/4] drm/amd/pp: move smu_version out vega to hwmgr Rex Zhu
[not found] ` <1513671094-5078-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 8:11 ` [PATCH 2/4] drm/amd/pp: update smu_version value for CI/VI Rex Zhu
[not found] ` <1513671094-5078-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 14:29 ` Alex Deucher
2017-12-19 8:11 ` [PATCH 3/4] drm/amd/pp: get Rv smu_version and notify amdgpu Rex Zhu
[not found] ` <1513671094-5078-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 14:35 ` Alex Deucher
2017-12-19 8:11 ` [PATCH 4/4] drm/amd/pp: implement force_dpm_level on rv Rex Zhu
[not found] ` <1513671094-5078-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-12-19 14:39 ` Alex Deucher
2017-12-19 14:28 ` [PATCH 1/4] drm/amd/pp: move smu_version out vega to hwmgr Alex Deucher
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