* [PATCH 1/2] drm/amd/pp: Add memory clock info display on Cz/St
@ 2018-01-08 9:57 Rex Zhu
[not found] ` <1515405451-16492-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Rex Zhu @ 2018-01-08 9:57 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
show mclk info as in MHz on Cz/St as
0: 333Mhz *
1: 800Mhz
Change-Id: Ie5932ac81b15565edb154ec6c00b35a99ab52b73
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index b83fe97..f68dd08 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1584,6 +1584,7 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
+ struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
struct phm_clock_voltage_dependency_table *sclk_table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
int i, now, size = 0;
@@ -1601,6 +1602,18 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
i, sclk_table->entries[i].clk / 100,
(i == now) ? "*" : "");
break;
+ case PP_MCLK:
+ now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC,
+ ixTARGET_AND_CURRENT_PROFILE_INDEX),
+ TARGET_AND_CURRENT_PROFILE_INDEX,
+ CURR_MCLK_INDEX);
+
+ for (i = CZ_NUM_NBPMEMORYCLOCK; i > 0; i--)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
+ (CZ_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
+ break;
default:
break;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
[not found] ` <1515405451-16492-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-08 9:57 ` Rex Zhu
[not found] ` <1515405451-16492-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-08 15:07 ` [PATCH 1/2] drm/amd/pp: Add memory clock info display on Cz/St Deucher, Alexander
1 sibling, 1 reply; 11+ messages in thread
From: Rex Zhu @ 2018-01-08 9:57 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
The additional output are at the end of sclk/mclk info as
cat pp_dpm_mclk
0: 300Mhz *
1: 1650Mhz
P: 300Mhz
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index f68dd08..03dfba0 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, sclk_table->entries[i].clk / 100,
(i == now) ? "*" : "");
+ size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
break;
case PP_MCLK:
now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
@@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
(CZ_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
+ size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 409a56b..88c6ad8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
data->gfx_max_freq_limit / 100,
((data->gfx_max_freq_limit / 100)
== now) ? "*" : "");
+ size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
break;
case PP_MCLK:
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
@@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
mclk_table->entries[i].clk / 100,
((mclk_table->entries[i].clk / 100)
== now) ? "*" : "");
+ size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 72031bd..1bdcd86 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, sclk_table->dpm_levels[i].value / 100,
(i == now) ? "*" : "");
+ size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
break;
case PP_MCLK:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
@@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, mclk_table->dpm_levels[i].value / 100,
(i == now) ? "*" : "");
+ size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
break;
case PP_PCIE:
pcie_speed = smu7_get_current_pcie_speed(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index cb35f4f..cab50fc 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, sclk_table->dpm_levels[i].value / 100,
(i == now) ? "*" : "");
+ size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
break;
case PP_MCLK:
if (data->registry_data.mclk_dpm_key_disabled)
@@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
size += sprintf(buf + size, "%d: %uMhz %s\n",
i, mclk_table->dpm_levels[i].value / 100,
(i == now) ? "*" : "");
+ size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
break;
case PP_PCIE:
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
--
1.9.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/2] drm/amd/pp: Add memory clock info display on Cz/St
[not found] ` <1515405451-16492-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-08 9:57 ` [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels Rex Zhu
@ 2018-01-08 15:07 ` Deucher, Alexander
1 sibling, 0 replies; 11+ messages in thread
From: Deucher, Alexander @ 2018-01-08 15:07 UTC (permalink / raw)
To: Zhu, Rex, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1: Type: text/plain, Size: 2619 bytes --]
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, January 8, 2018 4:57:30 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Zhu, Rex
Subject: [PATCH 1/2] drm/amd/pp: Add memory clock info display on Cz/St
show mclk info as in MHz on Cz/St as
0: 333Mhz *
1: 800Mhz
Change-Id: Ie5932ac81b15565edb154ec6c00b35a99ab52b73
Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index b83fe97..f68dd08 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1584,6 +1584,7 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
+ struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
struct phm_clock_voltage_dependency_table *sclk_table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
int i, now, size = 0;
@@ -1601,6 +1602,18 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
i, sclk_table->entries[i].clk / 100,
(i == now) ? "*" : "");
break;
+ case PP_MCLK:
+ now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC,
+ ixTARGET_AND_CURRENT_PROFILE_INDEX),
+ TARGET_AND_CURRENT_PROFILE_INDEX,
+ CURR_MCLK_INDEX);
+
+ for (i = CZ_NUM_NBPMEMORYCLOCK; i > 0; i--)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
+ (CZ_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
+ break;
default:
break;
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
[not found] ` <1515405451-16492-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-08 19:20 ` Felix Kuehling
[not found] ` <b0f6ccfc-eb6b-be04-9122-4b3dd9b73979-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Felix Kuehling @ 2018-01-08 19:20 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Russell, Kent
[+Kent]
What does stable pstate mean? What is it used for?
Hi Kent,
Is this going to confuse rocm_smi?
Regards,
Felix
On 2018-01-08 04:57 AM, Rex Zhu wrote:
> The additional output are at the end of sclk/mclk info as
> cat pp_dpm_mclk
> 0: 300Mhz *
> 1: 1650Mhz
> P: 300Mhz
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>
> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
> 4 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index f68dd08..03dfba0 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, sclk_table->entries[i].clk / 100,
> (i == now) ? "*" : "");
> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
> (CZ_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> index 409a56b..88c6ad8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
> data->gfx_max_freq_limit / 100,
> ((data->gfx_max_freq_limit / 100)
> == now) ? "*" : "");
> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
> mclk_table->entries[i].clk / 100,
> ((mclk_table->entries[i].clk / 100)
> == now) ? "*" : "");
> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 72031bd..1bdcd86 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, sclk_table->dpm_levels[i].value / 100,
> (i == now) ? "*" : "");
> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
> @@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, mclk_table->dpm_levels[i].value / 100,
> (i == now) ? "*" : "");
> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
> break;
> case PP_PCIE:
> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index cb35f4f..cab50fc 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, sclk_table->dpm_levels[i].value / 100,
> (i == now) ? "*" : "");
> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
> break;
> case PP_MCLK:
> if (data->registry_data.mclk_dpm_key_disabled)
> @@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> i, mclk_table->dpm_levels[i].value / 100,
> (i == now) ? "*" : "");
> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
> break;
> case PP_PCIE:
> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
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* Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
[not found] ` <b0f6ccfc-eb6b-be04-9122-4b3dd9b73979-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-08 19:34 ` Alex Deucher
[not found] ` <CADnq5_O_Dqj51NLAYddSsDg_9ZvLF-+niEmVwEZ45=OZ27PMYQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-01-08 20:22 ` Russell, Kent
0 siblings, 2 replies; 11+ messages in thread
From: Alex Deucher @ 2018-01-08 19:34 UTC (permalink / raw)
To: Felix Kuehling; +Cc: Russell, Kent, amd-gfx list
On Mon, Jan 8, 2018 at 2:20 PM, Felix Kuehling <felix.kuehling@amd.com> wrote:
> [+Kent]
>
> What does stable pstate mean? What is it used for?
This is used for the profiling stuff in force_performance_level. It
disables clock and power gating and sets stable clock levels for doing
performance profiling.
Alex
>
> Hi Kent,
>
> Is this going to confuse rocm_smi?
>
> Regards,
> Felix
>
>
> On 2018-01-08 04:57 AM, Rex Zhu wrote:
>> The additional output are at the end of sclk/mclk info as
>> cat pp_dpm_mclk
>> 0: 300Mhz *
>> 1: 1650Mhz
>> P: 300Mhz
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>>
>> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
>> ---
>> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>> 4 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index f68dd08..03dfba0 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->entries[i].clk / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
>> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
>> (CZ_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> index 409a56b..88c6ad8 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> data->gfx_max_freq_limit / 100,
>> ((data->gfx_max_freq_limit / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> mclk_table->entries[i].clk / 100,
>> ((mclk_table->entries[i].clk / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 72031bd..1bdcd86 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
>> @@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> index cb35f4f..cab50fc 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> @@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> if (data->registry_data.mclk_dpm_key_disabled)
>> @@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n", hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
[not found] ` <CADnq5_O_Dqj51NLAYddSsDg_9ZvLF-+niEmVwEZ45=OZ27PMYQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-01-08 19:51 ` Russell, Kent
[not found] ` <BN6PR1201MB01804E0A67A34D58715983AC85130-6iU6OBHu2P/H0AMcJMwsYmrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Russell, Kent @ 2018-01-08 19:51 UTC (permalink / raw)
To: Alex Deucher, Kuehling, Felix; +Cc: amd-gfx list
And yes, it will confuse the SMI in a couple functions, but thankfully it's nice enough that I can fix it with a couple lines.
So just to make sure that I understand this correctly, if a user were to echo P to the pp_dpm_mclk file, it would disable clockgating and powergating and keep the memory clocks at a stable level (likely level 0)? And this would have no impact on the SCLK or Power Profile or anything else, just the mclk? Just asking so I know how to implement it in the SMI. Thanks!
Kent
-----Original Message-----
From: Alex Deucher [mailto:alexdeucher@gmail.com]
Sent: Monday, January 08, 2018 2:35 PM
To: Kuehling, Felix
Cc: amd-gfx list; Russell, Kent
Subject: Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
On Mon, Jan 8, 2018 at 2:20 PM, Felix Kuehling <felix.kuehling@amd.com> wrote:
> [+Kent]
>
> What does stable pstate mean? What is it used for?
This is used for the profiling stuff in force_performance_level. It disables clock and power gating and sets stable clock levels for doing performance profiling.
Alex
>
> Hi Kent,
>
> Is this going to confuse rocm_smi?
>
> Regards,
> Felix
>
>
> On 2018-01-08 04:57 AM, Rex Zhu wrote:
>> The additional output are at the end of sclk/mclk info as cat
>> pp_dpm_mclk
>> 0: 300Mhz *
>> 1: 1650Mhz
>> P: 300Mhz
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>>
>> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
>> ---
>> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>> 4 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index f68dd08..03dfba0 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->entries[i].clk / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> now =
>> PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
>> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
>> (CZ_NUM_NBPMEMORYCLOCK-i ==
>> now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> index 409a56b..88c6ad8 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> data->gfx_max_freq_limit / 100,
>> ((data->gfx_max_freq_limit / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> mclk_table->entries[i].clk / 100,
>> ((mclk_table->entries[i].clk / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 72031bd..1bdcd86 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> smum_send_msg_to_smc(hwmgr,
>> PPSMC_MSG_API_GetMclkFrequency); @@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> index cb35f4f..cab50fc 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> @@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> if (data->registry_data.mclk_dpm_key_disabled)
>> @@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
2018-01-08 19:34 ` Alex Deucher
[not found] ` <CADnq5_O_Dqj51NLAYddSsDg_9ZvLF-+niEmVwEZ45=OZ27PMYQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2018-01-08 20:22 ` Russell, Kent
[not found] ` <BN6PR1201MB0180DCC58FCE82683ED7591485130-6iU6OBHu2P/H0AMcJMwsYmrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
1 sibling, 1 reply; 11+ messages in thread
From: Russell, Kent @ 2018-01-08 20:22 UTC (permalink / raw)
To: Alex Deucher, Kuehling, Felix; +Cc: amd-gfx list
Sorry, I just re-read and saw that this will be in sclk and mclk, not just mclk. So will this have a direct impact on any other functionality, or will it just disable clock/power gating and prevent the clocks from changing?
Kent
-----Original Message-----
From: Russell, Kent
Sent: Monday, January 08, 2018 2:52 PM
To: 'Alex Deucher'; Kuehling, Felix
Cc: amd-gfx list
Subject: RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
And yes, it will confuse the SMI in a couple functions, but thankfully it's nice enough that I can fix it with a couple lines.
So just to make sure that I understand this correctly, if a user were to echo P to the pp_dpm_mclk file, it would disable clockgating and powergating and keep the memory clocks at a stable level (likely level 0)? And this would have no impact on the SCLK or Power Profile or anything else, just the mclk? Just asking so I know how to implement it in the SMI. Thanks!
Kent
-----Original Message-----
From: Alex Deucher [mailto:alexdeucher@gmail.com]
Sent: Monday, January 08, 2018 2:35 PM
To: Kuehling, Felix
Cc: amd-gfx list; Russell, Kent
Subject: Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
On Mon, Jan 8, 2018 at 2:20 PM, Felix Kuehling <felix.kuehling@amd.com> wrote:
> [+Kent]
>
> What does stable pstate mean? What is it used for?
This is used for the profiling stuff in force_performance_level. It disables clock and power gating and sets stable clock levels for doing performance profiling.
Alex
>
> Hi Kent,
>
> Is this going to confuse rocm_smi?
>
> Regards,
> Felix
>
>
> On 2018-01-08 04:57 AM, Rex Zhu wrote:
>> The additional output are at the end of sclk/mclk info as cat
>> pp_dpm_mclk
>> 0: 300Mhz *
>> 1: 1650Mhz
>> P: 300Mhz
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>>
>> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
>> ---
>> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>> 4 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index f68dd08..03dfba0 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->entries[i].clk / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> now =
>> PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
>> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
>> (CZ_NUM_NBPMEMORYCLOCK-i ==
>> now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> index 409a56b..88c6ad8 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> data->gfx_max_freq_limit / 100,
>> ((data->gfx_max_freq_limit / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> mclk_table->entries[i].clk / 100,
>> ((mclk_table->entries[i].clk / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 72031bd..1bdcd86 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> smum_send_msg_to_smc(hwmgr,
>> PPSMC_MSG_API_GetMclkFrequency); @@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> index cb35f4f..cab50fc 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> @@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> if (data->registry_data.mclk_dpm_key_disabled)
>> @@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
[not found] ` <BN6PR1201MB0180DCC58FCE82683ED7591485130-6iU6OBHu2P/H0AMcJMwsYmrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
@ 2018-01-08 21:18 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652592A32877B4A306CA655F7130-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Deucher, Alexander @ 2018-01-08 21:18 UTC (permalink / raw)
To: Russell, Kent, Alex Deucher, Kuehling, Felix; +Cc: amd-gfx list
[-- Attachment #1.1: Type: text/plain, Size: 8570 bytes --]
The changes to the pp_dpm_files are purely informational with this patch (you can't actually interact with the stable pstate) so I think they should be dropped and exposed some other way. Setting the profile modes via force_performance_level forces the clocks and disables clock and power gating. That is the interface you should use to interact with it.
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Russell, Kent <Kent.Russell-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, January 8, 2018 3:22 PM
To: Alex Deucher; Kuehling, Felix
Cc: amd-gfx list
Subject: RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
Sorry, I just re-read and saw that this will be in sclk and mclk, not just mclk. So will this have a direct impact on any other functionality, or will it just disable clock/power gating and prevent the clocks from changing?
Kent
-----Original Message-----
From: Russell, Kent
Sent: Monday, January 08, 2018 2:52 PM
To: 'Alex Deucher'; Kuehling, Felix
Cc: amd-gfx list
Subject: RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
And yes, it will confuse the SMI in a couple functions, but thankfully it's nice enough that I can fix it with a couple lines.
So just to make sure that I understand this correctly, if a user were to echo P to the pp_dpm_mclk file, it would disable clockgating and powergating and keep the memory clocks at a stable level (likely level 0)? And this would have no impact on the SCLK or Power Profile or anything else, just the mclk? Just asking so I know how to implement it in the SMI. Thanks!
Kent
-----Original Message-----
From: Alex Deucher [mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org]
Sent: Monday, January 08, 2018 2:35 PM
To: Kuehling, Felix
Cc: amd-gfx list; Russell, Kent
Subject: Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
On Mon, Jan 8, 2018 at 2:20 PM, Felix Kuehling <felix.kuehling-5C7GfCeVMHo@public.gmane.org> wrote:
> [+Kent]
>
> What does stable pstate mean? What is it used for?
This is used for the profiling stuff in force_performance_level. It disables clock and power gating and sets stable clock levels for doing performance profiling.
Alex
>
> Hi Kent,
>
> Is this going to confuse rocm_smi?
>
> Regards,
> Felix
>
>
> On 2018-01-08 04:57 AM, Rex Zhu wrote:
>> The additional output are at the end of sclk/mclk info as cat
>> pp_dpm_mclk
>> 0: 300Mhz *
>> 1: 1650Mhz
>> P: 300Mhz
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
>>
>> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
>> ---
>> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>> 4 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index f68dd08..03dfba0 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->entries[i].clk / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> now =
>> PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
>> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
>> (CZ_NUM_NBPMEMORYCLOCK-i ==
>> now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> index 409a56b..88c6ad8 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> data->gfx_max_freq_limit / 100,
>> ((data->gfx_max_freq_limit / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> mclk_table->entries[i].clk / 100,
>> ((mclk_table->entries[i].clk / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 72031bd..1bdcd86 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> smum_send_msg_to_smc(hwmgr,
>> PPSMC_MSG_API_GetMclkFrequency); @@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> index cb35f4f..cab50fc 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> @@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> if (data->registry_data.mclk_dpm_key_disabled)
>> @@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
[not found] ` <BN6PR12MB1652592A32877B4A306CA655F7130-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-01-08 21:24 ` Russell, Kent
0 siblings, 0 replies; 11+ messages in thread
From: Russell, Kent @ 2018-01-08 21:24 UTC (permalink / raw)
To: Deucher, Alexander, Alex Deucher, Kuehling, Felix; +Cc: amd-gfx list
[-- Attachment #1.1: Type: text/plain, Size: 9337 bytes --]
Oh perfect. pp_dpm_sclk/pp_dpm_mclk just report what the stable pstate would be. To enact that pstate, we would use the options available in force_performance_level. Thank you for the clarification!
Kent
From: Deucher, Alexander
Sent: Monday, January 08, 2018 4:19 PM
To: Russell, Kent; Alex Deucher; Kuehling, Felix
Cc: amd-gfx list
Subject: Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
The changes to the pp_dpm_files are purely informational with this patch (you can't actually interact with the stable pstate) so I think they should be dropped and exposed some other way. Setting the profile modes via force_performance_level forces the clocks and disables clock and power gating. That is the interface you should use to interact with it.
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-bounces@lists.freedesktop.org>> on behalf of Russell, Kent <Kent.Russell-5C7GfCeVMHo@public.gmane.org<mailto:Kent.Russell-5C7GfCeVMHo@public.gmane.org>>
Sent: Monday, January 8, 2018 3:22 PM
To: Alex Deucher; Kuehling, Felix
Cc: amd-gfx list
Subject: RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
Sorry, I just re-read and saw that this will be in sclk and mclk, not just mclk. So will this have a direct impact on any other functionality, or will it just disable clock/power gating and prevent the clocks from changing?
Kent
-----Original Message-----
From: Russell, Kent
Sent: Monday, January 08, 2018 2:52 PM
To: 'Alex Deucher'; Kuehling, Felix
Cc: amd-gfx list
Subject: RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
And yes, it will confuse the SMI in a couple functions, but thankfully it's nice enough that I can fix it with a couple lines.
So just to make sure that I understand this correctly, if a user were to echo P to the pp_dpm_mclk file, it would disable clockgating and powergating and keep the memory clocks at a stable level (likely level 0)? And this would have no impact on the SCLK or Power Profile or anything else, just the mclk? Just asking so I know how to implement it in the SMI. Thanks!
Kent
-----Original Message-----
From: Alex Deucher [mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org]
Sent: Monday, January 08, 2018 2:35 PM
To: Kuehling, Felix
Cc: amd-gfx list; Russell, Kent
Subject: Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
On Mon, Jan 8, 2018 at 2:20 PM, Felix Kuehling <felix.kuehling-5C7GfCeVMHo@public.gmane.org<mailto:felix.kuehling-5C7GfCeVMHo@public.gmane.org>> wrote:
> [+Kent]
>
> What does stable pstate mean? What is it used for?
This is used for the profiling stuff in force_performance_level. It disables clock and power gating and sets stable clock levels for doing performance profiling.
Alex
>
> Hi Kent,
>
> Is this going to confuse rocm_smi?
>
> Regards,
> Felix
>
>
> On 2018-01-08 04:57 AM, Rex Zhu wrote:
>> The additional output are at the end of sclk/mclk info as cat
>> pp_dpm_mclk
>> 0: 300Mhz *
>> 1: 1650Mhz
>> P: 300Mhz
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org<mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org>>
>>
>> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
>> ---
>> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>> 4 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index f68dd08..03dfba0 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->entries[i].clk / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> now =
>> PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
>> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
>> (CZ_NUM_NBPMEMORYCLOCK-i ==
>> now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> index 409a56b..88c6ad8 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> data->gfx_max_freq_limit / 100,
>> ((data->gfx_max_freq_limit / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> mclk_table->entries[i].clk / 100,
>> ((mclk_table->entries[i].clk / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 72031bd..1bdcd86 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> smum_send_msg_to_smc(hwmgr,
>> PPSMC_MSG_API_GetMclkFrequency); @@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> index cb35f4f..cab50fc 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> @@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> if (data->registry_data.mclk_dpm_key_disabled)
>> @@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>
> _______________________________________________
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
[not found] ` <BN6PR1201MB01804E0A67A34D58715983AC85130-6iU6OBHu2P/H0AMcJMwsYmrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
@ 2018-01-08 21:31 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652949A18C06E8F94F14E8BF7130-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Deucher, Alexander @ 2018-01-08 21:31 UTC (permalink / raw)
To: Russell, Kent, Alex Deucher, Kuehling, Felix; +Cc: amd-gfx list
No, it doesn't do anything today and wouldn't do anything with this patch either. With this patch, it just prints the stable pstate clock level in the output if you read the files so you know what the clocks are when you enable the profiling modes. That's why I think we should expose the stable pstate clocks via a different interface to avoid confusion and not break anything (we can't break existing smi tools out in the wild. To actually enable the various profiling modes, you need to echo one of the profile_* options to force_performance_level. When you select a profile_* option, that disables clock and powergating and sets the stable pstate clocks.
Alex
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Russell, Kent
Sent: Monday, January 8, 2018 2:52 PM
To: Alex Deucher <alexdeucher@gmail.com>; Kuehling, Felix <Felix.Kuehling@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
And yes, it will confuse the SMI in a couple functions, but thankfully it's nice enough that I can fix it with a couple lines.
So just to make sure that I understand this correctly, if a user were to echo P to the pp_dpm_mclk file, it would disable clockgating and powergating and keep the memory clocks at a stable level (likely level 0)? And this would have no impact on the SCLK or Power Profile or anything else, just the mclk? Just asking so I know how to implement it in the SMI. Thanks!
Kent
-----Original Message-----
From: Alex Deucher [mailto:alexdeucher@gmail.com]
Sent: Monday, January 08, 2018 2:35 PM
To: Kuehling, Felix
Cc: amd-gfx list; Russell, Kent
Subject: Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
On Mon, Jan 8, 2018 at 2:20 PM, Felix Kuehling <felix.kuehling@amd.com> wrote:
> [+Kent]
>
> What does stable pstate mean? What is it used for?
This is used for the profiling stuff in force_performance_level. It disables clock and power gating and sets stable clock levels for doing performance profiling.
Alex
>
> Hi Kent,
>
> Is this going to confuse rocm_smi?
>
> Regards,
> Felix
>
>
> On 2018-01-08 04:57 AM, Rex Zhu wrote:
>> The additional output are at the end of sclk/mclk info as cat
>> pp_dpm_mclk
>> 0: 300Mhz *
>> 1: 1650Mhz
>> P: 300Mhz
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>>
>> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
>> ---
>> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>> 4 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index f68dd08..03dfba0 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->entries[i].clk / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> now =
>> PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
>> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
>> (CZ_NUM_NBPMEMORYCLOCK-i ==
>> now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> index 409a56b..88c6ad8 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> data->gfx_max_freq_limit / 100,
>> ((data->gfx_max_freq_limit / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> mclk_table->entries[i].clk / 100,
>> ((mclk_table->entries[i].clk / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 72031bd..1bdcd86 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> smum_send_msg_to_smc(hwmgr,
>> PPSMC_MSG_API_GetMclkFrequency); @@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> index cb35f4f..cab50fc 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> @@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> if (data->registry_data.mclk_dpm_key_disabled)
>> @@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
[not found] ` <BN6PR12MB1652949A18C06E8F94F14E8BF7130-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-01-09 12:25 ` Russell, Kent
0 siblings, 0 replies; 11+ messages in thread
From: Russell, Kent @ 2018-01-09 12:25 UTC (permalink / raw)
To: Deucher, Alexander, Alex Deucher, Kuehling, Felix; +Cc: amd-gfx list
If it helps, it would only break the SMI as it determines the Max Level by using the last line in the clock file as the max. So I made a patch to change that so that it uses the last line in the file that starts with a number (since the pstate starts with P:). But if you want to use a different interface, that’s alright, I am just letting you know that the SMI would break solely due to me making assumptions about the structure of the sclk/mclk file, and that a fix would be trivial.
Kent
-----Original Message-----
From: Deucher, Alexander
Sent: Monday, January 08, 2018 4:31 PM
To: Russell, Kent; Alex Deucher; Kuehling, Felix
Cc: amd-gfx list
Subject: RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
No, it doesn't do anything today and wouldn't do anything with this patch either. With this patch, it just prints the stable pstate clock level in the output if you read the files so you know what the clocks are when you enable the profiling modes. That's why I think we should expose the stable pstate clocks via a different interface to avoid confusion and not break anything (we can't break existing smi tools out in the wild. To actually enable the various profiling modes, you need to echo one of the profile_* options to force_performance_level. When you select a profile_* option, that disables clock and powergating and sets the stable pstate clocks.
Alex
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Russell, Kent
Sent: Monday, January 8, 2018 2:52 PM
To: Alex Deucher <alexdeucher@gmail.com>; Kuehling, Felix <Felix.Kuehling@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
And yes, it will confuse the SMI in a couple functions, but thankfully it's nice enough that I can fix it with a couple lines.
So just to make sure that I understand this correctly, if a user were to echo P to the pp_dpm_mclk file, it would disable clockgating and powergating and keep the memory clocks at a stable level (likely level 0)? And this would have no impact on the SCLK or Power Profile or anything else, just the mclk? Just asking so I know how to implement it in the SMI. Thanks!
Kent
-----Original Message-----
From: Alex Deucher [mailto:alexdeucher@gmail.com]
Sent: Monday, January 08, 2018 2:35 PM
To: Kuehling, Felix
Cc: amd-gfx list; Russell, Kent
Subject: Re: [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels
On Mon, Jan 8, 2018 at 2:20 PM, Felix Kuehling <felix.kuehling@amd.com> wrote:
> [+Kent]
>
> What does stable pstate mean? What is it used for?
This is used for the profiling stuff in force_performance_level. It disables clock and power gating and sets stable clock levels for doing performance profiling.
Alex
>
> Hi Kent,
>
> Is this going to confuse rocm_smi?
>
> Regards,
> Felix
>
>
> On 2018-01-08 04:57 AM, Rex Zhu wrote:
>> The additional output are at the end of sclk/mclk info as cat
>> pp_dpm_mclk
>> 0: 300Mhz *
>> 1: 1650Mhz
>> P: 300Mhz
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>>
>> Change-Id: Idf8eeedb5d399d9ffb7de7a2fb2976c7fa7c01a8
>> ---
>> drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 ++
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 ++
>> 4 files changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> index f68dd08..03dfba0 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
>> @@ -1601,6 +1601,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->entries[i].clk / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> now =
>> PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
>> @@ -1613,6 +1614,7 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
>> (CZ_NUM_NBPMEMORYCLOCK-i ==
>> now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> index 409a56b..88c6ad8 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
>> @@ -756,6 +756,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> data->gfx_max_freq_limit / 100,
>> ((data->gfx_max_freq_limit / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>> @@ -773,6 +774,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
>> mclk_table->entries[i].clk / 100,
>> ((mclk_table->entries[i].clk / 100)
>> == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> default:
>> break;
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> index 72031bd..1bdcd86 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
>> @@ -4372,6 +4372,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> smum_send_msg_to_smc(hwmgr,
>> PPSMC_MSG_API_GetMclkFrequency); @@ -4388,6 +4389,7 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> pcie_speed = smu7_get_current_pcie_speed(hwmgr);
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> index cb35f4f..cab50fc 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> @@ -4565,6 +4565,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, sclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_sclk/100);
>> break;
>> case PP_MCLK:
>> if (data->registry_data.mclk_dpm_key_disabled)
>> @@ -4583,6 +4584,7 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
>> size += sprintf(buf + size, "%d: %uMhz %s\n",
>> i, mclk_table->dpm_levels[i].value / 100,
>> (i == now) ? "*" : "");
>> + size += sprintf(buf + size, "P: %uMhz\n",
>> + hwmgr->pstate_mclk/100);
>> break;
>> case PP_PCIE:
>> PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
>
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-01-09 12:25 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-08 9:57 [PATCH 1/2] drm/amd/pp: Add memory clock info display on Cz/St Rex Zhu
[not found] ` <1515405451-16492-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-08 9:57 ` [PATCH 2/2] drm/amd/pp: Add stable Pstate clk display when print_clock_levels Rex Zhu
[not found] ` <1515405451-16492-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-08 19:20 ` Felix Kuehling
[not found] ` <b0f6ccfc-eb6b-be04-9122-4b3dd9b73979-5C7GfCeVMHo@public.gmane.org>
2018-01-08 19:34 ` Alex Deucher
[not found] ` <CADnq5_O_Dqj51NLAYddSsDg_9ZvLF-+niEmVwEZ45=OZ27PMYQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-01-08 19:51 ` Russell, Kent
[not found] ` <BN6PR1201MB01804E0A67A34D58715983AC85130-6iU6OBHu2P/H0AMcJMwsYmrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2018-01-08 21:31 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652949A18C06E8F94F14E8BF7130-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-01-09 12:25 ` Russell, Kent
2018-01-08 20:22 ` Russell, Kent
[not found] ` <BN6PR1201MB0180DCC58FCE82683ED7591485130-6iU6OBHu2P/H0AMcJMwsYmrFom/aUZj6nBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2018-01-08 21:18 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652592A32877B4A306CA655F7130-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-01-08 21:24 ` Russell, Kent
2018-01-08 15:07 ` [PATCH 1/2] drm/amd/pp: Add memory clock info display on Cz/St Deucher, Alexander
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