* [PATCH] drm/i915: Stop getting the fault address from RING_FAULT_REG
@ 2017-12-22 22:10 Oscar Mateo
2017-12-22 22:25 ` Chris Wilson
2017-12-22 23:18 ` ✗ Fi.CI.BAT: failure for drm/i915: Stop getting the fault address from RING_FAULT_REG (rev2) Patchwork
0 siblings, 2 replies; 7+ messages in thread
From: Oscar Mateo @ 2017-12-22 22:10 UTC (permalink / raw)
To: intel-gfx
This register does not contain it. Instead, we have to look into FAULT_TLB_DATA0 & 1
(where, by the way, we can also get the address space).
Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8 onwards")
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5f3938..2680219 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2287,12 +2287,22 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
u32 fault = I915_READ(GEN8_RING_FAULT_REG);
if (fault & RING_FAULT_VALID) {
+ u32 fault_data0, fault_data1;
+ u64 fault_addr;
+
+ fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
+ fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
+ fault_addr = ((u64)(fault_data1 & FAULT_VA_BITS_44_TO_47) << 44) |
+ ((u64)fault_data0 << PAGE_SHIFT);
+
DRM_DEBUG_DRIVER("Unexpected fault\n"
"\tAddr: 0x%08lx\n"
+ "\tAddress space: %s\n"
"\tEngine ID: %d\n"
"\tSource ID: %d\n"
"\tType: %d\n",
- fault & PAGE_MASK,
+ fault_addr,
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
GEN8_RING_FAULT_ENGINE_ID(fault),
RING_FAULT_SRCID(fault),
RING_FAULT_FAULT_TYPE(fault));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41285be..51c16a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2489,6 +2489,8 @@ enum i915_power_well_id {
#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
+#define FAULT_VA_BITS_44_TO_47 (0xf << 0)
+#define FAULT_GTT_SEL (1 << 4)
#define FPGA_DBG _MMIO(0x42300)
#define FPGA_DBG_RM_NOCLAIM (1<<31)
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: Stop getting the fault address from RING_FAULT_REG
2017-12-22 22:10 [PATCH] drm/i915: Stop getting the fault address from RING_FAULT_REG Oscar Mateo
@ 2017-12-22 22:25 ` Chris Wilson
2017-12-22 22:38 ` [PATCH v3] " Oscar Mateo
2017-12-22 23:18 ` ✗ Fi.CI.BAT: failure for drm/i915: Stop getting the fault address from RING_FAULT_REG (rev2) Patchwork
1 sibling, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2017-12-22 22:25 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Quoting Oscar Mateo (2017-12-22 22:10:29)
> This register does not contain it. Instead, we have to look into FAULT_TLB_DATA0 & 1
> (where, by the way, we can also get the address space).
>
> Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8 onwards")
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 12 +++++++++++-
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c5f3938..2680219 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2287,12 +2287,22 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
> u32 fault = I915_READ(GEN8_RING_FAULT_REG);
>
> if (fault & RING_FAULT_VALID) {
> + u32 fault_data0, fault_data1;
> + u64 fault_addr;
> +
> + fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
> + fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
> + fault_addr = ((u64)(fault_data1 & FAULT_VA_BITS_44_TO_47) << 44) |
> + ((u64)fault_data0 << PAGE_SHIFT);
That should be 12 not PAGE_SHIFT. Semantically different, the kernel's
choice of system page size and how the register stores its address.
> +
> DRM_DEBUG_DRIVER("Unexpected fault\n"
> " Addr: 0x%08lx\n"
%0x08lx_%08lx
upper_32_bits(fault_addr), lower_32_bits(fault_addr),
as is, it needs to be llx to prevent compiler warnings on 32b.
> + " Address space: %s\n"
> " Engine ID: %d\n"
> " Source ID: %d\n"
> " Type: %d\n",
> - fault & PAGE_MASK,
> + fault_addr,
> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> GEN8_RING_FAULT_ENGINE_ID(fault),
> RING_FAULT_SRCID(fault),
> RING_FAULT_FAULT_TYPE(fault));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 41285be..51c16a7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2489,6 +2489,8 @@ enum i915_power_well_id {
>
> #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
> #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
> +#define FAULT_VA_BITS_44_TO_47 (0xf << 0)
HIGHBITS?
-Chris
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3] drm/i915: Stop getting the fault address from RING_FAULT_REG
2017-12-22 22:25 ` Chris Wilson
@ 2017-12-22 22:38 ` Oscar Mateo
2018-01-10 18:18 ` Chris Wilson
0 siblings, 1 reply; 7+ messages in thread
From: Oscar Mateo @ 2017-12-22 22:38 UTC (permalink / raw)
To: intel-gfx
This register does not contain it. Instead, we have to look into FAULT_TLB_DATA0 & 1
(where, by the way, we can also get the address space).
v2: Right formatting
v3:
- Use 12 (as per the register format) instead of PAGE_SIZE (Chris)
- s/BITS_44_TO_47/HIGHBITS (Chris)
- Right formatting, this time for real
Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8 onwards")
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5f3938..0de4f3f 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2287,12 +2287,23 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
u32 fault = I915_READ(GEN8_RING_FAULT_REG);
if (fault & RING_FAULT_VALID) {
+ u32 fault_data0, fault_data1;
+ u64 fault_addr;
+
+ fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
+ fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
+ fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+ ((u64)fault_data0 << 12);
+
DRM_DEBUG_DRIVER("Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
"\tEngine ID: %d\n"
"\tSource ID: %d\n"
"\tType: %d\n",
- fault & PAGE_MASK,
+ upper_32_bits(fault_addr),
+ lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
GEN8_RING_FAULT_ENGINE_ID(fault),
RING_FAULT_SRCID(fault),
RING_FAULT_FAULT_TYPE(fault));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41285be..a499618 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2489,6 +2489,8 @@ enum i915_power_well_id {
#define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
#define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
+#define FAULT_VA_HIGH_BITS (0xf << 0)
+#define FAULT_GTT_SEL (1 << 4)
#define FPGA_DBG _MMIO(0x42300)
#define FPGA_DBG_RM_NOCLAIM (1<<31)
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Stop getting the fault address from RING_FAULT_REG (rev2)
2017-12-22 22:10 [PATCH] drm/i915: Stop getting the fault address from RING_FAULT_REG Oscar Mateo
2017-12-22 22:25 ` Chris Wilson
@ 2017-12-22 23:18 ` Patchwork
1 sibling, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-12-22 23:18 UTC (permalink / raw)
To: Oscar Mateo; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Stop getting the fault address from RING_FAULT_REG (rev2)
URL : https://patchwork.freedesktop.org/series/35743/
State : failure
== Summary ==
Series 35743v2 drm/i915: Stop getting the fault address from RING_FAULT_REG
https://patchwork.freedesktop.org/api/1.0/series/35743/revisions/2/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> DMESG-WARN (fi-elk-e7500) fdo#103989
Test gem_sync:
Subgroup basic-all:
skip -> PASS (fi-pnv-d510)
Subgroup basic-each:
skip -> PASS (fi-pnv-d510)
Subgroup basic-many-each:
skip -> PASS (fi-pnv-d510)
Subgroup basic-store-all:
skip -> PASS (fi-pnv-d510)
Subgroup basic-store-each:
skip -> PASS (fi-pnv-d510)
Test gem_tiled_blits:
Subgroup basic:
skip -> PASS (fi-pnv-d510)
Test gem_tiled_fence_blits:
Subgroup basic:
skip -> PASS (fi-pnv-d510)
Test gem_wait:
Subgroup basic-busy-all:
skip -> PASS (fi-pnv-d510)
Subgroup basic-wait-all:
skip -> PASS (fi-pnv-d510)
Subgroup basic-await-all:
skip -> PASS (fi-pnv-d510)
Test kms_busy:
Subgroup basic-flip-a:
skip -> PASS (fi-pnv-d510)
Subgroup basic-flip-b:
skip -> PASS (fi-pnv-d510)
Test kms_chamelium:
Subgroup common-hpd-after-suspend:
pass -> INCOMPLETE (fi-skl-6700k2)
Test kms_cursor_legacy:
Subgroup basic-busy-flip-before-cursor-legacy:
skip -> PASS (fi-pnv-d510)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Test kms_psr_sink_crc:
Subgroup psr_basic:
pass -> DMESG-WARN (fi-skl-6700hq) fdo#101144
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#101144 https://bugs.freedesktop.org/show_bug.cgi?id=101144
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:426s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:438s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:382s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:500s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:495s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:496s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:484s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:467s
fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:261s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:530s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:404s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:414s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:463s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:432s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:474s
fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:517s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:465s
fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:523s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:586s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:444s
fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:534s
fi-skl-6700hq total:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:558s
fi-skl-6700k2 total:207 pass:190 dwarn:0 dfail:0 fail:0 skip:16
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:486s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:445s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:408s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:597s
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:477s
7223e9864a303d6401054b0815acb5262726adf8 drm-tip: 2017y-12m-22d-21h-51m-04s UTC integration manifest
e99e3281886d drm/i915: Stop getting the fault address from RING_FAULT_REG
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7577/issues.html
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/i915: Stop getting the fault address from RING_FAULT_REG
2017-12-22 22:38 ` [PATCH v3] " Oscar Mateo
@ 2018-01-10 18:18 ` Chris Wilson
2018-01-10 19:04 ` Michel Thierry
0 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2018-01-10 18:18 UTC (permalink / raw)
To: Oscar Mateo, intel-gfx
Quoting Oscar Mateo (2017-12-22 22:38:49)
> This register does not contain it. Instead, we have to look into FAULT_TLB_DATA0 & 1
> (where, by the way, we can also get the address space).
>
> v2: Right formatting
> v3:
> - Use 12 (as per the register format) instead of PAGE_SIZE (Chris)
> - s/BITS_44_TO_47/HIGHBITS (Chris)
> - Right formatting, this time for real
>
> Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8 onwards")
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
Michel, can you double check the regs?
-Chris
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c5f3938..0de4f3f 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2287,12 +2287,23 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
> u32 fault = I915_READ(GEN8_RING_FAULT_REG);
>
> if (fault & RING_FAULT_VALID) {
> + u32 fault_data0, fault_data1;
> + u64 fault_addr;
> +
> + fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
> + fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
> + fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
> + ((u64)fault_data0 << 12);
> +
> DRM_DEBUG_DRIVER("Unexpected fault\n"
> - " Addr: 0x%08lx\n"
> + " Addr: 0x%08x_%08x\n"
> + " Address space: %s\n"
> " Engine ID: %d\n"
> " Source ID: %d\n"
> " Type: %d\n",
> - fault & PAGE_MASK,
> + upper_32_bits(fault_addr),
> + lower_32_bits(fault_addr),
> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> GEN8_RING_FAULT_ENGINE_ID(fault),
> RING_FAULT_SRCID(fault),
> RING_FAULT_FAULT_TYPE(fault));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 41285be..a499618 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2489,6 +2489,8 @@ enum i915_power_well_id {
>
> #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
> #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
> +#define FAULT_VA_HIGH_BITS (0xf << 0)
> +#define FAULT_GTT_SEL (1 << 4)
>
> #define FPGA_DBG _MMIO(0x42300)
> #define FPGA_DBG_RM_NOCLAIM (1<<31)
> --
> 1.9.1
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/i915: Stop getting the fault address from RING_FAULT_REG
2018-01-10 18:18 ` Chris Wilson
@ 2018-01-10 19:04 ` Michel Thierry
2018-01-10 19:09 ` Chris Wilson
0 siblings, 1 reply; 7+ messages in thread
From: Michel Thierry @ 2018-01-10 19:04 UTC (permalink / raw)
To: Chris Wilson, Oscar Mateo, intel-gfx
On 1/10/2018 10:18 AM, Chris Wilson wrote:
> Quoting Oscar Mateo (2017-12-22 22:38:49)
>> This register does not contain it. Instead, we have to look into FAULT_TLB_DATA0 & 1
>> (where, by the way, we can also get the address space).
>>
>> v2: Right formatting
>> v3:
>> - Use 12 (as per the register format) instead of PAGE_SIZE (Chris)
>> - s/BITS_44_TO_47/HIGHBITS (Chris)
>> - Right formatting, this time for real
>>
>> Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8 onwards")
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> Cc: Michel Thierry <michel.thierry@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>
> Michel, can you double check the regs?
Sorry, forgot about this.
> -Chris
>
>> ---
>> drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++++++++++++--
>> drivers/gpu/drm/i915/i915_reg.h | 2 ++
>> 2 files changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> index c5f3938..0de4f3f 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
>> @@ -2287,12 +2287,23 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
>> u32 fault = I915_READ(GEN8_RING_FAULT_REG);
>>
>> if (fault & RING_FAULT_VALID) {
>> + u32 fault_data0, fault_data1;
>> + u64 fault_addr;
>> +
>> + fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
>> + fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
>> + fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
>> + ((u64)fault_data0 << 12);
>> +
>> DRM_DEBUG_DRIVER("Unexpected fault\n"
>> - " Addr: 0x%08lx\n"
>> + " Addr: 0x%08x_%08x\n"
>> + " Address space: %s\n"
>> " Engine ID: %d\n"
>> " Source ID: %d\n"
>> " Type: %d\n",
>> - fault & PAGE_MASK,
>> + upper_32_bits(fault_addr),
>> + lower_32_bits(fault_addr),
>> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
>> GEN8_RING_FAULT_ENGINE_ID(fault),
>> RING_FAULT_SRCID(fault),
>> RING_FAULT_FAULT_TYPE(fault));
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 41285be..a499618 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2489,6 +2489,8 @@ enum i915_power_well_id {
>>
>> #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
>> #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
>> +#define FAULT_VA_HIGH_BITS (0xf << 0)
>> +#define FAULT_GTT_SEL (1 << 4)
>>
Matches what the spec says, IHD-OS-SKL-Vol 2c-05.16 pages 617-618 [1]
(which is not different from the BDW and CHV/BSW ones).
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
>> #define FPGA_DBG _MMIO(0x42300)
>> #define FPGA_DBG_RM_NOCLAIM (1<<31)
>> --
>> 1.9.1
>>
[1]
https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-skl-vol02c-commandreference-registers-part1.pdf
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/i915: Stop getting the fault address from RING_FAULT_REG
2018-01-10 19:04 ` Michel Thierry
@ 2018-01-10 19:09 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2018-01-10 19:09 UTC (permalink / raw)
To: Michel Thierry, Oscar Mateo, intel-gfx
Quoting Michel Thierry (2018-01-10 19:04:45)
> On 1/10/2018 10:18 AM, Chris Wilson wrote:
> > Quoting Oscar Mateo (2017-12-22 22:38:49)
> >> This register does not contain it. Instead, we have to look into FAULT_TLB_DATA0 & 1
> >> (where, by the way, we can also get the address space).
> >>
> >> v2: Right formatting
> >> v3:
> >> - Use 12 (as per the register format) instead of PAGE_SIZE (Chris)
> >> - s/BITS_44_TO_47/HIGHBITS (Chris)
> >> - Right formatting, this time for real
> >>
> >> Fixes: b03ec3d67ab8 ("drm/i915: There is only one fault register from GEN8 onwards")
> >> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> >> Cc: Michel Thierry <michel.thierry@intel.com>
> >> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> >
> > Michel, can you double check the regs?
>
> Sorry, forgot about this.
>
> > -Chris
> >
> >> ---
> >> drivers/gpu/drm/i915/i915_gem_gtt.c | 15 +++++++++++++--
> >> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> >> 2 files changed, 15 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> index c5f3938..0de4f3f 100644
> >> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> >> @@ -2287,12 +2287,23 @@ static void gen8_check_and_clear_faults(struct drm_i915_private *dev_priv)
> >> u32 fault = I915_READ(GEN8_RING_FAULT_REG);
> >>
> >> if (fault & RING_FAULT_VALID) {
> >> + u32 fault_data0, fault_data1;
> >> + u64 fault_addr;
> >> +
> >> + fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
> >> + fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
> >> + fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
> >> + ((u64)fault_data0 << 12);
> >> +
> >> DRM_DEBUG_DRIVER("Unexpected fault\n"
> >> - " Addr: 0x%08lx\n"
> >> + " Addr: 0x%08x_%08x\n"
> >> + " Address space: %s\n"
> >> " Engine ID: %d\n"
> >> " Source ID: %d\n"
> >> " Type: %d\n",
> >> - fault & PAGE_MASK,
> >> + upper_32_bits(fault_addr),
> >> + lower_32_bits(fault_addr),
> >> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> >> GEN8_RING_FAULT_ENGINE_ID(fault),
> >> RING_FAULT_SRCID(fault),
> >> RING_FAULT_FAULT_TYPE(fault));
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 41285be..a499618 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -2489,6 +2489,8 @@ enum i915_power_well_id {
> >>
> >> #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10)
> >> #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14)
> >> +#define FAULT_VA_HIGH_BITS (0xf << 0)
> >> +#define FAULT_GTT_SEL (1 << 4)
> >>
>
> Matches what the spec says, IHD-OS-SKL-Vol 2c-05.16 pages 617-618 [1]
> (which is not different from the BDW and CHV/BSW ones).
>
> Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Many thanks, for both the patch and review, pushed.
-Chris
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-01-10 19:09 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-22 22:10 [PATCH] drm/i915: Stop getting the fault address from RING_FAULT_REG Oscar Mateo
2017-12-22 22:25 ` Chris Wilson
2017-12-22 22:38 ` [PATCH v3] " Oscar Mateo
2018-01-10 18:18 ` Chris Wilson
2018-01-10 19:04 ` Michel Thierry
2018-01-10 19:09 ` Chris Wilson
2017-12-22 23:18 ` ✗ Fi.CI.BAT: failure for drm/i915: Stop getting the fault address from RING_FAULT_REG (rev2) Patchwork
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