* [PATCH 0/5] Add sysfs to support OverDrive feature
@ 2018-01-18 8:37 Rex Zhu
[not found] ` <1516264682-10037-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 11+ messages in thread
From: Rex Zhu @ 2018-01-18 8:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
OD feature is disabled by default.
can be enabled by module parameter
ppfeaturemask=0x7fff
(ppfeaturemask default value is 0x3fff)
Add new sysfs pp_od_clk_voltage.
cat pp_od_clk_voltage output as
OD_SCLK:
0: 300Mhz 800 mV
1: 466Mhz 818 mV
2: 751Mhz 824 mV
3: 1019Mhz 987 mV
4: 1074Mhz 1037 mV
5: 1126Mhz 1087 mV
6: 1169Mhz 1137 mV
7: 1206Mhz 1150 mV
OD_MCLK:
0: 300Mhz 800 mV
1: 1650Mhz 1000 mV
user can change clock/voltage by
echo "s/m level clock voltage">pp_od_clk_voltage
to change the sclk/mclk clock/voltage value in od dpm table.
and
echo "c" to commit the user's setting
when need to reset to default dpm table,
echo "r" to restore the od dpm table
echo "c" to commit the setting.
the clock's range is level0-level7*1.2
the voltage range is level0-level7*1.2
Rex Zhu (5):
drm/amd/pp: Add hwmgr interface for edit dpm table
drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs
drm/amd/pp: Implement edit_dpm_table on smu7
drm/amd/pp: Update smu7 dpm table with OD clock/voltage
drm/amd/pp: Add update_avfs call when set_power_state
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 +
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 96 ++++++-
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 7 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 ++
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 317 +++++++++++++--------
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 18 +-
.../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 18 +-
.../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 18 +-
9 files changed, 368 insertions(+), 132 deletions(-)
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/5] drm/amd/pp: Add hwmgr interface for edit dpm table
[not found] ` <1516264682-10037-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-18 8:37 ` Rex Zhu
[not found] ` <1516264682-10037-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 8:37 ` [PATCH 2/5] drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs Rex Zhu
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Rex Zhu @ 2018-01-18 8:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Add odn_edit_dpm_table function
points for setting user assigned clock/voltage.
Change-Id: I7e49ffdc30b77d07b46bf12ebb275fa0ff901588
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 6 ++++++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 103837c..3e8b9cc 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -161,6 +161,12 @@ enum {
PP_GROUP_MAX
};
+enum PP_ODN_DPM_TABLE_TYPE {
+ PP_ODN_SCLK_VDDC_TABLE,
+ PP_ODN_MCLK_VDDC_TABLE,
+ PP_ODN_RESET_DEFAULT_TABLE
+};
+
struct pp_states_info {
uint32_t nums;
uint32_t states[16];
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 7caab09..47afbca 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -345,6 +345,9 @@ struct pp_hwmgr_func {
struct PP_TemperatureRange *range);
int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
+ int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
+ enum PP_ODN_DPM_TABLE_TYPE type,
+ long *input, uint32_t size);
};
struct pp_table_func {
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/5] drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs
[not found] ` <1516264682-10037-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 8:37 ` [PATCH 1/5] drm/amd/pp: Add hwmgr interface for edit dpm table Rex Zhu
@ 2018-01-18 8:37 ` Rex Zhu
[not found] ` <1516264682-10037-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 8:38 ` [PATCH 3/5] drm/amd/pp: Implement edit_dpm_table on smu7 Rex Zhu
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Rex Zhu @ 2018-01-18 8:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
when cat pp_od_clk_voltage it show
OD_SCLK:
0: 300Mhz 800 mV
1: 466Mhz 818 mV
2: 751Mhz 824 mV
3: 1019Mhz 987 mV
4: 1074Mhz 1037 mV
5: 1126Mhz 1087 mV
6: 1169Mhz 1137 mV
7: 1206Mhz 1150 mV
OD_MCLK:
0: 300Mhz 800 mV
1: 1650Mhz 1000 mV
echo "s/m level clock voltage" to change
sclk/mclk's clock and voltage
echo "r" to restore default value.
echo "c" to commit the user setting.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 96 +++++++++++++++++++++++++-
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 +++++
4 files changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 986f1d5..4b5755e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->set_power_profile_mode(\
(adev)->powerplay.pp_handle, parameter, size))
+#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
+ ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
+ (adev)->powerplay.pp_handle, type, parameter, size))
+
struct amdgpu_dpm {
struct amdgpu_ps *ps;
/* number of valid power states */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ed9012a..f8ba194 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -360,6 +360,88 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
return count;
}
+static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t count)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+ int ret;
+ uint32_t parameter_size = 0;
+ long parameter[64];
+ char buf_cpy[128];
+ char *tmp_str;
+ char *sub_str;
+ const char delimiter[3] = {' ', '\n', '\0'};
+ uint32_t type;
+
+ if (count > 127)
+ return -EINVAL;
+
+ if (*buf == 'c') {
+ if (adev->powerplay.pp_funcs->dispatch_tasks) {
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
+ return count;
+ } else {
+ return -EINVAL;
+ }
+ }
+
+ if (*buf == 's')
+ type = PP_ODN_SCLK_VDDC_TABLE;
+ else if (*buf == 'm')
+ type = PP_ODN_MCLK_VDDC_TABLE;
+ else if(*buf == 'r')
+ type = PP_ODN_RESET_DEFAULT_TABLE;
+ else
+ return -EINVAL;
+
+ memcpy(buf_cpy, buf, count+1);
+
+ tmp_str = buf_cpy;
+
+ while (isspace(*++tmp_str));
+
+ while (tmp_str[0]) {
+ sub_str = strsep(&tmp_str, delimiter);
+ ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
+ if (ret)
+ return -EINVAL;
+ parameter_size++;
+
+ while (isspace(*tmp_str))
+ tmp_str++;
+ }
+
+ if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
+ ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
+ parameter, parameter_size);
+
+ if (ret)
+ return -EINVAL;
+
+ return count;
+}
+
+static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+ uint32_t size = 0;
+
+ if (adev->powerplay.pp_funcs->print_clock_levels) {
+ size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
+ size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
+ return size;
+ } else {
+ return snprintf(buf, PAGE_SIZE, "\n");
+ }
+
+}
+
static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -842,6 +924,10 @@ static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
amdgpu_get_pp_power_profile_mode,
amdgpu_set_pp_power_profile_mode);
+static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
+ amdgpu_get_pp_od_clk_voltage,
+ amdgpu_set_pp_od_clk_voltage);
+
static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -1481,7 +1567,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
"pp_power_profile_mode\n");
return ret;
}
-
+ ret = device_create_file(adev->dev,
+ &dev_attr_pp_od_clk_voltage);
+ if (ret) {
+ DRM_ERROR("failed to create device file "
+ "pp_od_clk_voltage\n");
+ return ret;
+ }
ret = amdgpu_debugfs_pm_init(adev);
if (ret) {
DRM_ERROR("Failed to register debugfs file for dpm!\n");
@@ -1519,6 +1611,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
&dev_attr_pp_compute_power_profile);
device_remove_file(adev->dev,
&dev_attr_pp_power_profile_mode);
+ device_remove_file(adev->dev,
+ &dev_attr_pp_od_clk_voltage);
}
void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 3e8b9cc..f7393f9 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -309,6 +309,7 @@ struct amd_pm_funcs {
struct amd_pp_simple_clock_info *clocks);
int (*get_power_profile_mode)(void *handle, char *buf);
int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
+ int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
};
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index d9cb424..854c43c 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1122,6 +1122,24 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
}
+static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
+{
+ struct pp_hwmgr *hwmgr;
+ struct pp_instance *pp_handle = (struct pp_instance *)handle;
+
+ if (pp_check(pp_handle))
+ return -EINVAL;
+
+ hwmgr = pp_handle->hwmgr;
+
+ if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
+ pr_info("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
+
+ return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
+}
+
static int pp_dpm_set_power_profile_state(void *handle,
struct amd_pp_profile *request)
{
@@ -1507,6 +1525,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
.notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
.get_power_profile_mode = pp_get_power_profile_mode,
.set_power_profile_mode = pp_set_power_profile_mode,
+ .odn_edit_dpm_table = pp_odn_edit_dpm_table,
/* export to DC */
.get_sclk = pp_dpm_get_sclk,
.get_mclk = pp_dpm_get_mclk,
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/5] drm/amd/pp: Implement edit_dpm_table on smu7
[not found] ` <1516264682-10037-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 8:37 ` [PATCH 1/5] drm/amd/pp: Add hwmgr interface for edit dpm table Rex Zhu
2018-01-18 8:37 ` [PATCH 2/5] drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs Rex Zhu
@ 2018-01-18 8:38 ` Rex Zhu
[not found] ` <1516264682-10037-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 8:38 ` [PATCH 4/5] drm/amd/pp: Update smu7 dpm table with OD clock/voltage Rex Zhu
2018-01-18 8:38 ` [PATCH 5/5] drm/amd/pp: Add update_avfs call when set_power_state Rex Zhu
4 siblings, 1 reply; 11+ messages in thread
From: Rex Zhu @ 2018-01-18 8:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
Change-Id: Ib7414e1afc49d7b313188349b396aeac3a5054b7
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 121 ++++++++++++++++++++++-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 4ccc910..0d14299 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4808,6 +4808,125 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
return 0;
}
+static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
+ enum PP_ODN_DPM_TABLE_TYPE type,
+ uint32_t clk,
+ uint32_t voltage)
+{
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (hwmgr->dyn_state.max_clock_voltage_on_ac.vddc * 120 / 100 < voltage)
+ return false;
+
+ if (type == PP_ODN_SCLK_VDDC_TABLE) {
+ if (data->vbios_boot_state.sclk_bootup_value > clk ||
+ hwmgr->dyn_state.max_clock_voltage_on_ac.sclk * 120 / 100 < clk)
+ return false;
+ } else if (type == PP_ODN_MCLK_VDDC_TABLE) {
+ if (data->vbios_boot_state.mclk_bootup_value > clk ||
+ hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * 120 / 100 < clk)
+ return false;
+ } else {
+ return false;
+ }
+
+ return true;
+}
+
+static void smu7_check_vddc_updated(struct pp_hwmgr *hwmgr,
+ struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
+ struct smu7_odn_clock_voltage_dependency_table *odn_vdd_dep)
+{
+ int i;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (dep_table->count == 0)
+ return;
+
+ for (i = 0; i < dep_table->count; i++) {
+ if (dep_table->entries[i].vddc != odn_vdd_dep->entries[i].vddc) {
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
+ return;
+ }
+ }
+}
+
+static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
+ enum PP_ODN_DPM_TABLE_TYPE type,
+ long *input, uint32_t size)
+{
+ uint32_t i;
+ phm_ppt_v1_clock_voltage_dependency_table *pgolden_vdd_dep_table = NULL;
+ struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
+ struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+ struct phm_ppt_v1_information *table_info =
+ (struct phm_ppt_v1_information *)hwmgr->pptable;
+ uint32_t input_clk;
+ uint32_t input_vol;
+ uint32_t input_level;
+
+ PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
+ return -EINVAL);
+
+ if (PP_ODN_SCLK_VDDC_TABLE == type) {
+ podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
+ podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
+ PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+ "Failed to get ODN SCLK and Voltage tables",
+ return -EINVAL);
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
+ } else if (PP_ODN_MCLK_VDDC_TABLE == type) {
+ podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
+ podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
+
+ PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
+ "Failed to get ODN MCLK and Voltage tables",
+ return -EINVAL);
+ data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
+ } else if (PP_ODN_RESET_DEFAULT_TABLE == type) {
+ smu7_odn_initial_default_setting(hwmgr);
+ data->need_update_smu7_dpm_table = DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
+ return 0;
+ } else {
+ return -EINVAL;
+ }
+
+ for (i = 0; i < size; i += 3) {
+ if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
+ pr_info("invalid clock voltage input \n");
+ return 0;
+ }
+ input_level = input[i];
+ input_clk = input[i+1] * 100;
+ input_vol = input[i+2];
+
+ if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
+ podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
+ podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
+ podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
+ podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
+ } else {
+ pr_info("invaid input clk/voltage");
+ }
+ }
+
+ if (hwmgr->pp_table_version == PP_TABLE_V1)
+ pgolden_vdd_dep_table = PP_ODN_MCLK_VDDC_TABLE == type ?
+ table_info->vdd_dep_on_mclk:
+ table_info->vdd_dep_on_sclk;
+
+ PP_ASSERT_WITH_CODE(pgolden_vdd_dep_table
+ && pgolden_vdd_dep_table->count > 0,
+ "Invalid golden_vdd_dep_table",
+ return -EINVAL);
+
+ smu7_check_vddc_updated(hwmgr, pgolden_vdd_dep_table, podn_vdd_dep_in_backend);
+
+ return 0;
+}
+
+
static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = &smu7_hwmgr_backend_init,
.backend_fini = &smu7_hwmgr_backend_fini,
@@ -4862,6 +4981,7 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
.notify_cac_buffer_info = smu7_notify_cac_buffer_info,
.get_max_high_clocks = smu7_get_max_high_clocks,
.get_thermal_temperature_range = smu7_get_thermal_temperature_range,
+ .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
};
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
@@ -4893,4 +5013,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
return ret;
}
-
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 4/5] drm/amd/pp: Update smu7 dpm table with OD clock/voltage
[not found] ` <1516264682-10037-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-01-18 8:38 ` [PATCH 3/5] drm/amd/pp: Implement edit_dpm_table on smu7 Rex Zhu
@ 2018-01-18 8:38 ` Rex Zhu
[not found] ` <1516264682-10037-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 8:38 ` [PATCH 5/5] drm/amd/pp: Add update_avfs call when set_power_state Rex Zhu
4 siblings, 1 reply; 11+ messages in thread
From: Rex Zhu @ 2018-01-18 8:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
delete old OD type code path when populate clk.
Change-Id: I9beb7e751ac720edb4ffb1deaf7984e86e2e41b1
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 110 ++++-----------------
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 18 +++-
.../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 18 +++-
.../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 18 +++-
4 files changed, 62 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 0d14299..ee70ef2 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3482,8 +3482,6 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
uint32_t i;
struct cgs_display_info info = {0};
- data->need_update_smu7_dpm_table = 0;
-
for (i = 0; i < sclk_table->count; i++) {
if (sclk == sclk_table->dpm_levels[i].value)
break;
@@ -3625,106 +3623,27 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
struct pp_hwmgr *hwmgr, const void *input)
{
int result = 0;
- const struct phm_set_power_state_input *states =
- (const struct phm_set_power_state_input *)input;
- const struct smu7_power_state *smu7_ps =
- cast_const_phw_smu7_power_state(states->pnew_state);
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
- uint32_t sclk = smu7_ps->performance_levels
- [smu7_ps->performance_level_count - 1].engine_clock;
- uint32_t mclk = smu7_ps->performance_levels
- [smu7_ps->performance_level_count - 1].memory_clock;
struct smu7_dpm_table *dpm_table = &data->dpm_table;
-
- struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
- uint32_t dpm_count, clock_percent;
- uint32_t i;
+ uint32_t count;
+ struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
+ struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
+ struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
if (0 == data->need_update_smu7_dpm_table)
return 0;
- if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
- dpm_table->sclk_table.dpm_levels
- [dpm_table->sclk_table.count - 1].value = sclk;
-
- if (hwmgr->od_enabled) {
- /* Need to do calculation based on the golden DPM table
- * as the Heatmap GPU Clock axis is also based on the default values
- */
- PP_ASSERT_WITH_CODE(
- (golden_dpm_table->sclk_table.dpm_levels
- [golden_dpm_table->sclk_table.count - 1].value != 0),
- "Divide by 0!",
- return -EINVAL);
- dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
-
- for (i = dpm_count; i > 1; i--) {
- if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
- clock_percent =
- ((sclk
- - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
- ) * 100)
- / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
- dpm_table->sclk_table.dpm_levels[i].value =
- golden_dpm_table->sclk_table.dpm_levels[i].value +
- (golden_dpm_table->sclk_table.dpm_levels[i].value *
- clock_percent)/100;
-
- } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
- clock_percent =
- ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
- - sclk) * 100)
- / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
-
- dpm_table->sclk_table.dpm_levels[i].value =
- golden_dpm_table->sclk_table.dpm_levels[i].value -
- (golden_dpm_table->sclk_table.dpm_levels[i].value *
- clock_percent) / 100;
- } else
- dpm_table->sclk_table.dpm_levels[i].value =
- golden_dpm_table->sclk_table.dpm_levels[i].value;
- }
+ if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+ for (count = 0; count < dpm_table->sclk_table.count; count++) {
+ dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
+ dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
}
}
- if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
- dpm_table->mclk_table.dpm_levels
- [dpm_table->mclk_table.count - 1].value = mclk;
-
- if (hwmgr->od_enabled) {
-
- PP_ASSERT_WITH_CODE(
- (golden_dpm_table->mclk_table.dpm_levels
- [golden_dpm_table->mclk_table.count-1].value != 0),
- "Divide by 0!",
- return -EINVAL);
- dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
- for (i = dpm_count; i > 1; i--) {
- if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
- clock_percent = ((mclk -
- golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
- / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-
- dpm_table->mclk_table.dpm_levels[i].value =
- golden_dpm_table->mclk_table.dpm_levels[i].value +
- (golden_dpm_table->mclk_table.dpm_levels[i].value *
- clock_percent) / 100;
-
- } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
- clock_percent = (
- (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
- * 100)
- / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
-
- dpm_table->mclk_table.dpm_levels[i].value =
- golden_dpm_table->mclk_table.dpm_levels[i].value -
- (golden_dpm_table->mclk_table.dpm_levels[i].value *
- clock_percent) / 100;
- } else
- dpm_table->mclk_table.dpm_levels[i].value =
- golden_dpm_table->mclk_table.dpm_levels[i].value;
- }
+ if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
+ for (count = 0; count < dpm_table->mclk_table.count; count++) {
+ dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
+ dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
}
}
@@ -4114,6 +4033,7 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
const struct smu7_power_state *psa;
const struct smu7_power_state *psb;
int i;
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
return -EINVAL;
@@ -4138,6 +4058,10 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
*equal &= (psa->sclk_threshold == psb->sclk_threshold);
+ /* For OD call, set value based on flag */
+ *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
+ DPMTABLE_OD_UPDATE_MCLK |
+ DPMTABLE_OD_UPDATE_VDDC));
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index 7d9e2cb..c4a94d0 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -981,12 +981,18 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
+ phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
result = fiji_calculate_sclk_params(hwmgr, clock, level);
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
+ vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+ else
+ vdd_dep_table = table_info->vdd_dep_on_sclk;
+
/* populate graphics levels */
result = fiji_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_sclk, clock,
+ vdd_dep_table, clock,
(uint32_t *)(&level->MinVoltage), &mvdd);
PP_ASSERT_WITH_CODE((0 == result),
"can not find VDDC voltage value for "
@@ -1202,10 +1208,16 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
(struct phm_ppt_v1_information *)(hwmgr->pptable);
int result = 0;
uint32_t mclk_stutter_mode_threshold = 60000;
+ phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
+
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
+ vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+ else
+ vdd_dep_table = table_info->vdd_dep_on_mclk;
- if (table_info->vdd_dep_on_mclk) {
+ if (vdd_dep_table) {
result = fiji_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_mclk, clock,
+ vdd_dep_table, clock,
(uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
PP_ASSERT_WITH_CODE((0 == result),
"can not find MinVddc voltage value from memory "
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index f1a3bc8..c0c627f 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -948,12 +948,18 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
struct phm_ppt_v1_information *table_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
SMU_SclkSetting curr_sclk_setting = { 0 };
+ phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
+ vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+ else
+ vdd_dep_table = table_info->vdd_dep_on_sclk;
+
/* populate graphics levels */
result = polaris10_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_sclk, clock,
+ vdd_dep_table, clock,
&level->MinVoltage, &mvdd);
PP_ASSERT_WITH_CODE((0 == result),
@@ -1107,12 +1113,18 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
int result = 0;
struct cgs_display_info info = {0, 0, NULL};
uint32_t mclk_stutter_mode_threshold = 40000;
+ phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
cgs_get_active_displays_info(hwmgr->device, &info);
- if (table_info->vdd_dep_on_mclk) {
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
+ vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+ else
+ vdd_dep_table = table_info->vdd_dep_on_mclk;
+
+ if (vdd_dep_table) {
result = polaris10_get_dependency_volt_by_clk(hwmgr,
- table_info->vdd_dep_on_mclk, clock,
+ vdd_dep_table, clock,
&mem_level->MinVoltage, &mem_level->MinMvdd);
PP_ASSERT_WITH_CODE((0 == result),
"can not find MinVddc voltage value from memory "
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index a03a345..52e69e8 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -620,12 +620,18 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
+ phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
+ vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+ else
+ vdd_dep_table = pptable_info->vdd_dep_on_sclk;
+
/* populate graphics levels*/
result = tonga_get_dependency_volt_by_clk(hwmgr,
- pptable_info->vdd_dep_on_sclk, engine_clock,
+ vdd_dep_table, engine_clock,
&graphic_level->MinVoltage, &mvdd);
PP_ASSERT_WITH_CODE((!result),
"can not find VDDC voltage value for VDDC "
@@ -966,10 +972,16 @@ static int tonga_populate_single_memory_level(
uint32_t mclk_stutter_mode_threshold = 30000;
uint32_t mclk_edc_enable_threshold = 40000;
uint32_t mclk_strobe_mode_threshold = 40000;
+ phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
+
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
+ vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
+ else
+ vdd_dep_table = pptable_info->vdd_dep_on_mclk;
- if (NULL != pptable_info->vdd_dep_on_mclk) {
+ if (NULL != vdd_dep_table) {
result = tonga_get_dependency_volt_by_clk(hwmgr,
- pptable_info->vdd_dep_on_mclk,
+ vdd_dep_table,
memory_clock,
&memory_level->MinVoltage, &mvdd);
PP_ASSERT_WITH_CODE(
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 5/5] drm/amd/pp: Add update_avfs call when set_power_state
[not found] ` <1516264682-10037-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2018-01-18 8:38 ` [PATCH 4/5] drm/amd/pp: Update smu7 dpm table with OD clock/voltage Rex Zhu
@ 2018-01-18 8:38 ` Rex Zhu
[not found] ` <1516264682-10037-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
4 siblings, 1 reply; 11+ messages in thread
From: Rex Zhu @ 2018-01-18 8:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu
when Overdrive voltage, need to disable AVFS.
when OverDriv engine clock, need to recalculate
AVFS voltage by disable/enable avfs feature.
Change-Id: Iac82ed92a8484c04c18339968f3d215b063ac050
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 86 ++++++++++++++++--------
1 file changed, 58 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index ee70ef2..91d89bd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
};
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, uint32_t mask);
@@ -1351,6 +1350,59 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
return 0;
}
+static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+
+ if (smu_data == NULL)
+ return -EINVAL;
+
+ if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+ return 0;
+
+ if (enable) {
+ if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+ hwmgr, PPSMC_MSG_EnableAvfs),
+ "Failed to enable AVFS!",
+ return -EINVAL);
+ }
+ } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
+ CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
+ PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
+ hwmgr, PPSMC_MSG_DisableAvfs),
+ "Failed to disable AVFS!",
+ return -EINVAL);
+ }
+
+ return 0;
+}
+
+static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
+{
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
+ struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+ if (smu_data == NULL)
+ return -EINVAL;
+
+ if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
+ return 0;
+
+ if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
+ smu7_avfs_control(hwmgr, false);
+ return 0;
+ } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
+ smu7_avfs_control(hwmgr, false);
+ smu7_avfs_control(hwmgr, true);
+ } else {
+ smu7_avfs_control(hwmgr, true);
+ }
+
+ return 0;
+}
+
int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
@@ -3842,6 +3894,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
"Failed to populate and upload SCLK MCLK DPM levels!",
result = tmp_result);
+ tmp_result = smu7_update_avfs(hwmgr);
+ PP_ASSERT_WITH_CODE((0 == tmp_result),
+ "Failed to update avfs voltages!",
+ result = tmp_result);
+
tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
PP_ASSERT_WITH_CODE((0 == tmp_result),
"Failed to generate DPM level enabled mask!",
@@ -4626,33 +4683,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
return result;
}
-static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
-{
- struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
-
- if (smu_data == NULL)
- return -EINVAL;
-
- if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
- return 0;
-
- if (enable) {
- if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr, PPSMC_MSG_EnableAvfs),
- "Failed to enable AVFS!",
- return -EINVAL);
- } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
- CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
- hwmgr, PPSMC_MSG_DisableAvfs),
- "Failed to disable AVFS!",
- return -EINVAL);
-
- return 0;
-}
-
static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
uint32_t virtual_addr_low,
uint32_t virtual_addr_hi,
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 3/5] drm/amd/pp: Implement edit_dpm_table on smu7
[not found] ` <1516264682-10037-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-18 16:34 ` Alex Deucher
0 siblings, 0 replies; 11+ messages in thread
From: Alex Deucher @ 2018-01-18 16:34 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Jan 18, 2018 at 3:38 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: Ib7414e1afc49d7b313188349b396aeac3a5054b7
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 121 ++++++++++++++++++++++-
> 1 file changed, 120 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 4ccc910..0d14299 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4808,6 +4808,125 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
> return 0;
> }
>
> +static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
> + enum PP_ODN_DPM_TABLE_TYPE type,
> + uint32_t clk,
> + uint32_t voltage)
> +{
> + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> + if (hwmgr->dyn_state.max_clock_voltage_on_ac.vddc * 120 / 100 < voltage)
> + return false;
> +
> + if (type == PP_ODN_SCLK_VDDC_TABLE) {
> + if (data->vbios_boot_state.sclk_bootup_value > clk ||
> + hwmgr->dyn_state.max_clock_voltage_on_ac.sclk * 120 / 100 < clk)
> + return false;
> + } else if (type == PP_ODN_MCLK_VDDC_TABLE) {
> + if (data->vbios_boot_state.mclk_bootup_value > clk ||
> + hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * 120 / 100 < clk)
> + return false;
Shouldn't we check against the overdriveLimit from the vbios rather
than 1.2x the clock?
Alex
> + } else {
> + return false;
> + }
> +
> + return true;
> +}
> +
> +static void smu7_check_vddc_updated(struct pp_hwmgr *hwmgr,
> + struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
> + struct smu7_odn_clock_voltage_dependency_table *odn_vdd_dep)
> +{
> + int i;
> + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> + if (dep_table->count == 0)
> + return;
> +
> + for (i = 0; i < dep_table->count; i++) {
> + if (dep_table->entries[i].vddc != odn_vdd_dep->entries[i].vddc) {
> + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC;
> + return;
> + }
> + }
> +}
> +
> +static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
> + enum PP_ODN_DPM_TABLE_TYPE type,
> + long *input, uint32_t size)
> +{
> + uint32_t i;
> + phm_ppt_v1_clock_voltage_dependency_table *pgolden_vdd_dep_table = NULL;
> + struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL;
> + struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL;
> + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> + struct phm_ppt_v1_information *table_info =
> + (struct phm_ppt_v1_information *)hwmgr->pptable;
> + uint32_t input_clk;
> + uint32_t input_vol;
> + uint32_t input_level;
> +
> + PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
> + return -EINVAL);
> +
> + if (PP_ODN_SCLK_VDDC_TABLE == type) {
> + podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels;
> + podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk;
> + PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
> + "Failed to get ODN SCLK and Voltage tables",
> + return -EINVAL);
> + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
> + } else if (PP_ODN_MCLK_VDDC_TABLE == type) {
> + podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels;
> + podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk;
> +
> + PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend),
> + "Failed to get ODN MCLK and Voltage tables",
> + return -EINVAL);
> + data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
> + } else if (PP_ODN_RESET_DEFAULT_TABLE == type) {
> + smu7_odn_initial_default_setting(hwmgr);
> + data->need_update_smu7_dpm_table = DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK;
> + return 0;
> + } else {
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < size; i += 3) {
> + if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) {
> + pr_info("invalid clock voltage input \n");
> + return 0;
> + }
> + input_level = input[i];
> + input_clk = input[i+1] * 100;
> + input_vol = input[i+2];
> +
> + if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
> + podn_dpm_table_in_backend->entries[input_level].clock = input_clk;
> + podn_vdd_dep_in_backend->entries[input_level].clk = input_clk;
> + podn_dpm_table_in_backend->entries[input_level].vddc = input_vol;
> + podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol;
> + } else {
> + pr_info("invaid input clk/voltage");
> + }
> + }
> +
> + if (hwmgr->pp_table_version == PP_TABLE_V1)
> + pgolden_vdd_dep_table = PP_ODN_MCLK_VDDC_TABLE == type ?
> + table_info->vdd_dep_on_mclk:
> + table_info->vdd_dep_on_sclk;
> +
> + PP_ASSERT_WITH_CODE(pgolden_vdd_dep_table
> + && pgolden_vdd_dep_table->count > 0,
> + "Invalid golden_vdd_dep_table",
> + return -EINVAL);
> +
> + smu7_check_vddc_updated(hwmgr, pgolden_vdd_dep_table, podn_vdd_dep_in_backend);
> +
> + return 0;
> +}
> +
> +
> static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
> .backend_init = &smu7_hwmgr_backend_init,
> .backend_fini = &smu7_hwmgr_backend_fini,
> @@ -4862,6 +4981,7 @@ static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
> .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
> .get_max_high_clocks = smu7_get_max_high_clocks,
> .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
> + .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
> };
>
> uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> @@ -4893,4 +5013,3 @@ int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
>
> return ret;
> }
> -
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 5/5] drm/amd/pp: Add update_avfs call when set_power_state
[not found] ` <1516264682-10037-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-18 16:40 ` Alex Deucher
0 siblings, 0 replies; 11+ messages in thread
From: Alex Deucher @ 2018-01-18 16:40 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Jan 18, 2018 at 3:38 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> when Overdrive voltage, need to disable AVFS.
> when OverDriv engine clock, need to recalculate
> AVFS voltage by disable/enable avfs feature.
>
> Change-Id: Iac82ed92a8484c04c18339968f3d215b063ac050
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 86 ++++++++++++++++--------
> 1 file changed, 58 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index ee70ef2..91d89bd 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
> DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
> };
>
> -static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
> static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
> static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
> enum pp_clock_type type, uint32_t mask);
> @@ -1351,6 +1350,59 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
> return 0;
> }
>
> +static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
> +{
> + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
> +
> + if (smu_data == NULL)
> + return -EINVAL;
> +
> + if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> + return 0;
> +
> + if (enable) {
> + if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> + CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
> + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> + hwmgr, PPSMC_MSG_EnableAvfs),
> + "Failed to enable AVFS!",
> + return -EINVAL);
> + }
> + } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> + CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
> + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> + hwmgr, PPSMC_MSG_DisableAvfs),
> + "Failed to disable AVFS!",
> + return -EINVAL);
> + }
> +
> + return 0;
> +}
> +
> +static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
> +{
> + struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
> + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +
> + if (smu_data == NULL)
> + return -EINVAL;
> +
> + if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> + return 0;
> +
> + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
> + smu7_avfs_control(hwmgr, false);
> + return 0;
You can drop the return 0; here. With that fixed, the patch is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> + } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
> + smu7_avfs_control(hwmgr, false);
> + smu7_avfs_control(hwmgr, true);
> + } else {
> + smu7_avfs_control(hwmgr, true);
> + }
> +
> + return 0;
> +}
> +
> int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
> {
> int tmp_result, result = 0;
> @@ -3842,6 +3894,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
> "Failed to populate and upload SCLK MCLK DPM levels!",
> result = tmp_result);
>
> + tmp_result = smu7_update_avfs(hwmgr);
> + PP_ASSERT_WITH_CODE((0 == tmp_result),
> + "Failed to update avfs voltages!",
> + result = tmp_result);
> +
> tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
> PP_ASSERT_WITH_CODE((0 == tmp_result),
> "Failed to generate DPM level enabled mask!",
> @@ -4626,33 +4683,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
> return result;
> }
>
> -static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
> -{
> - struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
> -
> - if (smu_data == NULL)
> - return -EINVAL;
> -
> - if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
> - return 0;
> -
> - if (enable) {
> - if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> - CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
> - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> - hwmgr, PPSMC_MSG_EnableAvfs),
> - "Failed to enable AVFS!",
> - return -EINVAL);
> - } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
> - CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
> - PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
> - hwmgr, PPSMC_MSG_DisableAvfs),
> - "Failed to disable AVFS!",
> - return -EINVAL);
> -
> - return 0;
> -}
> -
> static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
> uint32_t virtual_addr_low,
> uint32_t virtual_addr_hi,
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/5] drm/amd/pp: Add hwmgr interface for edit dpm table
[not found] ` <1516264682-10037-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-18 16:40 ` Alex Deucher
0 siblings, 0 replies; 11+ messages in thread
From: Alex Deucher @ 2018-01-18 16:40 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Jan 18, 2018 at 3:37 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Add odn_edit_dpm_table function
> points for setting user assigned clock/voltage.
>
> Change-Id: I7e49ffdc30b77d07b46bf12ebb275fa0ff901588
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 6 ++++++
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 3 +++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 103837c..3e8b9cc 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -161,6 +161,12 @@ enum {
> PP_GROUP_MAX
> };
>
> +enum PP_ODN_DPM_TABLE_TYPE {
> + PP_ODN_SCLK_VDDC_TABLE,
> + PP_ODN_MCLK_VDDC_TABLE,
> + PP_ODN_RESET_DEFAULT_TABLE
> +};
> +
> struct pp_states_info {
> uint32_t nums;
> uint32_t states[16];
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 7caab09..47afbca 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -345,6 +345,9 @@ struct pp_hwmgr_func {
> struct PP_TemperatureRange *range);
> int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
> int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
> + int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
> + enum PP_ODN_DPM_TABLE_TYPE type,
> + long *input, uint32_t size);
> };
>
> struct pp_table_func {
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/5] drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs
[not found] ` <1516264682-10037-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-18 16:41 ` Alex Deucher
0 siblings, 0 replies; 11+ messages in thread
From: Alex Deucher @ 2018-01-18 16:41 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Jan 18, 2018 at 3:37 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> when cat pp_od_clk_voltage it show
> OD_SCLK:
> 0: 300Mhz 800 mV
> 1: 466Mhz 818 mV
> 2: 751Mhz 824 mV
> 3: 1019Mhz 987 mV
> 4: 1074Mhz 1037 mV
> 5: 1126Mhz 1087 mV
> 6: 1169Mhz 1137 mV
> 7: 1206Mhz 1150 mV
> OD_MCLK:
> 0: 300Mhz 800 mV
> 1: 1650Mhz 1000 mV
>
> echo "s/m level clock voltage" to change
> sclk/mclk's clock and voltage
>
> echo "r" to restore default value.
> echo "c" to commit the user setting.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 ++
> drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 96 +++++++++++++++++++++++++-
> drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 19 +++++
> 4 files changed, 119 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> index 986f1d5..4b5755e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> @@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
> ((adev)->powerplay.pp_funcs->set_power_profile_mode(\
> (adev)->powerplay.pp_handle, parameter, size))
>
> +#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
> + ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
> + (adev)->powerplay.pp_handle, type, parameter, size))
> +
> struct amdgpu_dpm {
> struct amdgpu_ps *ps;
> /* number of valid power states */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index ed9012a..f8ba194 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -360,6 +360,88 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
> return count;
> }
>
> +static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t count)
> +{
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = ddev->dev_private;
> + int ret;
> + uint32_t parameter_size = 0;
> + long parameter[64];
> + char buf_cpy[128];
> + char *tmp_str;
> + char *sub_str;
> + const char delimiter[3] = {' ', '\n', '\0'};
> + uint32_t type;
> +
> + if (count > 127)
> + return -EINVAL;
> +
> + if (*buf == 'c') {
> + if (adev->powerplay.pp_funcs->dispatch_tasks) {
> + amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
> + return count;
> + } else {
> + return -EINVAL;
> + }
> + }
> +
> + if (*buf == 's')
> + type = PP_ODN_SCLK_VDDC_TABLE;
> + else if (*buf == 'm')
> + type = PP_ODN_MCLK_VDDC_TABLE;
> + else if(*buf == 'r')
> + type = PP_ODN_RESET_DEFAULT_TABLE;
> + else
> + return -EINVAL;
> +
> + memcpy(buf_cpy, buf, count+1);
> +
> + tmp_str = buf_cpy;
> +
> + while (isspace(*++tmp_str));
> +
> + while (tmp_str[0]) {
> + sub_str = strsep(&tmp_str, delimiter);
> + ret = kstrtol(sub_str, 0, ¶meter[parameter_size]);
> + if (ret)
> + return -EINVAL;
> + parameter_size++;
> +
> + while (isspace(*tmp_str))
> + tmp_str++;
> + }
> +
> + if (adev->powerplay.pp_funcs->odn_edit_dpm_table)
> + ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
> + parameter, parameter_size);
> +
> + if (ret)
> + return -EINVAL;
> +
> + return count;
> +}
> +
> +static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct drm_device *ddev = dev_get_drvdata(dev);
> + struct amdgpu_device *adev = ddev->dev_private;
> + uint32_t size = 0;
> +
> + if (adev->powerplay.pp_funcs->print_clock_levels) {
> + size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
> + size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
> + return size;
> + } else {
> + return snprintf(buf, PAGE_SIZE, "\n");
> + }
> +
> +}
> +
> static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -842,6 +924,10 @@ static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
> static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR,
> amdgpu_get_pp_power_profile_mode,
> amdgpu_set_pp_power_profile_mode);
> +static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR,
> + amdgpu_get_pp_od_clk_voltage,
> + amdgpu_set_pp_od_clk_voltage);
> +
> static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -1481,7 +1567,13 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
> "pp_power_profile_mode\n");
> return ret;
> }
> -
> + ret = device_create_file(adev->dev,
> + &dev_attr_pp_od_clk_voltage);
> + if (ret) {
> + DRM_ERROR("failed to create device file "
> + "pp_od_clk_voltage\n");
> + return ret;
> + }
> ret = amdgpu_debugfs_pm_init(adev);
> if (ret) {
> DRM_ERROR("Failed to register debugfs file for dpm!\n");
> @@ -1519,6 +1611,8 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
> &dev_attr_pp_compute_power_profile);
> device_remove_file(adev->dev,
> &dev_attr_pp_power_profile_mode);
> + device_remove_file(adev->dev,
> + &dev_attr_pp_od_clk_voltage);
> }
>
> void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index 3e8b9cc..f7393f9 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -309,6 +309,7 @@ struct amd_pm_funcs {
> struct amd_pp_simple_clock_info *clocks);
> int (*get_power_profile_mode)(void *handle, char *buf);
> int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
> + int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
> };
>
> #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index d9cb424..854c43c 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -1122,6 +1122,24 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
> return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
> }
>
> +static int pp_odn_edit_dpm_table(void *handle, uint32_t type, long *input, uint32_t size)
> +{
> + struct pp_hwmgr *hwmgr;
> + struct pp_instance *pp_handle = (struct pp_instance *)handle;
> +
> + if (pp_check(pp_handle))
> + return -EINVAL;
> +
> + hwmgr = pp_handle->hwmgr;
> +
> + if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
> + pr_info("%s was not implemented.\n", __func__);
> + return -EINVAL;
> + }
> +
> + return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
> +}
> +
> static int pp_dpm_set_power_profile_state(void *handle,
> struct amd_pp_profile *request)
> {
> @@ -1507,6 +1525,7 @@ static int pp_get_display_mode_validation_clocks(void *handle,
> .notify_smu_memory_info = pp_dpm_notify_smu_memory_info,
> .get_power_profile_mode = pp_get_power_profile_mode,
> .set_power_profile_mode = pp_set_power_profile_mode,
> + .odn_edit_dpm_table = pp_odn_edit_dpm_table,
> /* export to DC */
> .get_sclk = pp_dpm_get_sclk,
> .get_mclk = pp_dpm_get_mclk,
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 4/5] drm/amd/pp: Update smu7 dpm table with OD clock/voltage
[not found] ` <1516264682-10037-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-18 16:41 ` Alex Deucher
0 siblings, 0 replies; 11+ messages in thread
From: Alex Deucher @ 2018-01-18 16:41 UTC (permalink / raw)
To: Rex Zhu; +Cc: amd-gfx list
On Thu, Jan 18, 2018 at 3:38 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> delete old OD type code path when populate clk.
>
> Change-Id: I9beb7e751ac720edb4ffb1deaf7984e86e2e41b1
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 110 ++++-----------------
> drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 18 +++-
> .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 18 +++-
> .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 18 +++-
> 4 files changed, 62 insertions(+), 102 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 0d14299..ee70ef2 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3482,8 +3482,6 @@ static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, cons
> uint32_t i;
> struct cgs_display_info info = {0};
>
> - data->need_update_smu7_dpm_table = 0;
> -
> for (i = 0; i < sclk_table->count; i++) {
> if (sclk == sclk_table->dpm_levels[i].value)
> break;
> @@ -3625,106 +3623,27 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels(
> struct pp_hwmgr *hwmgr, const void *input)
> {
> int result = 0;
> - const struct phm_set_power_state_input *states =
> - (const struct phm_set_power_state_input *)input;
> - const struct smu7_power_state *smu7_ps =
> - cast_const_phw_smu7_power_state(states->pnew_state);
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> - uint32_t sclk = smu7_ps->performance_levels
> - [smu7_ps->performance_level_count - 1].engine_clock;
> - uint32_t mclk = smu7_ps->performance_levels
> - [smu7_ps->performance_level_count - 1].memory_clock;
> struct smu7_dpm_table *dpm_table = &data->dpm_table;
> -
> - struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table;
> - uint32_t dpm_count, clock_percent;
> - uint32_t i;
> + uint32_t count;
> + struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
> + struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels);
> + struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels);
>
> if (0 == data->need_update_smu7_dpm_table)
> return 0;
>
> - if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
> - dpm_table->sclk_table.dpm_levels
> - [dpm_table->sclk_table.count - 1].value = sclk;
> -
> - if (hwmgr->od_enabled) {
> - /* Need to do calculation based on the golden DPM table
> - * as the Heatmap GPU Clock axis is also based on the default values
> - */
> - PP_ASSERT_WITH_CODE(
> - (golden_dpm_table->sclk_table.dpm_levels
> - [golden_dpm_table->sclk_table.count - 1].value != 0),
> - "Divide by 0!",
> - return -EINVAL);
> - dpm_count = dpm_table->sclk_table.count < 2 ? 0 : dpm_table->sclk_table.count - 2;
> -
> - for (i = dpm_count; i > 1; i--) {
> - if (sclk > golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value) {
> - clock_percent =
> - ((sclk
> - - golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value
> - ) * 100)
> - / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
> -
> - dpm_table->sclk_table.dpm_levels[i].value =
> - golden_dpm_table->sclk_table.dpm_levels[i].value +
> - (golden_dpm_table->sclk_table.dpm_levels[i].value *
> - clock_percent)/100;
> -
> - } else if (golden_dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value > sclk) {
> - clock_percent =
> - ((golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value
> - - sclk) * 100)
> - / golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count-1].value;
> -
> - dpm_table->sclk_table.dpm_levels[i].value =
> - golden_dpm_table->sclk_table.dpm_levels[i].value -
> - (golden_dpm_table->sclk_table.dpm_levels[i].value *
> - clock_percent) / 100;
> - } else
> - dpm_table->sclk_table.dpm_levels[i].value =
> - golden_dpm_table->sclk_table.dpm_levels[i].value;
> - }
> + if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
> + for (count = 0; count < dpm_table->sclk_table.count; count++) {
> + dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled;
> + dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;
> }
> }
>
> - if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
> - dpm_table->mclk_table.dpm_levels
> - [dpm_table->mclk_table.count - 1].value = mclk;
> -
> - if (hwmgr->od_enabled) {
> -
> - PP_ASSERT_WITH_CODE(
> - (golden_dpm_table->mclk_table.dpm_levels
> - [golden_dpm_table->mclk_table.count-1].value != 0),
> - "Divide by 0!",
> - return -EINVAL);
> - dpm_count = dpm_table->mclk_table.count < 2 ? 0 : dpm_table->mclk_table.count - 2;
> - for (i = dpm_count; i > 1; i--) {
> - if (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value < mclk) {
> - clock_percent = ((mclk -
> - golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value) * 100)
> - / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
> -
> - dpm_table->mclk_table.dpm_levels[i].value =
> - golden_dpm_table->mclk_table.dpm_levels[i].value +
> - (golden_dpm_table->mclk_table.dpm_levels[i].value *
> - clock_percent) / 100;
> -
> - } else if (golden_dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value > mclk) {
> - clock_percent = (
> - (golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value - mclk)
> - * 100)
> - / golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count-1].value;
> -
> - dpm_table->mclk_table.dpm_levels[i].value =
> - golden_dpm_table->mclk_table.dpm_levels[i].value -
> - (golden_dpm_table->mclk_table.dpm_levels[i].value *
> - clock_percent) / 100;
> - } else
> - dpm_table->mclk_table.dpm_levels[i].value =
> - golden_dpm_table->mclk_table.dpm_levels[i].value;
> - }
> + if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
> + for (count = 0; count < dpm_table->mclk_table.count; count++) {
> + dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled;
> + dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;
> }
> }
>
> @@ -4114,6 +4033,7 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
> const struct smu7_power_state *psa;
> const struct smu7_power_state *psb;
> int i;
> + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
>
> if (pstate1 == NULL || pstate2 == NULL || equal == NULL)
> return -EINVAL;
> @@ -4138,6 +4058,10 @@ static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
> *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
> *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
> *equal &= (psa->sclk_threshold == psb->sclk_threshold);
> + /* For OD call, set value based on flag */
> + *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK |
> + DPMTABLE_OD_UPDATE_MCLK |
> + DPMTABLE_OD_UPDATE_VDDC));
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> index 7d9e2cb..c4a94d0 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
> @@ -981,12 +981,18 @@ static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> struct phm_ppt_v1_information *table_info =
> (struct phm_ppt_v1_information *)(hwmgr->pptable);
> + phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
>
> result = fiji_calculate_sclk_params(hwmgr, clock, level);
>
> + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
> + vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
> + else
> + vdd_dep_table = table_info->vdd_dep_on_sclk;
> +
> /* populate graphics levels */
> result = fiji_get_dependency_volt_by_clk(hwmgr,
> - table_info->vdd_dep_on_sclk, clock,
> + vdd_dep_table, clock,
> (uint32_t *)(&level->MinVoltage), &mvdd);
> PP_ASSERT_WITH_CODE((0 == result),
> "can not find VDDC voltage value for "
> @@ -1202,10 +1208,16 @@ static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
> (struct phm_ppt_v1_information *)(hwmgr->pptable);
> int result = 0;
> uint32_t mclk_stutter_mode_threshold = 60000;
> + phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
> +
> + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
> + vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
> + else
> + vdd_dep_table = table_info->vdd_dep_on_mclk;
>
> - if (table_info->vdd_dep_on_mclk) {
> + if (vdd_dep_table) {
> result = fiji_get_dependency_volt_by_clk(hwmgr,
> - table_info->vdd_dep_on_mclk, clock,
> + vdd_dep_table, clock,
> (uint32_t *)(&mem_level->MinVoltage), &mem_level->MinMvdd);
> PP_ASSERT_WITH_CODE((0 == result),
> "can not find MinVddc voltage value from memory "
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index f1a3bc8..c0c627f 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -948,12 +948,18 @@ static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
> struct phm_ppt_v1_information *table_info =
> (struct phm_ppt_v1_information *)(hwmgr->pptable);
> SMU_SclkSetting curr_sclk_setting = { 0 };
> + phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
>
> result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
>
> + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
> + vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
> + else
> + vdd_dep_table = table_info->vdd_dep_on_sclk;
> +
> /* populate graphics levels */
> result = polaris10_get_dependency_volt_by_clk(hwmgr,
> - table_info->vdd_dep_on_sclk, clock,
> + vdd_dep_table, clock,
> &level->MinVoltage, &mvdd);
>
> PP_ASSERT_WITH_CODE((0 == result),
> @@ -1107,12 +1113,18 @@ static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
> int result = 0;
> struct cgs_display_info info = {0, 0, NULL};
> uint32_t mclk_stutter_mode_threshold = 40000;
> + phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
>
> cgs_get_active_displays_info(hwmgr->device, &info);
>
> - if (table_info->vdd_dep_on_mclk) {
> + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
> + vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
> + else
> + vdd_dep_table = table_info->vdd_dep_on_mclk;
> +
> + if (vdd_dep_table) {
> result = polaris10_get_dependency_volt_by_clk(hwmgr,
> - table_info->vdd_dep_on_mclk, clock,
> + vdd_dep_table, clock,
> &mem_level->MinVoltage, &mem_level->MinMvdd);
> PP_ASSERT_WITH_CODE((0 == result),
> "can not find MinVddc voltage value from memory "
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> index a03a345..52e69e8 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
> @@ -620,12 +620,18 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
> struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> struct phm_ppt_v1_information *pptable_info =
> (struct phm_ppt_v1_information *)(hwmgr->pptable);
> + phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
>
> result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
>
> + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
> + vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
> + else
> + vdd_dep_table = pptable_info->vdd_dep_on_sclk;
> +
> /* populate graphics levels*/
> result = tonga_get_dependency_volt_by_clk(hwmgr,
> - pptable_info->vdd_dep_on_sclk, engine_clock,
> + vdd_dep_table, engine_clock,
> &graphic_level->MinVoltage, &mvdd);
> PP_ASSERT_WITH_CODE((!result),
> "can not find VDDC voltage value for VDDC "
> @@ -966,10 +972,16 @@ static int tonga_populate_single_memory_level(
> uint32_t mclk_stutter_mode_threshold = 30000;
> uint32_t mclk_edc_enable_threshold = 40000;
> uint32_t mclk_strobe_mode_threshold = 40000;
> + phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
> +
> + if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC)
> + vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
> + else
> + vdd_dep_table = pptable_info->vdd_dep_on_mclk;
>
> - if (NULL != pptable_info->vdd_dep_on_mclk) {
> + if (NULL != vdd_dep_table) {
> result = tonga_get_dependency_volt_by_clk(hwmgr,
> - pptable_info->vdd_dep_on_mclk,
> + vdd_dep_table,
> memory_clock,
> &memory_level->MinVoltage, &mvdd);
> PP_ASSERT_WITH_CODE(
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-01-18 16:41 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-18 8:37 [PATCH 0/5] Add sysfs to support OverDrive feature Rex Zhu
[not found] ` <1516264682-10037-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 8:37 ` [PATCH 1/5] drm/amd/pp: Add hwmgr interface for edit dpm table Rex Zhu
[not found] ` <1516264682-10037-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 16:40 ` Alex Deucher
2018-01-18 8:37 ` [PATCH 2/5] drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs Rex Zhu
[not found] ` <1516264682-10037-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 16:41 ` Alex Deucher
2018-01-18 8:38 ` [PATCH 3/5] drm/amd/pp: Implement edit_dpm_table on smu7 Rex Zhu
[not found] ` <1516264682-10037-4-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 16:34 ` Alex Deucher
2018-01-18 8:38 ` [PATCH 4/5] drm/amd/pp: Update smu7 dpm table with OD clock/voltage Rex Zhu
[not found] ` <1516264682-10037-5-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 16:41 ` Alex Deucher
2018-01-18 8:38 ` [PATCH 5/5] drm/amd/pp: Add update_avfs call when set_power_state Rex Zhu
[not found] ` <1516264682-10037-6-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-01-18 16:40 ` Alex Deucher
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.