[PATCH 0/2] Add dsi clock for stm32f469 board

[PATCH 0/2] Add dsi clock for stm32f469 board

[gabriel.fernandez]

From: Gabriel Fernandez <gabriel.fernandez@st.com>

This patch-set adds the dsi clock for stm32f469 board.

Gabriel Fernandez (2):
  clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK
  clk: stm32: Add DSI clock for STM32F469 Board

 drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
 include/dt-bindings/clock/stm32fx-clock.h |  7 ++++---
 2 files changed, 14 insertions(+), 4 deletions(-)

-- 
1.9.1

[PATCH 0/2] Add dsi clock for stm32f469 board

[gabriel.fernandez-qxv4g6HH51o]

From: Gabriel Fernandez <gabriel.fernandez-qxv4g6HH51o@public.gmane.org>

This patch-set adds the dsi clock for stm32f469 board.

Gabriel Fernandez (2):
  clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK
  clk: stm32: Add DSI clock for STM32F469 Board

 drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
 include/dt-bindings/clock/stm32fx-clock.h |  7 ++++---
 2 files changed, 14 insertions(+), 4 deletions(-)

-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 0/2] Add dsi clock for stm32f469 board

[gabriel.fernandez at st.com]

From: Gabriel Fernandez <gabriel.fernandez@st.com>

This patch-set adds the dsi clock for stm32f469 board.

Gabriel Fernandez (2):
  clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK
  clk: stm32: Add DSI clock for STM32F469 Board

 drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
 include/dt-bindings/clock/stm32fx-clock.h |  7 ++++---
 2 files changed, 14 insertions(+), 4 deletions(-)

-- 
1.9.1

[PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[gabriel.fernandez]

From: Gabriel Fernandez <gabriel.fernandez@st.com>

Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
hsi and sysclk are overwritten by gpioa and gpiob.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
 include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 49bb3c2..4d523b0 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -33,11 +33,11 @@
 #define CLK_SAI2		11
 #define CLK_I2SQ_PDIV		12
 #define CLK_SAIQ_PDIV		13
-
-#define END_PRIMARY_CLK		14
-
 #define CLK_HSI			14
 #define CLK_SYSCLK		15
+
+#define END_PRIMARY_CLK		16
+
 #define CLK_HDMI_CEC		16
 #define CLK_SPDIF		17
 #define CLK_USART1		18
-- 
1.9.1

[PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[gabriel.fernandez]

From: Gabriel Fernandez <gabriel.fernandez@st.com>

Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
hsi and sysclk are overwritten by gpioa and gpiob.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
 include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 49bb3c2..4d523b0 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -33,11 +33,11 @@
 #define CLK_SAI2		11
 #define CLK_I2SQ_PDIV		12
 #define CLK_SAIQ_PDIV		13
-
-#define END_PRIMARY_CLK		14
-
 #define CLK_HSI			14
 #define CLK_SYSCLK		15
+
+#define END_PRIMARY_CLK		16
+
 #define CLK_HDMI_CEC		16
 #define CLK_SPDIF		17
 #define CLK_USART1		18
-- 
1.9.1

[PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[gabriel.fernandez at st.com]

From: Gabriel Fernandez <gabriel.fernandez@st.com>

Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
hsi and sysclk are overwritten by gpioa and gpiob.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
 include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 49bb3c2..4d523b0 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -33,11 +33,11 @@
 #define CLK_SAI2		11
 #define CLK_I2SQ_PDIV		12
 #define CLK_SAIQ_PDIV		13
-
-#define END_PRIMARY_CLK		14
-
 #define CLK_HSI			14
 #define CLK_SYSCLK		15
+
+#define END_PRIMARY_CLK		16
+
 #define CLK_HDMI_CEC		16
 #define CLK_SPDIF		17
 #define CLK_USART1		18
-- 
1.9.1

[PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[gabriel.fernandez]

From: Gabriel Fernandez <gabriel.fernandez@st.com>

This patch adds DSI clock for STM32F469 board

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
 drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
 include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index da44f8d..3c28798 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -521,7 +521,7 @@ struct stm32f4_pll_data {
 };
 
 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
-	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
+	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
 	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
 	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
 };
@@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
 	"no-clock", "lse", "lsi", "hse-rtc"
 };
 
+static const char *dsi_parent[2] = { NULL, "pll-r" };
+
 static const char *lcd_parent[1] = { "pllsai-r-div" };
 
 static const char *i2s_parents[2] = { "plli2s-r", NULL };
@@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
 		NO_GATE, 0,
 		0
 	},
+	{
+		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
+		STM32F4_RCC_DCKCFGR, 29, 1,
+		STM32F4_RCC_APB2ENR, 27,
+		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+	},
 };
 
 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
@@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
 	stm32f4_gate_map = data->gates_map;
 
 	hse_clk = of_clk_get_parent_name(np, 0);
+	dsi_parent[0] = hse_clk;
 
 	i2s_in_clk = of_clk_get_parent_name(np, 1);
 
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 4d523b0..58d8b51 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -35,8 +35,9 @@
 #define CLK_SAIQ_PDIV		13
 #define CLK_HSI			14
 #define CLK_SYSCLK		15
+#define CLK_F469_DSI		16
 
-#define END_PRIMARY_CLK		16
+#define END_PRIMARY_CLK		17
 
 #define CLK_HDMI_CEC		16
 #define CLK_SPDIF		17
-- 
1.9.1

[PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[gabriel.fernandez]

From: Gabriel Fernandez <gabriel.fernandez@st.com>

This patch adds DSI clock for STM32F469 board

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
 drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
 include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index da44f8d..3c28798 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -521,7 +521,7 @@ struct stm32f4_pll_data {
 };
 
 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
-	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
+	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
 	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
 	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
 };
@@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
 	"no-clock", "lse", "lsi", "hse-rtc"
 };
 
+static const char *dsi_parent[2] = { NULL, "pll-r" };
+
 static const char *lcd_parent[1] = { "pllsai-r-div" };
 
 static const char *i2s_parents[2] = { "plli2s-r", NULL };
@@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
 		NO_GATE, 0,
 		0
 	},
+	{
+		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
+		STM32F4_RCC_DCKCFGR, 29, 1,
+		STM32F4_RCC_APB2ENR, 27,
+		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+	},
 };
 
 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
@@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
 	stm32f4_gate_map = data->gates_map;
 
 	hse_clk = of_clk_get_parent_name(np, 0);
+	dsi_parent[0] = hse_clk;
 
 	i2s_in_clk = of_clk_get_parent_name(np, 1);
 
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 4d523b0..58d8b51 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -35,8 +35,9 @@
 #define CLK_SAIQ_PDIV		13
 #define CLK_HSI			14
 #define CLK_SYSCLK		15
+#define CLK_F469_DSI		16
 
-#define END_PRIMARY_CLK		16
+#define END_PRIMARY_CLK		17
 
 #define CLK_HDMI_CEC		16
 #define CLK_SPDIF		17
-- 
1.9.1

[PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[gabriel.fernandez at st.com]

From: Gabriel Fernandez <gabriel.fernandez@st.com>

This patch adds DSI clock for STM32F469 board

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
---
 drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
 include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index da44f8d..3c28798 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -521,7 +521,7 @@ struct stm32f4_pll_data {
 };
 
 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
-	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
+	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
 	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
 	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
 };
@@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
 	"no-clock", "lse", "lsi", "hse-rtc"
 };
 
+static const char *dsi_parent[2] = { NULL, "pll-r" };
+
 static const char *lcd_parent[1] = { "pllsai-r-div" };
 
 static const char *i2s_parents[2] = { "plli2s-r", NULL };
@@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
 		NO_GATE, 0,
 		0
 	},
+	{
+		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
+		STM32F4_RCC_DCKCFGR, 29, 1,
+		STM32F4_RCC_APB2ENR, 27,
+		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
+	},
 };
 
 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
@@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
 	stm32f4_gate_map = data->gates_map;
 
 	hse_clk = of_clk_get_parent_name(np, 0);
+	dsi_parent[0] = hse_clk;
 
 	i2s_in_clk = of_clk_get_parent_name(np, 1);
 
diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
index 4d523b0..58d8b51 100644
--- a/include/dt-bindings/clock/stm32fx-clock.h
+++ b/include/dt-bindings/clock/stm32fx-clock.h
@@ -35,8 +35,9 @@
 #define CLK_SAIQ_PDIV		13
 #define CLK_HSI			14
 #define CLK_SYSCLK		15
+#define CLK_F469_DSI		16
 
-#define END_PRIMARY_CLK		16
+#define END_PRIMARY_CLK		17
 
 #define CLK_HDMI_CEC		16
 #define CLK_SPDIF		17
-- 
1.9.1

Re: [PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[Philippe CORNU]

Hi Gabriel,

Tested successfully on f469 disco board.

Tested-by: Philippe Cornu <philippe.cornu@st.com>

Many thanks,
Philippe :-)

On 01/18/2018 03:49 PM, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
> hsi and sysclk are overwritten by gpioa and gpiob.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>   include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
> index 49bb3c2..4d523b0 100644
> --- a/include/dt-bindings/clock/stm32fx-clock.h
> +++ b/include/dt-bindings/clock/stm32fx-clock.h
> @@ -33,11 +33,11 @@
>   #define CLK_SAI2		11
>   #define CLK_I2SQ_PDIV		12
>   #define CLK_SAIQ_PDIV		13
> -
> -#define END_PRIMARY_CLK		14
> -
>   #define CLK_HSI			14
>   #define CLK_SYSCLK		15
> +
> +#define END_PRIMARY_CLK		16
> +
>   #define CLK_HDMI_CEC		16
>   #define CLK_SPDIF		17
>   #define CLK_USART1		18
> 

Re: [PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[Philippe CORNU]

Hi Gabriel,

Tested successfully on f469 disco board.

Tested-by: Philippe Cornu <philippe.cornu@st.com>

Many thanks,
Philippe :-)

On 01/18/2018 03:49 PM, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
> hsi and sysclk are overwritten by gpioa and gpiob.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>   include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
> index 49bb3c2..4d523b0 100644
> --- a/include/dt-bindings/clock/stm32fx-clock.h
> +++ b/include/dt-bindings/clock/stm32fx-clock.h
> @@ -33,11 +33,11 @@
>   #define CLK_SAI2		11
>   #define CLK_I2SQ_PDIV		12
>   #define CLK_SAIQ_PDIV		13
> -
> -#define END_PRIMARY_CLK		14
> -
>   #define CLK_HSI			14
>   #define CLK_SYSCLK		15
> +
> +#define END_PRIMARY_CLK		16
> +
>   #define CLK_HDMI_CEC		16
>   #define CLK_SPDIF		17
>   #define CLK_USART1		18
> 

Re: [PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[Philippe CORNU]

SGkgR2FicmllbCwNCg0KVGVzdGVkIHN1Y2Nlc3NmdWxseSBvbiBmNDY5IGRpc2NvIGJvYXJkLg0K
DQpUZXN0ZWQtYnk6IFBoaWxpcHBlIENvcm51IDxwaGlsaXBwZS5jb3JudUBzdC5jb20+DQoNCk1h
bnkgdGhhbmtzLA0KUGhpbGlwcGUgOi0pDQoNCk9uIDAxLzE4LzIwMTggMDM6NDkgUE0sIGdhYnJp
ZWwuZmVybmFuZGV6QHN0LmNvbSB3cm90ZToNCj4gRnJvbTogR2FicmllbCBGZXJuYW5kZXogPGdh
YnJpZWwuZmVybmFuZGV6QHN0LmNvbT4NCj4gDQo+IFVwZGF0ZSBvZiBFTkRfUFJJTUFSWV9DTEsg
d2FzIG1pc3NlZCwgaXQgc2hvdWxkIGJlIGFmdGVyIENMS19TWVNDTEsNCj4gaHNpIGFuZCBzeXNj
bGsgYXJlIG92ZXJ3cml0dGVuIGJ5IGdwaW9hIGFuZCBncGlvYi4NCj4gDQo+IFNpZ25lZC1vZmYt
Ynk6IEdhYnJpZWwgRmVybmFuZGV6IDxnYWJyaWVsLmZlcm5hbmRlekBzdC5jb20+DQo+IC0tLQ0K
PiAgIGluY2x1ZGUvZHQtYmluZGluZ3MvY2xvY2svc3RtMzJmeC1jbG9jay5oIHwgNiArKystLS0N
Cj4gICAxIGZpbGUgY2hhbmdlZCwgMyBpbnNlcnRpb25zKCspLCAzIGRlbGV0aW9ucygtKQ0KPiAN
Cj4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvZHQtYmluZGluZ3MvY2xvY2svc3RtMzJmeC1jbG9jay5o
IGIvaW5jbHVkZS9kdC1iaW5kaW5ncy9jbG9jay9zdG0zMmZ4LWNsb2NrLmgNCj4gaW5kZXggNDli
YjNjMi4uNGQ1MjNiMCAxMDA2NDQNCj4gLS0tIGEvaW5jbHVkZS9kdC1iaW5kaW5ncy9jbG9jay9z
dG0zMmZ4LWNsb2NrLmgNCj4gKysrIGIvaW5jbHVkZS9kdC1iaW5kaW5ncy9jbG9jay9zdG0zMmZ4
LWNsb2NrLmgNCj4gQEAgLTMzLDExICszMywxMSBAQA0KPiAgICNkZWZpbmUgQ0xLX1NBSTIJCTEx
DQo+ICAgI2RlZmluZSBDTEtfSTJTUV9QRElWCQkxMg0KPiAgICNkZWZpbmUgQ0xLX1NBSVFfUERJ
VgkJMTMNCj4gLQ0KPiAtI2RlZmluZSBFTkRfUFJJTUFSWV9DTEsJCTE0DQo+IC0NCj4gICAjZGVm
aW5lIENMS19IU0kJCQkxNA0KPiAgICNkZWZpbmUgQ0xLX1NZU0NMSwkJMTUNCj4gKw0KPiArI2Rl
ZmluZSBFTkRfUFJJTUFSWV9DTEsJCTE2DQo+ICsNCj4gICAjZGVmaW5lIENMS19IRE1JX0NFQwkJ
MTYNCj4gICAjZGVmaW5lIENMS19TUERJRgkJMTcNCj4gICAjZGVmaW5lIENMS19VU0FSVDEJCTE4
DQo+IA==

[PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[Philippe CORNU]

Hi Gabriel,

Tested successfully on f469 disco board.

Tested-by: Philippe Cornu <philippe.cornu@st.com>

Many thanks,
Philippe :-)

On 01/18/2018 03:49 PM, gabriel.fernandez at st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
> hsi and sysclk are overwritten by gpioa and gpiob.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>   include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
> index 49bb3c2..4d523b0 100644
> --- a/include/dt-bindings/clock/stm32fx-clock.h
> +++ b/include/dt-bindings/clock/stm32fx-clock.h
> @@ -33,11 +33,11 @@
>   #define CLK_SAI2		11
>   #define CLK_I2SQ_PDIV		12
>   #define CLK_SAIQ_PDIV		13
> -
> -#define END_PRIMARY_CLK		14
> -
>   #define CLK_HSI			14
>   #define CLK_SYSCLK		15
> +
> +#define END_PRIMARY_CLK		16
> +
>   #define CLK_HDMI_CEC		16
>   #define CLK_SPDIF		17
>   #define CLK_USART1		18
> 

Re: [PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Philippe CORNU]

Hi Gabriel,

Tested successfully on f469 disco board.

Tested-by: Philippe Cornu <philippe.cornu@st.com>

Many thanks,
Philippe :-)

On 01/18/2018 03:49 PM, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> This patch adds DSI clock for STM32F469 board
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>   drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
>   include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
>   2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index da44f8d..3c28798 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -521,7 +521,7 @@ struct stm32f4_pll_data {
>   };
>   
>   static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
> -	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
> +	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
>   	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
>   	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
>   };
> @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>   	"no-clock", "lse", "lsi", "hse-rtc"
>   };
>   
> +static const char *dsi_parent[2] = { NULL, "pll-r" };
> +
>   static const char *lcd_parent[1] = { "pllsai-r-div" };
>   
>   static const char *i2s_parents[2] = { "plli2s-r", NULL };
> @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
>   		NO_GATE, 0,
>   		0
>   	},
> +	{
> +		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
> +		STM32F4_RCC_DCKCFGR, 29, 1,
> +		STM32F4_RCC_APB2ENR, 27,
> +		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
> +	},
>   };
>   
>   static const struct stm32_aux_clk stm32f746_aux_clk[] = {
> @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>   	stm32f4_gate_map = data->gates_map;
>   
>   	hse_clk = of_clk_get_parent_name(np, 0);
> +	dsi_parent[0] = hse_clk;
>   
>   	i2s_in_clk = of_clk_get_parent_name(np, 1);
>   
> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
> index 4d523b0..58d8b51 100644
> --- a/include/dt-bindings/clock/stm32fx-clock.h
> +++ b/include/dt-bindings/clock/stm32fx-clock.h
> @@ -35,8 +35,9 @@
>   #define CLK_SAIQ_PDIV		13
>   #define CLK_HSI			14
>   #define CLK_SYSCLK		15
> +#define CLK_F469_DSI		16
>   
> -#define END_PRIMARY_CLK		16
> +#define END_PRIMARY_CLK		17
>   
>   #define CLK_HDMI_CEC		16
>   #define CLK_SPDIF		17
> 

Re: [PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Philippe CORNU]

Hi Gabriel,

Tested successfully on f469 disco board.

Tested-by: Philippe Cornu <philippe.cornu@st.com>

Many thanks,
Philippe :-)

On 01/18/2018 03:49 PM, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> This patch adds DSI clock for STM32F469 board
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>   drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
>   include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
>   2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index da44f8d..3c28798 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -521,7 +521,7 @@ struct stm32f4_pll_data {
>   };
>   
>   static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
> -	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
> +	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
>   	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
>   	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
>   };
> @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>   	"no-clock", "lse", "lsi", "hse-rtc"
>   };
>   
> +static const char *dsi_parent[2] = { NULL, "pll-r" };
> +
>   static const char *lcd_parent[1] = { "pllsai-r-div" };
>   
>   static const char *i2s_parents[2] = { "plli2s-r", NULL };
> @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
>   		NO_GATE, 0,
>   		0
>   	},
> +	{
> +		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
> +		STM32F4_RCC_DCKCFGR, 29, 1,
> +		STM32F4_RCC_APB2ENR, 27,
> +		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
> +	},
>   };
>   
>   static const struct stm32_aux_clk stm32f746_aux_clk[] = {
> @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>   	stm32f4_gate_map = data->gates_map;
>   
>   	hse_clk = of_clk_get_parent_name(np, 0);
> +	dsi_parent[0] = hse_clk;
>   
>   	i2s_in_clk = of_clk_get_parent_name(np, 1);
>   
> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
> index 4d523b0..58d8b51 100644
> --- a/include/dt-bindings/clock/stm32fx-clock.h
> +++ b/include/dt-bindings/clock/stm32fx-clock.h
> @@ -35,8 +35,9 @@
>   #define CLK_SAIQ_PDIV		13
>   #define CLK_HSI			14
>   #define CLK_SYSCLK		15
> +#define CLK_F469_DSI		16
>   
> -#define END_PRIMARY_CLK		16
> +#define END_PRIMARY_CLK		17
>   
>   #define CLK_HDMI_CEC		16
>   #define CLK_SPDIF		17
> 

Re: [PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Philippe CORNU]

SGkgR2FicmllbCwNCg0KVGVzdGVkIHN1Y2Nlc3NmdWxseSBvbiBmNDY5IGRpc2NvIGJvYXJkLg0K
DQpUZXN0ZWQtYnk6IFBoaWxpcHBlIENvcm51IDxwaGlsaXBwZS5jb3JudUBzdC5jb20+DQoNCk1h
bnkgdGhhbmtzLA0KUGhpbGlwcGUgOi0pDQoNCk9uIDAxLzE4LzIwMTggMDM6NDkgUE0sIGdhYnJp
ZWwuZmVybmFuZGV6QHN0LmNvbSB3cm90ZToNCj4gRnJvbTogR2FicmllbCBGZXJuYW5kZXogPGdh
YnJpZWwuZmVybmFuZGV6QHN0LmNvbT4NCj4gDQo+IFRoaXMgcGF0Y2ggYWRkcyBEU0kgY2xvY2sg
Zm9yIFNUTTMyRjQ2OSBib2FyZA0KPiANCj4gU2lnbmVkLW9mZi1ieTogR2FicmllbCBGZXJuYW5k
ZXogPGdhYnJpZWwuZmVybmFuZGV6QHN0LmNvbT4NCj4gLS0tDQo+ICAgZHJpdmVycy9jbGsvY2xr
LXN0bTMyZjQuYyAgICAgICAgICAgICAgICAgfCAxMSArKysrKysrKysrLQ0KPiAgIGluY2x1ZGUv
ZHQtYmluZGluZ3MvY2xvY2svc3RtMzJmeC1jbG9jay5oIHwgIDMgKystDQo+ICAgMiBmaWxlcyBj
aGFuZ2VkLCAxMiBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKQ0KPiANCj4gZGlmZiAtLWdp
dCBhL2RyaXZlcnMvY2xrL2Nsay1zdG0zMmY0LmMgYi9kcml2ZXJzL2Nsay9jbGstc3RtMzJmNC5j
DQo+IGluZGV4IGRhNDRmOGQuLjNjMjg3OTggMTAwNjQ0DQo+IC0tLSBhL2RyaXZlcnMvY2xrL2Ns
ay1zdG0zMmY0LmMNCj4gKysrIGIvZHJpdmVycy9jbGsvY2xrLXN0bTMyZjQuYw0KPiBAQCAtNTIx
LDcgKzUyMSw3IEBAIHN0cnVjdCBzdG0zMmY0X3BsbF9kYXRhIHsNCj4gICB9Ow0KPiAgIA0KPiAg
IHN0YXRpYyBjb25zdCBzdHJ1Y3Qgc3RtMzJmNF9wbGxfZGF0YSBzdG0zMmY0NjlfcGxsW01BWF9Q
TExfRElWXSA9IHsNCj4gLQl7IFBMTCwJICAgNTAsIHsgInBsbCIsCSAgICAgInBsbC1xIiwgICAg
TlVMTAkgICAgfSB9LA0KPiArCXsgUExMLAkgICA1MCwgeyAicGxsIiwJICAgICAicGxsLXEiLCAg
ICAicGxsLXIiICAgIH0gfSwNCj4gICAJeyBQTExfSTJTLCA1MCwgeyAicGxsaTJzLXAiLCAicGxs
aTJzLXEiLCAicGxsaTJzLXIiIH0gfSwNCj4gICAJeyBQTExfU0FJLCA1MCwgeyAicGxsc2FpLXAi
LCAicGxsc2FpLXEiLCAicGxsc2FpLXIiIH0gfSwNCj4gICB9Ow0KPiBAQCAtMTA0Nyw2ICsxMDQ3
LDggQEAgc3RhdGljIHN0cnVjdCBjbGtfaHcgKnN0bTMyX3JlZ2lzdGVyX2NjbGsoc3RydWN0IGRl
dmljZSAqZGV2LCBjb25zdCBjaGFyICpuYW1lLA0KPiAgIAkibm8tY2xvY2siLCAibHNlIiwgImxz
aSIsICJoc2UtcnRjIg0KPiAgIH07DQo+ICAgDQo+ICtzdGF0aWMgY29uc3QgY2hhciAqZHNpX3Bh
cmVudFsyXSA9IHsgTlVMTCwgInBsbC1yIiB9Ow0KPiArDQo+ICAgc3RhdGljIGNvbnN0IGNoYXIg
KmxjZF9wYXJlbnRbMV0gPSB7ICJwbGxzYWktci1kaXYiIH07DQo+ICAgDQo+ICAgc3RhdGljIGNv
bnN0IGNoYXIgKmkyc19wYXJlbnRzWzJdID0geyAicGxsaTJzLXIiLCBOVUxMIH07DQo+IEBAIC0x
MTU2LDYgKzExNTgsMTIgQEAgc3RydWN0IHN0bTMyZjRfY2xrX2RhdGEgew0KPiAgIAkJTk9fR0FU
RSwgMCwNCj4gICAJCTANCj4gICAJfSwNCj4gKwl7DQo+ICsJCUNMS19GNDY5X0RTSSwgImRzaSIs
IGRzaV9wYXJlbnQsIEFSUkFZX1NJWkUoZHNpX3BhcmVudCksDQo+ICsJCVNUTTMyRjRfUkNDX0RD
S0NGR1IsIDI5LCAxLA0KPiArCQlTVE0zMkY0X1JDQ19BUEIyRU5SLCAyNywNCj4gKwkJQ0xLX1NF
VF9SQVRFX1BBUkVOVCB8IENMS19TRVRfUkFURV9OT19SRVBBUkVOVA0KPiArCX0sDQo+ICAgfTsN
Cj4gICANCj4gICBzdGF0aWMgY29uc3Qgc3RydWN0IHN0bTMyX2F1eF9jbGsgc3RtMzJmNzQ2X2F1
eF9jbGtbXSA9IHsNCj4gQEAgLTE0NTAsNiArMTQ1OCw3IEBAIHN0YXRpYyB2b2lkIF9faW5pdCBz
dG0zMmY0X3JjY19pbml0KHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnApDQo+ICAgCXN0bTMyZjRfZ2F0
ZV9tYXAgPSBkYXRhLT5nYXRlc19tYXA7DQo+ICAgDQo+ICAgCWhzZV9jbGsgPSBvZl9jbGtfZ2V0
X3BhcmVudF9uYW1lKG5wLCAwKTsNCj4gKwlkc2lfcGFyZW50WzBdID0gaHNlX2NsazsNCj4gICAN
Cj4gICAJaTJzX2luX2NsayA9IG9mX2Nsa19nZXRfcGFyZW50X25hbWUobnAsIDEpOw0KPiAgIA0K
PiBkaWZmIC0tZ2l0IGEvaW5jbHVkZS9kdC1iaW5kaW5ncy9jbG9jay9zdG0zMmZ4LWNsb2NrLmgg
Yi9pbmNsdWRlL2R0LWJpbmRpbmdzL2Nsb2NrL3N0bTMyZngtY2xvY2suaA0KPiBpbmRleCA0ZDUy
M2IwLi41OGQ4YjUxIDEwMDY0NA0KPiAtLS0gYS9pbmNsdWRlL2R0LWJpbmRpbmdzL2Nsb2NrL3N0
bTMyZngtY2xvY2suaA0KPiArKysgYi9pbmNsdWRlL2R0LWJpbmRpbmdzL2Nsb2NrL3N0bTMyZngt
Y2xvY2suaA0KPiBAQCAtMzUsOCArMzUsOSBAQA0KPiAgICNkZWZpbmUgQ0xLX1NBSVFfUERJVgkJ
MTMNCj4gICAjZGVmaW5lIENMS19IU0kJCQkxNA0KPiAgICNkZWZpbmUgQ0xLX1NZU0NMSwkJMTUN
Cj4gKyNkZWZpbmUgQ0xLX0Y0NjlfRFNJCQkxNg0KPiAgIA0KPiAtI2RlZmluZSBFTkRfUFJJTUFS
WV9DTEsJCTE2DQo+ICsjZGVmaW5lIEVORF9QUklNQVJZX0NMSwkJMTcNCj4gICANCj4gICAjZGVm
aW5lIENMS19IRE1JX0NFQwkJMTYNCj4gICAjZGVmaW5lIENMS19TUERJRgkJMTcNCj4g

[PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Philippe CORNU]

Hi Gabriel,

Tested successfully on f469 disco board.

Tested-by: Philippe Cornu <philippe.cornu@st.com>

Many thanks,
Philippe :-)

On 01/18/2018 03:49 PM, gabriel.fernandez at st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> This patch adds DSI clock for STM32F469 board
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>   drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
>   include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
>   2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index da44f8d..3c28798 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -521,7 +521,7 @@ struct stm32f4_pll_data {
>   };
>   
>   static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
> -	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
> +	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
>   	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
>   	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
>   };
> @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>   	"no-clock", "lse", "lsi", "hse-rtc"
>   };
>   
> +static const char *dsi_parent[2] = { NULL, "pll-r" };
> +
>   static const char *lcd_parent[1] = { "pllsai-r-div" };
>   
>   static const char *i2s_parents[2] = { "plli2s-r", NULL };
> @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
>   		NO_GATE, 0,
>   		0
>   	},
> +	{
> +		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
> +		STM32F4_RCC_DCKCFGR, 29, 1,
> +		STM32F4_RCC_APB2ENR, 27,
> +		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
> +	},
>   };
>   
>   static const struct stm32_aux_clk stm32f746_aux_clk[] = {
> @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>   	stm32f4_gate_map = data->gates_map;
>   
>   	hse_clk = of_clk_get_parent_name(np, 0);
> +	dsi_parent[0] = hse_clk;
>   
>   	i2s_in_clk = of_clk_get_parent_name(np, 1);
>   
> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
> index 4d523b0..58d8b51 100644
> --- a/include/dt-bindings/clock/stm32fx-clock.h
> +++ b/include/dt-bindings/clock/stm32fx-clock.h
> @@ -35,8 +35,9 @@
>   #define CLK_SAIQ_PDIV		13
>   #define CLK_HSI			14
>   #define CLK_SYSCLK		15
> +#define CLK_F469_DSI		16
>   
> -#define END_PRIMARY_CLK		16
> +#define END_PRIMARY_CLK		17
>   
>   #define CLK_HDMI_CEC		16
>   #define CLK_SPDIF		17
> 

Re: [PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[Rob Herring]

On Thu, Jan 18, 2018 at 03:49:39PM +0100, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
> hsi and sysclk are overwritten by gpioa and gpiob.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>  include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[Rob Herring]

On Thu, Jan 18, 2018 at 03:49:39PM +0100, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
> hsi and sysclk are overwritten by gpioa and gpiob.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>  include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH 1/2] clk: stm32: END_PRIMARY_CLK should be declare after CLK_SYSCLK

[Rob Herring]

On Thu, Jan 18, 2018 at 03:49:39PM +0100, gabriel.fernandez at st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> Update of END_PRIMARY_CLK was missed, it should be after CLK_SYSCLK
> hsi and sysclk are overwritten by gpioa and gpiob.
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>  include/dt-bindings/clock/stm32fx-clock.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Rob Herring]

On Thu, Jan 18, 2018 at 03:49:40PM +0100, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> This patch adds DSI clock for STM32F469 board
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>  drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
>  include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index da44f8d..3c28798 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -521,7 +521,7 @@ struct stm32f4_pll_data {
>  };
>  
>  static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
> -	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
> +	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
>  	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
>  	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
>  };
> @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>  	"no-clock", "lse", "lsi", "hse-rtc"
>  };
>  
> +static const char *dsi_parent[2] = { NULL, "pll-r" };
> +
>  static const char *lcd_parent[1] = { "pllsai-r-div" };
>  
>  static const char *i2s_parents[2] = { "plli2s-r", NULL };
> @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
>  		NO_GATE, 0,
>  		0
>  	},
> +	{
> +		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
> +		STM32F4_RCC_DCKCFGR, 29, 1,
> +		STM32F4_RCC_APB2ENR, 27,
> +		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
> +	},
>  };
>  
>  static const struct stm32_aux_clk stm32f746_aux_clk[] = {
> @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>  	stm32f4_gate_map = data->gates_map;
>  
>  	hse_clk = of_clk_get_parent_name(np, 0);
> +	dsi_parent[0] = hse_clk;
>  
>  	i2s_in_clk = of_clk_get_parent_name(np, 1);
>  
> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
> index 4d523b0..58d8b51 100644
> --- a/include/dt-bindings/clock/stm32fx-clock.h
> +++ b/include/dt-bindings/clock/stm32fx-clock.h
> @@ -35,8 +35,9 @@
>  #define CLK_SAIQ_PDIV		13
>  #define CLK_HSI			14
>  #define CLK_SYSCLK		15
> +#define CLK_F469_DSI		16
>  
> -#define END_PRIMARY_CLK		16
> +#define END_PRIMARY_CLK		17
>  
>  #define CLK_HDMI_CEC		16
>  #define CLK_SPDIF		17

This looks suspicious. What's the relationship of these clocks?

Rob

[PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Rob Herring]

On Thu, Jan 18, 2018 at 03:49:40PM +0100, gabriel.fernandez at st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
> 
> This patch adds DSI clock for STM32F469 board
> 
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
>  drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
>  include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index da44f8d..3c28798 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -521,7 +521,7 @@ struct stm32f4_pll_data {
>  };
>  
>  static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
> -	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
> +	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
>  	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
>  	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
>  };
> @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>  	"no-clock", "lse", "lsi", "hse-rtc"
>  };
>  
> +static const char *dsi_parent[2] = { NULL, "pll-r" };
> +
>  static const char *lcd_parent[1] = { "pllsai-r-div" };
>  
>  static const char *i2s_parents[2] = { "plli2s-r", NULL };
> @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
>  		NO_GATE, 0,
>  		0
>  	},
> +	{
> +		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
> +		STM32F4_RCC_DCKCFGR, 29, 1,
> +		STM32F4_RCC_APB2ENR, 27,
> +		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
> +	},
>  };
>  
>  static const struct stm32_aux_clk stm32f746_aux_clk[] = {
> @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>  	stm32f4_gate_map = data->gates_map;
>  
>  	hse_clk = of_clk_get_parent_name(np, 0);
> +	dsi_parent[0] = hse_clk;
>  
>  	i2s_in_clk = of_clk_get_parent_name(np, 1);
>  
> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
> index 4d523b0..58d8b51 100644
> --- a/include/dt-bindings/clock/stm32fx-clock.h
> +++ b/include/dt-bindings/clock/stm32fx-clock.h
> @@ -35,8 +35,9 @@
>  #define CLK_SAIQ_PDIV		13
>  #define CLK_HSI			14
>  #define CLK_SYSCLK		15
> +#define CLK_F469_DSI		16
>  
> -#define END_PRIMARY_CLK		16
> +#define END_PRIMARY_CLK		17
>  
>  #define CLK_HDMI_CEC		16
>  #define CLK_SPDIF		17

This looks suspicious. What's the relationship of these clocks?

Rob

Re: [PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Gabriel FERNANDEZ]

Hi Rob,

Thanks for reviewing.


On 01/29/2018 07:56 PM, Rob Herring wrote:
> On Thu, Jan 18, 2018 at 03:49:40PM +0100, gabriel.fernandez@st.com wrote:
>> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>>
>> This patch adds DSI clock for STM32F469 board
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
>> ---
>>   drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
>>   include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
>>   2 files changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
>> index da44f8d..3c28798 100644
>> --- a/drivers/clk/clk-stm32f4.c
>> +++ b/drivers/clk/clk-stm32f4.c
>> @@ -521,7 +521,7 @@ struct stm32f4_pll_data {
>>   };
>>   
>>   static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
>> -	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
>> +	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
>>   	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
>>   	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
>>   };
>> @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>>   	"no-clock", "lse", "lsi", "hse-rtc"
>>   };
>>   
>> +static const char *dsi_parent[2] = { NULL, "pll-r" };
>> +
>>   static const char *lcd_parent[1] = { "pllsai-r-div" };
>>   
>>   static const char *i2s_parents[2] = { "plli2s-r", NULL };
>> @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
>>   		NO_GATE, 0,
>>   		0
>>   	},
>> +	{
>> +		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
>> +		STM32F4_RCC_DCKCFGR, 29, 1,
>> +		STM32F4_RCC_APB2ENR, 27,
>> +		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
>> +	},
>>   };
>>   
>>   static const struct stm32_aux_clk stm32f746_aux_clk[] = {
>> @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>>   	stm32f4_gate_map = data->gates_map;
>>   
>>   	hse_clk = of_clk_get_parent_name(np, 0);
>> +	dsi_parent[0] = hse_clk;
>>   
>>   	i2s_in_clk = of_clk_get_parent_name(np, 1);
>>   
>> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
>> index 4d523b0..58d8b51 100644
>> --- a/include/dt-bindings/clock/stm32fx-clock.h
>> +++ b/include/dt-bindings/clock/stm32fx-clock.h
>> @@ -35,8 +35,9 @@
>>   #define CLK_SAIQ_PDIV		13
>>   #define CLK_HSI			14
>>   #define CLK_SYSCLK		15
>> +#define CLK_F469_DSI		16
>>   
>> -#define END_PRIMARY_CLK		16
>> +#define END_PRIMARY_CLK		17
>>   
>>   #define CLK_HDMI_CEC		16
>>   #define CLK_SPDIF		17
> This looks suspicious. What's the relationship of these clocks?
I have just added CLK_F469_DSI in the binding, and shifted the end of 
primary clock for F4 clocks.

'CLK_F469_DSI' binding is only used for STM32F469 and not for STM32F746 
(that why CLK_HDMI_CEC can use the index 16)


BR

Gabriel.
>
> Rob

Re: [PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Gabriel FERNANDEZ]

SGkgUm9iLA0KDQpUaGFua3MgZm9yIHJldmlld2luZy4NCg0KDQpPbiAwMS8yOS8yMDE4IDA3OjU2
IFBNLCBSb2IgSGVycmluZyB3cm90ZToNCj4gT24gVGh1LCBKYW4gMTgsIDIwMTggYXQgMDM6NDk6
NDBQTSArMDEwMCwgZ2FicmllbC5mZXJuYW5kZXpAc3QuY29tIHdyb3RlOg0KPj4gRnJvbTogR2Fi
cmllbCBGZXJuYW5kZXogPGdhYnJpZWwuZmVybmFuZGV6QHN0LmNvbT4NCj4+DQo+PiBUaGlzIHBh
dGNoIGFkZHMgRFNJIGNsb2NrIGZvciBTVE0zMkY0NjkgYm9hcmQNCj4+DQo+PiBTaWduZWQtb2Zm
LWJ5OiBHYWJyaWVsIEZlcm5hbmRleiA8Z2FicmllbC5mZXJuYW5kZXpAc3QuY29tPg0KPj4gLS0t
DQo+PiAgIGRyaXZlcnMvY2xrL2Nsay1zdG0zMmY0LmMgICAgICAgICAgICAgICAgIHwgMTEgKysr
KysrKysrKy0NCj4+ICAgaW5jbHVkZS9kdC1iaW5kaW5ncy9jbG9jay9zdG0zMmZ4LWNsb2NrLmgg
fCAgMyArKy0NCj4+ICAgMiBmaWxlcyBjaGFuZ2VkLCAxMiBpbnNlcnRpb25zKCspLCAyIGRlbGV0
aW9ucygtKQ0KPj4NCj4+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2Nsay9jbGstc3RtMzJmNC5jIGIv
ZHJpdmVycy9jbGsvY2xrLXN0bTMyZjQuYw0KPj4gaW5kZXggZGE0NGY4ZC4uM2MyODc5OCAxMDA2
NDQNCj4+IC0tLSBhL2RyaXZlcnMvY2xrL2Nsay1zdG0zMmY0LmMNCj4+ICsrKyBiL2RyaXZlcnMv
Y2xrL2Nsay1zdG0zMmY0LmMNCj4+IEBAIC01MjEsNyArNTIxLDcgQEAgc3RydWN0IHN0bTMyZjRf
cGxsX2RhdGEgew0KPj4gICB9Ow0KPj4gICANCj4+ICAgc3RhdGljIGNvbnN0IHN0cnVjdCBzdG0z
MmY0X3BsbF9kYXRhIHN0bTMyZjQ2OV9wbGxbTUFYX1BMTF9ESVZdID0gew0KPj4gLQl7IFBMTCwJ
ICAgNTAsIHsgInBsbCIsCSAgICAgInBsbC1xIiwgICAgTlVMTAkgICAgfSB9LA0KPj4gKwl7IFBM
TCwJICAgNTAsIHsgInBsbCIsCSAgICAgInBsbC1xIiwgICAgInBsbC1yIiAgICB9IH0sDQo+PiAg
IAl7IFBMTF9JMlMsIDUwLCB7ICJwbGxpMnMtcCIsICJwbGxpMnMtcSIsICJwbGxpMnMtciIgfSB9
LA0KPj4gICAJeyBQTExfU0FJLCA1MCwgeyAicGxsc2FpLXAiLCAicGxsc2FpLXEiLCAicGxsc2Fp
LXIiIH0gfSwNCj4+ICAgfTsNCj4+IEBAIC0xMDQ3LDYgKzEwNDcsOCBAQCBzdGF0aWMgc3RydWN0
IGNsa19odyAqc3RtMzJfcmVnaXN0ZXJfY2NsayhzdHJ1Y3QgZGV2aWNlICpkZXYsIGNvbnN0IGNo
YXIgKm5hbWUsDQo+PiAgIAkibm8tY2xvY2siLCAibHNlIiwgImxzaSIsICJoc2UtcnRjIg0KPj4g
ICB9Ow0KPj4gICANCj4+ICtzdGF0aWMgY29uc3QgY2hhciAqZHNpX3BhcmVudFsyXSA9IHsgTlVM
TCwgInBsbC1yIiB9Ow0KPj4gKw0KPj4gICBzdGF0aWMgY29uc3QgY2hhciAqbGNkX3BhcmVudFsx
XSA9IHsgInBsbHNhaS1yLWRpdiIgfTsNCj4+ICAgDQo+PiAgIHN0YXRpYyBjb25zdCBjaGFyICpp
MnNfcGFyZW50c1syXSA9IHsgInBsbGkycy1yIiwgTlVMTCB9Ow0KPj4gQEAgLTExNTYsNiArMTE1
OCwxMiBAQCBzdHJ1Y3Qgc3RtMzJmNF9jbGtfZGF0YSB7DQo+PiAgIAkJTk9fR0FURSwgMCwNCj4+
ICAgCQkwDQo+PiAgIAl9LA0KPj4gKwl7DQo+PiArCQlDTEtfRjQ2OV9EU0ksICJkc2kiLCBkc2lf
cGFyZW50LCBBUlJBWV9TSVpFKGRzaV9wYXJlbnQpLA0KPj4gKwkJU1RNMzJGNF9SQ0NfRENLQ0ZH
UiwgMjksIDEsDQo+PiArCQlTVE0zMkY0X1JDQ19BUEIyRU5SLCAyNywNCj4+ICsJCUNMS19TRVRf
UkFURV9QQVJFTlQgfCBDTEtfU0VUX1JBVEVfTk9fUkVQQVJFTlQNCj4+ICsJfSwNCj4+ICAgfTsN
Cj4+ICAgDQo+PiAgIHN0YXRpYyBjb25zdCBzdHJ1Y3Qgc3RtMzJfYXV4X2NsayBzdG0zMmY3NDZf
YXV4X2Nsa1tdID0gew0KPj4gQEAgLTE0NTAsNiArMTQ1OCw3IEBAIHN0YXRpYyB2b2lkIF9faW5p
dCBzdG0zMmY0X3JjY19pbml0KHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnApDQo+PiAgIAlzdG0zMmY0
X2dhdGVfbWFwID0gZGF0YS0+Z2F0ZXNfbWFwOw0KPj4gICANCj4+ICAgCWhzZV9jbGsgPSBvZl9j
bGtfZ2V0X3BhcmVudF9uYW1lKG5wLCAwKTsNCj4+ICsJZHNpX3BhcmVudFswXSA9IGhzZV9jbGs7
DQo+PiAgIA0KPj4gICAJaTJzX2luX2NsayA9IG9mX2Nsa19nZXRfcGFyZW50X25hbWUobnAsIDEp
Ow0KPj4gICANCj4+IGRpZmYgLS1naXQgYS9pbmNsdWRlL2R0LWJpbmRpbmdzL2Nsb2NrL3N0bTMy
ZngtY2xvY2suaCBiL2luY2x1ZGUvZHQtYmluZGluZ3MvY2xvY2svc3RtMzJmeC1jbG9jay5oDQo+
PiBpbmRleCA0ZDUyM2IwLi41OGQ4YjUxIDEwMDY0NA0KPj4gLS0tIGEvaW5jbHVkZS9kdC1iaW5k
aW5ncy9jbG9jay9zdG0zMmZ4LWNsb2NrLmgNCj4+ICsrKyBiL2luY2x1ZGUvZHQtYmluZGluZ3Mv
Y2xvY2svc3RtMzJmeC1jbG9jay5oDQo+PiBAQCAtMzUsOCArMzUsOSBAQA0KPj4gICAjZGVmaW5l
IENMS19TQUlRX1BESVYJCTEzDQo+PiAgICNkZWZpbmUgQ0xLX0hTSQkJCTE0DQo+PiAgICNkZWZp
bmUgQ0xLX1NZU0NMSwkJMTUNCj4+ICsjZGVmaW5lIENMS19GNDY5X0RTSQkJMTYNCj4+ICAgDQo+
PiAtI2RlZmluZSBFTkRfUFJJTUFSWV9DTEsJCTE2DQo+PiArI2RlZmluZSBFTkRfUFJJTUFSWV9D
TEsJCTE3DQo+PiAgIA0KPj4gICAjZGVmaW5lIENMS19IRE1JX0NFQwkJMTYNCj4+ICAgI2RlZmlu
ZSBDTEtfU1BESUYJCTE3DQo+IFRoaXMgbG9va3Mgc3VzcGljaW91cy4gV2hhdCdzIHRoZSByZWxh
dGlvbnNoaXAgb2YgdGhlc2UgY2xvY2tzPw0KSSBoYXZlIGp1c3QgYWRkZWQgQ0xLX0Y0NjlfRFNJ
IGluIHRoZSBiaW5kaW5nLCBhbmQgc2hpZnRlZCB0aGUgZW5kIG9mIA0KcHJpbWFyeSBjbG9jayBm
b3IgRjQgY2xvY2tzLg0KDQonQ0xLX0Y0NjlfRFNJJyBiaW5kaW5nIGlzIG9ubHkgdXNlZCBmb3Ig
U1RNMzJGNDY5IGFuZCBub3QgZm9yIFNUTTMyRjc0NiANCih0aGF0IHdoeSBDTEtfSERNSV9DRUMg
Y2FuIHVzZSB0aGUgaW5kZXggMTYpDQoNCg0KQlINCg0KR2FicmllbC4NCj4NCj4gUm9iDQo=

[PATCH 2/2] clk: stm32: Add DSI clock for STM32F469 Board

[Gabriel FERNANDEZ]

Hi Rob,

Thanks for reviewing.


On 01/29/2018 07:56 PM, Rob Herring wrote:
> On Thu, Jan 18, 2018 at 03:49:40PM +0100, gabriel.fernandez at st.com wrote:
>> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>>
>> This patch adds DSI clock for STM32F469 board
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
>> ---
>>   drivers/clk/clk-stm32f4.c                 | 11 ++++++++++-
>>   include/dt-bindings/clock/stm32fx-clock.h |  3 ++-
>>   2 files changed, 12 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
>> index da44f8d..3c28798 100644
>> --- a/drivers/clk/clk-stm32f4.c
>> +++ b/drivers/clk/clk-stm32f4.c
>> @@ -521,7 +521,7 @@ struct stm32f4_pll_data {
>>   };
>>   
>>   static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
>> -	{ PLL,	   50, { "pll",	     "pll-q",    NULL	    } },
>> +	{ PLL,	   50, { "pll",	     "pll-q",    "pll-r"    } },
>>   	{ PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
>>   	{ PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
>>   };
>> @@ -1047,6 +1047,8 @@ static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
>>   	"no-clock", "lse", "lsi", "hse-rtc"
>>   };
>>   
>> +static const char *dsi_parent[2] = { NULL, "pll-r" };
>> +
>>   static const char *lcd_parent[1] = { "pllsai-r-div" };
>>   
>>   static const char *i2s_parents[2] = { "plli2s-r", NULL };
>> @@ -1156,6 +1158,12 @@ struct stm32f4_clk_data {
>>   		NO_GATE, 0,
>>   		0
>>   	},
>> +	{
>> +		CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
>> +		STM32F4_RCC_DCKCFGR, 29, 1,
>> +		STM32F4_RCC_APB2ENR, 27,
>> +		CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
>> +	},
>>   };
>>   
>>   static const struct stm32_aux_clk stm32f746_aux_clk[] = {
>> @@ -1450,6 +1458,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
>>   	stm32f4_gate_map = data->gates_map;
>>   
>>   	hse_clk = of_clk_get_parent_name(np, 0);
>> +	dsi_parent[0] = hse_clk;
>>   
>>   	i2s_in_clk = of_clk_get_parent_name(np, 1);
>>   
>> diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h
>> index 4d523b0..58d8b51 100644
>> --- a/include/dt-bindings/clock/stm32fx-clock.h
>> +++ b/include/dt-bindings/clock/stm32fx-clock.h
>> @@ -35,8 +35,9 @@
>>   #define CLK_SAIQ_PDIV		13
>>   #define CLK_HSI			14
>>   #define CLK_SYSCLK		15
>> +#define CLK_F469_DSI		16
>>   
>> -#define END_PRIMARY_CLK		16
>> +#define END_PRIMARY_CLK		17
>>   
>>   #define CLK_HDMI_CEC		16
>>   #define CLK_SPDIF		17
> This looks suspicious. What's the relationship of these clocks?
I have just added CLK_F469_DSI in the binding, and shifted the end of 
primary clock for F4 clocks.

'CLK_F469_DSI' binding is only used for STM32F469 and not for STM32F746 
(that why CLK_HDMI_CEC can use the index 16)


BR

Gabriel.
>
> Rob