* [U-Boot] [PATCH v8 0/2] DW SPI: Get clock value from Device Tree
@ 2017-12-28 12:09 Eugeniy Paltsev
2017-12-28 12:09 ` [U-Boot] [PATCH v8 1/2] SOCFPGA: clock manager: implement dw_spi_get_clk function Eugeniy Paltsev
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Eugeniy Paltsev @ 2017-12-28 12:09 UTC (permalink / raw)
To: u-boot
As discussed with Marek during the LINUX-PITER here is v* patch:
Add option to set spi controller clock frequency via device tree
using standard clock bindings.
Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.
Get rid of clock_manager.h include in designware_spi.c as we don't use
cm_get_spi_controller_clk_hz function anymore - we use redefined
dw_spi_get_clk in SOCFPGA clock managers (clock_manager_gen5.c and
clock_manager_arria10.c) instead.
Changes v7->v8:
* Fix typo in comments.
Changes v6->v7:
* Cleanup error handling.
* Don't free clock after we successfully requeste it.
Changes v5->v6:
* Put the clock handle into the private data
Changes v4->v5:
* Get rid of usless ifdef in dw_spi_get_clk function
Eugeniy Paltsev (2):
SOCFPGA: clock manager: implement dw_spi_get_clk function
DW SPI: Get clock value from Device Tree
arch/arm/mach-socfpga/clock_manager_arria10.c | 9 +++++
arch/arm/mach-socfpga/clock_manager_gen5.c | 9 +++++
drivers/spi/designware_spi.c | 47 +++++++++++++++++++++++++--
3 files changed, 63 insertions(+), 2 deletions(-)
--
2.9.3
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v8 1/2] SOCFPGA: clock manager: implement dw_spi_get_clk function
2017-12-28 12:09 [U-Boot] [PATCH v8 0/2] DW SPI: Get clock value from Device Tree Eugeniy Paltsev
@ 2017-12-28 12:09 ` Eugeniy Paltsev
2017-12-28 12:09 ` [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree Eugeniy Paltsev
2017-12-28 12:18 ` [U-Boot] [PATCH v8 0/2] " Marek Vasut
2 siblings, 0 replies; 9+ messages in thread
From: Eugeniy Paltsev @ 2017-12-28 12:09 UTC (permalink / raw)
To: u-boot
Implement dw_spi_get_clk function to override its weak
implementation in designware_spi.c driver.
We need this change to get rid of cm_get_spi_controller_clk_hz
function and clock_manager.h include in designware_spi.c driver.
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
arch/arm/mach-socfpga/clock_manager_arria10.c | 9 +++++++++
arch/arm/mach-socfpga/clock_manager_gen5.c | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 482b854..623a266 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
+#include <dm.h>
#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -1076,6 +1077,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
}
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ *rate = cm_get_spi_controller_clk_hz();
+
+ return 0;
+}
+
void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 31fd510..a371d83 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/io.h>
+#include <dm.h>
#include <asm/arch/clock_manager.h>
#include <wait_bit.h>
@@ -509,6 +510,14 @@ unsigned int cm_get_spi_controller_clk_hz(void)
return clock;
}
+/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ *rate = cm_get_spi_controller_clk_hz();
+
+ return 0;
+}
+
void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
--
2.9.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree
2017-12-28 12:09 [U-Boot] [PATCH v8 0/2] DW SPI: Get clock value from Device Tree Eugeniy Paltsev
2017-12-28 12:09 ` [U-Boot] [PATCH v8 1/2] SOCFPGA: clock manager: implement dw_spi_get_clk function Eugeniy Paltsev
@ 2017-12-28 12:09 ` Eugeniy Paltsev
2018-01-19 13:17 ` Eugeniy Paltsev
2017-12-28 12:18 ` [U-Boot] [PATCH v8 0/2] " Marek Vasut
2 siblings, 1 reply; 9+ messages in thread
From: Eugeniy Paltsev @ 2017-12-28 12:09 UTC (permalink / raw)
To: u-boot
Add option to set spi controller clock frequency via device tree
using standard clock bindings.
Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.
Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
drivers/spi/designware_spi.c | 45 ++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 5aa507b..c501aee 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -11,6 +11,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
@@ -18,7 +19,6 @@
#include <fdtdec.h>
#include <linux/compat.h>
#include <asm/io.h>
-#include <asm/arch/clock_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -94,6 +94,8 @@ struct dw_spi_priv {
void __iomem *regs;
unsigned int freq; /* Default frequency */
unsigned int mode;
+ struct clk clk;
+ unsigned long bus_clk_rate;
int bits_per_word;
u8 cs; /* chip select pin */
@@ -176,14 +178,53 @@ static void spi_hw_init(struct dw_spi_priv *priv)
debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
}
+/*
+ * We define dw_spi_get_clk function as 'weak' as some targets
+ * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
+ * and implement dw_spi_get_clk their own way in their clock manager.
+ */
+__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ ret = clk_get_by_index(bus, 0, &priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_enable(&priv->clk);
+ if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
+ return ret;
+
+ *rate = clk_get_rate(&priv->clk);
+ if (!*rate)
+ goto err_rate;
+
+ debug("%s: get spi controller clk via device tree: %lu Hz\n",
+ __func__, *rate);
+
+ return 0;
+
+err_rate:
+ clk_disable(&priv->clk);
+ clk_free(&priv->clk);
+
+ return -EINVAL;
+}
+
static int dw_spi_probe(struct udevice *bus)
{
struct dw_spi_platdata *plat = dev_get_platdata(bus);
struct dw_spi_priv *priv = dev_get_priv(bus);
+ int ret;
priv->regs = plat->regs;
priv->freq = plat->frequency;
+ ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
+ if (ret)
+ return ret;
+
/* Currently only bits_per_word == 8 supported */
priv->bits_per_word = 8;
@@ -369,7 +410,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
spi_enable_chip(priv, 0);
/* clk_div doesn't support odd number */
- clk_div = cm_get_spi_controller_clk_hz() / speed;
+ clk_div = priv->bus_clk_rate / speed;
clk_div = (clk_div + 1) & 0xfffe;
dw_writel(priv, DW_SPI_BAUDR, clk_div);
--
2.9.3
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v8 0/2] DW SPI: Get clock value from Device Tree
2017-12-28 12:09 [U-Boot] [PATCH v8 0/2] DW SPI: Get clock value from Device Tree Eugeniy Paltsev
2017-12-28 12:09 ` [U-Boot] [PATCH v8 1/2] SOCFPGA: clock manager: implement dw_spi_get_clk function Eugeniy Paltsev
2017-12-28 12:09 ` [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree Eugeniy Paltsev
@ 2017-12-28 12:18 ` Marek Vasut
2 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2017-12-28 12:18 UTC (permalink / raw)
To: u-boot
On 12/28/2017 01:09 PM, Eugeniy Paltsev wrote:
> As discussed with Marek during the LINUX-PITER here is v* patch:
>
> Add option to set spi controller clock frequency via device tree
> using standard clock bindings.
>
> Define dw_spi_get_clk function as 'weak' as some targets
> (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
> and implement dw_spi_get_clk their own way in their clock manager.
>
> Get rid of clock_manager.h include in designware_spi.c as we don't use
> cm_get_spi_controller_clk_hz function anymore - we use redefined
> dw_spi_get_clk in SOCFPGA clock managers (clock_manager_gen5.c and
> clock_manager_arria10.c) instead.
>
> Changes v7->v8:
> * Fix typo in comments.
>
> Changes v6->v7:
> * Cleanup error handling.
> * Don't free clock after we successfully requeste it.
>
> Changes v5->v6:
> * Put the clock handle into the private data
>
> Changes v4->v5:
> * Get rid of usless ifdef in dw_spi_get_clk function
>
> Eugeniy Paltsev (2):
> SOCFPGA: clock manager: implement dw_spi_get_clk function
> DW SPI: Get clock value from Device Tree
>
> arch/arm/mach-socfpga/clock_manager_arria10.c | 9 +++++
> arch/arm/mach-socfpga/clock_manager_gen5.c | 9 +++++
> drivers/spi/designware_spi.c | 47 +++++++++++++++++++++++++--
> 3 files changed, 63 insertions(+), 2 deletions(-)
>
Thanks for keeping it up ! And I hope this ends up in after 2018.01 :-)
Please keep an eye on these patches and poke in case these patches
aren't in after 2018.01 is out ...
btw it was nice talking during Piter, I hope to come back next year too!
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree
2017-12-28 12:09 ` [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree Eugeniy Paltsev
@ 2018-01-19 13:17 ` Eugeniy Paltsev
2018-01-25 12:45 ` Alexey Brodkin
0 siblings, 1 reply; 9+ messages in thread
From: Eugeniy Paltsev @ 2018-01-19 13:17 UTC (permalink / raw)
To: u-boot
Hi Jagan,
Could you please pull these patches to your tree?
It would be really nice to see this patch in the nearest release.
Thanks.
On Thu, 2017-12-28 at 15:09 +0300, Eugeniy Paltsev wrote:
> Add option to set spi controller clock frequency via device tree
> using standard clock bindings.
>
> Define dw_spi_get_clk function as 'weak' as some targets
> (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
> and implement dw_spi_get_clk their own way in their clock manager.
>
> Get rid of clock_manager.h include as we don't use
> cm_get_spi_controller_clk_hz function anymore. (we use redefined
> dw_spi_get_clk in SOCFPGA clock managers instead)
>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> ---
> drivers/spi/designware_spi.c | 45 ++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 43 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> index 5aa507b..c501aee 100644
> --- a/drivers/spi/designware_spi.c
> +++ b/drivers/spi/designware_spi.c
> @@ -11,6 +11,7 @@
> */
>
> #include <common.h>
> +#include <clk.h>
> #include <dm.h>
> #include <errno.h>
> #include <malloc.h>
> @@ -18,7 +19,6 @@
> #include <fdtdec.h>
> #include <linux/compat.h>
> #include <asm/io.h>
> -#include <asm/arch/clock_manager.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -94,6 +94,8 @@ struct dw_spi_priv {
> void __iomem *regs;
> unsigned int freq; /* Default frequency */
> unsigned int mode;
> + struct clk clk;
> + unsigned long bus_clk_rate;
>
> int bits_per_word;
> u8 cs; /* chip select pin */
> @@ -176,14 +178,53 @@ static void spi_hw_init(struct dw_spi_priv *priv)
> debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
> }
>
> +/*
> + * We define dw_spi_get_clk function as 'weak' as some targets
> + * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
> + * and implement dw_spi_get_clk their own way in their clock manager.
> + */
> +__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
> +{
> + struct dw_spi_priv *priv = dev_get_priv(bus);
> + int ret;
> +
> + ret = clk_get_by_index(bus, 0, &priv->clk);
> + if (ret)
> + return ret;
> +
> + ret = clk_enable(&priv->clk);
> + if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
> + return ret;
> +
> + *rate = clk_get_rate(&priv->clk);
> + if (!*rate)
> + goto err_rate;
> +
> + debug("%s: get spi controller clk via device tree: %lu Hz\n",
> + __func__, *rate);
> +
> + return 0;
> +
> +err_rate:
> + clk_disable(&priv->clk);
> + clk_free(&priv->clk);
> +
> + return -EINVAL;
> +}
> +
> static int dw_spi_probe(struct udevice *bus)
> {
> struct dw_spi_platdata *plat = dev_get_platdata(bus);
> struct dw_spi_priv *priv = dev_get_priv(bus);
> + int ret;
>
> priv->regs = plat->regs;
> priv->freq = plat->frequency;
>
> + ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
> + if (ret)
> + return ret;
> +
> /* Currently only bits_per_word == 8 supported */
> priv->bits_per_word = 8;
>
> @@ -369,7 +410,7 @@ static int dw_spi_set_speed(struct udevice *bus, uint speed)
> spi_enable_chip(priv, 0);
>
> /* clk_div doesn't support odd number */
> - clk_div = cm_get_spi_controller_clk_hz() / speed;
> + clk_div = priv->bus_clk_rate / speed;
> clk_div = (clk_div + 1) & 0xfffe;
> dw_writel(priv, DW_SPI_BAUDR, clk_div);
>
--
Eugeniy Paltsev
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree
2018-01-19 13:17 ` Eugeniy Paltsev
@ 2018-01-25 12:45 ` Alexey Brodkin
2018-01-25 13:07 ` Jagan Teki
0 siblings, 1 reply; 9+ messages in thread
From: Alexey Brodkin @ 2018-01-25 12:45 UTC (permalink / raw)
To: u-boot
Hi Jagan,
On Fri, 2018-01-19 at 14:17 +0100, Eugeniy Paltsev wrote:
> Hi Jagan,
>
> Could you please pull these patches to your tree?
> It would be really nice to see this patch in the nearest release.
>
> Thanks.
>
> On Thu, 2017-12-28 at 15:09 +0300, Eugeniy Paltsev wrote:
> > Add option to set spi controller clock frequency via device tree
> > using standard clock bindings.
> >
> > Define dw_spi_get_clk function as 'weak' as some targets
> > (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
> > and implement dw_spi_get_clk their own way in their clock manager.
> >
> > Get rid of clock_manager.h include as we don't use
> > cm_get_spi_controller_clk_hz function anymore. (we use redefined
> > dw_spi_get_clk in SOCFPGA clock managers instead)
> >
> > Reviewed-by: Marek Vasut <marex@denx.de>
> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > ---
Any chance for this one to be applied sometime soon?
Note this is a prerequisite for our further work and it's been floating
and discussed on the mailing list for a couple of months now,
that said we'd really like to get this as a part of U-Boot 2018.03.
-Alexey
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree
2018-01-25 12:45 ` Alexey Brodkin
@ 2018-01-25 13:07 ` Jagan Teki
2018-01-25 16:31 ` Tom Rini
0 siblings, 1 reply; 9+ messages in thread
From: Jagan Teki @ 2018-01-25 13:07 UTC (permalink / raw)
To: u-boot
On Thu, Jan 25, 2018 at 6:15 PM, Alexey Brodkin
<Alexey.Brodkin@synopsys.com> wrote:
> Hi Jagan,
>
> On Fri, 2018-01-19 at 14:17 +0100, Eugeniy Paltsev wrote:
>> Hi Jagan,
>>
>> Could you please pull these patches to your tree?
>> It would be really nice to see this patch in the nearest release.
>>
>> Thanks.
>>
>> On Thu, 2017-12-28 at 15:09 +0300, Eugeniy Paltsev wrote:
>> > Add option to set spi controller clock frequency via device tree
>> > using standard clock bindings.
>> >
>> > Define dw_spi_get_clk function as 'weak' as some targets
>> > (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
>> > and implement dw_spi_get_clk their own way in their clock manager.
>> >
>> > Get rid of clock_manager.h include as we don't use
>> > cm_get_spi_controller_clk_hz function anymore. (we use redefined
>> > dw_spi_get_clk in SOCFPGA clock managers instead)
>> >
>> > Reviewed-by: Marek Vasut <marex@denx.de>
>> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
>> > ---
>
> Any chance for this one to be applied sometime soon?
> Note this is a prerequisite for our further work and it's been floating
> and discussed on the mailing list for a couple of months now,
> that said we'd really like to get this as a part of U-Boot 2018.03.
Since delegate has marked to 'marek' it wasn't showed with me, yes
will take this.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree
2018-01-25 13:07 ` Jagan Teki
@ 2018-01-25 16:31 ` Tom Rini
2018-01-26 5:57 ` Jagan Teki
0 siblings, 1 reply; 9+ messages in thread
From: Tom Rini @ 2018-01-25 16:31 UTC (permalink / raw)
To: u-boot
On Thu, Jan 25, 2018 at 06:37:20PM +0530, Jagan Teki wrote:
> On Thu, Jan 25, 2018 at 6:15 PM, Alexey Brodkin
> <Alexey.Brodkin@synopsys.com> wrote:
> > Hi Jagan,
> >
> > On Fri, 2018-01-19 at 14:17 +0100, Eugeniy Paltsev wrote:
> >> Hi Jagan,
> >>
> >> Could you please pull these patches to your tree?
> >> It would be really nice to see this patch in the nearest release.
> >>
> >> Thanks.
> >>
> >> On Thu, 2017-12-28 at 15:09 +0300, Eugeniy Paltsev wrote:
> >> > Add option to set spi controller clock frequency via device tree
> >> > using standard clock bindings.
> >> >
> >> > Define dw_spi_get_clk function as 'weak' as some targets
> >> > (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
> >> > and implement dw_spi_get_clk their own way in their clock manager.
> >> >
> >> > Get rid of clock_manager.h include as we don't use
> >> > cm_get_spi_controller_clk_hz function anymore. (we use redefined
> >> > dw_spi_get_clk in SOCFPGA clock managers instead)
> >> >
> >> > Reviewed-by: Marek Vasut <marex@denx.de>
> >> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> >> > ---
> >
> > Any chance for this one to be applied sometime soon?
> > Note this is a prerequisite for our further work and it's been floating
> > and discussed on the mailing list for a couple of months now,
> > that said we'd really like to get this as a part of U-Boot 2018.03.
>
> Since delegate has marked to 'marek' it wasn't showed with me, yes
> will take this.
As always, oops, my bad. I think I saw Marek commenting at one point
and kept delegating to him. And I missed that it now has his
Reviewed-by, so yes, please pick this up in patchwork, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree
2018-01-25 16:31 ` Tom Rini
@ 2018-01-26 5:57 ` Jagan Teki
0 siblings, 0 replies; 9+ messages in thread
From: Jagan Teki @ 2018-01-26 5:57 UTC (permalink / raw)
To: u-boot
On Thu, Jan 25, 2018 at 10:01 PM, Tom Rini <trini@konsulko.com> wrote:
> On Thu, Jan 25, 2018 at 06:37:20PM +0530, Jagan Teki wrote:
>> On Thu, Jan 25, 2018 at 6:15 PM, Alexey Brodkin
>> <Alexey.Brodkin@synopsys.com> wrote:
>> > Hi Jagan,
>> >
>> > On Fri, 2018-01-19 at 14:17 +0100, Eugeniy Paltsev wrote:
>> >> Hi Jagan,
>> >>
>> >> Could you please pull these patches to your tree?
>> >> It would be really nice to see this patch in the nearest release.
>> >>
>> >> Thanks.
>> >>
>> >> On Thu, 2017-12-28 at 15:09 +0300, Eugeniy Paltsev wrote:
>> >> > Add option to set spi controller clock frequency via device tree
>> >> > using standard clock bindings.
>> >> >
>> >> > Define dw_spi_get_clk function as 'weak' as some targets
>> >> > (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
>> >> > and implement dw_spi_get_clk their own way in their clock manager.
>> >> >
>> >> > Get rid of clock_manager.h include as we don't use
>> >> > cm_get_spi_controller_clk_hz function anymore. (we use redefined
>> >> > dw_spi_get_clk in SOCFPGA clock managers instead)
>> >> >
>> >> > Reviewed-by: Marek Vasut <marex@denx.de>
>> >> > Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
>> >> > ---
>> >
>> > Any chance for this one to be applied sometime soon?
>> > Note this is a prerequisite for our further work and it's been floating
>> > and discussed on the mailing list for a couple of months now,
>> > that said we'd really like to get this as a part of U-Boot 2018.03.
>>
>> Since delegate has marked to 'marek' it wasn't showed with me, yes
>> will take this.
>
> As always, oops, my bad. I think I saw Marek commenting at one point
> and kept delegating to him. And I missed that it now has his
> Reviewed-by, so yes, please pick this up in patchwork, thanks!
Applied to u-boot-spi/master, thanks!
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-01-26 5:57 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-28 12:09 [U-Boot] [PATCH v8 0/2] DW SPI: Get clock value from Device Tree Eugeniy Paltsev
2017-12-28 12:09 ` [U-Boot] [PATCH v8 1/2] SOCFPGA: clock manager: implement dw_spi_get_clk function Eugeniy Paltsev
2017-12-28 12:09 ` [U-Boot] [PATCH v8 2/2] DW SPI: Get clock value from Device Tree Eugeniy Paltsev
2018-01-19 13:17 ` Eugeniy Paltsev
2018-01-25 12:45 ` Alexey Brodkin
2018-01-25 13:07 ` Jagan Teki
2018-01-25 16:31 ` Tom Rini
2018-01-26 5:57 ` Jagan Teki
2017-12-28 12:18 ` [U-Boot] [PATCH v8 0/2] " Marek Vasut
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