* [PATCH v3 1/2] i386: Add Intel Processor Trace feature support
@ 2018-01-31 15:57 ` Luwei Kang
0 siblings, 0 replies; 8+ messages in thread
From: Luwei Kang @ 2018-01-31 15:57 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: pbonzini, rth, ehabkost, mtosatti, Chao Peng, Luwei Kang
From: Chao Peng <chao.p.peng@linux.intel.com>
Expose Intel Processor Trace feature to guest.
To make Intel PT live migration safe and get same CPUID information
with same CPU model on diffrent host. CPUID[14] is constant in this
patch. Intel PT use EPT is first supported in IceLake, the CPUID[14]
get on this machine as default value. Intel PT would be disabled
If any machine don't support this minial feature list.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
target/i386/cpu.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++--
target/i386/cpu.h | 1 +
target/i386/kvm.c | 23 +++++++++++++++++++++++
3 files changed, 75 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a49d222..aaa427a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -172,7 +172,14 @@
#define L2_ITLB_4K_ASSOC 4
#define L2_ITLB_4K_ENTRIES 512
-
+/* CPUID Leaf 0x14 constants: */
+#define INTLE_PT_MAX_SUBLEAF 0x1
+#define INTEL_PT_MINIMAL_EBX 0xf
+#define INTEL_PT_MINIMAL_ECX 0x7
+#define INTLE_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
+#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
+#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
+#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
uint32_t vendor2, uint32_t vendor3)
@@ -427,7 +434,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, "mpx", NULL,
"avx512f", "avx512dq", "rdseed", "adx",
"smap", "avx512ifma", "pcommit", "clflushopt",
- "clwb", NULL, "avx512pf", "avx512er",
+ "clwb", "intel-pt", "avx512pf", "avx512er",
"avx512cd", "sha-ni", "avx512bw", "avx512vl",
},
.cpuid_eax = 7,
@@ -3452,6 +3459,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
}
break;
}
+ case 0x14: {
+ /* Intel Processor Trace Enumeration */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
+ !kvm_enabled()) {
+ break;
+ }
+
+ if (count == 0) {
+ *eax = INTLE_PT_MAX_SUBLEAF;
+ *ebx = INTEL_PT_MINIMAL_EBX;
+ *ecx = INTEL_PT_MINIMAL_ECX;
+ } else if (count == 1) {
+ *eax = INTEL_PT_MTC_BITMAP | INTLE_PT_ADDR_RANGES_NUM;
+ *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
+ }
+ break;
+ }
case 0x40000000:
/*
* CPUID code in kvm_arch_init_vcpu() ignores stuff
@@ -4082,6 +4110,27 @@ static int x86_cpu_filter_features(X86CPU *cpu)
}
}
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
+ KVMState *s = CPU(cpu)->kvm_state;
+ uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
+ uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
+ uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
+ uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
+ uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
+
+ if (!eax_0 ||
+ ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
+ ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
+ ((eax_1 & (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) !=
+ (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) ||
+ ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
+ (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) {
+ env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
+ cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
+ rv = 1;
+ }
+ }
+
return rv;
}
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f91e37d..7facc8b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -644,6 +644,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
+#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index ad4b159..f9f4cd1 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -865,6 +865,29 @@ int kvm_arch_init_vcpu(CPUState *cs)
c = &cpuid_data.entries[cpuid_i++];
}
break;
+ case 0x14: {
+ uint32_t times;
+
+ c->function = i;
+ c->index = 0;
+ c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+ cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
+ times = c->eax;
+
+ for (j = 1; j <= times; ++j) {
+ if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
+ fprintf(stderr, "cpuid_data is full, no space for "
+ "cpuid(eax:0x14,ecx:0x%x)\n", j);
+ abort();
+ }
+ c = &cpuid_data.entries[cpuid_i++];
+ c->function = i;
+ c->index = j;
+ c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+ cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
+ }
+ break;
+ }
default:
c->function = i;
c->flags = 0;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH v3 1/2] i386: Add Intel Processor Trace feature support
@ 2018-01-31 15:57 ` Luwei Kang
0 siblings, 0 replies; 8+ messages in thread
From: Luwei Kang @ 2018-01-31 15:57 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: pbonzini, rth, ehabkost, mtosatti, Chao Peng, Luwei Kang
From: Chao Peng <chao.p.peng@linux.intel.com>
Expose Intel Processor Trace feature to guest.
To make Intel PT live migration safe and get same CPUID information
with same CPU model on diffrent host. CPUID[14] is constant in this
patch. Intel PT use EPT is first supported in IceLake, the CPUID[14]
get on this machine as default value. Intel PT would be disabled
If any machine don't support this minial feature list.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
target/i386/cpu.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++--
target/i386/cpu.h | 1 +
target/i386/kvm.c | 23 +++++++++++++++++++++++
3 files changed, 75 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a49d222..aaa427a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -172,7 +172,14 @@
#define L2_ITLB_4K_ASSOC 4
#define L2_ITLB_4K_ENTRIES 512
-
+/* CPUID Leaf 0x14 constants: */
+#define INTLE_PT_MAX_SUBLEAF 0x1
+#define INTEL_PT_MINIMAL_EBX 0xf
+#define INTEL_PT_MINIMAL_ECX 0x7
+#define INTLE_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
+#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
+#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
+#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
uint32_t vendor2, uint32_t vendor3)
@@ -427,7 +434,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
NULL, NULL, "mpx", NULL,
"avx512f", "avx512dq", "rdseed", "adx",
"smap", "avx512ifma", "pcommit", "clflushopt",
- "clwb", NULL, "avx512pf", "avx512er",
+ "clwb", "intel-pt", "avx512pf", "avx512er",
"avx512cd", "sha-ni", "avx512bw", "avx512vl",
},
.cpuid_eax = 7,
@@ -3452,6 +3459,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
}
break;
}
+ case 0x14: {
+ /* Intel Processor Trace Enumeration */
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = 0;
+ if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
+ !kvm_enabled()) {
+ break;
+ }
+
+ if (count == 0) {
+ *eax = INTLE_PT_MAX_SUBLEAF;
+ *ebx = INTEL_PT_MINIMAL_EBX;
+ *ecx = INTEL_PT_MINIMAL_ECX;
+ } else if (count == 1) {
+ *eax = INTEL_PT_MTC_BITMAP | INTLE_PT_ADDR_RANGES_NUM;
+ *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
+ }
+ break;
+ }
case 0x40000000:
/*
* CPUID code in kvm_arch_init_vcpu() ignores stuff
@@ -4082,6 +4110,27 @@ static int x86_cpu_filter_features(X86CPU *cpu)
}
}
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
+ KVMState *s = CPU(cpu)->kvm_state;
+ uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
+ uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
+ uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
+ uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
+ uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
+
+ if (!eax_0 ||
+ ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
+ ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
+ ((eax_1 & (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) !=
+ (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) ||
+ ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
+ (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) {
+ env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
+ cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
+ rv = 1;
+ }
+ }
+
return rv;
}
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index f91e37d..7facc8b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -644,6 +644,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
+#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index ad4b159..f9f4cd1 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -865,6 +865,29 @@ int kvm_arch_init_vcpu(CPUState *cs)
c = &cpuid_data.entries[cpuid_i++];
}
break;
+ case 0x14: {
+ uint32_t times;
+
+ c->function = i;
+ c->index = 0;
+ c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+ cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
+ times = c->eax;
+
+ for (j = 1; j <= times; ++j) {
+ if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
+ fprintf(stderr, "cpuid_data is full, no space for "
+ "cpuid(eax:0x14,ecx:0x%x)\n", j);
+ abort();
+ }
+ c = &cpuid_data.entries[cpuid_i++];
+ c->function = i;
+ c->index = j;
+ c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
+ cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
+ }
+ break;
+ }
default:
c->function = i;
c->flags = 0;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] i386: Add support to get/set/migrate Intel Processor Trace feature
2018-01-31 15:57 ` [Qemu-devel] " Luwei Kang
@ 2018-01-31 15:57 ` Luwei Kang
-1 siblings, 0 replies; 8+ messages in thread
From: Luwei Kang @ 2018-01-31 15:57 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: pbonzini, rth, ehabkost, mtosatti, Chao Peng, Luwei Kang
From: Chao Peng <chao.p.peng@linux.intel.com>
Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
target/i386/cpu.h | 22 ++++++++++++++++++++++
target/i386/kvm.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
target/i386/machine.c | 38 ++++++++++++++++++++++++++++++++++++++
3 files changed, 111 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7facc8b..164d17f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -419,6 +419,21 @@ typedef enum X86Seg {
#define MSR_MC0_ADDR 0x402
#define MSR_MC0_MISC 0x403
+#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
+#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
+#define MSR_IA32_RTIT_CTL 0x570
+#define MSR_IA32_RTIT_STATUS 0x571
+#define MSR_IA32_RTIT_CR3_MATCH 0x572
+#define MSR_IA32_RTIT_ADDR0_A 0x580
+#define MSR_IA32_RTIT_ADDR0_B 0x581
+#define MSR_IA32_RTIT_ADDR1_A 0x582
+#define MSR_IA32_RTIT_ADDR1_B 0x583
+#define MSR_IA32_RTIT_ADDR2_A 0x584
+#define MSR_IA32_RTIT_ADDR2_B 0x585
+#define MSR_IA32_RTIT_ADDR3_A 0x586
+#define MSR_IA32_RTIT_ADDR3_B 0x587
+#define MAX_RTIT_ADDRS 8
+
#define MSR_EFER 0xc0000080
#define MSR_EFER_SCE (1 << 0)
@@ -1158,6 +1173,13 @@ typedef struct CPUX86State {
uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
+ uint64_t msr_rtit_ctrl;
+ uint64_t msr_rtit_status;
+ uint64_t msr_rtit_output_base;
+ uint64_t msr_rtit_output_mask;
+ uint64_t msr_rtit_cr3_match;
+ uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
+
/* exception/interrupt handling */
int error_code;
int exception_is_int;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index f9f4cd1..097c953 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1811,6 +1811,25 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
}
}
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
+ int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
+ 0x14, 1, R_EAX) & 0x7;
+
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
+ env->msr_rtit_ctrl);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
+ env->msr_rtit_status);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
+ env->msr_rtit_output_base);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
+ env->msr_rtit_output_mask);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
+ env->msr_rtit_cr3_match);
+ for (i = 0; i < addr_num; i++) {
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
+ env->msr_rtit_addrs[i]);
+ }
+ }
/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
* kvm_put_msr_feature_control. */
@@ -2124,6 +2143,20 @@ static int kvm_get_msrs(X86CPU *cpu)
}
}
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
+ int addr_num =
+ kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
+
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
+ for (i = 0; i < addr_num; i++) {
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
+ }
+ }
+
ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
if (ret < 0) {
return ret;
@@ -2364,6 +2397,24 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_SPEC_CTRL:
env->spec_ctrl = msrs[i].data;
break;
+ case MSR_IA32_RTIT_CTL:
+ env->msr_rtit_ctrl = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_STATUS:
+ env->msr_rtit_status = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_OUTPUT_BASE:
+ env->msr_rtit_output_base = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_OUTPUT_MASK:
+ env->msr_rtit_output_mask = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_CR3_MATCH:
+ env->msr_rtit_cr3_match = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
+ env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
+ break;
}
}
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 361c05a..c05fe6f 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -837,6 +837,43 @@ static const VMStateDescription vmstate_spec_ctrl = {
}
};
+static bool intel_pt_enable_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+ int i;
+
+ if (env->msr_rtit_ctrl || env->msr_rtit_status ||
+ env->msr_rtit_output_base || env->msr_rtit_output_mask ||
+ env->msr_rtit_cr3_match) {
+ return true;
+ }
+
+ for (i = 0; i < MAX_RTIT_ADDRS; i++) {
+ if (env->msr_rtit_addrs[i]) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static const VMStateDescription vmstate_msr_intel_pt = {
+ .name = "cpu/intel_pt",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = intel_pt_enable_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.msr_rtit_ctrl, X86CPU),
+ VMSTATE_UINT64(env.msr_rtit_status, X86CPU),
+ VMSTATE_UINT64(env.msr_rtit_output_base, X86CPU),
+ VMSTATE_UINT64(env.msr_rtit_output_mask, X86CPU),
+ VMSTATE_UINT64(env.msr_rtit_cr3_match, X86CPU),
+ VMSTATE_UINT64_ARRAY(env.msr_rtit_addrs, X86CPU, MAX_RTIT_ADDRS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -957,6 +994,7 @@ VMStateDescription vmstate_x86_cpu = {
#endif
&vmstate_spec_ctrl,
&vmstate_mcg_ext_ctl,
+ &vmstate_msr_intel_pt,
NULL
}
};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH v3 2/2] i386: Add support to get/set/migrate Intel Processor Trace feature
@ 2018-01-31 15:57 ` Luwei Kang
0 siblings, 0 replies; 8+ messages in thread
From: Luwei Kang @ 2018-01-31 15:57 UTC (permalink / raw)
To: qemu-devel, kvm; +Cc: pbonzini, rth, ehabkost, mtosatti, Chao Peng, Luwei Kang
From: Chao Peng <chao.p.peng@linux.intel.com>
Add Intel Processor Trace related definition. It also add
corresponding part to kvm_get/set_msr and vmstate.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
target/i386/cpu.h | 22 ++++++++++++++++++++++
target/i386/kvm.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
target/i386/machine.c | 38 ++++++++++++++++++++++++++++++++++++++
3 files changed, 111 insertions(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7facc8b..164d17f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -419,6 +419,21 @@ typedef enum X86Seg {
#define MSR_MC0_ADDR 0x402
#define MSR_MC0_MISC 0x403
+#define MSR_IA32_RTIT_OUTPUT_BASE 0x560
+#define MSR_IA32_RTIT_OUTPUT_MASK 0x561
+#define MSR_IA32_RTIT_CTL 0x570
+#define MSR_IA32_RTIT_STATUS 0x571
+#define MSR_IA32_RTIT_CR3_MATCH 0x572
+#define MSR_IA32_RTIT_ADDR0_A 0x580
+#define MSR_IA32_RTIT_ADDR0_B 0x581
+#define MSR_IA32_RTIT_ADDR1_A 0x582
+#define MSR_IA32_RTIT_ADDR1_B 0x583
+#define MSR_IA32_RTIT_ADDR2_A 0x584
+#define MSR_IA32_RTIT_ADDR2_B 0x585
+#define MSR_IA32_RTIT_ADDR3_A 0x586
+#define MSR_IA32_RTIT_ADDR3_B 0x587
+#define MAX_RTIT_ADDRS 8
+
#define MSR_EFER 0xc0000080
#define MSR_EFER_SCE (1 << 0)
@@ -1158,6 +1173,13 @@ typedef struct CPUX86State {
uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
+ uint64_t msr_rtit_ctrl;
+ uint64_t msr_rtit_status;
+ uint64_t msr_rtit_output_base;
+ uint64_t msr_rtit_output_mask;
+ uint64_t msr_rtit_cr3_match;
+ uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
+
/* exception/interrupt handling */
int error_code;
int exception_is_int;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index f9f4cd1..097c953 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -1811,6 +1811,25 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
}
}
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
+ int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
+ 0x14, 1, R_EAX) & 0x7;
+
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
+ env->msr_rtit_ctrl);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
+ env->msr_rtit_status);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
+ env->msr_rtit_output_base);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
+ env->msr_rtit_output_mask);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
+ env->msr_rtit_cr3_match);
+ for (i = 0; i < addr_num; i++) {
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
+ env->msr_rtit_addrs[i]);
+ }
+ }
/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
* kvm_put_msr_feature_control. */
@@ -2124,6 +2143,20 @@ static int kvm_get_msrs(X86CPU *cpu)
}
}
+ if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
+ int addr_num =
+ kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
+
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
+ for (i = 0; i < addr_num; i++) {
+ kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
+ }
+ }
+
ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
if (ret < 0) {
return ret;
@@ -2364,6 +2397,24 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_SPEC_CTRL:
env->spec_ctrl = msrs[i].data;
break;
+ case MSR_IA32_RTIT_CTL:
+ env->msr_rtit_ctrl = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_STATUS:
+ env->msr_rtit_status = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_OUTPUT_BASE:
+ env->msr_rtit_output_base = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_OUTPUT_MASK:
+ env->msr_rtit_output_mask = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_CR3_MATCH:
+ env->msr_rtit_cr3_match = msrs[i].data;
+ break;
+ case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
+ env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
+ break;
}
}
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 361c05a..c05fe6f 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -837,6 +837,43 @@ static const VMStateDescription vmstate_spec_ctrl = {
}
};
+static bool intel_pt_enable_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+ int i;
+
+ if (env->msr_rtit_ctrl || env->msr_rtit_status ||
+ env->msr_rtit_output_base || env->msr_rtit_output_mask ||
+ env->msr_rtit_cr3_match) {
+ return true;
+ }
+
+ for (i = 0; i < MAX_RTIT_ADDRS; i++) {
+ if (env->msr_rtit_addrs[i]) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static const VMStateDescription vmstate_msr_intel_pt = {
+ .name = "cpu/intel_pt",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = intel_pt_enable_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(env.msr_rtit_ctrl, X86CPU),
+ VMSTATE_UINT64(env.msr_rtit_status, X86CPU),
+ VMSTATE_UINT64(env.msr_rtit_output_base, X86CPU),
+ VMSTATE_UINT64(env.msr_rtit_output_mask, X86CPU),
+ VMSTATE_UINT64(env.msr_rtit_cr3_match, X86CPU),
+ VMSTATE_UINT64_ARRAY(env.msr_rtit_addrs, X86CPU, MAX_RTIT_ADDRS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -957,6 +994,7 @@ VMStateDescription vmstate_x86_cpu = {
#endif
&vmstate_spec_ctrl,
&vmstate_mcg_ext_ctl,
+ &vmstate_msr_intel_pt,
NULL
}
};
--
1.8.3.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH v3 1/2] i386: Add Intel Processor Trace feature support
2018-01-31 15:57 ` [Qemu-devel] " Luwei Kang
(?)
(?)
@ 2018-02-07 14:53 ` Eduardo Habkost
2018-02-08 1:24 ` Kang, Luwei
-1 siblings, 1 reply; 8+ messages in thread
From: Eduardo Habkost @ 2018-02-07 14:53 UTC (permalink / raw)
To: Luwei Kang; +Cc: qemu-devel, kvm, mtosatti, Chao Peng, pbonzini, rth
On Wed, Jan 31, 2018 at 11:57:45PM +0800, Luwei Kang wrote:
> From: Chao Peng <chao.p.peng@linux.intel.com>
>
> Expose Intel Processor Trace feature to guest.
>
> To make Intel PT live migration safe and get same CPUID information
> with same CPU model on diffrent host. CPUID[14] is constant in this
> patch. Intel PT use EPT is first supported in IceLake, the CPUID[14]
> get on this machine as default value. Intel PT would be disabled
> If any machine don't support this minial feature list.
>
> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> ---
> target/i386/cpu.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++--
> target/i386/cpu.h | 1 +
> target/i386/kvm.c | 23 +++++++++++++++++++++++
> 3 files changed, 75 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index a49d222..aaa427a 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -172,7 +172,14 @@
> #define L2_ITLB_4K_ASSOC 4
> #define L2_ITLB_4K_ENTRIES 512
>
> -
> +/* CPUID Leaf 0x14 constants: */
> +#define INTLE_PT_MAX_SUBLEAF 0x1
Typo.
> +#define INTEL_PT_MINIMAL_EBX 0xf
> +#define INTEL_PT_MINIMAL_ECX 0x7
I suggest documenting what capabilities are included in
INTEL_PT_MINIMAL_* here.
> +#define INTLE_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
Typo.
> +#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
> +#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
> +#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
>
> static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
> uint32_t vendor2, uint32_t vendor3)
> @@ -427,7 +434,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> NULL, NULL, "mpx", NULL,
> "avx512f", "avx512dq", "rdseed", "adx",
> "smap", "avx512ifma", "pcommit", "clflushopt",
> - "clwb", NULL, "avx512pf", "avx512er",
> + "clwb", "intel-pt", "avx512pf", "avx512er",
> "avx512cd", "sha-ni", "avx512bw", "avx512vl",
> },
> .cpuid_eax = 7,
> @@ -3452,6 +3459,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> }
> break;
> }
> + case 0x14: {
> + /* Intel Processor Trace Enumeration */
> + *eax = 0;
> + *ebx = 0;
> + *ecx = 0;
> + *edx = 0;
> + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
> + !kvm_enabled()) {
> + break;
> + }
> +
> + if (count == 0) {
> + *eax = INTLE_PT_MAX_SUBLEAF;
> + *ebx = INTEL_PT_MINIMAL_EBX;
> + *ecx = INTEL_PT_MINIMAL_ECX;
> + } else if (count == 1) {
> + *eax = INTEL_PT_MTC_BITMAP | INTLE_PT_ADDR_RANGES_NUM;
> + *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
> + }
> + break;
> + }
> case 0x40000000:
> /*
> * CPUID code in kvm_arch_init_vcpu() ignores stuff
> @@ -4082,6 +4110,27 @@ static int x86_cpu_filter_features(X86CPU *cpu)
> }
> }
>
> + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
What if the accelerator is not KVM, but is reporting intel-pt as
supported?
> + KVMState *s = CPU(cpu)->kvm_state;
> + uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
> + uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
> + uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
> + uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
> + uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
> +
> + if (!eax_0 ||
OK.
> + ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
How do we know if KVM is going to emulate #GP properly when
setting a bit that is supported by the host CPU but cleared on
the guest CPUID? Do we care?
> + ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
Same comment as above.
Also: bit 31 must match the host, meaning we must reject a host
where ecx_0 & (1 << 31) is set.
> + ((eax_1 & (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) !=
> + (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) ||
This will make the code accept hosts with 3 address ranges
(0b011), but reject ones with 4 address ranges (0b100). This
doesn't sound right to me.
> + ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
> + (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) {
How do we know if KVM is going to emulate #GP properly when
setting an invalid CycThresh or PSBFreq value? Do we care?
> + env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
> + cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
This matches what I have suggested. But I recommend adding a
comment mentioning why we do this. Something like:
/*
* Processor Trace capabilities aren't configurable, so if the
* host can't emulate the capabilities we report on
* cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
*/
> + rv = 1;
> + }
> + }
> +
> return rv;
> }
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index f91e37d..7facc8b 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -644,6 +644,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
> #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
> #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
> +#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
> #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
> #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
> #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
> diff --git a/target/i386/kvm.c b/target/i386/kvm.c
> index ad4b159..f9f4cd1 100644
> --- a/target/i386/kvm.c
> +++ b/target/i386/kvm.c
> @@ -865,6 +865,29 @@ int kvm_arch_init_vcpu(CPUState *cs)
> c = &cpuid_data.entries[cpuid_i++];
> }
> break;
> + case 0x14: {
> + uint32_t times;
> +
> + c->function = i;
> + c->index = 0;
> + c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
> + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
> + times = c->eax;
> +
> + for (j = 1; j <= times; ++j) {
> + if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
> + fprintf(stderr, "cpuid_data is full, no space for "
> + "cpuid(eax:0x14,ecx:0x%x)\n", j);
> + abort();
> + }
> + c = &cpuid_data.entries[cpuid_i++];
> + c->function = i;
> + c->index = j;
> + c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
> + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
> + }
> + break;
> + }
> default:
> c->function = i;
> c->flags = 0;
> --
> 1.8.3.1
>
>
--
Eduardo
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [Qemu-devel] [PATCH v3 1/2] i386: Add Intel Processor Trace feature support
2018-02-07 14:53 ` [Qemu-devel] [PATCH v3 1/2] i386: Add Intel Processor Trace feature support Eduardo Habkost
@ 2018-02-08 1:24 ` Kang, Luwei
0 siblings, 0 replies; 8+ messages in thread
From: Kang, Luwei @ 2018-02-08 1:24 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: qemu-devel, kvm, mtosatti, Chao Peng, pbonzini, rth
> On Wed, Jan 31, 2018 at 11:57:45PM +0800, Luwei Kang wrote:
> > From: Chao Peng <chao.p.peng@linux.intel.com>
> >
> > Expose Intel Processor Trace feature to guest.
> >
> > To make Intel PT live migration safe and get same CPUID information
> > with same CPU model on diffrent host. CPUID[14] is constant in this
> > patch. Intel PT use EPT is first supported in IceLake, the CPUID[14]
> > get on this machine as default value. Intel PT would be disabled If
> > any machine don't support this minial feature list.
> >
> > Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> > Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> > ---
> > target/i386/cpu.c | 53
> > +++++++++++++++++++++++++++++++++++++++++++++++++++--
> > target/i386/cpu.h | 1 +
> > target/i386/kvm.c | 23 +++++++++++++++++++++++
> > 3 files changed, 75 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index
> > a49d222..aaa427a 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -172,7 +172,14 @@
> > #define L2_ITLB_4K_ASSOC 4
> > #define L2_ITLB_4K_ENTRIES 512
> >
> > -
> > +/* CPUID Leaf 0x14 constants: */
> > +#define INTLE_PT_MAX_SUBLEAF 0x1
>
> Typo.
>
> > +#define INTEL_PT_MINIMAL_EBX 0xf
> > +#define INTEL_PT_MINIMAL_ECX 0x7
>
> I suggest documenting what capabilities are included in
> INTEL_PT_MINIMAL_* here.
>
>
> > +#define INTLE_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable
> > +address ranges */
>
> Typo.
>
> > +#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
> > +#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
> > +#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
> >
> > static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
> > uint32_t vendor2, uint32_t
> > vendor3) @@ -427,7 +434,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> > NULL, NULL, "mpx", NULL,
> > "avx512f", "avx512dq", "rdseed", "adx",
> > "smap", "avx512ifma", "pcommit", "clflushopt",
> > - "clwb", NULL, "avx512pf", "avx512er",
> > + "clwb", "intel-pt", "avx512pf", "avx512er",
> > "avx512cd", "sha-ni", "avx512bw", "avx512vl",
> > },
> > .cpuid_eax = 7,
> > @@ -3452,6 +3459,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> > }
> > break;
> > }
> > + case 0x14: {
> > + /* Intel Processor Trace Enumeration */
> > + *eax = 0;
> > + *ebx = 0;
> > + *ecx = 0;
> > + *edx = 0;
> > + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
> > + !kvm_enabled()) {
> > + break;
> > + }
> > +
> > + if (count == 0) {
> > + *eax = INTLE_PT_MAX_SUBLEAF;
> > + *ebx = INTEL_PT_MINIMAL_EBX;
> > + *ecx = INTEL_PT_MINIMAL_ECX;
> > + } else if (count == 1) {
> > + *eax = INTEL_PT_MTC_BITMAP | INTLE_PT_ADDR_RANGES_NUM;
> > + *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
> > + }
> > + break;
> > + }
> > case 0x40000000:
> > /*
> > * CPUID code in kvm_arch_init_vcpu() ignores stuff @@
> > -4082,6 +4110,27 @@ static int x86_cpu_filter_features(X86CPU *cpu)
> > }
> > }
> >
> > + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
>
> What if the accelerator is not KVM, but is reporting intel-pt as supported?
I have add this check in cpu_x86_cpuid() but I think we'd better add kvm_enabled() check here as well.
What is your opinion?
>
> > + KVMState *s = CPU(cpu)->kvm_state;
> > + uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
> > + uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
> > + uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
> > + uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
> > + uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1,
> > + R_EBX);
> > +
> > + if (!eax_0 ||
>
> OK.
>
> > + ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX)
> > + ||
>
> How do we know if KVM is going to emulate #GP properly when setting a bit that is supported by the host CPU but cleared on the
> guest CPUID? Do we care?
I think it need KVM make this check and Qemu don't need aware this.
For example, EBX[0].CR3_filter (IA32_RTIT_CTL.cr3 can't be set if 0) is support by host but we mask off this bit in kvm guest. Qemu will set the CPUID to KVM by ioctl KVM_SET_CPUID2. KVM will trap the behavior when KVM guest want to set IA32_RTIT_CTL.cr3. If we find EBX[0].CR3_filter is not supported a #GP will be emulated. This check will added in KVM patch set V5 and it still working in progress.
>
> > + ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX)
> > + ||
>
> Same comment as above.
>
> Also: bit 31 must match the host, meaning we must reject a host where ecx_0 & (1 << 31) is set.
Get it, will add in next version.
>
>
> > + ((eax_1 & (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) !=
> > + (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) ||
>
> This will make the code accept hosts with 3 address ranges (0b011), but reject ones with 4 address ranges (0b100). This doesn't
> sound right to me.
I see, will fix it.
>
>
> > + ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
> > + (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) {
>
> How do we know if KVM is going to emulate #GP properly when setting an invalid CycThresh or PSBFreq value? Do we care?
It will check in KVM and will emulate a #GP if set an invalid value but I think qemu can't aware this.
>From my point of view, I think qemu don't need to care or get this information.
>
>
> > + env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
> > + cpu->filtered_features[FEAT_7_0_EBX] |=
> > + CPUID_7_0_EBX_INTEL_PT;
>
> This matches what I have suggested. But I recommend adding a comment mentioning why we do this. Something like:
>
> /*
> * Processor Trace capabilities aren't configurable, so if the
> * host can't emulate the capabilities we report on
> * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
> */
Agree.
Thanks a lot for the code review.
Luwei Kang
>
>
> > + rv = 1;
> > + }
> > + }
> > +
> > return rv;
> > }
> >
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h index
> > f91e37d..7facc8b 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -644,6 +644,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> > #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
> > #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
> > #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
> > +#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
> > #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
> > #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and
> > Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512
> > Conflict Detection */ diff --git a/target/i386/kvm.c
> > b/target/i386/kvm.c index ad4b159..f9f4cd1 100644
> > --- a/target/i386/kvm.c
> > +++ b/target/i386/kvm.c
> > @@ -865,6 +865,29 @@ int kvm_arch_init_vcpu(CPUState *cs)
> > c = &cpuid_data.entries[cpuid_i++];
> > }
> > break;
> > + case 0x14: {
> > + uint32_t times;
> > +
> > + c->function = i;
> > + c->index = 0;
> > + c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
> > + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
> > + times = c->eax;
> > +
> > + for (j = 1; j <= times; ++j) {
> > + if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
> > + fprintf(stderr, "cpuid_data is full, no space for "
> > + "cpuid(eax:0x14,ecx:0x%x)\n", j);
> > + abort();
> > + }
> > + c = &cpuid_data.entries[cpuid_i++];
> > + c->function = i;
> > + c->index = j;
> > + c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
> > + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
> > + }
> > + break;
> > + }
> > default:
> > c->function = i;
> > c->flags = 0;
> > --
> > 1.8.3.1
> >
> >
>
> --
> Eduardo
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH v3 1/2] i386: Add Intel Processor Trace feature support
@ 2018-02-08 1:24 ` Kang, Luwei
0 siblings, 0 replies; 8+ messages in thread
From: Kang, Luwei @ 2018-02-08 1:24 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: qemu-devel, kvm, mtosatti, Chao Peng, pbonzini, rth
> On Wed, Jan 31, 2018 at 11:57:45PM +0800, Luwei Kang wrote:
> > From: Chao Peng <chao.p.peng@linux.intel.com>
> >
> > Expose Intel Processor Trace feature to guest.
> >
> > To make Intel PT live migration safe and get same CPUID information
> > with same CPU model on diffrent host. CPUID[14] is constant in this
> > patch. Intel PT use EPT is first supported in IceLake, the CPUID[14]
> > get on this machine as default value. Intel PT would be disabled If
> > any machine don't support this minial feature list.
> >
> > Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> > Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> > ---
> > target/i386/cpu.c | 53
> > +++++++++++++++++++++++++++++++++++++++++++++++++++--
> > target/i386/cpu.h | 1 +
> > target/i386/kvm.c | 23 +++++++++++++++++++++++
> > 3 files changed, 75 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index
> > a49d222..aaa427a 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -172,7 +172,14 @@
> > #define L2_ITLB_4K_ASSOC 4
> > #define L2_ITLB_4K_ENTRIES 512
> >
> > -
> > +/* CPUID Leaf 0x14 constants: */
> > +#define INTLE_PT_MAX_SUBLEAF 0x1
>
> Typo.
>
> > +#define INTEL_PT_MINIMAL_EBX 0xf
> > +#define INTEL_PT_MINIMAL_ECX 0x7
>
> I suggest documenting what capabilities are included in
> INTEL_PT_MINIMAL_* here.
>
>
> > +#define INTLE_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable
> > +address ranges */
>
> Typo.
>
> > +#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
> > +#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
> > +#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
> >
> > static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
> > uint32_t vendor2, uint32_t
> > vendor3) @@ -427,7 +434,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> > NULL, NULL, "mpx", NULL,
> > "avx512f", "avx512dq", "rdseed", "adx",
> > "smap", "avx512ifma", "pcommit", "clflushopt",
> > - "clwb", NULL, "avx512pf", "avx512er",
> > + "clwb", "intel-pt", "avx512pf", "avx512er",
> > "avx512cd", "sha-ni", "avx512bw", "avx512vl",
> > },
> > .cpuid_eax = 7,
> > @@ -3452,6 +3459,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> > }
> > break;
> > }
> > + case 0x14: {
> > + /* Intel Processor Trace Enumeration */
> > + *eax = 0;
> > + *ebx = 0;
> > + *ecx = 0;
> > + *edx = 0;
> > + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
> > + !kvm_enabled()) {
> > + break;
> > + }
> > +
> > + if (count == 0) {
> > + *eax = INTLE_PT_MAX_SUBLEAF;
> > + *ebx = INTEL_PT_MINIMAL_EBX;
> > + *ecx = INTEL_PT_MINIMAL_ECX;
> > + } else if (count == 1) {
> > + *eax = INTEL_PT_MTC_BITMAP | INTLE_PT_ADDR_RANGES_NUM;
> > + *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
> > + }
> > + break;
> > + }
> > case 0x40000000:
> > /*
> > * CPUID code in kvm_arch_init_vcpu() ignores stuff @@
> > -4082,6 +4110,27 @@ static int x86_cpu_filter_features(X86CPU *cpu)
> > }
> > }
> >
> > + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
>
> What if the accelerator is not KVM, but is reporting intel-pt as supported?
I have add this check in cpu_x86_cpuid() but I think we'd better add kvm_enabled() check here as well.
What is your opinion?
>
> > + KVMState *s = CPU(cpu)->kvm_state;
> > + uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
> > + uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
> > + uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
> > + uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
> > + uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1,
> > + R_EBX);
> > +
> > + if (!eax_0 ||
>
> OK.
>
> > + ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX)
> > + ||
>
> How do we know if KVM is going to emulate #GP properly when setting a bit that is supported by the host CPU but cleared on the
> guest CPUID? Do we care?
I think it need KVM make this check and Qemu don't need aware this.
For example, EBX[0].CR3_filter (IA32_RTIT_CTL.cr3 can't be set if 0) is support by host but we mask off this bit in kvm guest. Qemu will set the CPUID to KVM by ioctl KVM_SET_CPUID2. KVM will trap the behavior when KVM guest want to set IA32_RTIT_CTL.cr3. If we find EBX[0].CR3_filter is not supported a #GP will be emulated. This check will added in KVM patch set V5 and it still working in progress.
>
> > + ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX)
> > + ||
>
> Same comment as above.
>
> Also: bit 31 must match the host, meaning we must reject a host where ecx_0 & (1 << 31) is set.
Get it, will add in next version.
>
>
> > + ((eax_1 & (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) !=
> > + (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) ||
>
> This will make the code accept hosts with 3 address ranges (0b011), but reject ones with 4 address ranges (0b100). This doesn't
> sound right to me.
I see, will fix it.
>
>
> > + ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
> > + (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) {
>
> How do we know if KVM is going to emulate #GP properly when setting an invalid CycThresh or PSBFreq value? Do we care?
It will check in KVM and will emulate a #GP if set an invalid value but I think qemu can't aware this.
>From my point of view, I think qemu don't need to care or get this information.
>
>
> > + env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
> > + cpu->filtered_features[FEAT_7_0_EBX] |=
> > + CPUID_7_0_EBX_INTEL_PT;
>
> This matches what I have suggested. But I recommend adding a comment mentioning why we do this. Something like:
>
> /*
> * Processor Trace capabilities aren't configurable, so if the
> * host can't emulate the capabilities we report on
> * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
> */
Agree.
Thanks a lot for the code review.
Luwei Kang
>
>
> > + rv = 1;
> > + }
> > + }
> > +
> > return rv;
> > }
> >
> > diff --git a/target/i386/cpu.h b/target/i386/cpu.h index
> > f91e37d..7facc8b 100644
> > --- a/target/i386/cpu.h
> > +++ b/target/i386/cpu.h
> > @@ -644,6 +644,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> > #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
> > #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
> > #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
> > +#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
> > #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
> > #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and
> > Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512
> > Conflict Detection */ diff --git a/target/i386/kvm.c
> > b/target/i386/kvm.c index ad4b159..f9f4cd1 100644
> > --- a/target/i386/kvm.c
> > +++ b/target/i386/kvm.c
> > @@ -865,6 +865,29 @@ int kvm_arch_init_vcpu(CPUState *cs)
> > c = &cpuid_data.entries[cpuid_i++];
> > }
> > break;
> > + case 0x14: {
> > + uint32_t times;
> > +
> > + c->function = i;
> > + c->index = 0;
> > + c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
> > + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
> > + times = c->eax;
> > +
> > + for (j = 1; j <= times; ++j) {
> > + if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
> > + fprintf(stderr, "cpuid_data is full, no space for "
> > + "cpuid(eax:0x14,ecx:0x%x)\n", j);
> > + abort();
> > + }
> > + c = &cpuid_data.entries[cpuid_i++];
> > + c->function = i;
> > + c->index = j;
> > + c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
> > + cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
> > + }
> > + break;
> > + }
> > default:
> > c->function = i;
> > c->flags = 0;
> > --
> > 1.8.3.1
> >
> >
>
> --
> Eduardo
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [Qemu-devel] [PATCH v3 1/2] i386: Add Intel Processor Trace feature support
2018-02-08 1:24 ` Kang, Luwei
(?)
@ 2018-02-08 18:23 ` Eduardo Habkost
-1 siblings, 0 replies; 8+ messages in thread
From: Eduardo Habkost @ 2018-02-08 18:23 UTC (permalink / raw)
To: Kang, Luwei; +Cc: qemu-devel, kvm, mtosatti, Chao Peng, pbonzini, rth
On Thu, Feb 08, 2018 at 01:24:46AM +0000, Kang, Luwei wrote:
> > On Wed, Jan 31, 2018 at 11:57:45PM +0800, Luwei Kang wrote:
> > > From: Chao Peng <chao.p.peng@linux.intel.com>
> > >
> > > Expose Intel Processor Trace feature to guest.
> > >
> > > To make Intel PT live migration safe and get same CPUID information
> > > with same CPU model on diffrent host. CPUID[14] is constant in this
> > > patch. Intel PT use EPT is first supported in IceLake, the CPUID[14]
> > > get on this machine as default value. Intel PT would be disabled If
> > > any machine don't support this minial feature list.
> > >
> > > Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> > > Signed-off-by: Luwei Kang <luwei.kang@intel.com>
> > > ---
> > > target/i386/cpu.c | 53
> > > +++++++++++++++++++++++++++++++++++++++++++++++++++--
> > > target/i386/cpu.h | 1 +
> > > target/i386/kvm.c | 23 +++++++++++++++++++++++
> > > 3 files changed, 75 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index
> > > a49d222..aaa427a 100644
> > > --- a/target/i386/cpu.c
> > > +++ b/target/i386/cpu.c
> > > @@ -172,7 +172,14 @@
> > > #define L2_ITLB_4K_ASSOC 4
> > > #define L2_ITLB_4K_ENTRIES 512
> > >
> > > -
> > > +/* CPUID Leaf 0x14 constants: */
> > > +#define INTLE_PT_MAX_SUBLEAF 0x1
> >
> > Typo.
> >
> > > +#define INTEL_PT_MINIMAL_EBX 0xf
> > > +#define INTEL_PT_MINIMAL_ECX 0x7
> >
> > I suggest documenting what capabilities are included in
> > INTEL_PT_MINIMAL_* here.
> >
> >
> > > +#define INTLE_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable
> > > +address ranges */
> >
> > Typo.
> >
> > > +#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
> > > +#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
> > > +#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
> > >
> > > static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
> > > uint32_t vendor2, uint32_t
> > > vendor3) @@ -427,7 +434,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> > > NULL, NULL, "mpx", NULL,
> > > "avx512f", "avx512dq", "rdseed", "adx",
> > > "smap", "avx512ifma", "pcommit", "clflushopt",
> > > - "clwb", NULL, "avx512pf", "avx512er",
> > > + "clwb", "intel-pt", "avx512pf", "avx512er",
> > > "avx512cd", "sha-ni", "avx512bw", "avx512vl",
> > > },
> > > .cpuid_eax = 7,
> > > @@ -3452,6 +3459,27 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
> > > }
> > > break;
> > > }
> > > + case 0x14: {
> > > + /* Intel Processor Trace Enumeration */
> > > + *eax = 0;
> > > + *ebx = 0;
> > > + *ecx = 0;
> > > + *edx = 0;
> > > + if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
> > > + !kvm_enabled()) {
> > > + break;
> > > + }
> > > +
> > > + if (count == 0) {
> > > + *eax = INTLE_PT_MAX_SUBLEAF;
> > > + *ebx = INTEL_PT_MINIMAL_EBX;
> > > + *ecx = INTEL_PT_MINIMAL_ECX;
> > > + } else if (count == 1) {
> > > + *eax = INTEL_PT_MTC_BITMAP | INTLE_PT_ADDR_RANGES_NUM;
> > > + *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
> > > + }
> > > + break;
> > > + }
> > > case 0x40000000:
> > > /*
> > > * CPUID code in kvm_arch_init_vcpu() ignores stuff @@
> > > -4082,6 +4110,27 @@ static int x86_cpu_filter_features(X86CPU *cpu)
> > > }
> > > }
> > >
> > > + if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
> >
> > What if the accelerator is not KVM, but is reporting intel-pt as supported?
>
> I have add this check in cpu_x86_cpuid() but I think we'd better add kvm_enabled() check here as well.
> What is your opinion?
The function is going to crash if KVM is not enabled and the
accelerator returns intel-pt is supported, as cpu->kvm_state will
be NULL.
>
> >
> > > + KVMState *s = CPU(cpu)->kvm_state;
> > > + uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
> > > + uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
> > > + uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
> > > + uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
> > > + uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1,
> > > + R_EBX);
> > > +
> > > + if (!eax_0 ||
> >
> > OK.
> >
> > > + ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX)
> > > + ||
> >
> > How do we know if KVM is going to emulate #GP properly when
> > setting a bit that is supported by the host CPU but cleared
> > on the guest CPUID? Do we care?
>
> I think it need KVM make this check and Qemu don't need aware
> this.
> For example, EBX[0].CR3_filter (IA32_RTIT_CTL.cr3 can't be set
> if 0) is support by host but we mask off this bit in kvm guest.
> Qemu will set the CPUID to KVM by ioctl KVM_SET_CPUID2. KVM
> will trap the behavior when KVM guest want to set
> IA32_RTIT_CTL.cr3. If we find EBX[0].CR3_filter is not
> supported a #GP will be emulated. This check will added in KVM
> patch set V5 and it still working in progress.
I was assuming there would be released Linux versions where this
wasn't implemented yet. If nothing was merged yet, we should be
safe.
>
> >
> > > + ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX)
> > > + ||
> >
> > Same comment as above.
> >
> > Also: bit 31 must match the host, meaning we must reject a
> > host where ecx_0 & (1 << 31) is set.
>
> Get it, will add in next version.
>
> >
> >
> > > + ((eax_1 & (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) !=
> > > + (INTLE_PT_ADDR_RANGES_NUM | INTEL_PT_MTC_BITMAP)) ||
> >
> > This will make the code accept hosts with 3 address ranges
> > (0b011), but reject ones with 4 address ranges (0b100). This
> > doesn't sound right to me.
>
> I see, will fix it.
>
> >
> >
> > > + ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
> > > + (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) {
> >
> > How do we know if KVM is going to emulate #GP properly when
> > setting an invalid CycThresh or PSBFreq value? Do we care?
>
> It will check in KVM and will emulate a #GP if set an invalid
> value but I think qemu can't aware this. From my point of
> view, I think qemu don't need to care or get this information.
If all KVM versions that return 0x14 on GET_SUPPORTED_CPUID will
emulate #GP properly, this will be OK.
--
Eduardo
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-02-08 18:23 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-31 15:57 [PATCH v3 1/2] i386: Add Intel Processor Trace feature support Luwei Kang
2018-01-31 15:57 ` [Qemu-devel] " Luwei Kang
2018-01-31 15:57 ` [PATCH v3 2/2] i386: Add support to get/set/migrate Intel Processor Trace feature Luwei Kang
2018-01-31 15:57 ` [Qemu-devel] " Luwei Kang
2018-02-07 14:53 ` [Qemu-devel] [PATCH v3 1/2] i386: Add Intel Processor Trace feature support Eduardo Habkost
2018-02-08 1:24 ` Kang, Luwei
2018-02-08 1:24 ` Kang, Luwei
2018-02-08 18:23 ` Eduardo Habkost
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