* [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support
@ 2018-02-02 13:43 Rajneesh Bhardwaj
2018-02-02 13:43 ` [Patch v2 1/5] ACPI / LPIT: Export lpit_read_residency_count_address() Rajneesh Bhardwaj
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Rajneesh Bhardwaj @ 2018-02-02 13:43 UTC (permalink / raw)
To: platform-driver-x86
Cc: dvhart, andy, linux-kernel, vishwanath.somayaji,
srinivas.pandruvada, Rajneesh Bhardwaj, Rafael J . Wysocki,
Len Brown, Thomas Gleixner, linux-acpi, x86
This series contains the remaining (rebased) patches that were not applied
to the pdx tree earlier. This also includes Acked-by / Reviewed-by tags from
Rafael and Thomas.
Rebased and tested on:
http://git.infradead.org/linux-platform-drivers-x86.git/shortlog/refs/heads/review-andy
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Cc: Len Brown <lenb@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-acpi@vger.kernel.org
Cc: x86@kernel.org
Rajneesh Bhardwaj (3):
x86/cpu: Add Cannonlake to Intel family
platform/x86: intel_pmc_core: Add CannonLake PCH support
platform/x86: intel_pmc_core: Special case for Coffeelake
Srinivas Pandruvada (2):
ACPI / LPIT: Export lpit_read_residency_count_address()
platform/x86: intel_pmc_core: Read base address from LPIT
arch/x86/include/asm/intel-family.h | 6 ++
drivers/acpi/acpi_lpit.c | 1 +
drivers/platform/x86/intel_pmc_core.c | 108 +++++++++++++++++++++++++++++++++-
drivers/platform/x86/intel_pmc_core.h | 13 ++++
4 files changed, 127 insertions(+), 1 deletion(-)
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread* [Patch v2 1/5] ACPI / LPIT: Export lpit_read_residency_count_address() 2018-02-02 13:43 [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Rajneesh Bhardwaj @ 2018-02-02 13:43 ` Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 2/5] platform/x86: intel_pmc_core: Read base address from LPIT Rajneesh Bhardwaj ` (4 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Rajneesh Bhardwaj @ 2018-02-02 13:43 UTC (permalink / raw) To: platform-driver-x86 Cc: dvhart, andy, linux-kernel, vishwanath.somayaji, srinivas.pandruvada, Rafael J . Wysocki, Len Brown, linux-acpi From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Export lpit_read_residency_count_address(), so that it can be used from drivers built as module. With the recent changes, the builtin_pci functionality of the intel_pmc_core driver is removed and now it can be built as a module to read this exported interface to calculate the PMC base address. Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Len Brown <lenb@kernel.org> Cc: linux-acpi@vger.kernel.org Acked-by: Rafael J. Wysocki <rafael@kernel.org> Tested-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> --- drivers/acpi/acpi_lpit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/acpi_lpit.c b/drivers/acpi/acpi_lpit.c index e94e478dd18b..cf4fc0161164 100644 --- a/drivers/acpi/acpi_lpit.c +++ b/drivers/acpi/acpi_lpit.c @@ -100,6 +100,7 @@ int lpit_read_residency_count_address(u64 *address) return 0; } +EXPORT_SYMBOL_GPL(lpit_read_residency_count_address); static void lpit_update_residency(struct lpit_residency_info *info, struct acpi_lpit_native *lpit_native) -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Patch v2 2/5] platform/x86: intel_pmc_core: Read base address from LPIT 2018-02-02 13:43 [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 1/5] ACPI / LPIT: Export lpit_read_residency_count_address() Rajneesh Bhardwaj @ 2018-02-02 13:43 ` Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 3/5] x86/cpu: Add Cannonlake to Intel family Rajneesh Bhardwaj ` (3 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Rajneesh Bhardwaj @ 2018-02-02 13:43 UTC (permalink / raw) To: platform-driver-x86 Cc: dvhart, andy, linux-kernel, vishwanath.somayaji, srinivas.pandruvada, Rajneesh Bhardwaj From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Read SLP_S0 address from ACPI LPIT table when present and use PMC specific SLP_S0 offset to get the base address of PMC MMIO. Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> --- drivers/platform/x86/intel_pmc_core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 5c401e17cfb6..bb80aed4c3c1 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -20,6 +20,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include <linux/acpi.h> #include <linux/debugfs.h> #include <linux/delay.h> #include <linux/io.h> @@ -455,6 +456,7 @@ static int __init pmc_core_probe(void) { struct pmc_dev *pmcdev = &pmc; const struct x86_cpu_id *cpu_id; + u64 slp_s0_addr; int err; cpu_id = x86_match_cpu(intel_pmc_core_ids); @@ -462,7 +464,12 @@ static int __init pmc_core_probe(void) return -ENODEV; pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data; - pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; + + if (lpit_read_residency_count_address(&slp_s0_addr)) + pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; + else + pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset; + pmcdev->regbase = ioremap(pmcdev->base_addr, pmcdev->map->regmap_length); if (!pmcdev->regbase) -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Patch v2 3/5] x86/cpu: Add Cannonlake to Intel family 2018-02-02 13:43 [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 1/5] ACPI / LPIT: Export lpit_read_residency_count_address() Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 2/5] platform/x86: intel_pmc_core: Read base address from LPIT Rajneesh Bhardwaj @ 2018-02-02 13:43 ` Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 4/5] platform/x86: intel_pmc_core: Add CannonLake PCH support Rajneesh Bhardwaj ` (2 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: Rajneesh Bhardwaj @ 2018-02-02 13:43 UTC (permalink / raw) To: platform-driver-x86 Cc: dvhart, andy, linux-kernel, vishwanath.somayaji, srinivas.pandruvada, Rajneesh Bhardwaj, Dave Hansen, Thomas Gleixner, Ingo Molnar, H. Peter Anvin, x86 Add CPUID of Cannonlake (CNL) processors to Intel family list. Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Thomas Gleixner <tglx@linutronix.de> cc: Ingo Molnar <mingo@redhat.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: x86@kernel.org Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Suggested-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Megha Dey <megha.dey@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> --- arch/x86/include/asm/intel-family.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 35a6bc4da8ad..cf090e584202 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -10,6 +10,10 @@ * * Things ending in "2" are usually because we have no better * name for them. There's no processor called "SILVERMONT2". + * + * While adding a new CPUID for a new microarchitecture, add a new + * group to keep logically sorted out in chronological order. Within + * that group keep the CPUID for the variants sorted by model number. */ #define INTEL_FAM6_CORE_YONAH 0x0E @@ -49,6 +53,8 @@ #define INTEL_FAM6_KABYLAKE_MOBILE 0x8E #define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E +#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66 + /* "Small Core" Processors (Atom) */ #define INTEL_FAM6_ATOM_PINEVIEW 0x1C -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Patch v2 4/5] platform/x86: intel_pmc_core: Add CannonLake PCH support 2018-02-02 13:43 [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Rajneesh Bhardwaj ` (2 preceding siblings ...) 2018-02-02 13:43 ` [Patch v2 3/5] x86/cpu: Add Cannonlake to Intel family Rajneesh Bhardwaj @ 2018-02-02 13:43 ` Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 5/5] platform/x86: intel_pmc_core: Special case for Coffeelake Rajneesh Bhardwaj 2018-02-02 20:14 ` [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Andy Shevchenko 5 siblings, 0 replies; 7+ messages in thread From: Rajneesh Bhardwaj @ 2018-02-02 13:43 UTC (permalink / raw) To: platform-driver-x86 Cc: dvhart, andy, linux-kernel, vishwanath.somayaji, srinivas.pandruvada, Rajneesh Bhardwaj This adds support for Cannonlake PCH which is used by Cannonlake and Coffeelake SoCs. Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> --- drivers/platform/x86/intel_pmc_core.c | 85 +++++++++++++++++++++++++++++++++++ drivers/platform/x86/intel_pmc_core.h | 11 +++++ 2 files changed, 96 insertions(+) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index bb80aed4c3c1..a255c4b0f7a8 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -122,6 +122,90 @@ static const struct pmc_reg_map spt_reg_map = { .pm_read_disable_bit = SPT_PMC_READ_DISABLE_BIT, }; +/* Cannonlake: PGD PFET Enable Ack Status Register(s) bitmap */ +static const struct pmc_bit_map cnp_pfear_map[] = { + {"PMC", BIT(0)}, + {"OPI-DMI", BIT(1)}, + {"SPI/eSPI", BIT(2)}, + {"XHCI", BIT(3)}, + {"SPA", BIT(4)}, + {"SPB", BIT(5)}, + {"SPC", BIT(6)}, + {"GBE", BIT(7)}, + + {"SATA", BIT(0)}, + {"HDA_PGD0", BIT(1)}, + {"HDA_PGD1", BIT(2)}, + {"HDA_PGD2", BIT(3)}, + {"HDA_PGD3", BIT(4)}, + {"SPD", BIT(5)}, + {"LPSS", BIT(6)}, + {"LPC", BIT(7)}, + + {"SMB", BIT(0)}, + {"ISH", BIT(1)}, + {"P2SB", BIT(2)}, + {"NPK_VNN", BIT(3)}, + {"SDX", BIT(4)}, + {"SPE", BIT(5)}, + {"Fuse", BIT(6)}, + {"Res_23", BIT(7)}, + + {"CSME_FSC", BIT(0)}, + {"USB3_OTG", BIT(1)}, + {"EXI", BIT(2)}, + {"CSE", BIT(3)}, + {"csme_kvm", BIT(4)}, + {"csme_pmt", BIT(5)}, + {"csme_clink", BIT(6)}, + {"csme_ptio", BIT(7)}, + + {"csme_usbr", BIT(0)}, + {"csme_susram", BIT(1)}, + {"csme_smt1", BIT(2)}, + {"CSME_SMT4", BIT(3)}, + {"csme_sms2", BIT(4)}, + {"csme_sms1", BIT(5)}, + {"csme_rtc", BIT(6)}, + {"csme_psf", BIT(7)}, + + {"SBR0", BIT(0)}, + {"SBR1", BIT(1)}, + {"SBR2", BIT(2)}, + {"SBR3", BIT(3)}, + {"SBR4", BIT(4)}, + {"SBR5", BIT(5)}, + {"CSME_PECI", BIT(6)}, + {"PSF1", BIT(7)}, + + {"PSF2", BIT(0)}, + {"PSF3", BIT(1)}, + {"PSF4", BIT(2)}, + {"CNVI", BIT(3)}, + {"UFS0", BIT(4)}, + {"EMMC", BIT(5)}, + {"Res_6", BIT(6)}, + {"SBR6", BIT(7)}, + + {"SBR7", BIT(0)}, + {"NPK_AON", BIT(1)}, + {"HDA_PGD4", BIT(2)}, + {"HDA_PGD5", BIT(3)}, + {"HDA_PGD6", BIT(4)}, + {} +}; + +static const struct pmc_reg_map cnp_reg_map = { + .pfear_sts = cnp_pfear_map, + .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET, + .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET, + .regmap_length = CNP_PMC_MMIO_REG_LEN, + .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A, + .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES, + .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET, + .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT, +}; + static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset) { return readb(pmcdev->regbase + offset); @@ -447,6 +531,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, &spt_reg_map), ICPU(INTEL_FAM6_KABYLAKE_MOBILE, &spt_reg_map), ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, &spt_reg_map), + ICPU(INTEL_FAM6_CANNONLAKE_MOBILE, &cnp_reg_map), {} }; diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 9df4a60a179f..8b7731e6dea2 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -121,6 +121,17 @@ enum ppfear_regs { #define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2) #define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3) +/* Cannonlake Power Management Controller register offsets */ +#define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C +#define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C +#define CNP_PMC_PM_CFG_OFFSET 0x1818 +/* Cannonlake: PGD PFET Enable Ack Status Register(s) start */ +#define CNP_PMC_HOST_PPFEAR0A 0x1D90 + +#define CNP_PMC_MMIO_REG_LEN 0x2000 +#define CNP_PPFEAR_NUM_ENTRIES 8 +#define CNP_PMC_READ_DISABLE_BIT 22 + struct pmc_bit_map { const char *name; u32 bit_mask; -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Patch v2 5/5] platform/x86: intel_pmc_core: Special case for Coffeelake 2018-02-02 13:43 [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Rajneesh Bhardwaj ` (3 preceding siblings ...) 2018-02-02 13:43 ` [Patch v2 4/5] platform/x86: intel_pmc_core: Add CannonLake PCH support Rajneesh Bhardwaj @ 2018-02-02 13:43 ` Rajneesh Bhardwaj 2018-02-02 20:14 ` [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Andy Shevchenko 5 siblings, 0 replies; 7+ messages in thread From: Rajneesh Bhardwaj @ 2018-02-02 13:43 UTC (permalink / raw) To: platform-driver-x86 Cc: dvhart, andy, linux-kernel, vishwanath.somayaji, srinivas.pandruvada, Rajneesh Bhardwaj Intel CoffeeLake SoC uses CPU ID of KabyLake but has Cannonlake PCH, so in this case PMC register details from Cannonlake PCH must be used. In order to identify whether the given platform is Coffeelake, scan for the Sunrisepoint PMC PCI Id. KBL CPUID SPT PCIID ------------------------------------- KBL | Y | Y | ------------------------------------- CFL | Y | N | ------------------------------------- Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> --- drivers/platform/x86/intel_pmc_core.c | 14 ++++++++++++++ drivers/platform/x86/intel_pmc_core.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index a255c4b0f7a8..b89bef140c8b 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -25,6 +25,7 @@ #include <linux/delay.h> #include <linux/io.h> #include <linux/module.h> +#include <linux/pci.h> #include <linux/uaccess.h> #include <asm/cpu_device_id.h> @@ -537,6 +538,11 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = { MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids); +static const struct pci_device_id pmc_pci_ids[] = { + { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0}, + { 0, }, +}; + static int __init pmc_core_probe(void) { struct pmc_dev *pmcdev = &pmc; @@ -550,6 +556,14 @@ static int __init pmc_core_probe(void) pmcdev->map = (struct pmc_reg_map *)cpu_id->driver_data; + /* + * Coffeelake has CPU ID of Kabylake and Cannonlake PCH. So here + * Sunrisepoint PCH regmap can't be used. Use Cannonlake PCH regmap + * in this case. + */ + if (!pci_dev_present(pmc_pci_ids)) + pmcdev->map = (struct pmc_reg_map *)&cnp_reg_map; + if (lpit_read_residency_count_address(&slp_s0_addr)) pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT; else diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index 8b7731e6dea2..5fa5f97870aa 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -23,6 +23,8 @@ #define PMC_BASE_ADDR_DEFAULT 0xFE000000 +/* Sunrise Point Power Management Controller PCI Device ID */ +#define SPT_PMC_PCI_DEVICE_ID 0x9d21 #define SPT_PMC_BASE_ADDR_OFFSET 0x48 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c #define SPT_PMC_PM_CFG_OFFSET 0x18 -- 2.7.4 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support 2018-02-02 13:43 [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Rajneesh Bhardwaj ` (4 preceding siblings ...) 2018-02-02 13:43 ` [Patch v2 5/5] platform/x86: intel_pmc_core: Special case for Coffeelake Rajneesh Bhardwaj @ 2018-02-02 20:14 ` Andy Shevchenko 5 siblings, 0 replies; 7+ messages in thread From: Andy Shevchenko @ 2018-02-02 20:14 UTC (permalink / raw) To: Rajneesh Bhardwaj Cc: Platform Driver, Darren Hart, Andy Shevchenko, Linux Kernel Mailing List, Vishwanath Somayaji, Srinivas Pandruvada, Rafael J . Wysocki, Len Brown, Thomas Gleixner, ACPI Devel Maling List, x86 On Fri, Feb 2, 2018 at 3:43 PM, Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> wrote: > This series contains the remaining (rebased) patches that were not applied > to the pdx tree earlier. This also includes Acked-by / Reviewed-by tags from > Rafael and Thomas. > > Rebased and tested on: > http://git.infradead.org/linux-platform-drivers-x86.git/shortlog/refs/heads/review-andy > All 5 pushed to my review and testing queue. Thanks! > Cc: Rafael J. Wysocki <rjw@rjwysocki.net> > Cc: Len Brown <lenb@kernel.org> > Cc: Thomas Gleixner <tglx@linutronix.de> > > Cc: linux-acpi@vger.kernel.org > Cc: x86@kernel.org > > Rajneesh Bhardwaj (3): > x86/cpu: Add Cannonlake to Intel family > platform/x86: intel_pmc_core: Add CannonLake PCH support > platform/x86: intel_pmc_core: Special case for Coffeelake > > Srinivas Pandruvada (2): > ACPI / LPIT: Export lpit_read_residency_count_address() > platform/x86: intel_pmc_core: Read base address from LPIT > > arch/x86/include/asm/intel-family.h | 6 ++ > drivers/acpi/acpi_lpit.c | 1 + > drivers/platform/x86/intel_pmc_core.c | 108 +++++++++++++++++++++++++++++++++- > drivers/platform/x86/intel_pmc_core.h | 13 ++++ > 4 files changed, 127 insertions(+), 1 deletion(-) > > -- > 2.7.4 > -- With Best Regards, Andy Shevchenko ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-02-02 20:14 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-02-02 13:43 [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 1/5] ACPI / LPIT: Export lpit_read_residency_count_address() Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 2/5] platform/x86: intel_pmc_core: Read base address from LPIT Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 3/5] x86/cpu: Add Cannonlake to Intel family Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 4/5] platform/x86: intel_pmc_core: Add CannonLake PCH support Rajneesh Bhardwaj 2018-02-02 13:43 ` [Patch v2 5/5] platform/x86: intel_pmc_core: Special case for Coffeelake Rajneesh Bhardwaj 2018-02-02 20:14 ` [Patch v2 0/5] platform/x86: intel_pmc_core: Add CFL/CNL Support Andy Shevchenko
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.