[igt-dev] [PATCH v2 i-g-t 0/9] perf_pmu reliability improvements

[igt-dev] [PATCH v2 i-g-t 0/9] perf_pmu reliability improvements

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Some reworks to hopefully improve the reliability of tests on small core
machines.

Mostly ensuring measured sleep approach is always used in tests which look at
time, and that time spent setting up the test is ignored as much as possible.

v2:

More tests and more fixes, most notably test for the PMU enable vs execlists
tasklet race and CPU hotplug test fix for trigger happy hangcheck.

Tvrtko Ursulin (9):
  tests/perf_pmu: Tighten busy measurement
  tests/perf_pmu: More busy measurement tightening
  tests/perf_pmu: Use measured sleep in all time based tests
  tests/perf_pmu: Convert to flags
  tests/perf_pmu: Add trailing edge idle test variants
  tests/perf_pmu: PMU enable race test
  tests/perf_pmu: Always skip missing engines
  tests/perf_pmu: Explicitly test for engine availability in init tests
  tests/perf_pmu: Use short batches from hotplug test

 tests/perf_pmu.c | 320 +++++++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 249 insertions(+), 71 deletions(-)

-- 
2.14.1

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[igt-dev] [PATCH i-g-t 1/9] tests/perf_pmu: Tighten busy measurement

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

In cases where we manually terminate the busy batch, we always want to
sample busyness while the batch is running, just before we will
terminate it, and not the other way around. This way we make the window
for unwated idleness getting sampled smaller.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/perf_pmu.c | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 2f7d33414a53..bf16e5e8b1f9 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -146,10 +146,9 @@ single(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
 		spin = NULL;
 
 	slept = measured_usleep(batch_duration_ns / 1000);
-	igt_spin_batch_end(spin);
-
 	val = pmu_read_single(fd);
 
+	igt_spin_batch_end(spin);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd);
 
@@ -256,7 +255,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	gem_quiescent_gpu(gem_fd);
 }
 
-static void log_busy(int fd, unsigned int num_engines, uint64_t *val)
+static void log_busy(unsigned int num_engines, uint64_t *val)
 {
 	char buf[1024];
 	int rem = sizeof(buf);
@@ -303,14 +302,14 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
 	slept = measured_usleep(batch_duration_ns / 1000);
-	igt_spin_batch_end(spin);
-
 	pmu_read_multi(fd[0], num_engines, val);
-	log_busy(fd[0], num_engines, val);
 
+	igt_spin_batch_end(spin);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
+	log_busy(num_engines, val);
+
 	assert_within_epsilon(val[busy_idx], slept, tolerance);
 	for (i = 0; i < num_engines; i++) {
 		if (i == busy_idx)
@@ -364,14 +363,14 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 		fd[i] = open_group(val[i], fd[0]);
 
 	slept = measured_usleep(batch_duration_ns / 1000);
-	igt_spin_batch_end(spin);
-
 	pmu_read_multi(fd[0], num_engines, val);
-	log_busy(fd[0], num_engines, val);
 
+	igt_spin_batch_end(spin);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
+	log_busy(num_engines, val);
+
 	for (i = 0; i < num_engines; i++) {
 		if (i == idle_idx)
 			assert_within_epsilon(val[i], 0.0f, tolerance);
@@ -420,14 +419,14 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines)
 		fd[i] = open_group(val[i], fd[0]);
 
 	slept = measured_usleep(batch_duration_ns / 1000);
-	igt_spin_batch_end(spin);
-
 	pmu_read_multi(fd[0], num_engines, val);
-	log_busy(fd[0], num_engines, val);
 
+	igt_spin_batch_end(spin);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
+	log_busy(num_engines, val);
+
 	for (i = 0; i < num_engines; i++)
 		assert_within_epsilon(val[i], slept, tolerance);
 	gem_quiescent_gpu(gem_fd);
@@ -903,12 +902,11 @@ static void cpu_hotplug(int gem_fd)
 
 	igt_waitchildren();
 
-	igt_spin_batch_end(spin);
-	gem_sync(gem_fd, spin->handle);
-
 	ref = igt_nsec_elapsed(&start);
 	val = pmu_read_single(fd);
 
+	igt_spin_batch_end(spin);
+	gem_sync(gem_fd, spin->handle);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd);
 
-- 
2.14.1

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[igt-dev] [PATCH i-g-t 2/9] tests/perf_pmu: More busy measurement tightening

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Where we use measured sleeps, take PMU samples immediately before and
after and look at their delta in order to minimize the effect of any
test setup delays.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/perf_pmu.c | 36 ++++++++++++++++++++++++++++--------
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index bf16e5e8b1f9..bdf452c8347c 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -145,8 +145,9 @@ single(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
 	else
 		spin = NULL;
 
-	slept = measured_usleep(batch_duration_ns / 1000);
 	val = pmu_read_single(fd);
+	slept = measured_usleep(batch_duration_ns / 1000);
+	val = pmu_read_single(fd) - val;
 
 	igt_spin_batch_end(spin);
 	igt_spin_batch_free(gem_fd, spin);
@@ -180,8 +181,9 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
 
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
-	slept = measured_usleep(batch_duration_ns / 1000);
 	val = pmu_read_single(fd);
+	slept = measured_usleep(batch_duration_ns / 1000);
+	val = pmu_read_single(fd) - val;
 
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd);
@@ -227,8 +229,9 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	 */
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
-	slept = measured_usleep(batch_duration_ns / 1000);
 	val = pmu_read_single(fd);
+	slept = measured_usleep(batch_duration_ns / 1000);
+	val = pmu_read_single(fd) - val;
 
 	igt_spin_batch_end(spin[0]);
 	igt_spin_batch_end(spin[1]);
@@ -279,6 +282,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	       const unsigned int num_engines)
 {
 	const struct intel_execution_engine2 *e_;
+	uint64_t tval[2][num_engines];
 	uint64_t val[num_engines];
 	int fd[num_engines];
 	unsigned long slept;
@@ -301,13 +305,17 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	igt_assert_eq(i, num_engines);
 
 	spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
+	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
-	pmu_read_multi(fd[0], num_engines, val);
+	pmu_read_multi(fd[0], num_engines, tval[1]);
 
 	igt_spin_batch_end(spin);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
+	for (i = 0; i < num_engines; i++)
+		val[i] = tval[1][i] - tval[0][i];
+
 	log_busy(num_engines, val);
 
 	assert_within_epsilon(val[busy_idx], slept, tolerance);
@@ -324,6 +332,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 		    const unsigned int num_engines)
 {
 	const struct intel_execution_engine2 *e_;
+	uint64_t tval[2][num_engines];
 	uint64_t val[num_engines];
 	int fd[num_engines];
 	unsigned long slept;
@@ -362,13 +371,17 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	for (i = 0; i < num_engines; i++)
 		fd[i] = open_group(val[i], fd[0]);
 
+	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
-	pmu_read_multi(fd[0], num_engines, val);
+	pmu_read_multi(fd[0], num_engines, tval[1]);
 
 	igt_spin_batch_end(spin);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
+	for (i = 0; i < num_engines; i++)
+		val[i] = tval[1][i] - tval[0][i];
+
 	log_busy(num_engines, val);
 
 	for (i = 0; i < num_engines; i++) {
@@ -384,6 +397,7 @@ static void
 all_busy_check_all(int gem_fd, const unsigned int num_engines)
 {
 	const struct intel_execution_engine2 *e;
+	uint64_t tval[2][num_engines];
 	uint64_t val[num_engines];
 	int fd[num_engines];
 	unsigned long slept;
@@ -418,13 +432,17 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines)
 	for (i = 0; i < num_engines; i++)
 		fd[i] = open_group(val[i], fd[0]);
 
+	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
-	pmu_read_multi(fd[0], num_engines, val);
+	pmu_read_multi(fd[0], num_engines, tval[1]);
 
 	igt_spin_batch_end(spin);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
+	for (i = 0; i < num_engines; i++)
+		val[i] = tval[1][i] - tval[0][i];
+
 	log_busy(num_engines, val);
 
 	for (i = 0; i < num_engines; i++)
@@ -765,13 +783,15 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
 	igt_spin_batch_set_timeout(spin, 2 * batch_duration_ns);
 
-	slept = measured_usleep(batch_duration_ns / 1000);
+	val[0] = pmu_read_single(fd[0]);
 	val[1] = pmu_read_single(fd[1]);
+	slept = measured_usleep(batch_duration_ns / 1000);
+	val[1] = pmu_read_single(fd[1]) - val[1];
 	close(fd[1]);
 
 	gem_sync(gem_fd, spin->handle);
 
-	val[0] = pmu_read_single(fd[0]);
+	val[0] = pmu_read_single(fd[0]) - val[0];
 
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
-- 
2.14.1

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[igt-dev] [PATCH i-g-t 3/9] tests/perf_pmu: Use measured sleep in all time based tests

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Stop relying on timers to end spin batches but use measured sleep, which
was established to work better, in all time based tests.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/perf_pmu.c | 42 +++++++++++++++++++++---------------------
 1 file changed, 21 insertions(+), 21 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index bdf452c8347c..e27e74abe686 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -454,30 +454,31 @@ static void
 no_sema(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
 {
 	igt_spin_t *spin;
-	uint64_t val[2];
+	uint64_t val[2][2];
 	int fd;
 
 	fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
 	open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
 
-	if (busy) {
+	if (busy)
 		spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
-		igt_spin_batch_set_timeout(spin, batch_duration_ns);
-	} else {
-		usleep(batch_duration_ns / 1000);
-	}
 
-	if (busy)
-		gem_sync(gem_fd, spin->handle);
+	pmu_read_multi(fd, 2, val[0]);
+	measured_usleep(batch_duration_ns / 1000);
+	pmu_read_multi(fd, 2, val[1]);
 
-	pmu_read_multi(fd, 2, val);
+	val[0][0] = val[1][0] - val[0][0];
+	val[0][1] = val[1][1] - val[0][1];
 
-	if (busy)
+	if (busy) {
+		igt_spin_batch_end(spin);
+		gem_sync(gem_fd, spin->handle);
 		igt_spin_batch_free(gem_fd, spin);
+	}
 	close(fd);
 
-	assert_within_epsilon(val[0], 0.0f, tolerance);
-	assert_within_epsilon(val[1], 0.0f, tolerance);
+	assert_within_epsilon(val[0][0], 0.0f, tolerance);
+	assert_within_epsilon(val[0][1], 0.0f, tolerance);
 }
 
 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
@@ -766,7 +767,7 @@ static void
 multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 {
 	uint64_t config = I915_PMU_ENGINE_BUSY(e->class, e->instance);
-	unsigned int slept;
+	unsigned int slept[2];
 	igt_spin_t *spin;
 	uint64_t val[2];
 	int fd[2];
@@ -781,23 +782,22 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	fd[1] = open_pmu(config);
 
 	spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
-	igt_spin_batch_set_timeout(spin, 2 * batch_duration_ns);
 
-	val[0] = pmu_read_single(fd[0]);
-	val[1] = pmu_read_single(fd[1]);
-	slept = measured_usleep(batch_duration_ns / 1000);
+	val[0] = val[1] = pmu_read_single(fd[0]);
+	slept[1] = measured_usleep(batch_duration_ns / 1000);
 	val[1] = pmu_read_single(fd[1]) - val[1];
 	close(fd[1]);
 
-	gem_sync(gem_fd, spin->handle);
-
+	slept[0] = measured_usleep(batch_duration_ns / 1000) + slept[1];
 	val[0] = pmu_read_single(fd[0]) - val[0];
 
+	igt_spin_batch_end(spin);
+	gem_sync(gem_fd, spin->handle);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
-	assert_within_epsilon(val[0], 2 * batch_duration_ns, tolerance);
-	assert_within_epsilon(val[1], slept, tolerance);
+	assert_within_epsilon(val[0], slept[0], tolerance);
+	assert_within_epsilon(val[1], slept[1], tolerance);
 }
 
 /**
-- 
2.14.1

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[igt-dev] [PATCH i-g-t 4/9] tests/perf_pmu: Convert to flags

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Will need more modes soon.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e27e74abe686..3faa04a4f68a 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -130,8 +130,10 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
 	return gem_class_instance_to_eb_flags(gem_fd, e->class, e->instance);
 }
 
+#define TEST_BUSY (1)
+
 static void
-single(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
+single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 {
 	unsigned long slept;
 	igt_spin_t *spin;
@@ -140,7 +142,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
 
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
-	if (busy)
+	if (flags & TEST_BUSY)
 		spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
 	else
 		spin = NULL;
@@ -153,7 +155,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd);
 
-	assert_within_epsilon(val, busy ? slept : 0.f, tolerance);
+	assert_within_epsilon(val, flags & TEST_BUSY ? slept : 0.f, tolerance);
 	gem_quiescent_gpu(gem_fd);
 }
 
@@ -451,7 +453,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines)
 }
 
 static void
-no_sema(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
+no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 {
 	igt_spin_t *spin;
 	uint64_t val[2][2];
@@ -460,7 +462,7 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
 	fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
 	open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
 
-	if (busy)
+	if (flags & TEST_BUSY)
 		spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
 
 	pmu_read_multi(fd, 2, val[0]);
@@ -470,7 +472,7 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
 	val[0][0] = val[1][0] - val[0][0];
 	val[0][1] = val[1][1] - val[0][1];
 
-	if (busy) {
+	if (flags & TEST_BUSY) {
 		igt_spin_batch_end(spin);
 		gem_sync(gem_fd, spin->handle);
 		igt_spin_batch_free(gem_fd, spin);
@@ -1231,13 +1233,13 @@ igt_main
 		 * Test that engines show no load when idle.
 		 */
 		igt_subtest_f("idle-%s", e->name)
-			single(fd, e, false);
+			single(fd, e, 0);
 
 		/**
 		 * Test that a single engine reports load correctly.
 		 */
 		igt_subtest_f("busy-%s", e->name)
-			single(fd, e, true);
+			single(fd, e, TEST_BUSY);
 
 		/**
 		 * Test that when one engine is loaded other report no load.
@@ -1257,10 +1259,10 @@ igt_main
 		 * or busy engines.
 		 */
 		igt_subtest_f("idle-no-semaphores-%s", e->name)
-			no_sema(fd, e, false);
+			no_sema(fd, e, 0);
 
 		igt_subtest_f("busy-no-semaphores-%s", e->name)
-			no_sema(fd, e, true);
+			no_sema(fd, e, TEST_BUSY);
 
 		/**
 		 * Test that semaphore waits are correctly reported.
@@ -1358,7 +1360,7 @@ igt_main
 
 		for_each_engine_class_instance(fd, e) {
 			igt_subtest_f("render-node-busy-%s", e->name)
-				single(fd, e, true);
+				single(fd, e, TEST_BUSY);
 		}
 
 		igt_fixture {
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t 4/9] tests/perf_pmu: Convert to flags

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-02 18:37:49)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Will need more modes soon.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[igt-dev] [PATCH i-g-t 5/9] tests/perf_pmu: Add trailing edge idle test variants

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Additional set of tests which stops the batch and sleeps for a bit
before sampling the counter in order to test that the busyness stop
being recorded correctly.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/perf_pmu.c | 81 +++++++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 66 insertions(+), 15 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 3faa04a4f68a..27f32b8a1602 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -131,6 +131,21 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
 }
 
 #define TEST_BUSY (1)
+#define FLAG_SYNC (2)
+#define TEST_TRAILING_IDLE (4)
+
+static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
+{
+	if (!spin)
+		return;
+
+	igt_spin_batch_end(spin);
+
+	if (flags & FLAG_SYNC)
+		gem_sync(fd, spin->handle);
+	else
+		usleep(batch_duration_ns / 5000);
+}
 
 static void
 single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
@@ -149,9 +164,11 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 
 	val = pmu_read_single(fd);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (spin && (flags & TEST_TRAILING_IDLE))
+		end_spin(gem_fd, spin, flags);
 	val = pmu_read_single(fd) - val;
 
-	igt_spin_batch_end(spin);
+	end_spin(gem_fd, spin, flags | FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd);
 
@@ -281,7 +298,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val)
 
 static void
 busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
-	       const unsigned int num_engines)
+	       const unsigned int num_engines, unsigned int flags)
 {
 	const struct intel_execution_engine2 *e_;
 	uint64_t tval[2][num_engines];
@@ -309,9 +326,11 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		end_spin(gem_fd, spin, 0);
 	pmu_read_multi(fd[0], num_engines, tval[1]);
 
-	igt_spin_batch_end(spin);
+	end_spin(gem_fd, spin, flags | FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
@@ -331,7 +350,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 static void
 most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
-		    const unsigned int num_engines)
+		    const unsigned int num_engines, unsigned int flags)
 {
 	const struct intel_execution_engine2 *e_;
 	uint64_t tval[2][num_engines];
@@ -375,9 +394,11 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		end_spin(gem_fd, spin, 0);
 	pmu_read_multi(fd[0], num_engines, tval[1]);
 
-	igt_spin_batch_end(spin);
+	end_spin(gem_fd, spin, flags | FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
@@ -396,7 +417,8 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 }
 
 static void
-all_busy_check_all(int gem_fd, const unsigned int num_engines)
+all_busy_check_all(int gem_fd, const unsigned int num_engines,
+		   unsigned int flags)
 {
 	const struct intel_execution_engine2 *e;
 	uint64_t tval[2][num_engines];
@@ -436,9 +458,11 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines)
 
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		end_spin(gem_fd, spin, 0);
 	pmu_read_multi(fd[0], num_engines, tval[1]);
 
-	igt_spin_batch_end(spin);
+	end_spin(gem_fd, spin, flags | FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
@@ -464,17 +488,20 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 
 	if (flags & TEST_BUSY)
 		spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
+	else
+		spin = NULL;
 
 	pmu_read_multi(fd, 2, val[0]);
 	measured_usleep(batch_duration_ns / 1000);
+	if (spin && (flags & TEST_TRAILING_IDLE))
+		end_spin(gem_fd, spin, 0);
 	pmu_read_multi(fd, 2, val[1]);
 
 	val[0][0] = val[1][0] - val[0][0];
 	val[0][1] = val[1][1] - val[0][1];
 
-	if (flags & TEST_BUSY) {
-		igt_spin_batch_end(spin);
-		gem_sync(gem_fd, spin->handle);
+	if (spin) {
+		end_spin(gem_fd, spin, flags | FLAG_SYNC);
 		igt_spin_batch_free(gem_fd, spin);
 	}
 	close(fd);
@@ -489,7 +516,8 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 #define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)
 
 static void
-sema_wait(int gem_fd, const struct intel_execution_engine2 *e)
+sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
+	  unsigned int flags)
 {
 	struct drm_i915_gem_relocation_entry reloc[2] = {};
 	struct drm_i915_gem_exec_object2 obj[2] = {};
@@ -564,6 +592,8 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e)
 
 	val[0] = pmu_read_single(fd);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		obj_ptr[0] = 1;
 	val[1] = pmu_read_single(fd);
 	igt_debug("slept %.3fms, sampled %.3fms\n",
 		  slept*1e-6, (val[1] - val[0])*1e-6);
@@ -774,6 +804,8 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	uint64_t val[2];
 	int fd[2];
 
+	gem_quiescent_gpu(gem_fd);
+
 	fd[0] = open_pmu(config);
 
 	/*
@@ -1240,19 +1272,27 @@ igt_main
 		 */
 		igt_subtest_f("busy-%s", e->name)
 			single(fd, e, TEST_BUSY);
+		igt_subtest_f("busy-idle-%s", e->name)
+			single(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
 		/**
 		 * Test that when one engine is loaded other report no load.
 		 */
 		igt_subtest_f("busy-check-all-%s", e->name)
-			busy_check_all(fd, e, num_engines);
+			busy_check_all(fd, e, num_engines, TEST_BUSY);
+		igt_subtest_f("busy-idle-check-all-%s", e->name)
+			busy_check_all(fd, e, num_engines,
+				       TEST_BUSY | TEST_TRAILING_IDLE);
 
 		/**
 		 * Test that when all except one engine are loaded all loads
 		 * are correctly reported.
 		 */
 		igt_subtest_f("most-busy-check-all-%s", e->name)
-			most_busy_check_all(fd, e, num_engines);
+			most_busy_check_all(fd, e, num_engines, TEST_BUSY);
+		igt_subtest_f("most-busy-idle-check-all-%s", e->name)
+			most_busy_check_all(fd, e, num_engines,
+					    TEST_BUSY | TEST_TRAILING_IDLE);
 
 		/**
 		 * Test that semphore counters report no activity on idle
@@ -1264,11 +1304,17 @@ igt_main
 		igt_subtest_f("busy-no-semaphores-%s", e->name)
 			no_sema(fd, e, TEST_BUSY);
 
+		igt_subtest_f("busy-idle-no-semaphores-%s", e->name)
+			no_sema(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+
 		/**
 		 * Test that semaphore waits are correctly reported.
 		 */
 		igt_subtest_f("semaphore-wait-%s", e->name)
-			sema_wait(fd, e);
+			sema_wait(fd, e, TEST_BUSY);
+
+		igt_subtest_f("semaphore-wait-idle-%s", e->name)
+			sema_wait(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
 		/**
 		 * Test that event waits are correctly reported.
@@ -1304,7 +1350,10 @@ igt_main
 	 * correctly reported.
 	 */
 	igt_subtest("all-busy-check-all")
-		all_busy_check_all(fd, num_engines);
+		all_busy_check_all(fd, num_engines, TEST_BUSY);
+	igt_subtest("all-busy-idle-check-all")
+		all_busy_check_all(fd, num_engines,
+				   TEST_BUSY | TEST_TRAILING_IDLE);
 
 	/**
 	 * Test that non-engine counters can be initialized and read. Apart
@@ -1361,6 +1410,8 @@ igt_main
 		for_each_engine_class_instance(fd, e) {
 			igt_subtest_f("render-node-busy-%s", e->name)
 				single(fd, e, TEST_BUSY);
+			igt_subtest_f("render-node-busy-idle-%s", e->name)
+				single(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
 		}
 
 		igt_fixture {
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t 5/9] tests/perf_pmu: Add trailing edge idle test variants

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-02 18:37:50)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Additional set of tests which stops the batch and sleeps for a bit
> before sampling the counter in order to test that the busyness stop
> being recorded correctly.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  tests/perf_pmu.c | 81 +++++++++++++++++++++++++++++++++++++++++++++-----------
>  1 file changed, 66 insertions(+), 15 deletions(-)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 3faa04a4f68a..27f32b8a1602 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -131,6 +131,21 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
>  }
>  
>  #define TEST_BUSY (1)
> +#define FLAG_SYNC (2)
> +#define TEST_TRAILING_IDLE (4)
> +
> +static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
> +{
> +       if (!spin)
> +               return;
> +
> +       igt_spin_batch_end(spin);
> +
> +       if (flags & FLAG_SYNC)
> +               gem_sync(fd, spin->handle);
> +       else
> +               usleep(batch_duration_ns / 5000);

Split this to

	if (flags & FLAG_SYNC)
		gem_sync();
	
	if (flags & TEST_TRAILING_IDLE)
		usleep();

That keeps it descriptive.

> +}
>  
>  static void
>  single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> @@ -149,9 +164,11 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
>  
>         val = pmu_read_single(fd);
>         slept = measured_usleep(batch_duration_ns / 1000);
> +       if (spin && (flags & TEST_TRAILING_IDLE))
> +               end_spin(gem_fd, spin, flags);

Can simplify and miss the first if (spin) here as end_spin does it for
you. And later again in no_sema()

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [igt-dev] [PATCH i-g-t 5/9] tests/perf_pmu: Add trailing edge idle test variants

[Tvrtko Ursulin]

On 02/02/2018 20:45, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-02 18:37:50)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Additional set of tests which stops the batch and sleeps for a bit
>> before sampling the counter in order to test that the busyness stop
>> being recorded correctly.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>>   tests/perf_pmu.c | 81 +++++++++++++++++++++++++++++++++++++++++++++-----------
>>   1 file changed, 66 insertions(+), 15 deletions(-)
>>
>> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
>> index 3faa04a4f68a..27f32b8a1602 100644
>> --- a/tests/perf_pmu.c
>> +++ b/tests/perf_pmu.c
>> @@ -131,6 +131,21 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
>>   }
>>   
>>   #define TEST_BUSY (1)
>> +#define FLAG_SYNC (2)
>> +#define TEST_TRAILING_IDLE (4)
>> +
>> +static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>> +{
>> +       if (!spin)
>> +               return;
>> +
>> +       igt_spin_batch_end(spin);
>> +
>> +       if (flags & FLAG_SYNC)
>> +               gem_sync(fd, spin->handle);
>> +       else
>> +               usleep(batch_duration_ns / 5000);
> 
> Split this to
> 
> 	if (flags & FLAG_SYNC)
> 		gem_sync();
> 	
> 	if (flags & TEST_TRAILING_IDLE)
> 		usleep();
> 
> That keeps it descriptive.

I wanted to only do one per invocation. For tests that have flags = 
TEST_TRAILING_IDLE | FLAG_SYNC, but I think I can also change those to 
not or the flags on the second invocation but only pass in FLAG_SYNC. I 
think it works for now.

>> +}
>>   
>>   static void
>>   single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
>> @@ -149,9 +164,11 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
>>   
>>          val = pmu_read_single(fd);
>>          slept = measured_usleep(batch_duration_ns / 1000);
>> +       if (spin && (flags & TEST_TRAILING_IDLE))
>> +               end_spin(gem_fd, spin, flags);
> 
> Can simplify and miss the first if (spin) here as end_spin does it for
> you. And later again in no_sema()

True.

> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Thanks, I'll sent the updated version.

Regards,

Tvrtko
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[igt-dev] [PATCH i-g-t v2 5/9] tests/perf_pmu: Add trailing edge idle test variants

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Additional set of tests which stops the batch and sleeps for a bit
before sampling the counter in order to test that the busyness stop
being recorded correctly.

v2: Reorganize end_spin and guards a bit. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v1
---
 tests/perf_pmu.c | 82 +++++++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 67 insertions(+), 15 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 3faa04a4f68a..5c7eb28a3920 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -131,6 +131,22 @@ static unsigned int e2ring(int gem_fd, const struct intel_execution_engine2 *e)
 }
 
 #define TEST_BUSY (1)
+#define FLAG_SYNC (2)
+#define TEST_TRAILING_IDLE (4)
+
+static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
+{
+	if (!spin)
+		return;
+
+	igt_spin_batch_end(spin);
+
+	if (flags & FLAG_SYNC)
+		gem_sync(fd, spin->handle);
+
+	if (flags & TEST_TRAILING_IDLE)
+		usleep(batch_duration_ns / 5000);
+}
 
 static void
 single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
@@ -149,9 +165,11 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 
 	val = pmu_read_single(fd);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		end_spin(gem_fd, spin, flags);
 	val = pmu_read_single(fd) - val;
 
-	igt_spin_batch_end(spin);
+	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd);
 
@@ -281,7 +299,7 @@ static void log_busy(unsigned int num_engines, uint64_t *val)
 
 static void
 busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
-	       const unsigned int num_engines)
+	       const unsigned int num_engines, unsigned int flags)
 {
 	const struct intel_execution_engine2 *e_;
 	uint64_t tval[2][num_engines];
@@ -309,9 +327,11 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		end_spin(gem_fd, spin, flags);
 	pmu_read_multi(fd[0], num_engines, tval[1]);
 
-	igt_spin_batch_end(spin);
+	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
@@ -331,7 +351,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 static void
 most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
-		    const unsigned int num_engines)
+		    const unsigned int num_engines, unsigned int flags)
 {
 	const struct intel_execution_engine2 *e_;
 	uint64_t tval[2][num_engines];
@@ -375,9 +395,11 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		end_spin(gem_fd, spin, flags);
 	pmu_read_multi(fd[0], num_engines, tval[1]);
 
-	igt_spin_batch_end(spin);
+	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
@@ -396,7 +418,8 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 }
 
 static void
-all_busy_check_all(int gem_fd, const unsigned int num_engines)
+all_busy_check_all(int gem_fd, const unsigned int num_engines,
+		   unsigned int flags)
 {
 	const struct intel_execution_engine2 *e;
 	uint64_t tval[2][num_engines];
@@ -436,9 +459,11 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines)
 
 	pmu_read_multi(fd[0], num_engines, tval[0]);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		end_spin(gem_fd, spin, flags);
 	pmu_read_multi(fd[0], num_engines, tval[1]);
 
-	igt_spin_batch_end(spin);
+	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
 	close(fd[0]);
 
@@ -464,17 +489,20 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 
 	if (flags & TEST_BUSY)
 		spin = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
+	else
+		spin = NULL;
 
 	pmu_read_multi(fd, 2, val[0]);
 	measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		end_spin(gem_fd, spin, flags);
 	pmu_read_multi(fd, 2, val[1]);
 
 	val[0][0] = val[1][0] - val[0][0];
 	val[0][1] = val[1][1] - val[0][1];
 
-	if (flags & TEST_BUSY) {
-		igt_spin_batch_end(spin);
-		gem_sync(gem_fd, spin->handle);
+	if (spin) {
+		end_spin(gem_fd, spin, FLAG_SYNC);
 		igt_spin_batch_free(gem_fd, spin);
 	}
 	close(fd);
@@ -489,7 +517,8 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 #define   MI_SEMAPHORE_SAD_GTE_SDD	(1<<12)
 
 static void
-sema_wait(int gem_fd, const struct intel_execution_engine2 *e)
+sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
+	  unsigned int flags)
 {
 	struct drm_i915_gem_relocation_entry reloc[2] = {};
 	struct drm_i915_gem_exec_object2 obj[2] = {};
@@ -564,6 +593,8 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e)
 
 	val[0] = pmu_read_single(fd);
 	slept = measured_usleep(batch_duration_ns / 1000);
+	if (flags & TEST_TRAILING_IDLE)
+		obj_ptr[0] = 1;
 	val[1] = pmu_read_single(fd);
 	igt_debug("slept %.3fms, sampled %.3fms\n",
 		  slept*1e-6, (val[1] - val[0])*1e-6);
@@ -774,6 +805,8 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	uint64_t val[2];
 	int fd[2];
 
+	gem_quiescent_gpu(gem_fd);
+
 	fd[0] = open_pmu(config);
 
 	/*
@@ -1240,19 +1273,27 @@ igt_main
 		 */
 		igt_subtest_f("busy-%s", e->name)
 			single(fd, e, TEST_BUSY);
+		igt_subtest_f("busy-idle-%s", e->name)
+			single(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
 		/**
 		 * Test that when one engine is loaded other report no load.
 		 */
 		igt_subtest_f("busy-check-all-%s", e->name)
-			busy_check_all(fd, e, num_engines);
+			busy_check_all(fd, e, num_engines, TEST_BUSY);
+		igt_subtest_f("busy-idle-check-all-%s", e->name)
+			busy_check_all(fd, e, num_engines,
+				       TEST_BUSY | TEST_TRAILING_IDLE);
 
 		/**
 		 * Test that when all except one engine are loaded all loads
 		 * are correctly reported.
 		 */
 		igt_subtest_f("most-busy-check-all-%s", e->name)
-			most_busy_check_all(fd, e, num_engines);
+			most_busy_check_all(fd, e, num_engines, TEST_BUSY);
+		igt_subtest_f("most-busy-idle-check-all-%s", e->name)
+			most_busy_check_all(fd, e, num_engines,
+					    TEST_BUSY | TEST_TRAILING_IDLE);
 
 		/**
 		 * Test that semphore counters report no activity on idle
@@ -1264,11 +1305,17 @@ igt_main
 		igt_subtest_f("busy-no-semaphores-%s", e->name)
 			no_sema(fd, e, TEST_BUSY);
 
+		igt_subtest_f("busy-idle-no-semaphores-%s", e->name)
+			no_sema(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+
 		/**
 		 * Test that semaphore waits are correctly reported.
 		 */
 		igt_subtest_f("semaphore-wait-%s", e->name)
-			sema_wait(fd, e);
+			sema_wait(fd, e, TEST_BUSY);
+
+		igt_subtest_f("semaphore-wait-idle-%s", e->name)
+			sema_wait(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
 		/**
 		 * Test that event waits are correctly reported.
@@ -1304,7 +1351,10 @@ igt_main
 	 * correctly reported.
 	 */
 	igt_subtest("all-busy-check-all")
-		all_busy_check_all(fd, num_engines);
+		all_busy_check_all(fd, num_engines, TEST_BUSY);
+	igt_subtest("all-busy-idle-check-all")
+		all_busy_check_all(fd, num_engines,
+				   TEST_BUSY | TEST_TRAILING_IDLE);
 
 	/**
 	 * Test that non-engine counters can be initialized and read. Apart
@@ -1361,6 +1411,8 @@ igt_main
 		for_each_engine_class_instance(fd, e) {
 			igt_subtest_f("render-node-busy-%s", e->name)
 				single(fd, e, TEST_BUSY);
+			igt_subtest_f("render-node-busy-idle-%s", e->name)
+				single(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
 		}
 
 		igt_fixture {
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t v2 5/9] tests/perf_pmu: Add trailing edge idle test variants

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-05 11:36:12)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Additional set of tests which stops the batch and sleeps for a bit
> before sampling the counter in order to test that the busyness stop
> being recorded correctly.
> 
> v2: Reorganize end_spin and guards a bit. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v1

Lgtm,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[igt-dev] [PATCH i-g-t 6/9] tests/perf_pmu: PMU enable race test

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test that the PMU can be safely enabled in face of interrupt-heavy load on
an engine.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 27f32b8a1602..de0a1c7d936c 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1221,6 +1221,51 @@ test_rc6(int gem_fd)
 	assert_within_epsilon(busy - prev, 0.0, tolerance);
 }
 
+static void
+test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
+{
+	uint64_t config = I915_PMU_ENGINE_BUSY(e->class, e->instance);
+	struct igt_helper_process engine_load = { };
+	const uint32_t bbend = MI_BATCH_BUFFER_END;
+	struct drm_i915_gem_exec_object2 obj = { };
+	struct drm_i915_gem_execbuffer2 eb = { };
+	int fd;
+
+	igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
+	igt_require(gem_has_engine(gem_fd, e->class, e->instance));
+
+	obj.handle = gem_create(gem_fd, 4096);
+	gem_write(gem_fd, obj.handle, 0, &bbend, sizeof(bbend));
+
+	eb.buffer_count = 1;
+	eb.buffers_ptr = to_user_pointer(&obj);
+	eb.flags = e2ring(gem_fd, e);
+
+	/*
+	 * Defeat the busy stats delayed disable, we need to guarantee we are
+	 * the first user.
+	 */
+	sleep(2);
+
+	/* Apply interrupt-heavy load on the engine. */
+	igt_fork_helper(&engine_load) {
+		for (;;)
+			gem_execbuf(gem_fd, &eb);
+	}
+
+	/* Wait a bit to allow engine load to start. */
+	usleep(500e3);
+
+	/* Enable the PMU. */
+	fd = open_pmu(config);
+
+	/* Cleanup. */
+	igt_stop_helper(&engine_load);
+	close(fd);
+	gem_close(gem_fd, obj.handle);
+	gem_quiescent_gpu(gem_fd);
+}
+
 igt_main
 {
 	const unsigned int num_other_metrics =
@@ -1343,6 +1388,13 @@ igt_main
 		 */
 		igt_subtest_f("busy-double-start-%s", e->name)
 			busy_double_start(fd, e);
+
+		/**
+		 * Check that the PMU can be safely enabled in face of
+		 * interrupt-heavy engine load.
+		 */
+		igt_subtest_f("enable-race-%s", e->name)
+			test_enable_race(fd, e);
 	}
 
 	/**
-- 
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Re: [igt-dev] [PATCH i-g-t 6/9] tests/perf_pmu: PMU enable race test

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-02 18:37:51)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Test that the PMU can be safely enabled in face of interrupt-heavy load on
> an engine.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  tests/perf_pmu.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 27f32b8a1602..de0a1c7d936c 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -1221,6 +1221,51 @@ test_rc6(int gem_fd)
>         assert_within_epsilon(busy - prev, 0.0, tolerance);
>  }
>  
> +static void
> +test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
> +{
> +       uint64_t config = I915_PMU_ENGINE_BUSY(e->class, e->instance);
> +       struct igt_helper_process engine_load = { };
> +       const uint32_t bbend = MI_BATCH_BUFFER_END;
> +       struct drm_i915_gem_exec_object2 obj = { };
> +       struct drm_i915_gem_execbuffer2 eb = { };
> +       int fd;
> +
> +       igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);

	igt_require(gem_has_execlists(gem_fd));

may be clearer, it's still a proxy for has_stats. :|

> +       igt_require(gem_has_engine(gem_fd, e->class, e->instance));
> +
> +       obj.handle = gem_create(gem_fd, 4096);
> +       gem_write(gem_fd, obj.handle, 0, &bbend, sizeof(bbend));
> +
> +       eb.buffer_count = 1;
> +       eb.buffers_ptr = to_user_pointer(&obj);
> +       eb.flags = e2ring(gem_fd, e);
> +
> +       /*
> +        * Defeat the busy stats delayed disable, we need to guarantee we are
> +        * the first user.
> +        */

gem_quiescent_gpu(); as well?

> +       sleep(2);
> +
> +       /* Apply interrupt-heavy load on the engine. */

s/load/nop load/ ?

> +       igt_fork_helper(&engine_load) {
> +               for (;;)
> +                       gem_execbuf(gem_fd, &eb);
> +       }
> +
> +       /* Wait a bit to allow engine load to start. */
> +       usleep(500e3);

.5s, I guess we aren't too concerned with paring it down to the
minimum here as we've already spent 2s for idling.

> +
> +       /* Enable the PMU. */
> +       fd = open_pmu(config);

fd = -1;
igt_until_timeout(1) {
	close(fd);
	fd = open_pmu(config);
}

It's a race, so don't expect it to happen first time?

> +       /* Cleanup. */
> +       igt_stop_helper(&engine_load);
> +       close(fd);

Another race, right? Wrap it all in a 10x loop? Or separate out the
close race to another lop.

> +       gem_close(gem_fd, obj.handle);
> +       gem_quiescent_gpu(gem_fd);
> +}

The gist of the test looks fine, so please consider exercising the race
more than once and with that have a
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [igt-dev] [PATCH i-g-t 6/9] tests/perf_pmu: PMU enable race test

[Tvrtko Ursulin]

On 02/02/2018 20:52, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-02 18:37:51)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Test that the PMU can be safely enabled in face of interrupt-heavy load on
>> an engine.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   tests/perf_pmu.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
>>   1 file changed, 52 insertions(+)
>>
>> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
>> index 27f32b8a1602..de0a1c7d936c 100644
>> --- a/tests/perf_pmu.c
>> +++ b/tests/perf_pmu.c
>> @@ -1221,6 +1221,51 @@ test_rc6(int gem_fd)
>>          assert_within_epsilon(busy - prev, 0.0, tolerance);
>>   }
>>   
>> +static void
>> +test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
>> +{
>> +       uint64_t config = I915_PMU_ENGINE_BUSY(e->class, e->instance);
>> +       struct igt_helper_process engine_load = { };
>> +       const uint32_t bbend = MI_BATCH_BUFFER_END;
>> +       struct drm_i915_gem_exec_object2 obj = { };
>> +       struct drm_i915_gem_execbuffer2 eb = { };
>> +       int fd;
>> +
>> +       igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
> 
> 	igt_require(gem_has_execlists(gem_fd));
> 
> may be clearer, it's still a proxy for has_stats. :|

Better, yes.

> 
>> +       igt_require(gem_has_engine(gem_fd, e->class, e->instance));
>> +
>> +       obj.handle = gem_create(gem_fd, 4096);
>> +       gem_write(gem_fd, obj.handle, 0, &bbend, sizeof(bbend));
>> +
>> +       eb.buffer_count = 1;
>> +       eb.buffers_ptr = to_user_pointer(&obj);
>> +       eb.flags = e2ring(gem_fd, e);
>> +
>> +       /*
>> +        * Defeat the busy stats delayed disable, we need to guarantee we are
>> +        * the first user.
>> +        */
> 
> gem_quiescent_gpu(); as well?

Can do.

>> +       sleep(2);
>> +
>> +       /* Apply interrupt-heavy load on the engine. */
> 
> s/load/nop load/ ?
> 
>> +       igt_fork_helper(&engine_load) {
>> +               for (;;)
>> +                       gem_execbuf(gem_fd, &eb);
>> +       }
>> +
>> +       /* Wait a bit to allow engine load to start. */
>> +       usleep(500e3);
> 
> .5s, I guess we aren't too concerned with paring it down to the
> minimum here as we've already spent 2s for idling.
> 
>> +
>> +       /* Enable the PMU. */
>> +       fd = open_pmu(config);
> 
> fd = -1;
> igt_until_timeout(1) {
> 	close(fd);
> 	fd = open_pmu(config);
> }
> 
> It's a race, so don't expect it to happen first time?

Definitely don't, but the delayed disable currently makes it hard to 
test (slow).

> 
>> +       /* Cleanup. */
>> +       igt_stop_helper(&engine_load);
>> +       close(fd);
> 
> Another race, right? Wrap it all in a 10x loop? Or separate out the
> close race to another lop.

Don't think so, disable is done from the delayed worker already.

> 
>> +       gem_close(gem_fd, obj.handle);
>> +       gem_quiescent_gpu(gem_fd);
>> +}
> 
> The gist of the test looks fine, so please consider exercising the race
> more than once and with that have a
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

I can wrap it in a 10x loop but until the PMU is fixed that means 10x 
longer runtime as well which I wanted to avoid, and instead count on 
execution in numbers across the shards.

Regards,

Tvrtko
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Re: [igt-dev] [PATCH i-g-t 6/9] tests/perf_pmu: PMU enable race test

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-05 10:07:02)
> I can wrap it in a 10x loop but until the PMU is fixed that means 10x 
> longer runtime as well which I wanted to avoid, and instead count on 
> execution in numbers across the shards.

Otoh, I want a test that we can reliably run locally to determine if we
have a problem or not. A difficult balance. What should we aim for
flip-floppy tests, >50% error rate? >10%? Certainly has to be >1% or we
will struggle to notice the pattern. My finger in the air would say >33%.
-Chris
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Re: [igt-dev] [PATCH i-g-t 6/9] tests/perf_pmu: PMU enable race test

[Tvrtko Ursulin]

On 05/02/2018 10:16, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-05 10:07:02)
>> I can wrap it in a 10x loop but until the PMU is fixed that means 10x
>> longer runtime as well which I wanted to avoid, and instead count on
>> execution in numbers across the shards.
> 
> Otoh, I want a test that we can reliably run locally to determine if we
> have a problem or not. A difficult balance. What should we aim for
> flip-floppy tests, >50% error rate? >10%? Certainly has to be >1% or we
> will struggle to notice the pattern. My finger in the air would say >33%.

I don't know how we do that since it will depend on so many factors. On 
my SKL GT2 and my kernel config, it is maybe around 10%. So if we cannot 
reach >33% what do we, don't add the test?

Regards,

Tvrtko
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Re: [igt-dev] [PATCH i-g-t 6/9] tests/perf_pmu: PMU enable race test

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-05 10:40:01)
> 
> On 05/02/2018 10:16, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-02-05 10:07:02)
> >> I can wrap it in a 10x loop but until the PMU is fixed that means 10x
> >> longer runtime as well which I wanted to avoid, and instead count on
> >> execution in numbers across the shards.
> > 
> > Otoh, I want a test that we can reliably run locally to determine if we
> > have a problem or not. A difficult balance. What should we aim for
> > flip-floppy tests, >50% error rate? >10%? Certainly has to be >1% or we
> > will struggle to notice the pattern. My finger in the air would say >33%.
> 
> I don't know how we do that since it will depend on so many factors. On 
> my SKL GT2 and my kernel config, it is maybe around 10%. So if we cannot 
> reach >33% what do we, don't add the test?

I'm flexible, though if we can't force it to hit the race even when we
know what we're looking for, that doesn't bode well :) I think if we
knowingly add a flip-flop, we at least try to capture what the
reliability of the test is for a given setup in the changelog and
comments. Just so we know what we are looking at in 6 months time.
-Chris
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[igt-dev] [PATCH i-g-t v3 6/9] tests/perf_pmu: PMU enable race test

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test that the PMU can be safely enabled in face of interrupt-heavy load on
an engine.

The test is probabilistic so run it for ten seconds in a loop to increase
the odds of hitting the race.

v2: Repeat the test a few times, until a timeout. (Chris Wilson)
v3: Added note in code and commit about probabilistic nature of the test.
    (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/perf_pmu.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 5c7eb28a3920..9559cc3030ef 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1222,6 +1222,60 @@ test_rc6(int gem_fd)
 	assert_within_epsilon(busy - prev, 0.0, tolerance);
 }
 
+static void
+test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
+{
+	uint64_t config = I915_PMU_ENGINE_BUSY(e->class, e->instance);
+	struct igt_helper_process engine_load = { };
+	const uint32_t bbend = MI_BATCH_BUFFER_END;
+	struct drm_i915_gem_exec_object2 obj = { };
+	struct drm_i915_gem_execbuffer2 eb = { };
+	int fd;
+
+	igt_require(gem_has_execlists(gem_fd));
+	igt_require(gem_has_engine(gem_fd, e->class, e->instance));
+
+	obj.handle = gem_create(gem_fd, 4096);
+	gem_write(gem_fd, obj.handle, 0, &bbend, sizeof(bbend));
+
+	eb.buffer_count = 1;
+	eb.buffers_ptr = to_user_pointer(&obj);
+	eb.flags = e2ring(gem_fd, e);
+
+	/*
+	 * This test is probabilistic so run in a few times to increase the
+	 * chance of hitting the race.
+	 */
+	igt_until_timeout(10) {
+		/*
+		 * Defeat the busy stats delayed disable, we need to guarantee
+		 * we are the first PMU user.
+		 */
+		gem_quiescent_gpu(gem_fd);
+		sleep(2);
+
+		/* Apply interrupt-heavy load on the engine. */
+		igt_fork_helper(&engine_load) {
+			for (;;)
+				gem_execbuf(gem_fd, &eb);
+		}
+
+		/* Wait a bit to allow engine load to start. */
+		usleep(500e3);
+
+		/* Enable the PMU. */
+		fd = open_pmu(config);
+
+		/* Stop load and close the PMU. */
+		igt_stop_helper(&engine_load);
+		close(fd);
+	}
+
+	/* Cleanup. */
+	gem_close(gem_fd, obj.handle);
+	gem_quiescent_gpu(gem_fd);
+}
+
 igt_main
 {
 	const unsigned int num_other_metrics =
@@ -1344,6 +1398,13 @@ igt_main
 		 */
 		igt_subtest_f("busy-double-start-%s", e->name)
 			busy_double_start(fd, e);
+
+		/**
+		 * Check that the PMU can be safely enabled in face of
+		 * interrupt-heavy engine load.
+		 */
+		igt_subtest_f("enable-race-%s", e->name)
+			test_enable_race(fd, e);
 	}
 
 	/**
-- 
2.14.1

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[igt-dev] [PATCH i-g-t v2 6/9] tests/perf_pmu: PMU enable race test

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test that the PMU can be safely enabled in face of interrupt-heavy load on
an engine.

v2: Repeat the test a few times, until a timeout. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/perf_pmu.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 5c7eb28a3920..ae322fd869d8 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -1222,6 +1222,56 @@ test_rc6(int gem_fd)
 	assert_within_epsilon(busy - prev, 0.0, tolerance);
 }
 
+static void
+test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
+{
+	uint64_t config = I915_PMU_ENGINE_BUSY(e->class, e->instance);
+	struct igt_helper_process engine_load = { };
+	const uint32_t bbend = MI_BATCH_BUFFER_END;
+	struct drm_i915_gem_exec_object2 obj = { };
+	struct drm_i915_gem_execbuffer2 eb = { };
+	int fd;
+
+	igt_require(gem_has_execlists(gem_fd));
+	igt_require(gem_has_engine(gem_fd, e->class, e->instance));
+
+	obj.handle = gem_create(gem_fd, 4096);
+	gem_write(gem_fd, obj.handle, 0, &bbend, sizeof(bbend));
+
+	eb.buffer_count = 1;
+	eb.buffers_ptr = to_user_pointer(&obj);
+	eb.flags = e2ring(gem_fd, e);
+
+	igt_until_timeout(10) {
+		/*
+		 * Defeat the busy stats delayed disable, we need to guarantee
+		 * we are the first PMU user.
+		 */
+		gem_quiescent_gpu(gem_fd);
+		sleep(2);
+
+		/* Apply interrupt-heavy load on the engine. */
+		igt_fork_helper(&engine_load) {
+			for (;;)
+				gem_execbuf(gem_fd, &eb);
+		}
+
+		/* Wait a bit to allow engine load to start. */
+		usleep(500e3);
+
+		/* Enable the PMU. */
+		fd = open_pmu(config);
+
+		/* Stop load and close the PMU. */
+		igt_stop_helper(&engine_load);
+		close(fd);
+	}
+
+	/* Cleanup. */
+	gem_close(gem_fd, obj.handle);
+	gem_quiescent_gpu(gem_fd);
+}
+
 igt_main
 {
 	const unsigned int num_other_metrics =
@@ -1344,6 +1394,13 @@ igt_main
 		 */
 		igt_subtest_f("busy-double-start-%s", e->name)
 			busy_double_start(fd, e);
+
+		/**
+		 * Check that the PMU can be safely enabled in face of
+		 * interrupt-heavy engine load.
+		 */
+		igt_subtest_f("enable-race-%s", e->name)
+			test_enable_race(fd, e);
 	}
 
 	/**
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t v2 6/9] tests/perf_pmu: PMU enable race test

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-05 11:36:40)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Test that the PMU can be safely enabled in face of interrupt-heavy load on
> an engine.
> 
> v2: Repeat the test a few times, until a timeout. (Chris Wilson)

I'm happy with that compromise, yup. Personally I tend to pass the
timeout in as a parameter and quite often repeat the test with a longer
timeout much to everyone's chagrin.
-Chris
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[igt-dev] [PATCH i-g-t 7/9] tests/perf_pmu: Always skip missing engines

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Always skip missing engines to make tests skips very early and avoid
losing time in tests which need to do setups or waits before they would
otherwise detect this.

To ensure PMU is rejecting opening missing engines we will add an explicit
test later.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index de0a1c7d936c..d654ece63bb7 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -155,6 +155,8 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	uint64_t val;
 	int fd;
 
+	gem_require_engine(gem_fd, e->class, e->instance);
+
 	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
 
 	if (flags & TEST_BUSY)
@@ -184,6 +186,8 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
 	uint64_t val;
 	int fd;
 
+	gem_require_engine(gem_fd, e->class, e->instance);
+
 	/*
 	 * Defeat the busy stats delayed disable, we need to guarantee we are
 	 * the first user.
@@ -225,6 +229,8 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
 	uint32_t ctx;
 	int fd;
 
+	gem_require_engine(gem_fd, e->class, e->instance);
+
 	ctx = gem_context_create(gem_fd);
 
 	/*
@@ -308,6 +314,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	igt_spin_t *spin;
 	unsigned int busy_idx, i;
 
+	gem_require_engine(gem_fd, e->class, e->instance);
+
 	i = 0;
 	fd[0] = -1;
 	for_each_engine_class_instance(fd, e_) {
@@ -483,6 +491,8 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
 	uint64_t val[2][2];
 	int fd;
 
+	gem_require_engine(gem_fd, e->class, e->instance);
+
 	fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
 	open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
 
@@ -530,6 +540,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
 	int fd;
 
 	igt_require(intel_gen(intel_get_drm_devid(gem_fd)) >= 8);
+	gem_require_engine(gem_fd, e->class, e->instance);
 
 	/**
 	 * Setup up a batchbuffer with a polling semaphore wait command which
@@ -688,6 +699,7 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
 	devid = intel_get_drm_devid(gem_fd);
 	igt_require(intel_gen(devid) >= 7);
 	igt_skip_on(IS_VALLEYVIEW(devid) || IS_CHERRYVIEW(devid));
+	gem_require_engine(gem_fd, e->class, e->instance);
 
 	kmstest_set_vt_graphics_mode();
 	igt_display_init(&data.display, gem_fd);
@@ -804,6 +816,8 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	uint64_t val[2];
 	int fd[2];
 
+	gem_require_engine(gem_fd, e->class, e->instance);
+
 	gem_quiescent_gpu(gem_fd);
 
 	fd[0] = open_pmu(config);
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t 7/9] tests/perf_pmu: Always skip missing engines

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-02 18:37:52)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Always skip missing engines to make tests skips very early and avoid
> losing time in tests which need to do setups or waits before they would
> otherwise detect this.
> 
> To ensure PMU is rejecting opening missing engines we will add an explicit
> test later.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  tests/perf_pmu.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index de0a1c7d936c..d654ece63bb7 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -155,6 +155,8 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
>         uint64_t val;
>         int fd;
>  
> +       gem_require_engine(gem_fd, e->class, e->instance);
> +
>         fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
>  
>         if (flags & TEST_BUSY)

I feel these probably deserve to be in an
for_each_engine(...)
	igt_subtest_group {
		igt_fixture {
			gem_require_engine(...)
		}

		igt_subtest() {
			single(...)
		}
		etc.
	}
-Chris
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[igt-dev] [PATCH i-g-t v2 7/9] tests/perf_pmu: Always skip missing engines

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Always skip missing engines to make tests skips very early and avoid
losing time in tests which need to do setups or waits before they would
otherwise detect this.

To ensure PMU is rejecting opening missing engines we will add an explicit
test later.

v2: Use subtest groups for engine checking. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 191 ++++++++++++++++++++++++++++++-------------------------
 1 file changed, 105 insertions(+), 86 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index ae322fd869d8..d00838c41333 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -361,8 +361,6 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
 	igt_spin_t *spin = NULL;
 	unsigned int idle_idx, i;
 
-	gem_require_engine(gem_fd, e->class, e->instance);
-
 	i = 0;
 	for_each_engine_class_instance(fd, e_) {
 		if (!gem_has_engine(gem_fd, e_->class, e_->instance))
@@ -1301,7 +1299,8 @@ igt_main
 
 	for_each_engine_class_instance(fd, e) {
 		/**
-		 * Test that a single engine metric can be initialized.
+		 * Test that a single engine metric can be initialized or it
+		 * is correctly rejected.
 		 */
 		igt_subtest_f("init-busy-%s", e->name)
 			init(fd, e, I915_SAMPLE_BUSY);
@@ -1312,60 +1311,98 @@ igt_main
 		igt_subtest_f("init-sema-%s", e->name)
 			init(fd, e, I915_SAMPLE_SEMA);
 
-		/**
-		 * Test that engines show no load when idle.
-		 */
-		igt_subtest_f("idle-%s", e->name)
-			single(fd, e, 0);
-
-		/**
-		 * Test that a single engine reports load correctly.
-		 */
-		igt_subtest_f("busy-%s", e->name)
-			single(fd, e, TEST_BUSY);
-		igt_subtest_f("busy-idle-%s", e->name)
-			single(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
-
-		/**
-		 * Test that when one engine is loaded other report no load.
-		 */
-		igt_subtest_f("busy-check-all-%s", e->name)
-			busy_check_all(fd, e, num_engines, TEST_BUSY);
-		igt_subtest_f("busy-idle-check-all-%s", e->name)
-			busy_check_all(fd, e, num_engines,
-				       TEST_BUSY | TEST_TRAILING_IDLE);
-
-		/**
-		 * Test that when all except one engine are loaded all loads
-		 * are correctly reported.
-		 */
-		igt_subtest_f("most-busy-check-all-%s", e->name)
-			most_busy_check_all(fd, e, num_engines, TEST_BUSY);
-		igt_subtest_f("most-busy-idle-check-all-%s", e->name)
-			most_busy_check_all(fd, e, num_engines,
-					    TEST_BUSY | TEST_TRAILING_IDLE);
-
-		/**
-		 * Test that semphore counters report no activity on idle
-		 * or busy engines.
-		 */
-		igt_subtest_f("idle-no-semaphores-%s", e->name)
-			no_sema(fd, e, 0);
-
-		igt_subtest_f("busy-no-semaphores-%s", e->name)
-			no_sema(fd, e, TEST_BUSY);
+		igt_subtest_group {
+			igt_fixture {
+				gem_require_engine(fd, e->class, e->instance);
+			}
 
-		igt_subtest_f("busy-idle-no-semaphores-%s", e->name)
-			no_sema(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+			/**
+			 * Test that engines show no load when idle.
+			 */
+			igt_subtest_f("idle-%s", e->name)
+				single(fd, e, 0);
 
-		/**
-		 * Test that semaphore waits are correctly reported.
-		 */
-		igt_subtest_f("semaphore-wait-%s", e->name)
-			sema_wait(fd, e, TEST_BUSY);
+			/**
+			 * Test that a single engine reports load correctly.
+			 */
+			igt_subtest_f("busy-%s", e->name)
+				single(fd, e, TEST_BUSY);
+			igt_subtest_f("busy-idle-%s", e->name)
+				single(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
 
-		igt_subtest_f("semaphore-wait-idle-%s", e->name)
-			sema_wait(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+			/**
+			 * Test that when one engine is loaded other report no
+			 * load.
+			 */
+			igt_subtest_f("busy-check-all-%s", e->name)
+				busy_check_all(fd, e, num_engines, TEST_BUSY);
+			igt_subtest_f("busy-idle-check-all-%s", e->name)
+				busy_check_all(fd, e, num_engines,
+					       TEST_BUSY | TEST_TRAILING_IDLE);
+
+			/**
+			 * Test that when all except one engine are loaded all
+			 * loads are correctly reported.
+			 */
+			igt_subtest_f("most-busy-check-all-%s", e->name)
+				most_busy_check_all(fd, e, num_engines,
+						    TEST_BUSY);
+			igt_subtest_f("most-busy-idle-check-all-%s", e->name)
+				most_busy_check_all(fd, e, num_engines,
+						    TEST_BUSY |
+						    TEST_TRAILING_IDLE);
+
+			/**
+			 * Test that semphore counters report no activity on
+			 * idle or busy engines.
+			 */
+			igt_subtest_f("idle-no-semaphores-%s", e->name)
+				no_sema(fd, e, 0);
+
+			igt_subtest_f("busy-no-semaphores-%s", e->name)
+				no_sema(fd, e, TEST_BUSY);
+
+			igt_subtest_f("busy-idle-no-semaphores-%s", e->name)
+				no_sema(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+
+			/**
+			 * Test that semaphore waits are correctly reported.
+			 */
+			igt_subtest_f("semaphore-wait-%s", e->name)
+				sema_wait(fd, e, TEST_BUSY);
+
+			igt_subtest_f("semaphore-wait-idle-%s", e->name)
+				sema_wait(fd, e,
+					  TEST_BUSY | TEST_TRAILING_IDLE);
+
+			/**
+			 * Check that two perf clients do not influence each
+			 * others observations.
+			 */
+			igt_subtest_f("multi-client-%s", e->name)
+				multi_client(fd, e);
+
+			/**
+			* Check that reported usage is correct when PMU is
+			* enabled after the batch is running.
+			*/
+			igt_subtest_f("busy-start-%s", e->name)
+				busy_start(fd, e);
+
+			/**
+			 * Check that reported usage is correct when PMU is
+			 * enabled after two batches are running.
+			 */
+			igt_subtest_f("busy-double-start-%s", e->name)
+				busy_double_start(fd, e);
+
+			/**
+			 * Check that the PMU can be safely enabled in face of
+			 * interrupt-heavy engine load.
+			 */
+			igt_subtest_f("enable-race-%s", e->name)
+				test_enable_race(fd, e);
+		}
 
 		/**
 		 * Test that event waits are correctly reported.
@@ -1373,34 +1410,6 @@ igt_main
 		if (e->class == I915_ENGINE_CLASS_RENDER)
 			igt_subtest_f("event-wait-%s", e->name)
 				event_wait(fd, e);
-
-		/**
-		 * Check that two perf clients do not influence each others
-		 * observations.
-		 */
-		igt_subtest_f("multi-client-%s", e->name)
-			multi_client(fd, e);
-
-		/**
-		 * Check that reported usage is correct when PMU is enabled
-		 * after the batch is running.
-		 */
-		igt_subtest_f("busy-start-%s", e->name)
-			busy_start(fd, e);
-
-		/**
-		 * Check that reported usage is correct when PMU is enabled
-		 * after two batches are running.
-		 */
-		igt_subtest_f("busy-double-start-%s", e->name)
-			busy_double_start(fd, e);
-
-		/**
-		 * Check that the PMU can be safely enabled in face of
-		 * interrupt-heavy engine load.
-		 */
-		igt_subtest_f("enable-race-%s", e->name)
-			test_enable_race(fd, e);
 	}
 
 	/**
@@ -1466,10 +1475,20 @@ igt_main
 		}
 
 		for_each_engine_class_instance(fd, e) {
-			igt_subtest_f("render-node-busy-%s", e->name)
-				single(fd, e, TEST_BUSY);
-			igt_subtest_f("render-node-busy-idle-%s", e->name)
-				single(fd, e, TEST_BUSY | TEST_TRAILING_IDLE);
+			igt_subtest_group {
+				igt_fixture {
+					gem_require_engine(render_fd,
+							   e->class,
+							   e->instance);
+				}
+
+				igt_subtest_f("render-node-busy-%s", e->name)
+					single(fd, e, TEST_BUSY);
+				igt_subtest_f("render-node-busy-idle-%s",
+					      e->name)
+					single(fd, e,
+					       TEST_BUSY | TEST_TRAILING_IDLE);
+			}
 		}
 
 		igt_fixture {
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t v2 7/9] tests/perf_pmu: Always skip missing engines

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-05 11:37:10)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Always skip missing engines to make tests skips very early and avoid
> losing time in tests which need to do setups or waits before they would
> otherwise detect this.
> 
> To ensure PMU is rejecting opening missing engines we will add an explicit
> test later.
> 
> v2: Use subtest groups for engine checking. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[igt-dev] [PATCH i-g-t 8/9] tests/perf_pmu: Explicitly test for engine availability in init tests

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test will succeed if present engine can be opened, or if the missing
engine reports the correct error code.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index d654ece63bb7..201aa0b40068 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -74,7 +74,12 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
 {
 	int fd;
 
-	fd = open_pmu(__I915_PMU_ENGINE(e->class, e->instance, sample));
+	fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+
+	if (gem_has_engine(gem_fd, e->class, e->instance))
+		igt_assert(fd >= 0);
+	else
+		igt_assert(fd < 0 && errno == ENODEV);
 
 	close(fd);
 }
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t 8/9] tests/perf_pmu: Explicitly test for engine availability in init tests

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-02 18:37:53)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Test will succeed if present engine can be opened, or if the missing
> engine reports the correct error code.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  tests/perf_pmu.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index d654ece63bb7..201aa0b40068 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -74,7 +74,12 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
>  {
>         int fd;
>  
> -       fd = open_pmu(__I915_PMU_ENGINE(e->class, e->instance, sample));
> +       fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
> +
> +       if (gem_has_engine(gem_fd, e->class, e->instance))
> +               igt_assert(fd >= 0);
> +       else
> +               igt_assert(fd < 0 && errno == ENODEV);
>  
>         close(fd);

Be valgrind friendly and only close() after success.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

(Do I have to go looking for other cases where we could be checking for
missed invalid tests? I hope not!)
-Chris
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[igt-dev] [PATCH i-g-t v2 8/9] tests/perf_pmu: Explicitly test for engine availability in init tests

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test will succeed if present engine can be opened, or if the missing
engine reports the correct error code.

v2:
 * Use the right errno.
 * Close fd only on success. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v1
---
 tests/perf_pmu.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index d00838c41333..260b04b09c86 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -72,11 +72,20 @@ static int open_group(uint64_t config, int group)
 static void
 init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
 {
-	int fd;
+	int fd, err = 0;
 
-	fd = open_pmu(__I915_PMU_ENGINE(e->class, e->instance, sample));
+	errno = 0;
+	fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+	err = errno;
 
-	close(fd);
+	if (gem_has_engine(gem_fd, e->class, e->instance)) {
+		igt_assert_eq(err, 0);
+		igt_assert_fd(fd);
+		close(fd);
+	} else {
+		igt_assert_lt(fd, 0);
+		igt_assert_eq(err, ENODEV);
+	}
 }
 
 static uint64_t pmu_read_single(int fd)
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t v2 8/9] tests/perf_pmu: Explicitly test for engine availability in init tests

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-05 11:37:41)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Test will succeed if present engine can be opened, or if the missing
> engine reports the correct error code.
> 
> v2:
>  * Use the right errno.
>  * Close fd only on success. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> # v1
> ---
>  tests/perf_pmu.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index d00838c41333..260b04b09c86 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -72,11 +72,20 @@ static int open_group(uint64_t config, int group)
>  static void
>  init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
>  {
> -       int fd;
> +       int fd, err = 0;
>  
> -       fd = open_pmu(__I915_PMU_ENGINE(e->class, e->instance, sample));
> +       errno = 0;
> +       fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
> +       err = errno;

To be really pedantic, errno is only valid on success.

err = 0;
if (fd < 0)
	err = errno;

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[igt-dev] [PATCH i-g-t v3 8/9] tests/perf_pmu: Explicitly test for engine availability in init tests

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Test will succeed if present engine can be opened, or if the missing
engine reports the correct error code.

v2:
 * Use the right errno.
 * Close fd only on success. (Chris Wilson)

v3:
 * Only sample errno on failure. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/perf_pmu.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 3d1b3a2c7c61..5b38712fe734 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -72,11 +72,21 @@ static int open_group(uint64_t config, int group)
 static void
 init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
 {
-	int fd;
+	int fd, err = 0;
 
-	fd = open_pmu(__I915_PMU_ENGINE(e->class, e->instance, sample));
+	errno = 0;
+	fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+	if (fd < 0)
+		err = errno;
 
-	close(fd);
+	if (gem_has_engine(gem_fd, e->class, e->instance)) {
+		igt_assert_eq(err, 0);
+		igt_assert_fd(fd);
+		close(fd);
+	} else {
+		igt_assert_lt(fd, 0);
+		igt_assert_eq(err, ENODEV);
+	}
 }
 
 static uint64_t pmu_read_single(int fd)
-- 
2.14.1

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[igt-dev] [PATCH i-g-t 9/9] tests/perf_pmu: Use short batches from hotplug test

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This test emits a spin batch which runs roughly for N CPU cores seconds
As such these can be declared as GPU hangs, so work around that by looping
with shorter batches.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 66 +++++++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 51 insertions(+), 15 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 201aa0b40068..7f2fa64834d7 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -84,15 +84,23 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
 	close(fd);
 }
 
-static uint64_t pmu_read_single(int fd)
+static uint64_t __pmu_read_single(int fd, uint64_t *ts)
 {
 	uint64_t data[2];
 
 	igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
 
+	if (ts)
+		*ts = data[1];
+
 	return data[0];
 }
 
+static uint64_t pmu_read_single(int fd)
+{
+	return __pmu_read_single(fd, NULL);
+}
+
 static void pmu_read_multi(int fd, unsigned int num, uint64_t *val)
 {
 	uint64_t buf[2 + num];
@@ -148,7 +156,7 @@ static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
 
 	if (flags & FLAG_SYNC)
 		gem_sync(fd, spin->handle);
-	else
+	else if (flags & TEST_TRAILING_IDLE)
 		usleep(batch_duration_ns / 5000);
 }
 
@@ -930,27 +938,33 @@ static bool cpu0_hotplug_support(void)
 
 static void cpu_hotplug(int gem_fd)
 {
-	struct timespec start = { };
+	struct igt_helper_process cpu_shuffle = { };
 	igt_spin_t *spin;
-	uint64_t val, ref;
-	int fd;
+	uint64_t ts[2];
+	uint64_t val;
+	int link[2];
+	int fd, ret;
 
 	igt_require(cpu0_hotplug_support());
 
-	fd = perf_i915_open(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
-	igt_assert(fd >= 0);
+	fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
 
 	spin = igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
 
-	igt_nsec_elapsed(&start);
+	val = __pmu_read_single(fd, &ts[0]);
+
+	ret = pipe2(link, O_NONBLOCK);
+	igt_assert_eq(ret, 0);
 
 	/*
 	 * Toggle online status of all the CPUs in a child process and ensure
 	 * this has not affected busyness stats in the parent.
 	 */
-	igt_fork(child, 1) {
+	igt_fork_helper(&cpu_shuffle) {
 		int cpu = 0;
 
+		close(link[0]);
+
 		for (;;) {
 			char name[128];
 			int cpufd;
@@ -960,6 +974,7 @@ static void cpu_hotplug(int gem_fd)
 			cpufd = open(name, O_WRONLY);
 			if (cpufd == -1) {
 				igt_assert(cpu > 0);
+				igt_assert_eq(write(link[1], "*", 1), 1);
 				break;
 			}
 			igt_assert_eq(write(cpufd, "0", 2), 2);
@@ -971,19 +986,40 @@ static void cpu_hotplug(int gem_fd)
 			close(cpufd);
 			cpu++;
 		}
+
+		/* Wait to be terminated. */
+		for (;;)
+			sleep(1);
 	}
 
-	igt_waitchildren();
+	close(link[1]);
 
-	ref = igt_nsec_elapsed(&start);
-	val = pmu_read_single(fd);
+	/*
+	 * Very long batches can be declared as GPU hangs so emit shorter ones
+	 * until the CPU core shuffler finishes one loop.
+	 */
+	for (;;) {
+		char buf;
+		int ret2;
 
-	igt_spin_batch_end(spin);
-	gem_sync(gem_fd, spin->handle);
+		usleep(500e3);
+		end_spin(gem_fd, spin, 0);
+		ret2 = read(link[0], &buf, 1);
+		if ( ret2 == 1 || (ret2 < 0 && errno != EAGAIN))
+			break;
+		igt_spin_batch_free(gem_fd, spin);
+		spin = __igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
+	}
+
+	val = __pmu_read_single(fd, &ts[1]) - val;
+
+	end_spin(gem_fd, spin, FLAG_SYNC);
 	igt_spin_batch_free(gem_fd, spin);
+	igt_stop_helper(&cpu_shuffle);
 	close(fd);
+	close(link[0]);
 
-	assert_within_epsilon(val, ref, tolerance);
+	assert_within_epsilon(val, ts[1] - ts[0], tolerance);
 }
 
 static void
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t 9/9] tests/perf_pmu: Use short batches from hotplug test

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-02 18:37:54)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> This test emits a spin batch which runs roughly for N CPU cores seconds
> As such these can be declared as GPU hangs, so work around that by looping
> with shorter batches.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  tests/perf_pmu.c | 66 +++++++++++++++++++++++++++++++++++++++++++-------------
>  1 file changed, 51 insertions(+), 15 deletions(-)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 201aa0b40068..7f2fa64834d7 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -84,15 +84,23 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
>         close(fd);
>  }
>  
> -static uint64_t pmu_read_single(int fd)
> +static uint64_t __pmu_read_single(int fd, uint64_t *ts)
>  {
>         uint64_t data[2];
>  
>         igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
>  
> +       if (ts)
> +               *ts = data[1];
> +
>         return data[0];
>  }
>  
> +static uint64_t pmu_read_single(int fd)
> +{
> +       return __pmu_read_single(fd, NULL);
> +}
> +
>  static void pmu_read_multi(int fd, unsigned int num, uint64_t *val)
>  {
>         uint64_t buf[2 + num];
> @@ -148,7 +156,7 @@ static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>  
>         if (flags & FLAG_SYNC)
>                 gem_sync(fd, spin->handle);
> -       else
> +       else if (flags & TEST_TRAILING_IDLE)
>                 usleep(batch_duration_ns / 5000);
>  }
>  
> @@ -930,27 +938,33 @@ static bool cpu0_hotplug_support(void)
>  
>  static void cpu_hotplug(int gem_fd)
>  {
> -       struct timespec start = { };
> +       struct igt_helper_process cpu_shuffle = { };
>         igt_spin_t *spin;
> -       uint64_t val, ref;
> -       int fd;
> +       uint64_t ts[2];
> +       uint64_t val;
> +       int link[2];
> +       int fd, ret;
>  
>         igt_require(cpu0_hotplug_support());

Now I know why I don't see any ill effects ;)

> -       fd = perf_i915_open(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
> -       igt_assert(fd >= 0);
> +       fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>  
>         spin = igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
>  
> -       igt_nsec_elapsed(&start);
> +       val = __pmu_read_single(fd, &ts[0]);
> +
> +       ret = pipe2(link, O_NONBLOCK);
> +       igt_assert_eq(ret, 0);
>  
>         /*
>          * Toggle online status of all the CPUs in a child process and ensure
>          * this has not affected busyness stats in the parent.
>          */
> -       igt_fork(child, 1) {
> +       igt_fork_helper(&cpu_shuffle) {
>                 int cpu = 0;
>  
> +               close(link[0]);

Honestly would not bother close()ing the temporary fd in the child, the
child isn't resource hungry and will die in due course.

> +
>                 for (;;) {
>                         char name[128];
>                         int cpufd;
> @@ -960,6 +974,7 @@ static void cpu_hotplug(int gem_fd)
>                         cpufd = open(name, O_WRONLY);
>                         if (cpufd == -1) {
>                                 igt_assert(cpu > 0);
> +                               igt_assert_eq(write(link[1], "*", 1), 1);
>                                 break;
>                         }
>                         igt_assert_eq(write(cpufd, "0", 2), 2);
> @@ -971,19 +986,40 @@ static void cpu_hotplug(int gem_fd)
>                         close(cpufd);
>                         cpu++;
>                 }
> +
> +               /* Wait to be terminated. */
> +               for (;;)
> +                       sleep(1);

Why wait? This process isn't doing at this point, so can just gracefully
die. Oh, is it because fork_helper demands you keep it around. So not
seeing the point of not using a child then.

>         }
>  
> -       igt_waitchildren();
> +       close(link[1]);
>  
> -       ref = igt_nsec_elapsed(&start);
> -       val = pmu_read_single(fd);
> +       /*
> +        * Very long batches can be declared as GPU hangs so emit shorter ones
> +        * until the CPU core shuffler finishes one loop.
> +        */
> +       for (;;) {
> +               char buf;
> +               int ret2;
>  
> -       igt_spin_batch_end(spin);
> -       gem_sync(gem_fd, spin->handle);
> +               usleep(500e3);
> +               end_spin(gem_fd, spin, 0);
> +               ret2 = read(link[0], &buf, 1);
> +               if ( ret2 == 1 || (ret2 < 0 && errno != EAGAIN))
> +                       break;

Ok. Whitespace please :) (ret seems perfectly fine to reuse and less
scary than ret2)

Do you want to create a pair of overlapping spinners to prevent the
temporary idleness? Haven't thought about whether that has any
significance, but that seems to a slight difference wrt the old test.

Consider it's a BUSY PMU and you expect the two to match implies that
you would prefer to keep the engine always busy.
-Chris
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[igt-dev] [PATCH i-g-t v2 9/9] tests/perf_pmu: Use short batches from hotplug test

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

This test emits a spin batch which runs roughly for N CPU cores seconds
As such these can be declared as GPU hangs, so work around that by looping
with shorter batches.

v2:
 * Use overlapping spinners. (Chris Wilson)
 * Go back to igt_fork. (Chris Wilson)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 89 +++++++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 69 insertions(+), 20 deletions(-)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 260b04b09c86..ffa67ffd2d09 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -88,15 +88,23 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
 	}
 }
 
-static uint64_t pmu_read_single(int fd)
+static uint64_t __pmu_read_single(int fd, uint64_t *ts)
 {
 	uint64_t data[2];
 
 	igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
 
+	if (ts)
+		*ts = data[1];
+
 	return data[0];
 }
 
+static uint64_t pmu_read_single(int fd)
+{
+	return __pmu_read_single(fd, NULL);
+}
+
 static void pmu_read_multi(int fd, unsigned int num, uint64_t *val)
 {
 	uint64_t buf[2 + num];
@@ -919,19 +927,28 @@ static bool cpu0_hotplug_support(void)
 
 static void cpu_hotplug(int gem_fd)
 {
-	struct timespec start = { };
-	igt_spin_t *spin;
-	uint64_t val, ref;
-	int fd;
+	igt_spin_t *spin[2];
+	uint64_t ts[2];
+	uint64_t val;
+	int link[2];
+	int fd, ret;
+	int cur = 0;
 
 	igt_require(cpu0_hotplug_support());
 
-	fd = perf_i915_open(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
-	igt_assert(fd >= 0);
+	fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
 
-	spin = igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
+	/*
+	 * Create two spinners so test can ensure shorter gaps in engine
+	 * busyness as it is terminating one and re-starting the other.
+	 */
+	spin[0] = igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
+	spin[1] = __igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
 
-	igt_nsec_elapsed(&start);
+	val = __pmu_read_single(fd, &ts[0]);
+
+	ret = pipe2(link, O_NONBLOCK);
+	igt_assert_eq(ret, 0);
 
 	/*
 	 * Toggle online status of all the CPUs in a child process and ensure
@@ -940,21 +957,29 @@ static void cpu_hotplug(int gem_fd)
 	igt_fork(child, 1) {
 		int cpu = 0;
 
+		close(link[0]);
+
 		for (;;) {
 			char name[128];
 			int cpufd;
 
-			sprintf(name, "/sys/devices/system/cpu/cpu%d/online",
-				cpu);
+			igt_assert_lt(snprintf(name, sizeof(name),
+					       "/sys/devices/system/cpu/cpu%d/online",
+					       cpu), sizeof(name));
 			cpufd = open(name, O_WRONLY);
 			if (cpufd == -1) {
 				igt_assert(cpu > 0);
+				/*
+				 * Signal parent that we cycled through all
+				 * CPUs and we are done.
+				 */
+				igt_assert_eq(write(link[1], "*", 1), 1);
 				break;
 			}
-			igt_assert_eq(write(cpufd, "0", 2), 2);
 
+			/* Offline followed by online a CPU. */
+			igt_assert_eq(write(cpufd, "0", 2), 2);
 			usleep(1e6);
-
 			igt_assert_eq(write(cpufd, "1", 2), 2);
 
 			close(cpufd);
@@ -962,17 +987,41 @@ static void cpu_hotplug(int gem_fd)
 		}
 	}
 
-	igt_waitchildren();
+	close(link[1]);
 
-	ref = igt_nsec_elapsed(&start);
-	val = pmu_read_single(fd);
+	/*
+	 * Very long batches can be declared as GPU hangs so emit shorter ones
+	 * until the CPU core shuffler finishes one loop.
+	 */
+	for (;;) {
+		char buf;
+		int ret2;
 
-	igt_spin_batch_end(spin);
-	gem_sync(gem_fd, spin->handle);
-	igt_spin_batch_free(gem_fd, spin);
+		usleep(500e3);
+		end_spin(gem_fd, spin[cur], 0);
+
+		/* Check if the child is signaling completion. */
+		ret2 = read(link[0], &buf, 1);
+		if ( ret2 == 1 || (ret2 < 0 && errno != EAGAIN))
+			break;
+
+		igt_spin_batch_free(gem_fd, spin[cur]);
+		spin[cur] = __igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER,
+						 0);
+		cur ^= 1;
+	}
+
+	val = __pmu_read_single(fd, &ts[1]) - val;
+
+	end_spin(gem_fd, spin[0], FLAG_SYNC);
+	end_spin(gem_fd, spin[1], FLAG_SYNC);
+	igt_spin_batch_free(gem_fd, spin[0]);
+	igt_spin_batch_free(gem_fd, spin[1]);
+	igt_waitchildren();
 	close(fd);
+	close(link[0]);
 
-	assert_within_epsilon(val, ref, tolerance);
+	assert_within_epsilon(val, ts[1] - ts[0], tolerance);
 }
 
 static void
-- 
2.14.1

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Re: [igt-dev] [PATCH i-g-t v2 9/9] tests/perf_pmu: Use short batches from hotplug test

[Chris Wilson]

Quoting Tvrtko Ursulin (2018-02-05 11:38:10)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> This test emits a spin batch which runs roughly for N CPU cores seconds
> As such these can be declared as GPU hangs, so work around that by looping
> with shorter batches.
> 
> v2:
>  * Use overlapping spinners. (Chris Wilson)
>  * Go back to igt_fork. (Chris Wilson)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> +       /*
> +        * Very long batches can be declared as GPU hangs so emit shorter ones
> +        * until the CPU core shuffler finishes one loop.
> +        */
> +       for (;;) {
> +               char buf;
> +               int ret2;

I didn't mean a new "int ret;" here, just reuse the outer ret :)

>  
> -       igt_spin_batch_end(spin);
> -       gem_sync(gem_fd, spin->handle);
> -       igt_spin_batch_free(gem_fd, spin);
> +               usleep(500e3);
> +               end_spin(gem_fd, spin[cur], 0);
> +
> +               /* Check if the child is signaling completion. */
> +               ret2 = read(link[0], &buf, 1);
> +               if ( ret2 == 1 || (ret2 < 0 && errno != EAGAIN))
                      ^ spare space.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [igt-dev] [PATCH i-g-t 9/9] tests/perf_pmu: Use short batches from hotplug test

[Tvrtko Ursulin]

On 02/02/2018 21:43, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2018-02-02 18:37:54)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> This test emits a spin batch which runs roughly for N CPU cores seconds
>> As such these can be declared as GPU hangs, so work around that by looping
>> with shorter batches.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> ---
>>   tests/perf_pmu.c | 66 +++++++++++++++++++++++++++++++++++++++++++-------------
>>   1 file changed, 51 insertions(+), 15 deletions(-)
>>
>> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
>> index 201aa0b40068..7f2fa64834d7 100644
>> --- a/tests/perf_pmu.c
>> +++ b/tests/perf_pmu.c
>> @@ -84,15 +84,23 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
>>          close(fd);
>>   }
>>   
>> -static uint64_t pmu_read_single(int fd)
>> +static uint64_t __pmu_read_single(int fd, uint64_t *ts)
>>   {
>>          uint64_t data[2];
>>   
>>          igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
>>   
>> +       if (ts)
>> +               *ts = data[1];
>> +
>>          return data[0];
>>   }
>>   
>> +static uint64_t pmu_read_single(int fd)
>> +{
>> +       return __pmu_read_single(fd, NULL);
>> +}
>> +
>>   static void pmu_read_multi(int fd, unsigned int num, uint64_t *val)
>>   {
>>          uint64_t buf[2 + num];
>> @@ -148,7 +156,7 @@ static void end_spin(int fd, igt_spin_t *spin, unsigned int flags)
>>   
>>          if (flags & FLAG_SYNC)
>>                  gem_sync(fd, spin->handle);
>> -       else
>> +       else if (flags & TEST_TRAILING_IDLE)
>>                  usleep(batch_duration_ns / 5000);
>>   }
>>   
>> @@ -930,27 +938,33 @@ static bool cpu0_hotplug_support(void)
>>   
>>   static void cpu_hotplug(int gem_fd)
>>   {
>> -       struct timespec start = { };
>> +       struct igt_helper_process cpu_shuffle = { };
>>          igt_spin_t *spin;
>> -       uint64_t val, ref;
>> -       int fd;
>> +       uint64_t ts[2];
>> +       uint64_t val;
>> +       int link[2];
>> +       int fd, ret;
>>   
>>          igt_require(cpu0_hotplug_support());
> 
> Now I know why I don't see any ill effects ;)
> 
>> -       fd = perf_i915_open(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>> -       igt_assert(fd >= 0);
>> +       fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>>   
>>          spin = igt_spin_batch_new(gem_fd, 0, I915_EXEC_RENDER, 0);
>>   
>> -       igt_nsec_elapsed(&start);
>> +       val = __pmu_read_single(fd, &ts[0]);
>> +
>> +       ret = pipe2(link, O_NONBLOCK);
>> +       igt_assert_eq(ret, 0);
>>   
>>          /*
>>           * Toggle online status of all the CPUs in a child process and ensure
>>           * this has not affected busyness stats in the parent.
>>           */
>> -       igt_fork(child, 1) {
>> +       igt_fork_helper(&cpu_shuffle) {
>>                  int cpu = 0;
>>   
>> +               close(link[0]);
> 
> Honestly would not bother close()ing the temporary fd in the child, the
> child isn't resource hungry and will die in due course.
> 
>> +
>>                  for (;;) {
>>                          char name[128];
>>                          int cpufd;
>> @@ -960,6 +974,7 @@ static void cpu_hotplug(int gem_fd)
>>                          cpufd = open(name, O_WRONLY);
>>                          if (cpufd == -1) {
>>                                  igt_assert(cpu > 0);
>> +                               igt_assert_eq(write(link[1], "*", 1), 1);
>>                                  break;
>>                          }
>>                          igt_assert_eq(write(cpufd, "0", 2), 2);
>> @@ -971,19 +986,40 @@ static void cpu_hotplug(int gem_fd)
>>                          close(cpufd);
>>                          cpu++;
>>                  }
>> +
>> +               /* Wait to be terminated. */
>> +               for (;;)
>> +                       sleep(1);
> 
> Why wait? This process isn't doing at this point, so can just gracefully
> die. Oh, is it because fork_helper demands you keep it around. So not
> seeing the point of not using a child then.
> 
>>          }
>>   
>> -       igt_waitchildren();
>> +       close(link[1]);
>>   
>> -       ref = igt_nsec_elapsed(&start);
>> -       val = pmu_read_single(fd);
>> +       /*
>> +        * Very long batches can be declared as GPU hangs so emit shorter ones
>> +        * until the CPU core shuffler finishes one loop.
>> +        */
>> +       for (;;) {
>> +               char buf;
>> +               int ret2;
>>   
>> -       igt_spin_batch_end(spin);
>> -       gem_sync(gem_fd, spin->handle);
>> +               usleep(500e3);
>> +               end_spin(gem_fd, spin, 0);
>> +               ret2 = read(link[0], &buf, 1);
>> +               if ( ret2 == 1 || (ret2 < 0 && errno != EAGAIN))
>> +                       break;
> 
> Ok. Whitespace please :) (ret seems perfectly fine to reuse and less
> scary than ret2)

Gcc complains about shadowing ret. :I I did most of the other 
suggestions in v2.

Regards,

Tvrtko

> Do you want to create a pair of overlapping spinners to prevent the
> temporary idleness? Haven't thought about whether that has any
> significance, but that seems to a slight difference wrt the old test.
> 
> Consider it's a BUSY PMU and you expect the two to match implies that
> you would prefer to keep the engine always busy.
> -Chris
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
> 
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[igt-dev] ✓ Fi.CI.BAT: success for perf_pmu reliability improvements (rev2)

[Patchwork]

== Series Details ==

Series: perf_pmu reliability improvements (rev2)
URL   : https://patchwork.freedesktop.org/series/37481/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c219cc5307474cb53612ca759354f9473955e110 tools: Clear unused fields in register spec

with latest DRM-Tip kernel build CI_DRM_3718
bde4e003ce54 drm-tip: 2018y-02m-02d-15h-03m-15s UTC integration manifest

Testlist changes:
+igt@perf_pmu@all-busy-idle-check-all
+igt@perf_pmu@busy-idle-bcs0
+igt@perf_pmu@busy-idle-check-all-bcs0
+igt@perf_pmu@busy-idle-check-all-rcs0
+igt@perf_pmu@busy-idle-check-all-vcs0
+igt@perf_pmu@busy-idle-check-all-vcs1
+igt@perf_pmu@busy-idle-check-all-vecs0
+igt@perf_pmu@busy-idle-no-semaphores-bcs0
+igt@perf_pmu@busy-idle-no-semaphores-rcs0
+igt@perf_pmu@busy-idle-no-semaphores-vcs0
+igt@perf_pmu@busy-idle-no-semaphores-vcs1
+igt@perf_pmu@busy-idle-no-semaphores-vecs0
+igt@perf_pmu@busy-idle-rcs0
+igt@perf_pmu@busy-idle-vcs0
+igt@perf_pmu@busy-idle-vcs1
+igt@perf_pmu@busy-idle-vecs0
+igt@perf_pmu@enable-race-bcs0
+igt@perf_pmu@enable-race-rcs0
+igt@perf_pmu@enable-race-vcs0
+igt@perf_pmu@enable-race-vcs1
+igt@perf_pmu@enable-race-vecs0
+igt@perf_pmu@most-busy-idle-check-all-bcs0
+igt@perf_pmu@most-busy-idle-check-all-rcs0
+igt@perf_pmu@most-busy-idle-check-all-vcs0
+igt@perf_pmu@most-busy-idle-check-all-vcs1
+igt@perf_pmu@most-busy-idle-check-all-vecs0
+igt@perf_pmu@render-node-busy-idle-bcs0
+igt@perf_pmu@render-node-busy-idle-rcs0
+igt@perf_pmu@render-node-busy-idle-vcs0
+igt@perf_pmu@render-node-busy-idle-vcs1
+igt@perf_pmu@render-node-busy-idle-vecs0
+igt@perf_pmu@semaphore-wait-idle-bcs0
+igt@perf_pmu@semaphore-wait-idle-rcs0
+igt@perf_pmu@semaphore-wait-idle-vcs0
+igt@perf_pmu@semaphore-wait-idle-vcs1
+igt@perf_pmu@semaphore-wait-idle-vecs0

Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713
Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                incomplete -> PASS       (fi-bdw-5557u) fdo#104162

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104162 https://bugs.freedesktop.org/show_bug.cgi?id=104162

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:417s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:423s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:377s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:490s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:283s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:497s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:483s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:472s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:457s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:564s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:410s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:281s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:512s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:391s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:397s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:413s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:460s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:412s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:456s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:498s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:497s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:583s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:428s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:507s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:525s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:493s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:487s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:416s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:431s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:528s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:403s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:470s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_859/issues.html
_______________________________________________
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[igt-dev] ✗ Fi.CI.IGT: failure for perf_pmu reliability improvements (rev2)

[Patchwork]

== Series Details ==

Series: perf_pmu reliability improvements (rev2)
URL   : https://patchwork.freedesktop.org/series/37481/
State : failure

== Summary ==

Test kms_flip:
        Subgroup 2x-plain-flip-ts-check:
                fail       -> PASS       (shard-hsw)
        Subgroup dpms-vs-vblank-race-interruptible:
                pass       -> FAIL       (shard-apl) fdo#103060
        Subgroup plain-flip-ts-check:
                fail       -> PASS       (shard-hsw) fdo#100368
        Subgroup flip-vs-expired-vblank-interruptible:
                pass       -> FAIL       (shard-hsw) fdo#102887
Test perf_pmu:
        Subgroup init-sema-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                skip       -> PASS       (shard-apl)
        Subgroup init-busy-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                skip       -> PASS       (shard-apl)
        Subgroup init-wait-vecs0:
                skip       -> FAIL       (shard-snb)
        Subgroup busy-double-start-vcs0:
                incomplete -> PASS       (shard-apl)
        Subgroup init-busy-vecs0:
                skip       -> FAIL       (shard-snb)
        Subgroup init-wait-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                skip       -> PASS       (shard-apl)
        Subgroup init-sema-vecs0:
                skip       -> FAIL       (shard-snb)
Test gem_eio:
        Subgroup in-flight-suspend:
                fail       -> PASS       (shard-hsw) fdo#104676
Test kms_cursor_crc:
        Subgroup cursor-128x128-suspend:
                incomplete -> PASS       (shard-hsw) fdo#103540
Test perf:
        Subgroup buffer-fill:
                pass       -> FAIL       (shard-apl) fdo#103755
        Subgroup enable-disable:
                fail       -> PASS       (shard-apl) fdo#103715
        Subgroup blocking:
                fail       -> PASS       (shard-hsw) fdo#102252
Test kms_plane_lowres:
        Subgroup pipe-c-tiling-y:
                pass       -> FAIL       (shard-apl) fdo#103166

fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#103715 https://bugs.freedesktop.org/show_bug.cgi?id=103715
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166

shard-apl        total:2872 pass:1780 dwarn:1   dfail:0   fail:23  skip:1068 time:12562s
shard-hsw        total:2872 pass:1757 dwarn:1   dfail:0   fail:11  skip:1102 time:11709s
shard-snb        total:2872 pass:1347 dwarn:1   dfail:0   fail:13  skip:1511 time:6551s
Blacklisted hosts:
shard-kbl        total:2848 pass:1878 dwarn:9   dfail:0   fail:21  skip:938 time:9014s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_859/shards.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✓ Fi.CI.BAT: success for perf_pmu reliability improvements (rev7)

[Patchwork]

== Series Details ==

Series: perf_pmu reliability improvements (rev7)
URL   : https://patchwork.freedesktop.org/series/37481/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
c219cc5307474cb53612ca759354f9473955e110 tools: Clear unused fields in register spec

with latest DRM-Tip kernel build CI_DRM_3721
04c7e906ad23 drm-tip: 2018y-02m-05d-11h-21m-11s UTC integration manifest

Testlist changes:
+igt@perf_pmu@all-busy-idle-check-all
+igt@perf_pmu@busy-idle-bcs0
+igt@perf_pmu@busy-idle-check-all-bcs0
+igt@perf_pmu@busy-idle-check-all-rcs0
+igt@perf_pmu@busy-idle-check-all-vcs0
+igt@perf_pmu@busy-idle-check-all-vcs1
+igt@perf_pmu@busy-idle-check-all-vecs0
+igt@perf_pmu@busy-idle-no-semaphores-bcs0
+igt@perf_pmu@busy-idle-no-semaphores-rcs0
+igt@perf_pmu@busy-idle-no-semaphores-vcs0
+igt@perf_pmu@busy-idle-no-semaphores-vcs1
+igt@perf_pmu@busy-idle-no-semaphores-vecs0
+igt@perf_pmu@busy-idle-rcs0
+igt@perf_pmu@busy-idle-vcs0
+igt@perf_pmu@busy-idle-vcs1
+igt@perf_pmu@busy-idle-vecs0
+igt@perf_pmu@enable-race-bcs0
+igt@perf_pmu@enable-race-rcs0
+igt@perf_pmu@enable-race-vcs0
+igt@perf_pmu@enable-race-vcs1
+igt@perf_pmu@enable-race-vecs0
+igt@perf_pmu@most-busy-idle-check-all-bcs0
+igt@perf_pmu@most-busy-idle-check-all-rcs0
+igt@perf_pmu@most-busy-idle-check-all-vcs0
+igt@perf_pmu@most-busy-idle-check-all-vcs1
+igt@perf_pmu@most-busy-idle-check-all-vecs0
+igt@perf_pmu@render-node-busy-idle-bcs0
+igt@perf_pmu@render-node-busy-idle-rcs0
+igt@perf_pmu@render-node-busy-idle-vcs0
+igt@perf_pmu@render-node-busy-idle-vcs1
+igt@perf_pmu@render-node-busy-idle-vecs0
+igt@perf_pmu@semaphore-wait-idle-bcs0
+igt@perf_pmu@semaphore-wait-idle-rcs0
+igt@perf_pmu@semaphore-wait-idle-vcs0
+igt@perf_pmu@semaphore-wait-idle-vcs1
+igt@perf_pmu@semaphore-wait-idle-vecs0

Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713
Test gem_ringfill:
        Subgroup basic-default-hang:
                incomplete -> DMESG-WARN (fi-pnv-d510) fdo#101600

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#101600 https://bugs.freedesktop.org/show_bug.cgi?id=101600

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:420s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:426s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:373s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:490s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:282s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:485s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:486s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:470s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:456s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:563s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:413s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:280s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:510s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:391s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:398s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:418s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:456s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:413s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:457s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:498s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:454s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:503s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:582s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:428s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:508s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:530s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:496s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:477s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:414s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:431s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:531s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:399s
Blacklisted hosts:
fi-cnl-y3        total:288  pass:261  dwarn:1   dfail:0   fail:0   skip:26  time:571s
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:473s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_863/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
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[igt-dev] ✓ Fi.CI.IGT: success for perf_pmu reliability improvements (rev7)

[Patchwork]

== Series Details ==

Series: perf_pmu reliability improvements (rev7)
URL   : https://patchwork.freedesktop.org/series/37481/
State : success

== Summary ==

Warning: bzip CI_DRM_3721/shard-glkb6/results32.json.bz2 wasn't in correct JSON format
Test perf_pmu:
        Subgroup init-busy-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                skip       -> PASS       (shard-apl)
        Subgroup init-wait-vecs0:
                skip       -> PASS       (shard-snb)
        Subgroup init-sema-vecs0:
                skip       -> PASS       (shard-snb)
        Subgroup init-busy-vecs0:
                skip       -> PASS       (shard-snb)
        Subgroup init-sema-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                skip       -> PASS       (shard-apl)
        Subgroup init-wait-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                skip       -> PASS       (shard-apl)
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-primscrn-cur-indfb-draw-pwrite:
                fail       -> PASS       (shard-apl) fdo#101623
Test pm_rc6_residency:
        Subgroup rc6-accuracy:
                skip       -> PASS       (shard-snb)
Test perf:
        Subgroup buffer-fill:
                pass       -> FAIL       (shard-apl) fdo#103755
Test kms_sysfs_edid_timing:
                warn       -> PASS       (shard-apl) fdo#100047
Test kms_flip:
        Subgroup 2x-plain-flip-fb-recreate:
                pass       -> FAIL       (shard-hsw) fdo#100368
        Subgroup dpms-vs-vblank-race:
                pass       -> FAIL       (shard-hsw) fdo#103060

fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060

shard-apl        total:2815 pass:1748 dwarn:1   dfail:0   fail:20  skip:1045 time:12313s
shard-hsw        total:2872 pass:1755 dwarn:1   dfail:0   fail:13  skip:1102 time:11534s
shard-snb        total:2872 pass:1351 dwarn:1   dfail:0   fail:10  skip:1510 time:6547s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_863/shards.html
_______________________________________________
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[igt-dev] ✓ Fi.CI.BAT: success for perf_pmu reliability improvements (rev9)

[Patchwork]

== Series Details ==

Series: perf_pmu reliability improvements (rev9)
URL   : https://patchwork.freedesktop.org/series/37481/
State : success

== Summary ==

IGT patchset tested on top of latest successful build
08e8621aaaed6853ecaede6325512e2775b78dea tests/kms_plane_scaling: Test all pixel formats with clamping and clipping too

with latest DRM-Tip kernel build CI_DRM_3723
ff0257f786f3 drm-tip: 2018y-02m-05d-13h-26m-33s UTC integration manifest

Testlist changes:
+igt@perf_pmu@all-busy-idle-check-all
+igt@perf_pmu@busy-idle-bcs0
+igt@perf_pmu@busy-idle-check-all-bcs0
+igt@perf_pmu@busy-idle-check-all-rcs0
+igt@perf_pmu@busy-idle-check-all-vcs0
+igt@perf_pmu@busy-idle-check-all-vcs1
+igt@perf_pmu@busy-idle-check-all-vecs0
+igt@perf_pmu@busy-idle-no-semaphores-bcs0
+igt@perf_pmu@busy-idle-no-semaphores-rcs0
+igt@perf_pmu@busy-idle-no-semaphores-vcs0
+igt@perf_pmu@busy-idle-no-semaphores-vcs1
+igt@perf_pmu@busy-idle-no-semaphores-vecs0
+igt@perf_pmu@busy-idle-rcs0
+igt@perf_pmu@busy-idle-vcs0
+igt@perf_pmu@busy-idle-vcs1
+igt@perf_pmu@busy-idle-vecs0
+igt@perf_pmu@enable-race-bcs0
+igt@perf_pmu@enable-race-rcs0
+igt@perf_pmu@enable-race-vcs0
+igt@perf_pmu@enable-race-vcs1
+igt@perf_pmu@enable-race-vecs0
+igt@perf_pmu@most-busy-idle-check-all-bcs0
+igt@perf_pmu@most-busy-idle-check-all-rcs0
+igt@perf_pmu@most-busy-idle-check-all-vcs0
+igt@perf_pmu@most-busy-idle-check-all-vcs1
+igt@perf_pmu@most-busy-idle-check-all-vecs0
+igt@perf_pmu@render-node-busy-idle-bcs0
+igt@perf_pmu@render-node-busy-idle-rcs0
+igt@perf_pmu@render-node-busy-idle-vcs0
+igt@perf_pmu@render-node-busy-idle-vcs1
+igt@perf_pmu@render-node-busy-idle-vecs0
+igt@perf_pmu@semaphore-wait-idle-bcs0
+igt@perf_pmu@semaphore-wait-idle-rcs0
+igt@perf_pmu@semaphore-wait-idle-vcs0
+igt@perf_pmu@semaphore-wait-idle-vcs1
+igt@perf_pmu@semaphore-wait-idle-vecs0

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                pass       -> FAIL       (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713
                dmesg-warn -> PASS       (fi-cnl-y3) fdo#104951

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:420s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:423s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:375s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:491s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:485s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:488s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:468s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:456s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:570s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:575s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:414s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:280s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:515s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:391s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:398s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:412s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:460s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:417s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:454s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:498s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:456s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:506s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:586s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:429s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:507s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:528s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:486s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:486s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:415s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:431s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:526s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:398s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:469s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_865/issues.html
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[igt-dev] ✓ Fi.CI.IGT: success for perf_pmu reliability improvements (rev9)

[Patchwork]

== Series Details ==

Series: perf_pmu reliability improvements (rev9)
URL   : https://patchwork.freedesktop.org/series/37481/
State : success

== Summary ==

Test gem_softpin:
        Subgroup noreloc-s3:
                skip       -> PASS       (shard-snb) fdo#103375 +1
Test perf_pmu:
        Subgroup busy-no-semaphores-vcs0:
                fail       -> PASS       (shard-apl)
        Subgroup init-wait-vecs0:
                skip       -> PASS       (shard-snb)
        Subgroup cpu-hotplug:
                fail       -> PASS       (shard-snb)
                fail       -> PASS       (shard-hsw)
                fail       -> INCOMPLETE (shard-apl)
        Subgroup init-wait-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                fail       -> PASS       (shard-apl)
        Subgroup init-sema-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                skip       -> PASS       (shard-apl)
        Subgroup init-busy-vecs0:
                skip       -> PASS       (shard-snb)
        Subgroup init-sema-vecs0:
                skip       -> PASS       (shard-snb)
        Subgroup init-busy-vcs1:
                skip       -> PASS       (shard-snb)
                skip       -> PASS       (shard-hsw)
                skip       -> PASS       (shard-apl)
        Subgroup other-init-3:
                fail       -> PASS       (shard-apl)
Test kms_flip:
        Subgroup wf_vblank-ts-check-interruptible:
                fail       -> PASS       (shard-hsw) fdo#100368 +1
        Subgroup 2x-dpms-vs-vblank-race-interruptible:
                fail       -> PASS       (shard-hsw)
        Subgroup flip-vs-modeset-vs-hang-interruptible:
                dmesg-warn -> PASS       (shard-snb) fdo#104311
Test kms_rotation_crc:
        Subgroup sprite-rotation-90:
                dmesg-warn -> PASS       (shard-apl) fdo#103356 +1
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-offscren-pri-indfb-draw-pwrite:
                pass       -> FAIL       (shard-apl) fdo#101623
Test perf:
        Subgroup buffer-fill:
                fail       -> PASS       (shard-apl) fdo#103755
Test pm_rc6_residency:
        Subgroup rc6-accuracy:
                skip       -> PASS       (shard-snb)
Test gem_eio:
        Subgroup in-flight-contexts:
                fail       -> PASS       (shard-hsw) fdo#104676

fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104311 https://bugs.freedesktop.org/show_bug.cgi?id=104311
fdo#103356 https://bugs.freedesktop.org/show_bug.cgi?id=103356
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103755 https://bugs.freedesktop.org/show_bug.cgi?id=103755
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676

shard-apl        total:2828 pass:1755 dwarn:2   dfail:0   fail:21  skip:1049 time:12106s
shard-hsw        total:2872 pass:1759 dwarn:1   dfail:0   fail:10  skip:1101 time:11594s
shard-snb        total:2872 pass:1352 dwarn:1   dfail:0   fail:9   skip:1510 time:6468s
Blacklisted hosts:
shard-kbl        total:2872 pass:1909 dwarn:2   dfail:0   fail:21  skip:940 time:9513s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_865/shards.html
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