* [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip
@ 2018-02-03 6:51 David Wu
2018-02-03 6:51 ` [U-Boot] [PATCH 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
` (8 more replies)
0 siblings, 9 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:51 UTC (permalink / raw)
To: u-boot
The common pinctrl driver for rockchip Socs, it depends the PINCTRL_FULL config.
If use it, the default pinctrl setup from DTS could be configured at device probe.
David Wu (9):
rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new
pinctrl driver
ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl
driver
pinctrl: rockchip: Add common rockchip pinctrl driver
rockchip: defconfig: Clean the unused pinctrl config
pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
ARM: dts: rk322x: Correct the uart2 default pin configuration
arch/arm/dts/rk322x.dtsi | 11 +-
arch/arm/mach-rockchip/Kconfig | 1 -
arch/arm/mach-rockchip/rk3188-board-spl.c | 42 +-
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 -
configs/chromebit_mickey_defconfig | 4 -
configs/chromebook_jerry_defconfig | 4 -
configs/chromebook_minnie_defconfig | 4 -
configs/evb-px5_defconfig | 1 -
configs/evb-rk3128_defconfig | 1 -
configs/evb-rk3229_defconfig | 1 -
configs/evb-rk3288_defconfig | 2 -
configs/evb-rk3399_defconfig | 2 -
configs/evb-rv1108_defconfig | 1 -
configs/fennec-rk3288_defconfig | 2 -
configs/firefly-rk3288_defconfig | 2 -
configs/firefly-rk3399_defconfig | 1 -
configs/geekbox_defconfig | 1 -
configs/kylin-rk3036_defconfig | 1 -
configs/lion-rk3368_defconfig | 1 -
configs/miqi-rk3288_defconfig | 2 -
configs/phycore-rk3288_defconfig | 2 -
configs/popmetal-rk3288_defconfig | 2 -
configs/puma-rk3399_defconfig | 1 -
configs/rock2_defconfig | 2 -
configs/rock_defconfig | 1 -
configs/sandbox_defconfig | 2 -
configs/sandbox_flattree_defconfig | 2 -
configs/sandbox_noblk_defconfig | 2 -
configs/sheep-rk3368_defconfig | 1 -
configs/tinker-rk3288_defconfig | 2 -
configs/vyasa-rk3288_defconfig | 2 -
drivers/pinctrl/Kconfig | 98 +-
drivers/pinctrl/Makefile | 2 +-
drivers/pinctrl/pinctrl-rockchip.c | 2440 +++++++++++++++++++++++++++++
drivers/pinctrl/rockchip/Makefile | 15 -
drivers/pinctrl/rockchip/pinctrl_rk3036.c | 264 ----
drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 ---
drivers/pinctrl/rockchip/pinctrl_rk3188.c | 610 --------
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 895 -----------
drivers/pinctrl/rockchip/pinctrl_rk3288.c | 870 ----------
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 708 ---------
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 742 ---------
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 457 ------
drivers/pinctrl/rockchip/pinctrl_rv1108.c | 582 -------
44 files changed, 2466 insertions(+), 5586 deletions(-)
create mode 100644 drivers/pinctrl/pinctrl-rockchip.c
delete mode 100644 drivers/pinctrl/rockchip/Makefile
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3399.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rv1108.c
--
2.7.4
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
@ 2018-02-03 6:51 ` David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-18 18:57 ` Philipp Tomsich
2018-02-03 6:51 ` [U-Boot] [PATCH 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL David Wu
` (7 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:51 UTC (permalink / raw)
To: u-boot
The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make fdedesc be built in.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
configs/evb-rk3399_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index e8e52c3..54eb703 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -22,7 +22,6 @@ CONFIG_CMD_USB=y
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
2018-02-03 6:51 ` [U-Boot] [PATCH 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
@ 2018-02-03 6:51 ` David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-18 19:00 ` Philipp Tomsich
2018-02-03 6:51 ` [U-Boot] [PATCH 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 David Wu
` (6 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:51 UTC (permalink / raw)
To: u-boot
When the boot ROM sets up MMC we don't need to do it again. Remove the
MMC setup code entirely, but we also need to enable uart for debug message.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
arch/arm/mach-rockchip/rk3188-board-spl.c | 42 +++----------------------------
1 file changed, 3 insertions(+), 39 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
index 8e3b8ae..8371a31 100644
--- a/arch/arm/mach-rockchip/rk3188-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
@@ -100,10 +100,11 @@ static int setup_arm_clock(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl, *dev;
+ struct udevice *dev;
int ret;
/* Example code showing how to enable the debug UART on RK3188 */
+#define EARLY_UART
#ifdef EARLY_UART
#include <asm/arch/grf_rk3188.h>
/* Enable early UART on the RK3188 */
@@ -124,10 +125,7 @@ void board_init_f(ulong dummy)
* printascii("string");
*/
debug_uart_init();
- printch('s');
- printch('p');
- printch('l');
- printch('\n');
+ printascii("U-Boot SPL board init");
#endif
ret = spl_early_init();
@@ -144,12 +142,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
debug("DRAM init failed: %d\n", ret);
@@ -187,7 +179,6 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
@@ -196,36 +187,9 @@ void spl_board_init(void)
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
2018-02-03 6:51 ` [U-Boot] [PATCH 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
2018-02-03 6:51 ` [U-Boot] [PATCH 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL David Wu
@ 2018-02-03 6:51 ` David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
2018-02-03 6:51 ` [U-Boot] [PATCH 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl David Wu
` (5 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:51 UTC (permalink / raw)
To: u-boot
It seems that pinctrl is not requested for rk3188 SPL, remove it so
that can save more space for SPL image size.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
arch/arm/mach-rockchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 1e5a7bb..8a0fb83 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -29,7 +29,6 @@ config ROCKCHIP_RK3188
select SUPPORT_SPL
select SPL
select SPL_CLK
- select SPL_PINCTRL
select SPL_REGMAP
select SPL_SYSCON
select SPL_RAM
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
` (2 preceding siblings ...)
2018-02-03 6:51 ` [U-Boot] [PATCH 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 David Wu
@ 2018-02-03 6:51 ` David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
2018-02-03 6:55 ` [U-Boot] [PATCH 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
` (4 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:51 UTC (permalink / raw)
To: u-boot
If we use the new pinctrl driver, the pinctrl setup will be done
by device probe. Remove the pinctrl setup at rk3288-board-spl.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
arch/arm/mach-rockchip/rk3288-board-spl.c | 79 -------------------------------
1 file changed, 79 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
index f64a548..0e68382 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -83,45 +83,6 @@ u32 spl_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
}
-#ifdef CONFIG_SPL_MMC_SUPPORT
-static int configure_emmc(struct udevice *pinctrl)
-{
-#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
-
- struct gpio_desc desc;
- int ret;
-
- pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
-
- /*
- * TODO(sjg at chromium.org): Pick this up from device tree or perhaps
- * use the EMMC_PWREN setting.
- */
- ret = dm_gpio_lookup_name("D9", &desc);
- if (ret) {
- debug("gpio ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_request(&desc, "emmc_pwren");
- if (ret) {
- debug("gpio_request ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
- if (ret) {
- debug("gpio dir ret=%d\n", ret);
- return ret;
- }
- ret = dm_gpio_set_value(&desc, 1);
- if (ret) {
- debug("gpio value ret=%d\n", ret);
- return ret;
- }
-#endif
- return 0;
-}
-#endif
-
#if !defined(CONFIG_SPL_OF_PLATDATA)
static int phycore_init(void)
{
@@ -150,7 +111,6 @@ static int phycore_init(void)
void board_init_f(ulong dummy)
{
- struct udevice *pinctrl;
struct udevice *dev;
int ret;
@@ -189,12 +149,6 @@ void board_init_f(ulong dummy)
return;
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("Pinctrl init failed: %d\n", ret);
- return;
- }
-
#if !defined(CONFIG_SPL_OF_PLATDATA)
if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
ret = phycore_init();
@@ -245,52 +199,19 @@ static int setup_led(void)
void spl_board_init(void)
{
- struct udevice *pinctrl;
int ret;
ret = setup_led();
-
if (ret) {
debug("LED ret=%d\n", ret);
hang();
}
- ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
- if (ret) {
- debug("%s: Cannot find pinctrl device\n", __func__);
- goto err;
- }
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
- if (ret) {
- debug("%s: Failed to set up SD card\n", __func__);
- goto err;
- }
- ret = configure_emmc(pinctrl);
- if (ret) {
- debug("%s: Failed to set up eMMC\n", __func__);
- goto err;
- }
-#endif
-
- /* Enable debug UART */
- ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
- if (ret) {
- debug("%s: Failed to set up console UART\n", __func__);
- goto err;
- }
-
preloader_console_init();
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
return;
-err:
- printf("spl_board_init: Error %d\n", ret);
-
- /* No way to report error here */
- hang();
}
#ifdef CONFIG_SPL_OS_BOOT
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
` (3 preceding siblings ...)
2018-02-03 6:51 ` [U-Boot] [PATCH 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl David Wu
@ 2018-02-03 6:55 ` David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-18 19:01 ` Philipp Tomsich
2018-02-03 6:56 ` [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip " David Wu
` (3 subsequent siblings)
8 siblings, 2 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:55 UTC (permalink / raw)
To: u-boot
The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
to make fdedesc be built in.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
configs/chromebit_mickey_defconfig | 2 --
configs/chromebook_jerry_defconfig | 2 --
configs/chromebook_minnie_defconfig | 2 --
3 files changed, 6 deletions(-)
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index b350811..93c5c4e 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -34,7 +34,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
@@ -88,7 +87,6 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
-# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_GADGET_VBUS_DRAW=0
CONFIG_G_DNL_MANUFACTURER="Rockchip"
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index f80faae..57d35e9 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -36,7 +36,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
@@ -90,7 +89,6 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
-# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_GADGET_VBUS_DRAW=0
CONFIG_G_DNL_MANUFACTURER="Rockchip"
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index ff94a4d..529444a 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -35,7 +35,6 @@ CONFIG_CMD_REGULATOR=y
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_SPL_OF_PLATDATA=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
@@ -90,7 +89,6 @@ CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_USE_TINY_PRINTF=y
CONFIG_CMD_DHRYSTONE=y
CONFIG_ERRNO_STR=y
-# CONFIG_SPL_OF_LIBFDT is not set
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_GADGET_VBUS_DRAW=0
CONFIG_G_DNL_MANUFACTURER="Rockchip"
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
` (4 preceding siblings ...)
2018-02-03 6:55 ` [U-Boot] [PATCH 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
@ 2018-02-03 6:56 ` David Wu
2018-02-04 7:45 ` Kever Yang
` (2 more replies)
2018-02-03 6:56 ` [U-Boot] [PATCH 7/9] rockchip: defconfig: Clean the unused pinctrl config David Wu
` (2 subsequent siblings)
8 siblings, 3 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:56 UTC (permalink / raw)
To: u-boot
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
drivers/pinctrl/Kconfig | 98 +-
drivers/pinctrl/Makefile | 2 +-
drivers/pinctrl/pinctrl-rockchip.c | 2440 ++++++++++++++++++++++++++++++++++++
3 files changed, 2454 insertions(+), 86 deletions(-)
create mode 100644 drivers/pinctrl/pinctrl-rockchip.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 7e8e4b0..6177e7c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -158,95 +158,23 @@ config PINCTRL_QCA953X
the GPIO definitions and pin control functions for each available
multiplex function.
-config PINCTRL_ROCKCHIP_RK3036
- bool "Rockchip rk3036 pin control driver"
- depends on DM
- help
- Support pin multiplexing control on Rockchip rk3036 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
-config PINCTRL_ROCKCHIP_RK3128
- bool "Rockchip rk3128 pin control driver"
- depends on DM
- help
- Support pin multiplexing control on Rockchip rk3128 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
-config PINCTRL_ROCKCHIP_RK3188
- bool "Rockchip rk3188 pin control driver"
- depends on DM
- help
- Support pin multiplexing control on Rockchip rk3188 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
-config PINCTRL_ROCKCHIP_RK322X
- bool "Rockchip rk322x pin control driver"
- depends on DM
- help
- Support pin multiplexing control on Rockchip rk322x SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
-config PINCTRL_ROCKCHIP_RK3288
- bool "Rockchip rk3288 pin control driver"
- depends on DM
- help
- Support pin multiplexing control on Rockchip rk3288 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
-config PINCTRL_ROCKCHIP_RK3328
- bool "Rockchip rk3328 pin control driver"
- depends on DM
- help
- Support pin multiplexing control on Rockchip rk3328 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
-config PINCTRL_ROCKCHIP_RK3368
- bool "Rockchip RK3368 pin control driver"
- depends on DM
- help
- Support pin multiplexing control on Rockchip rk3368 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
-config PINCTRL_ROCKCHIP_RK3399
- bool "Rockchip rk3399 pin control driver"
- depends on DM
+config PINCTRL_ROCKCHIP
+ bool "Rockchip pin control driver"
+ depends on PINCTRL_FULL
+ default y
help
- Support pin multiplexing control on Rockchip rk3399 SoCs.
+ Support pin multiplexing control on Rockchip SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
+ The driver is controlled by a device tree node which contains pin
+ control functions for each available multiplex function.
-config PINCTRL_ROCKCHIP_RV1108
- bool "Rockchip rv1108 pin control driver"
- depends on DM
+config SPL_PINCTRL_ROCKCHIP
+ bool "Support Rockchip pin controllers in SPL"
+ depends on SPL_PINCTRL_FULL
+ default y
help
- Support pin multiplexing control on Rockchip rv1108 SoC.
-
- The driver is controlled by a device tree node which contains
- both the GPIO definitions and pin control functions for each
- available multiplex function.
+ This option is an SPL-variant of the PINCTRL_ROCKCHIP option.
+ See the help of PINCTRL_ROCKCHIP for details.
config PINCTRL_SANDBOX
bool "Sandbox pinctrl driver"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 8c04028..2429eb9 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -11,7 +11,7 @@ obj-y += nxp/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_ATH79) += ath79/
obj-$(CONFIG_ARCH_RMOBILE) += renesas/
-obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
+obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
new file mode 100644
index 0000000..68bf30d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -0,0 +1,2440 @@
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#define MAX_ROCKCHIP_GPIO_PER_BANK 32
+#define RK_FUNC_GPIO 0
+#define MAX_ROCKCHIP_PINS_ENTRIES 20
+
+enum rockchip_pinctrl_type {
+ PX30,
+ RV1108,
+ RK2928,
+ RK3066B,
+ RK3128,
+ RK3188,
+ RK3288,
+ RK3368,
+ RK3399,
+};
+
+/**
+ * Encode variants of iomux registers into a type variable
+ */
+#define IOMUX_GPIO_ONLY BIT(0)
+#define IOMUX_WIDTH_4BIT BIT(1)
+#define IOMUX_SOURCE_PMU BIT(2)
+#define IOMUX_UNROUTED BIT(3)
+#define IOMUX_WIDTH_3BIT BIT(4)
+
+/**
+ * @type: iomux variant using IOMUX_* constants
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ * an initial offset value the relevant source offset can be reset
+ * to a new value for autocalculating the following iomux registers.
+ */
+struct rockchip_iomux {
+ int type;
+ int offset;
+};
+
+/**
+ * enum type index corresponding to rockchip_perpin_drv_list arrays index.
+ */
+enum rockchip_pin_drv_type {
+ DRV_TYPE_IO_DEFAULT = 0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_ONLY,
+ DRV_TYPE_IO_1V8_3V0_AUTO,
+ DRV_TYPE_IO_3V3_ONLY,
+ DRV_TYPE_MAX
+};
+
+/**
+ * enum type index corresponding to rockchip_pull_list arrays index.
+ */
+enum rockchip_pin_pull_type {
+ PULL_TYPE_IO_DEFAULT = 0,
+ PULL_TYPE_IO_1V8_ONLY,
+ PULL_TYPE_MAX
+};
+
+/**
+ * @drv_type: drive strength variant using rockchip_perpin_drv_type
+ * @offset: if initialized to -1 it will be autocalculated, by specifying
+ * an initial offset value the relevant source offset can be reset
+ * to a new value for autocalculating the following drive strength
+ * registers. if used chips own cal_drv func instead to calculate
+ * registers offset, the variant could be ignored.
+ */
+struct rockchip_drv {
+ enum rockchip_pin_drv_type drv_type;
+ int offset;
+};
+
+/**
+ * @priv: common pinctrl private basedata
+ * @pin_base: first pin number
+ * @nr_pins: number of pins in this bank
+ * @name: name of the bank
+ * @bank_num: number of the bank, to account for holes
+ * @iomux: array describing the 4 iomux sources of the bank
+ * @drv: array describing the 4 drive strength sources of the bank
+ * @pull_type: array describing the 4 pull type sources of the bank
+ * @recalced_mask: bits describing the mux recalced pins of per bank
+ * @route_mask: bits describing the routing pins of per bank
+ */
+struct rockchip_pin_bank {
+ struct rockchip_pinctrl_priv *priv;
+ u32 pin_base;
+ u8 nr_pins;
+ char *name;
+ u8 bank_num;
+ struct rockchip_iomux iomux[4];
+ struct rockchip_drv drv[4];
+ enum rockchip_pin_pull_type pull_type[4];
+ u32 recalced_mask;
+ u32 route_mask;
+};
+
+#define PIN_BANK(id, pins, label) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ }, \
+ }
+
+#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = -1 }, \
+ { .type = iom1, .offset = -1 }, \
+ { .type = iom2, .offset = -1 }, \
+ { .type = iom3, .offset = -1 }, \
+ }, \
+ }
+
+#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ }, \
+ .drv = { \
+ { .drv_type = type0, .offset = -1 }, \
+ { .drv_type = type1, .offset = -1 }, \
+ { .drv_type = type2, .offset = -1 }, \
+ { .drv_type = type3, .offset = -1 }, \
+ }, \
+ }
+
+#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
+ drv2, drv3, pull0, pull1, \
+ pull2, pull3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ { .offset = -1 }, \
+ }, \
+ .drv = { \
+ { .drv_type = drv0, .offset = -1 }, \
+ { .drv_type = drv1, .offset = -1 }, \
+ { .drv_type = drv2, .offset = -1 }, \
+ { .drv_type = drv3, .offset = -1 }, \
+ }, \
+ .pull_type[0] = pull0, \
+ .pull_type[1] = pull1, \
+ .pull_type[2] = pull2, \
+ .pull_type[3] = pull3, \
+ }
+
+#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
+ iom2, iom3, drv0, drv1, drv2, \
+ drv3, offset0, offset1, \
+ offset2, offset3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = -1 }, \
+ { .type = iom1, .offset = -1 }, \
+ { .type = iom2, .offset = -1 }, \
+ { .type = iom3, .offset = -1 }, \
+ }, \
+ .drv = { \
+ { .drv_type = drv0, .offset = offset0 }, \
+ { .drv_type = drv1, .offset = offset1 }, \
+ { .drv_type = drv2, .offset = offset2 }, \
+ { .drv_type = drv3, .offset = offset3 }, \
+ }, \
+ }
+
+#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
+ label, iom0, iom1, iom2, \
+ iom3, drv0, drv1, drv2, \
+ drv3, offset0, offset1, \
+ offset2, offset3, pull0, \
+ pull1, pull2, pull3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = -1 }, \
+ { .type = iom1, .offset = -1 }, \
+ { .type = iom2, .offset = -1 }, \
+ { .type = iom3, .offset = -1 }, \
+ }, \
+ .drv = { \
+ { .drv_type = drv0, .offset = offset0 }, \
+ { .drv_type = drv1, .offset = offset1 }, \
+ { .drv_type = drv2, .offset = offset2 }, \
+ { .drv_type = drv3, .offset = offset3 }, \
+ }, \
+ .pull_type[0] = pull0, \
+ .pull_type[1] = pull1, \
+ .pull_type[2] = pull2, \
+ .pull_type[3] = pull3, \
+ }
+
+/**
+ * struct rockchip_mux_recalced_data: represent a pin iomux data.
+ * @num: bank number.
+ * @pin: pin number.
+ * @bit: index at register.
+ * @reg: register offset.
+ * @mask: mask bit
+ */
+struct rockchip_mux_recalced_data {
+ u8 num;
+ u8 pin;
+ u32 reg;
+ u8 bit;
+ u8 mask;
+};
+
+/**
+ * struct rockchip_mux_recalced_data: represent a pin iomux data.
+ * @bank_num: bank number.
+ * @pin: index at register or used to calc index.
+ * @func: the min pin.
+ * @route_offset: the max pin.
+ * @route_val: the register offset.
+ */
+struct rockchip_mux_route_data {
+ u8 bank_num;
+ u8 pin;
+ u8 func;
+ u32 route_offset;
+ u32 route_val;
+};
+
+/**
+ */
+struct rockchip_pin_ctrl {
+ struct rockchip_pin_bank *pin_banks;
+ u32 nr_banks;
+ u32 nr_pins;
+ char *label;
+ enum rockchip_pinctrl_type type;
+ int grf_mux_offset;
+ int pmu_mux_offset;
+ int grf_drv_offset;
+ int pmu_drv_offset;
+ struct rockchip_mux_recalced_data *iomux_recalced;
+ u32 niomux_recalced;
+ struct rockchip_mux_route_data *iomux_routes;
+ u32 niomux_routes;
+
+ void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit);
+ void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit);
+ int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit);
+};
+
+/**
+ */
+struct rockchip_pinctrl_priv {
+ struct rockchip_pin_ctrl *ctrl;
+ struct regmap *regmap_base;
+ struct regmap *regmap_pmu;
+
+};
+
+static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
+{
+ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+
+ if (bank >= ctrl->nr_banks) {
+ debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
+ return -EINVAL;
+ }
+
+ if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
+ debug("pin conf pin %d >= %d\n", pin,
+ MAX_ROCKCHIP_GPIO_PER_BANK);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
+ {
+ .num = 1,
+ .pin = 0,
+ .reg = 0x418,
+ .bit = 0,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 1,
+ .reg = 0x418,
+ .bit = 2,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 2,
+ .reg = 0x418,
+ .bit = 4,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 3,
+ .reg = 0x418,
+ .bit = 6,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 4,
+ .reg = 0x418,
+ .bit = 8,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 5,
+ .reg = 0x418,
+ .bit = 10,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 6,
+ .reg = 0x418,
+ .bit = 12,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 7,
+ .reg = 0x418,
+ .bit = 14,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 8,
+ .reg = 0x41c,
+ .bit = 0,
+ .mask = 0x3
+ }, {
+ .num = 1,
+ .pin = 9,
+ .reg = 0x41c,
+ .bit = 2,
+ .mask = 0x3
+ },
+};
+
+static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
+ {
+ .num = 2,
+ .pin = 20,
+ .reg = 0xe8,
+ .bit = 0,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 21,
+ .reg = 0xe8,
+ .bit = 4,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 22,
+ .reg = 0xe8,
+ .bit = 8,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 23,
+ .reg = 0xe8,
+ .bit = 12,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 24,
+ .reg = 0xd4,
+ .bit = 12,
+ .mask = 0x7
+ },
+};
+
+static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
+ {
+ .num = 2,
+ .pin = 12,
+ .reg = 0x24,
+ .bit = 8,
+ .mask = 0x3
+ }, {
+ .num = 2,
+ .pin = 15,
+ .reg = 0x28,
+ .bit = 0,
+ .mask = 0x7
+ }, {
+ .num = 2,
+ .pin = 23,
+ .reg = 0x30,
+ .bit = 14,
+ .mask = 0x3
+ },
+};
+
+static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
+ int *reg, u8 *bit, int *mask)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+ struct rockchip_mux_recalced_data *data;
+ int i;
+
+ for (i = 0; i < ctrl->niomux_recalced; i++) {
+ data = &ctrl->iomux_recalced[i];
+ if (data->num == bank->bank_num &&
+ data->pin == pin)
+ break;
+ }
+
+ if (i >= ctrl->niomux_recalced)
+ return;
+
+ *reg = data->reg;
+ *mask = data->mask;
+ *bit = data->bit;
+}
+
+static struct rockchip_mux_route_data px30_mux_route_data[] = {
+ {
+ /* cif-d2m0 */
+ .bank_num = 2,
+ .pin = 0,
+ .func = 1,
+ .route_offset = 0x184,
+ .route_val = BIT(16 + 7),
+ }, {
+ /* cif-d2m1 */
+ .bank_num = 3,
+ .pin = 3,
+ .func = 3,
+ .route_offset = 0x184,
+ .route_val = BIT(16 + 7) | BIT(7),
+ }, {
+ /* pdm-m0 */
+ .bank_num = 3,
+ .pin = 22,
+ .func = 2,
+ .route_offset = 0x184,
+ .route_val = BIT(16 + 8),
+ }, {
+ /* pdm-m1 */
+ .bank_num = 2,
+ .pin = 22,
+ .func = 1,
+ .route_offset = 0x184,
+ .route_val = BIT(16 + 8) | BIT(8),
+ }, {
+ /* uart2-rxm0 */
+ .bank_num = 1,
+ .pin = 26,
+ .func = 2,
+ .route_offset = 0x184,
+ .route_val = BIT(16 + 9),
+ }, {
+ /* uart2-rxm1 */
+ .bank_num = 2,
+ .pin = 14,
+ .func = 2,
+ .route_offset = 0x184,
+ .route_val = BIT(16 + 9) | BIT(9),
+ }, {
+ /* uart3-rxm0 */
+ .bank_num = 0,
+ .pin = 17,
+ .func = 2,
+ .route_offset = 0x184,
+ .route_val = BIT(16 + 10),
+ }, {
+ /* uart3-rxm1 */
+ .bank_num = 1,
+ .pin = 13,
+ .func = 2,
+ .route_offset = 0x184,
+ .route_val = BIT(16 + 10) | BIT(10),
+ },
+};
+
+static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
+ {
+ /* spi-0 */
+ .bank_num = 1,
+ .pin = 10,
+ .func = 1,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 3) | BIT(16 + 4),
+ }, {
+ /* spi-1 */
+ .bank_num = 1,
+ .pin = 27,
+ .func = 3,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
+ }, {
+ /* spi-2 */
+ .bank_num = 0,
+ .pin = 13,
+ .func = 2,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
+ }, {
+ /* i2s-0 */
+ .bank_num = 1,
+ .pin = 5,
+ .func = 1,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 5),
+ }, {
+ /* i2s-1 */
+ .bank_num = 0,
+ .pin = 14,
+ .func = 1,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 5) | BIT(5),
+ }, {
+ /* emmc-0 */
+ .bank_num = 1,
+ .pin = 22,
+ .func = 2,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 6),
+ }, {
+ /* emmc-1 */
+ .bank_num = 2,
+ .pin = 4,
+ .func = 2,
+ .route_offset = 0x144,
+ .route_val = BIT(16 + 6) | BIT(6),
+ },
+};
+
+static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
+ {
+ /* pwm0-0 */
+ .bank_num = 0,
+ .pin = 26,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16),
+ }, {
+ /* pwm0-1 */
+ .bank_num = 3,
+ .pin = 21,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16) | BIT(0),
+ }, {
+ /* pwm1-0 */
+ .bank_num = 0,
+ .pin = 27,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 1),
+ }, {
+ /* pwm1-1 */
+ .bank_num = 0,
+ .pin = 30,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 1) | BIT(1),
+ }, {
+ /* pwm2-0 */
+ .bank_num = 0,
+ .pin = 28,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 2),
+ }, {
+ /* pwm2-1 */
+ .bank_num = 1,
+ .pin = 12,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 2) | BIT(2),
+ }, {
+ /* pwm3-0 */
+ .bank_num = 3,
+ .pin = 26,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 3),
+ }, {
+ /* pwm3-1 */
+ .bank_num = 1,
+ .pin = 11,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 3) | BIT(3),
+ }, {
+ /* sdio-0_d0 */
+ .bank_num = 1,
+ .pin = 1,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 4),
+ }, {
+ /* sdio-1_d0 */
+ .bank_num = 3,
+ .pin = 2,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 4) | BIT(4),
+ }, {
+ /* spi-0_rx */
+ .bank_num = 0,
+ .pin = 13,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 5),
+ }, {
+ /* spi-1_rx */
+ .bank_num = 2,
+ .pin = 0,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 5) | BIT(5),
+ }, {
+ /* emmc-0_cmd */
+ .bank_num = 1,
+ .pin = 22,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 7),
+ }, {
+ /* emmc-1_cmd */
+ .bank_num = 2,
+ .pin = 4,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 7) | BIT(7),
+ }, {
+ /* uart2-0_rx */
+ .bank_num = 1,
+ .pin = 19,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 8),
+ }, {
+ /* uart2-1_rx */
+ .bank_num = 1,
+ .pin = 10,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 8) | BIT(8),
+ }, {
+ /* uart1-0_rx */
+ .bank_num = 1,
+ .pin = 10,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 11),
+ }, {
+ /* uart1-1_rx */
+ .bank_num = 3,
+ .pin = 13,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 11) | BIT(11),
+ },
+};
+
+static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
+ {
+ /* edphdmi_cecinoutt1 */
+ .bank_num = 7,
+ .pin = 16,
+ .func = 2,
+ .route_offset = 0x264,
+ .route_val = BIT(16 + 12) | BIT(12),
+ }, {
+ /* edphdmi_cecinout */
+ .bank_num = 7,
+ .pin = 23,
+ .func = 4,
+ .route_offset = 0x264,
+ .route_val = BIT(16 + 12),
+ },
+};
+
+static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
+ {
+ /* uart2dbg_rxm0 */
+ .bank_num = 1,
+ .pin = 1,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16) | BIT(16 + 1),
+ }, {
+ /* uart2dbg_rxm1 */
+ .bank_num = 2,
+ .pin = 1,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
+ }, {
+ /* gmac-m1_rxd0 */
+ .bank_num = 1,
+ .pin = 11,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 2) | BIT(2),
+ }, {
+ /* gmac-m1-optimized_rxd3 */
+ .bank_num = 1,
+ .pin = 14,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 10) | BIT(10),
+ }, {
+ /* pdm_sdi0m0 */
+ .bank_num = 2,
+ .pin = 19,
+ .func = 2,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 3),
+ }, {
+ /* pdm_sdi0m1 */
+ .bank_num = 1,
+ .pin = 23,
+ .func = 3,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 3) | BIT(3),
+ }, {
+ /* spi_rxdm2 */
+ .bank_num = 3,
+ .pin = 2,
+ .func = 4,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
+ }, {
+ /* i2s2_sdim0 */
+ .bank_num = 1,
+ .pin = 24,
+ .func = 1,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 6),
+ }, {
+ /* i2s2_sdim1 */
+ .bank_num = 3,
+ .pin = 2,
+ .func = 6,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 6) | BIT(6),
+ }, {
+ /* card_iom1 */
+ .bank_num = 2,
+ .pin = 22,
+ .func = 3,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 7) | BIT(7),
+ }, {
+ /* tsp_d5m1 */
+ .bank_num = 2,
+ .pin = 16,
+ .func = 3,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 8) | BIT(8),
+ }, {
+ /* cif_data5m1 */
+ .bank_num = 2,
+ .pin = 16,
+ .func = 4,
+ .route_offset = 0x50,
+ .route_val = BIT(16 + 9) | BIT(9),
+ },
+};
+
+static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
+ {
+ /* uart2dbga_rx */
+ .bank_num = 4,
+ .pin = 8,
+ .func = 2,
+ .route_offset = 0xe21c,
+ .route_val = BIT(16 + 10) | BIT(16 + 11),
+ }, {
+ /* uart2dbgb_rx */
+ .bank_num = 4,
+ .pin = 16,
+ .func = 2,
+ .route_offset = 0xe21c,
+ .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
+ }, {
+ /* uart2dbgc_rx */
+ .bank_num = 4,
+ .pin = 19,
+ .func = 1,
+ .route_offset = 0xe21c,
+ .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
+ }, {
+ /* pcie_clkreqn */
+ .bank_num = 2,
+ .pin = 26,
+ .func = 2,
+ .route_offset = 0xe21c,
+ .route_val = BIT(16 + 14),
+ }, {
+ /* pcie_clkreqnb */
+ .bank_num = 4,
+ .pin = 24,
+ .func = 1,
+ .route_offset = 0xe21c,
+ .route_val = BIT(16 + 14) | BIT(14),
+ },
+};
+
+static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
+ int mux, u32 *reg, u32 *value)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+ struct rockchip_mux_route_data *data;
+ int i;
+
+ for (i = 0; i < ctrl->niomux_routes; i++) {
+ data = &ctrl->iomux_routes[i];
+ if ((data->bank_num == bank->bank_num) &&
+ (data->pin == pin) && (data->func == mux))
+ break;
+ }
+
+ if (i >= ctrl->niomux_routes)
+ return false;
+
+ *reg = data->route_offset;
+ *value = data->route_val;
+
+ return true;
+}
+
+static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ unsigned int val;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+
+ if (iomux_num > 3)
+ return -EINVAL;
+
+ if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
+ debug("pin %d is unrouted\n", pin);
+ return -EINVAL;
+ }
+
+ if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
+ return RK_FUNC_GPIO;
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ if (mux_type & IOMUX_WIDTH_4BIT) {
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+ } else if (mux_type & IOMUX_WIDTH_3BIT) {
+ if ((pin % 8) >= 5)
+ reg += 0x4;
+ bit = (pin % 8 % 5) * 3;
+ mask = 0x7;
+ } else {
+ bit = (pin % 8) * 2;
+ mask = 0x3;
+ }
+
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+
+ ret = regmap_read(regmap, reg, &val);
+ if (ret)
+ return ret;
+
+ return ((val >> bit) & mask);
+}
+
+static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
+ int index)
+{ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+
+ return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
+}
+
+static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
+ int pin, int mux)
+{
+ int iomux_num = (pin / 8);
+
+ if (iomux_num > 3)
+ return -EINVAL;
+
+ if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
+ debug("pin %d is unrouted\n", pin);
+ return -EINVAL;
+ }
+
+ if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
+ if (mux != IOMUX_GPIO_ONLY) {
+ debug("pin %d only supports a gpio mux\n", pin);
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * Set a new mux function for a pin.
+ *
+ * The register is divided into the upper and lower 16 bit. When changing
+ * a value, the previous register value is not read and changed. Instead
+ * it seems the changed bits are marked in the upper 16 bit, while the
+ * changed value gets set in the same offset in the lower 16 bit.
+ * All pin settings seem to be 2 bit wide in both the upper and lower
+ * parts.
+ * @bank: pin bank to change
+ * @pin: pin to change
+ * @mux: new mux function to set
+ */
+static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask, mux_type;
+ u8 bit;
+ u32 data, route_reg, route_val;
+
+ ret = rockchip_verify_mux(bank, pin, mux);
+ if (ret < 0)
+ return ret;
+
+ if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
+ return 0;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ ? priv->regmap_pmu : priv->regmap_base;
+
+ /* get basic quadrupel of mux registers and the correct reg inside */
+ mux_type = bank->iomux[iomux_num].type;
+ reg = bank->iomux[iomux_num].offset;
+ if (mux_type & IOMUX_WIDTH_4BIT) {
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+ } else if (mux_type & IOMUX_WIDTH_3BIT) {
+ if ((pin % 8) >= 5)
+ reg += 0x4;
+ bit = (pin % 8 % 5) * 3;
+ mask = 0x7;
+ } else {
+ bit = (pin % 8) * 2;
+ mask = 0x3;
+ }
+
+ if (bank->recalced_mask & BIT(pin))
+ rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
+
+ if (bank->route_mask & BIT(pin)) {
+ if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
+ &route_val)) {
+ ret = regmap_write(regmap, route_reg, route_val);
+ if (ret)
+ return ret;
+ }
+ }
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define PX30_PULL_PMU_OFFSET 0x10
+#define PX30_PULL_GRF_OFFSET 0x60
+#define PX30_PULL_BITS_PER_PIN 2
+#define PX30_PULL_PINS_PER_REG 8
+#define PX30_PULL_BANK_STRIDE 16
+
+static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 32 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = PX30_PULL_PMU_OFFSET;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = PX30_PULL_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x10;
+ *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % PX30_PULL_PINS_PER_REG);
+ *bit *= PX30_PULL_BITS_PER_PIN;
+}
+
+#define PX30_DRV_PMU_OFFSET 0x20
+#define PX30_DRV_GRF_OFFSET 0xf0
+#define PX30_DRV_BITS_PER_PIN 2
+#define PX30_DRV_PINS_PER_REG 8
+#define PX30_DRV_BANK_STRIDE 16
+
+static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 32 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = PX30_DRV_PMU_OFFSET;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = PX30_DRV_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x10;
+ *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
+ *bit = (pin_num % PX30_DRV_PINS_PER_REG);
+ *bit *= PX30_DRV_BITS_PER_PIN;
+}
+
+#define PX30_SCHMITT_PMU_OFFSET 0x38
+#define PX30_SCHMITT_GRF_OFFSET 0xc0
+#define PX30_SCHMITT_PINS_PER_PMU_REG 16
+#define PX30_SCHMITT_BANK_STRIDE 16
+#define PX30_SCHMITT_PINS_PER_GRF_REG 8
+
+static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int pins_per_reg;
+
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = PX30_SCHMITT_PMU_OFFSET;
+ pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = PX30_SCHMITT_GRF_OFFSET;
+ pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
+ *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
+ }
+ *reg += ((pin_num / pins_per_reg) * 4);
+ *bit = pin_num % pins_per_reg;
+
+ return 0;
+}
+
+#define RV1108_PULL_PMU_OFFSET 0x10
+#define RV1108_PULL_OFFSET 0x110
+#define RV1108_PULL_PINS_PER_REG 8
+#define RV1108_PULL_BITS_PER_PIN 2
+#define RV1108_PULL_BANK_STRIDE 16
+
+static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = RV1108_PULL_PMU_OFFSET;
+ } else {
+ *reg = RV1108_PULL_OFFSET;
+ *regmap = priv->regmap_base;
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x10;
+ *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
+ *bit *= RV1108_PULL_BITS_PER_PIN;
+}
+
+#define RV1108_DRV_PMU_OFFSET 0x20
+#define RV1108_DRV_GRF_OFFSET 0x210
+#define RV1108_DRV_BITS_PER_PIN 2
+#define RV1108_DRV_PINS_PER_REG 8
+#define RV1108_DRV_BANK_STRIDE 16
+
+static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = RV1108_DRV_PMU_OFFSET;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = RV1108_DRV_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x10;
+ *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1108_DRV_PINS_PER_REG;
+ *bit *= RV1108_DRV_BITS_PER_PIN;
+}
+
+#define RV1108_SCHMITT_PMU_OFFSET 0x30
+#define RV1108_SCHMITT_GRF_OFFSET 0x388
+#define RV1108_SCHMITT_BANK_STRIDE 8
+#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
+#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
+
+static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int pins_per_reg;
+
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = RV1108_SCHMITT_PMU_OFFSET;
+ pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = RV1108_SCHMITT_GRF_OFFSET;
+ pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
+ *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
+ }
+ *reg += ((pin_num / pins_per_reg) * 4);
+ *bit = pin_num % pins_per_reg;
+
+ return 0;
+}
+
+#define RK2928_PULL_OFFSET 0x118
+#define RK2928_PULL_PINS_PER_REG 16
+#define RK2928_PULL_BANK_STRIDE 8
+
+static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ *reg = RK2928_PULL_OFFSET;
+ *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
+ *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
+
+ *bit = pin_num % RK2928_PULL_PINS_PER_REG;
+};
+
+#define RK3128_PULL_OFFSET 0x118
+
+static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ *reg = RK3128_PULL_OFFSET;
+ *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
+
+ *bit = pin_num % RK2928_PULL_PINS_PER_REG;
+}
+
+#define RK3188_PULL_OFFSET 0x164
+#define RK3188_PULL_BITS_PER_PIN 2
+#define RK3188_PULL_PINS_PER_REG 8
+#define RK3188_PULL_BANK_STRIDE 16
+#define RK3188_PULL_PMU_OFFSET 0x64
+
+static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 12 pins of the first bank are located elsewhere */
+ if (bank->bank_num == 0 && pin_num < 12) {
+ *regmap = priv->regmap_pmu;
+ *reg = RK3188_PULL_PMU_OFFSET;
+
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = RK3188_PULL_OFFSET;
+
+ /* correct the offset, as it is the 2nd pull register */
+ *reg -= 4;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ /*
+ * The bits in these registers have an inverse ordering
+ * with the lowest pin being in bits 15:14 and the highest
+ * pin in bits 1:0
+ */
+ *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ }
+}
+
+#define RK3288_PULL_OFFSET 0x140
+static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = RK3188_PULL_PMU_OFFSET;
+
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = RK3288_PULL_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x10;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ }
+}
+
+#define RK3288_DRV_PMU_OFFSET 0x70
+#define RK3288_DRV_GRF_OFFSET 0x1c0
+#define RK3288_DRV_BITS_PER_PIN 2
+#define RK3288_DRV_PINS_PER_REG 8
+#define RK3288_DRV_BANK_STRIDE 16
+
+static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = RK3288_DRV_PMU_OFFSET;
+
+ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3288_DRV_PINS_PER_REG;
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = RK3288_DRV_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x10;
+ *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+ }
+}
+
+#define RK3228_PULL_OFFSET 0x100
+
+static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ *reg = RK3228_PULL_OFFSET;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+}
+
+#define RK3228_DRV_GRF_OFFSET 0x200
+
+static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ *reg = RK3228_DRV_GRF_OFFSET;
+ *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+}
+
+#define RK3368_PULL_GRF_OFFSET 0x100
+#define RK3368_PULL_PMU_OFFSET 0x10
+
+static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 32 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = RK3368_PULL_PMU_OFFSET;
+
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = RK3368_PULL_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x10;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ }
+}
+
+#define RK3368_DRV_PMU_OFFSET 0x20
+#define RK3368_DRV_GRF_OFFSET 0x200
+
+static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The first 32 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = priv->regmap_pmu;
+ *reg = RK3368_DRV_PMU_OFFSET;
+
+ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3288_DRV_PINS_PER_REG;
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = RK3368_DRV_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 2nd bank */
+ *reg -= 0x10;
+ *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
+ *bit *= RK3288_DRV_BITS_PER_PIN;
+ }
+}
+
+#define RK3399_PULL_GRF_OFFSET 0xe040
+#define RK3399_PULL_PMU_OFFSET 0x40
+#define RK3399_DRV_3BITS_PER_PIN 3
+
+static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ /* The bank0:16 and bank1:32 pins are located in PMU */
+ if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
+ *regmap = priv->regmap_pmu;
+ *reg = RK3399_PULL_PMU_OFFSET;
+
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3188_PULL_PINS_PER_REG;
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ } else {
+ *regmap = priv->regmap_base;
+ *reg = RK3399_PULL_GRF_OFFSET;
+
+ /* correct the offset, as we're starting with the 3rd bank */
+ *reg -= 0x20;
+ *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+
+ *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
+ *bit *= RK3188_PULL_BITS_PER_PIN;
+ }
+}
+
+static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int drv_num = (pin_num / 8);
+
+ /* The bank0:16 and bank1:32 pins are located in PMU */
+ if ((bank->bank_num == 0) || (bank->bank_num == 1))
+ *regmap = priv->regmap_pmu;
+ else
+ *regmap = priv->regmap_base;
+
+ *reg = bank->drv[drv_num].offset;
+ if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
+ (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
+ *bit = (pin_num % 8) * 3;
+ else
+ *bit = (pin_num % 8) * 2;
+}
+
+static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
+ { 2, 4, 8, 12, -1, -1, -1, -1 },
+ { 3, 6, 9, 12, -1, -1, -1, -1 },
+ { 5, 10, 15, 20, -1, -1, -1, -1 },
+ { 4, 6, 8, 10, 12, 14, 16, 18 },
+ { 4, 7, 10, 13, 16, 19, 22, 26 }
+};
+
+static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+ struct regmap *regmap;
+ int reg, ret, i;
+ u32 data, rmask_bits, temp;
+ u8 bit;
+ int drv_type = bank->drv[pin_num / 8].drv_type;
+
+ debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
+ pin_num, strength);
+
+ ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
+
+ ret = -EINVAL;
+ for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
+ if (rockchip_perpin_drv_list[drv_type][i] == strength) {
+ ret = i;
+ break;
+ } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
+ ret = rockchip_perpin_drv_list[drv_type][i];
+ break;
+ }
+ }
+
+ if (ret < 0) {
+ debug("unsupported driver strength %d\n", strength);
+ return ret;
+ }
+
+ switch (drv_type) {
+ case DRV_TYPE_IO_1V8_3V0_AUTO:
+ case DRV_TYPE_IO_3V3_ONLY:
+ rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ switch (bit) {
+ case 0 ... 12:
+ /* regular case, nothing to do */
+ break;
+ case 15:
+ /*
+ * drive-strength offset is special, as it is spread
+ * over 2 registers, the bit data[15] contains bit 0
+ * of the value while temp[1:0] contains bits 2 and 1
+ */
+ data = (ret & 0x1) << 15;
+ temp = (ret >> 0x1) & 0x3;
+
+ data |= BIT(31);
+ ret = regmap_write(regmap, reg, data);
+ if (ret)
+ return ret;
+
+ temp |= (0x3 << 16);
+ reg += 0x4;
+ ret = regmap_write(regmap, reg, temp);
+
+ return ret;
+ case 18 ... 21:
+ /* setting fully enclosed in the second register */
+ reg += 4;
+ bit -= 16;
+ break;
+ default:
+ debug("unsupported bit: %d for pinctrl drive type: %d\n",
+ bit, drv_type);
+ return -EINVAL;
+ }
+ break;
+ case DRV_TYPE_IO_DEFAULT:
+ case DRV_TYPE_IO_1V8_OR_3V0:
+ case DRV_TYPE_IO_1V8_ONLY:
+ rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ break;
+ default:
+ debug("unsupported pinctrl drive type: %d\n",
+ drv_type);
+ return -EINVAL;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << rmask_bits) - 1) << (bit + 16);
+ data |= (ret << bit);
+
+ ret = regmap_write(regmap, reg, data);
+ return ret;
+}
+
+static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
+ {
+ PIN_CONFIG_BIAS_DISABLE,
+ PIN_CONFIG_BIAS_PULL_UP,
+ PIN_CONFIG_BIAS_PULL_DOWN,
+ PIN_CONFIG_BIAS_BUS_HOLD
+ },
+ {
+ PIN_CONFIG_BIAS_DISABLE,
+ PIN_CONFIG_BIAS_PULL_DOWN,
+ PIN_CONFIG_BIAS_DISABLE,
+ PIN_CONFIG_BIAS_PULL_UP
+ },
+};
+
+static int rockchip_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+ struct regmap *regmap;
+ int reg, ret, i, pull_type;
+ u8 bit;
+ u32 data;
+
+ debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
+ pin_num, pull);
+
+ /* rk3066b does support any pulls */
+ if (ctrl->type == RK3066B)
+ return pull ? -EINVAL : 0;
+
+ ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
+
+ switch (ctrl->type) {
+ case RK2928:
+ case RK3128:
+ data = BIT(bit + 16);
+ if (pull == PIN_CONFIG_BIAS_DISABLE)
+ data |= BIT(bit);
+ ret = regmap_write(regmap, reg, data);
+ break;
+ case PX30:
+ case RV1108:
+ case RK3188:
+ case RK3288:
+ case RK3368:
+ case RK3399:
+ pull_type = bank->pull_type[pin_num / 8];
+ ret = -EINVAL;
+ for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
+ i++) {
+ if (rockchip_pull_list[pull_type][i] == pull) {
+ ret = i;
+ break;
+ }
+ }
+
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (ret << bit);
+
+ ret = regmap_write(regmap, reg, data);
+ break;
+ default:
+ debug("unsupported pinctrl type\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+#define RK3328_SCHMITT_BITS_PER_PIN 1
+#define RK3328_SCHMITT_PINS_PER_REG 16
+#define RK3328_SCHMITT_BANK_STRIDE 8
+#define RK3328_SCHMITT_GRF_OFFSET 0x380
+
+static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ *reg = RK3328_SCHMITT_GRF_OFFSET;
+
+ *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
+ *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
+
+ return 0;
+}
+
+static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit;
+ u32 data;
+
+ debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
+ pin_num, enable);
+
+ ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
+ if (ret)
+ return ret;
+
+ /* enable the write to the equivalent lower bits */
+ data = BIT(bit + 16) | (enable << bit);
+
+ return regmap_write(regmap, reg, data);
+}
+
+/*
+ * Pinconf_ops handling
+ */
+static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
+ unsigned int pull)
+{
+ switch (ctrl->type) {
+ case RK2928:
+ case RK3128:
+ return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
+ pull == PIN_CONFIG_BIAS_DISABLE);
+ case RK3066B:
+ return pull ? false : true;
+ case PX30:
+ case RV1108:
+ case RK3188:
+ case RK3288:
+ case RK3368:
+ case RK3399:
+ return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
+ }
+
+ return false;
+}
+
+/* set the pin config settings for a specified pin */
+static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
+ u32 pin, u32 param, u32 arg)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+ int rc;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ rc = rockchip_set_pull(bank, pin, param);
+ if (rc)
+ return rc;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
+ case PIN_CONFIG_BIAS_BUS_HOLD:
+ if (!rockchip_pinconf_pull_valid(ctrl, param))
+ return -ENOTSUPP;
+
+ if (!arg)
+ return -EINVAL;
+
+ rc = rockchip_set_pull(bank, pin, param);
+ if (rc)
+ return rc;
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ if (!ctrl->drv_calc_reg)
+ return -ENOTSUPP;
+
+ rc = rockchip_set_drive_perpin(bank, pin, arg);
+ if (rc < 0)
+ return rc;
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (!ctrl->schmitt_calc_reg)
+ return -ENOTSUPP;
+
+ rc = rockchip_set_schmitt(bank, pin, arg);
+ if (rc < 0)
+ return rc;
+ break;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static const struct pinconf_param rockchip_conf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
+ { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
+ { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
+ { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
+ { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
+};
+
+static int rockchip_pinconf_prop_name_to_param(const char *property,
+ u32 *default_value)
+{
+ const struct pinconf_param *p, *end;
+
+ p = rockchip_conf_params;
+ end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
+
+ /* See if this pctldev supports this parameter */
+ for (; p < end; p++) {
+ if (!strcmp(property, p->property)) {
+ *default_value = p->default_value;
+ return p->param;
+ }
+ }
+
+ *default_value = 0;
+ return -EPERM;
+}
+
+static int rockchip_pinctrl_set_state(struct udevice *dev,
+ struct udevice *config)
+{
+ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
+ struct rockchip_pin_ctrl *ctrl = priv->ctrl;
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(config);
+ u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
+ u32 bank, pin, mux, conf, arg, default_val;
+ int ret, count, i;
+ const char *prop_name;
+ int pcfg_node, property_offset, prop_len, param;
+ const void *value;
+
+ count = fdtdec_get_int_array_count(blob, node, "rockchip,pins",
+ cells, ARRAY_SIZE(cells));
+ if (count < 0) {
+ debug("%s: bad array %d\n", __func__, count);
+ return -EINVAL;
+ }
+
+ if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
+ debug("%s: unsupported pins array count %d\n",
+ __func__, count);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < (count >> 2); i++) {
+ bank = cells[4 * i + 0];
+ pin = cells[4 * i + 1];
+ mux = cells[4 * i + 2];
+ conf = cells[4 * i + 3];
+
+ ret = rockchip_verify_config(dev, bank, pin);
+ if (ret)
+ return ret;
+
+ ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
+ if (ret)
+ return ret;
+
+ pcfg_node = fdt_node_offset_by_phandle(blob, conf);
+ if (pcfg_node < 0)
+ return -ENODEV;
+
+ fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
+ value = fdt_getprop_by_offset(blob, property_offset,
+ &prop_name, &prop_len);
+ if (!value)
+ return -ENOENT;
+
+ param = rockchip_pinconf_prop_name_to_param(prop_name,
+ &default_val);
+ if (param < 0)
+ break;
+
+ if (prop_len >= sizeof(fdt32_t))
+ arg = fdt32_to_cpu(*(fdt32_t *)value);
+ else
+ arg = default_val;
+
+ ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
+ param, arg);
+ if (ret) {
+ debug("%s: rockchip_pinconf_set fail: %d\n",
+ __func__, ret);
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops rockchip_pinctrl_ops = {
+ .set_state = rockchip_pinctrl_set_state,
+ .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
+};
+
+/* retrieve the soc specific data */
+static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
+{
+ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
+ struct rockchip_pin_ctrl *ctrl =
+ (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
+ struct rockchip_pin_bank *bank;
+ int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
+
+ grf_offs = ctrl->grf_mux_offset;
+ pmu_offs = ctrl->pmu_mux_offset;
+ drv_pmu_offs = ctrl->pmu_drv_offset;
+ drv_grf_offs = ctrl->grf_drv_offset;
+ bank = ctrl->pin_banks;
+
+ for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
+ int bank_pins = 0;
+
+ bank->priv = priv;
+ bank->pin_base = ctrl->nr_pins;
+ ctrl->nr_pins += bank->nr_pins;
+
+ /* calculate iomux and drv offsets */
+ for (j = 0; j < 4; j++) {
+ struct rockchip_iomux *iom = &bank->iomux[j];
+ struct rockchip_drv *drv = &bank->drv[j];
+ int inc;
+
+ if (bank_pins >= bank->nr_pins)
+ break;
+
+ /* preset iomux offset value, set new start value */
+ if (iom->offset >= 0) {
+ if (iom->type & IOMUX_SOURCE_PMU)
+ pmu_offs = iom->offset;
+ else
+ grf_offs = iom->offset;
+ } else { /* set current iomux offset */
+ iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+ pmu_offs : grf_offs;
+ }
+
+ /* preset drv offset value, set new start value */
+ if (drv->offset >= 0) {
+ if (iom->type & IOMUX_SOURCE_PMU)
+ drv_pmu_offs = drv->offset;
+ else
+ drv_grf_offs = drv->offset;
+ } else { /* set current drv offset */
+ drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+ drv_pmu_offs : drv_grf_offs;
+ }
+
+ debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
+ i, j, iom->offset, drv->offset);
+
+ /*
+ * Increase offset according to iomux width.
+ * 4bit iomux'es are spread over two registers.
+ */
+ inc = (iom->type & (IOMUX_WIDTH_4BIT |
+ IOMUX_WIDTH_3BIT)) ? 8 : 4;
+ if (iom->type & IOMUX_SOURCE_PMU)
+ pmu_offs += inc;
+ else
+ grf_offs += inc;
+
+ /*
+ * Increase offset according to drv width.
+ * 3bit drive-strenth'es are spread over two registers.
+ */
+ if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
+ (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
+ inc = 8;
+ else
+ inc = 4;
+
+ if (iom->type & IOMUX_SOURCE_PMU)
+ drv_pmu_offs += inc;
+ else
+ drv_grf_offs += inc;
+
+ bank_pins += 8;
+ }
+
+ /* calculate the per-bank recalced_mask */
+ for (j = 0; j < ctrl->niomux_recalced; j++) {
+ int pin = 0;
+
+ if (ctrl->iomux_recalced[j].num == bank->bank_num) {
+ pin = ctrl->iomux_recalced[j].pin;
+ bank->recalced_mask |= BIT(pin);
+ }
+ }
+
+ /* calculate the per-bank route_mask */
+ for (j = 0; j < ctrl->niomux_routes; j++) {
+ int pin = 0;
+
+ if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
+ pin = ctrl->iomux_routes[j].pin;
+ bank->route_mask |= BIT(pin);
+ }
+ }
+ }
+
+ return ctrl;
+}
+
+static int rockchip_pinctrl_probe(struct udevice *dev)
+{
+ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
+ struct rockchip_pin_ctrl *ctrl;
+ struct udevice *syscon;
+ struct regmap *regmap;
+ int ret = 0;
+
+ /* get rockchip grf syscon phandle */
+ ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
+ &syscon);
+ if (ret) {
+ debug("unable to find rockchip,grf syscon device (%d)\n", ret);
+ return ret;
+ }
+
+ /* get grf-reg base address */
+ regmap = syscon_get_regmap(syscon);
+ if (!regmap) {
+ debug("unable to find rockchip grf regmap\n");
+ return -ENODEV;
+ }
+ priv->regmap_base = regmap;
+
+ /* option: get pmu-reg base address */
+ ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
+ &syscon);
+ if (!ret) {
+ /* get pmugrf-reg base address */
+ regmap = syscon_get_regmap(syscon);
+ if (!regmap) {
+ debug("unable to find rockchip pmu regmap\n");
+ return -ENODEV;
+ }
+ priv->regmap_pmu = regmap;
+ }
+
+ ctrl = rockchip_pinctrl_get_soc_data(dev);
+ if (!ctrl) {
+ debug("driver data not available\n");
+ return -EINVAL;
+ }
+
+ priv->ctrl = ctrl;
+ return 0;
+}
+
+static struct rockchip_pin_bank px30_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU
+ ),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT
+ ),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT
+ ),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT
+ ),
+};
+
+static struct rockchip_pin_ctrl px30_pin_ctrl = {
+ .pin_banks = px30_pin_banks,
+ .nr_banks = ARRAY_SIZE(px30_pin_banks),
+ .label = "PX30-GPIO",
+ .type = PX30,
+ .grf_mux_offset = 0x0,
+ .pmu_mux_offset = 0x0,
+ .iomux_routes = px30_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
+ .pull_calc_reg = px30_calc_pull_reg_and_bit,
+ .drv_calc_reg = px30_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rv1108_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
+};
+
+static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
+ .pin_banks = rv1108_pin_banks,
+ .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
+ .label = "RV1108-GPIO",
+ .type = RV1108,
+ .grf_mux_offset = 0x10,
+ .pmu_mux_offset = 0x0,
+ .iomux_recalced = rv1108_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
+ .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
+ .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk2928_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+};
+
+static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
+ .pin_banks = rk2928_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
+ .label = "RK2928-GPIO",
+ .type = RK2928,
+ .grf_mux_offset = 0xa8,
+ .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3036_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+};
+
+static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
+ .pin_banks = rk3036_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
+ .label = "RK3036-GPIO",
+ .type = RK2928,
+ .grf_mux_offset = 0xa8,
+ .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3066a_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+ PIN_BANK(4, 32, "gpio4"),
+ PIN_BANK(6, 16, "gpio6"),
+};
+
+static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
+ .pin_banks = rk3066a_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
+ .label = "RK3066a-GPIO",
+ .type = RK2928,
+ .grf_mux_offset = 0xa8,
+ .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3066b_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+};
+
+static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
+ .pin_banks = rk3066b_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
+ .label = "RK3066b-GPIO",
+ .type = RK3066B,
+ .grf_mux_offset = 0x60,
+};
+
+static struct rockchip_pin_bank rk3128_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+};
+
+static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
+ .pin_banks = rk3128_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
+ .label = "RK3128-GPIO",
+ .type = RK3128,
+ .grf_mux_offset = 0xa8,
+ .iomux_recalced = rk3128_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
+ .iomux_routes = rk3128_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
+ .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3188_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+};
+
+static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
+ .pin_banks = rk3188_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
+ .label = "RK3188-GPIO",
+ .type = RK3188,
+ .grf_mux_offset = 0x60,
+ .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3228_pin_banks[] = {
+ PIN_BANK(0, 32, "gpio0"),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+};
+
+static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
+ .pin_banks = rk3228_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
+ .label = "RK3228-GPIO",
+ .type = RK3288,
+ .grf_mux_offset = 0x0,
+ .iomux_routes = rk3228_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
+ .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3288_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_UNROUTED
+ ),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
+ IOMUX_UNROUTED,
+ IOMUX_UNROUTED,
+ 0
+ ),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0,
+ 0
+ ),
+ PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
+ 0,
+ 0,
+ IOMUX_UNROUTED
+ ),
+ PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
+ PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
+ 0,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_UNROUTED
+ ),
+ PIN_BANK(8, 16, "gpio8"),
+};
+
+static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
+ .pin_banks = rk3288_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
+ .label = "RK3288-GPIO",
+ .type = RK3288,
+ .grf_mux_offset = 0x0,
+ .pmu_mux_offset = 0x84,
+ .iomux_routes = rk3288_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
+ .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3328_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
+ IOMUX_WIDTH_3BIT,
+ IOMUX_WIDTH_3BIT,
+ 0),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
+ IOMUX_WIDTH_3BIT,
+ IOMUX_WIDTH_3BIT,
+ 0,
+ 0),
+};
+
+static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
+ .pin_banks = rk3328_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
+ .label = "RK3328-GPIO",
+ .type = RK3288,
+ .grf_mux_offset = 0x0,
+ .iomux_recalced = rk3328_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
+ .iomux_routes = rk3328_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
+ .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3368_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU
+ ),
+ PIN_BANK(1, 32, "gpio1"),
+ PIN_BANK(2, 32, "gpio2"),
+ PIN_BANK(3, 32, "gpio3"),
+};
+
+static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
+ .pin_banks = rk3368_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
+ .label = "RK3368-GPIO",
+ .type = RK3368,
+ .grf_mux_offset = 0x0,
+ .pmu_mux_offset = 0x0,
+ .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
+};
+
+static struct rockchip_pin_bank rk3399_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ DRV_TYPE_IO_1V8_ONLY,
+ DRV_TYPE_IO_1V8_ONLY,
+ DRV_TYPE_IO_DEFAULT,
+ DRV_TYPE_IO_DEFAULT,
+ 0x80,
+ 0x88,
+ -1,
+ -1,
+ PULL_TYPE_IO_1V8_ONLY,
+ PULL_TYPE_IO_1V8_ONLY,
+ PULL_TYPE_IO_DEFAULT,
+ PULL_TYPE_IO_DEFAULT
+ ),
+ PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ IOMUX_SOURCE_PMU,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ 0xa0,
+ 0xa8,
+ 0xb0,
+ 0xb8
+ ),
+ PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_ONLY,
+ DRV_TYPE_IO_1V8_ONLY,
+ PULL_TYPE_IO_DEFAULT,
+ PULL_TYPE_IO_DEFAULT,
+ PULL_TYPE_IO_1V8_ONLY,
+ PULL_TYPE_IO_1V8_ONLY
+ ),
+ PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
+ DRV_TYPE_IO_3V3_ONLY,
+ DRV_TYPE_IO_3V3_ONLY,
+ DRV_TYPE_IO_1V8_OR_3V0
+ ),
+ PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_3V0_AUTO,
+ DRV_TYPE_IO_1V8_OR_3V0,
+ DRV_TYPE_IO_1V8_OR_3V0
+ ),
+};
+
+static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
+ .pin_banks = rk3399_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
+ .label = "RK3399-GPIO",
+ .type = RK3399,
+ .grf_mux_offset = 0xe000,
+ .pmu_mux_offset = 0x0,
+ .grf_drv_offset = 0xe100,
+ .pmu_drv_offset = 0x80,
+ .iomux_routes = rk3399_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
+ .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
+ .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
+};
+
+static const struct udevice_id rockchip_pinctrl_dt_match[] = {
+ { .compatible = "rockchip,px30-pinctrl",
+ .data = (ulong)&px30_pin_ctrl },
+ { .compatible = "rockchip,rv1108-pinctrl",
+ .data = (ulong)&rv1108_pin_ctrl },
+ { .compatible = "rockchip,rk2928-pinctrl",
+ .data = (ulong)&rk2928_pin_ctrl },
+ { .compatible = "rockchip,rk3036-pinctrl",
+ .data = (ulong)&rk3036_pin_ctrl },
+ { .compatible = "rockchip,rk3066a-pinctrl",
+ .data = (ulong)&rk3066a_pin_ctrl },
+ { .compatible = "rockchip,rk3066b-pinctrl",
+ .data = (ulong)&rk3066b_pin_ctrl },
+ { .compatible = "rockchip,rk3128-pinctrl",
+ .data = (ulong)&rk3128_pin_ctrl },
+ { .compatible = "rockchip,rk3188-pinctrl",
+ .data = (ulong)&rk3188_pin_ctrl },
+ { .compatible = "rockchip,rk3228-pinctrl",
+ .data = (ulong)&rk3228_pin_ctrl },
+ { .compatible = "rockchip,rk3288-pinctrl",
+ .data = (ulong)&rk3288_pin_ctrl },
+ { .compatible = "rockchip,rk3328-pinctrl",
+ .data = (ulong)&rk3328_pin_ctrl },
+ { .compatible = "rockchip,rk3368-pinctrl",
+ .data = (ulong)&rk3368_pin_ctrl },
+ { .compatible = "rockchip,rk3399-pinctrl",
+ .data = (ulong)&rk3399_pin_ctrl },
+ {},
+};
+
+U_BOOT_DRIVER(pinctrl_rockchip) = {
+ .name = "rockchip_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rockchip_pinctrl_dt_match,
+ .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 7/9] rockchip: defconfig: Clean the unused pinctrl config
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
` (5 preceding siblings ...)
2018-02-03 6:56 ` [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip " David Wu
@ 2018-02-03 6:56 ` David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
2018-02-03 6:57 ` [U-Boot] [PATCH 8/9] pinctrl: rockchip: Clean the unused rockchip pinctrl drivers David Wu
2018-02-03 6:57 ` [U-Boot] [PATCH 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration David Wu
8 siblings, 2 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:56 UTC (permalink / raw)
To: u-boot
If we used the pinctrl-rockchip driver, these config is not needed,
so remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
configs/chromebit_mickey_defconfig | 2 --
configs/chromebook_jerry_defconfig | 2 --
configs/chromebook_minnie_defconfig | 2 --
configs/evb-px5_defconfig | 1 -
configs/evb-rk3128_defconfig | 1 -
configs/evb-rk3229_defconfig | 1 -
configs/evb-rk3288_defconfig | 2 --
configs/evb-rk3399_defconfig | 1 -
configs/evb-rv1108_defconfig | 1 -
configs/fennec-rk3288_defconfig | 2 --
configs/firefly-rk3288_defconfig | 2 --
configs/firefly-rk3399_defconfig | 1 -
configs/geekbox_defconfig | 1 -
configs/kylin-rk3036_defconfig | 1 -
configs/lion-rk3368_defconfig | 1 -
configs/miqi-rk3288_defconfig | 2 --
configs/phycore-rk3288_defconfig | 2 --
configs/popmetal-rk3288_defconfig | 2 --
configs/puma-rk3399_defconfig | 1 -
configs/rock2_defconfig | 2 --
configs/rock_defconfig | 1 -
configs/sandbox_defconfig | 2 --
configs/sandbox_flattree_defconfig | 2 --
configs/sandbox_noblk_defconfig | 2 --
configs/sheep-rk3368_defconfig | 1 -
configs/tinker-rk3288_defconfig | 2 --
configs/vyasa-rk3288_defconfig | 2 --
27 files changed, 42 deletions(-)
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index 93c5c4e..7d51348 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -54,8 +54,6 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 57d35e9..76022fa 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -56,8 +56,6 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 529444a..c2d2422 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -55,8 +55,6 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index 0e8594c..663d9fc 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -16,7 +16,6 @@ CONFIG_CLK=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_RAM=y
CONFIG_DEBUG_UART_BASE=0xFF1c0000
CONFIG_DEBUG_UART_CLOCK=24000000
diff --git a/configs/evb-rk3128_defconfig b/configs/evb-rk3128_defconfig
index d49cea0..a767154 100644
--- a/configs/evb-rk3128_defconfig
+++ b/configs/evb-rk3128_defconfig
@@ -24,7 +24,6 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3128=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_RAM=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 39469b4..c203d6f 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -37,7 +37,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PHY=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK322X=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index 09a8844..34498fa 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -51,8 +51,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
CONFIG_REGULATOR_ACT8846=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 54eb703..d026d0a 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -40,7 +40,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3399=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig
index a59d89e..5b80988 100644
--- a/configs/evb-rv1108_defconfig
+++ b/configs/evb-rv1108_defconfig
@@ -31,7 +31,6 @@ CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RV1108=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_BAUDRATE=1500000
# CONFIG_SPL_SERIAL_PRESENT is not set
diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig
index 9ae1b33..89546a6 100644
--- a/configs/fennec-rk3288_defconfig
+++ b/configs/fennec-rk3288_defconfig
@@ -50,8 +50,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 3a0bd79..cf18ae7 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -54,8 +54,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_ACT8846=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 4071fea..6cd0818 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -43,7 +43,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3399=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_PWM=y
diff --git a/configs/geekbox_defconfig b/configs/geekbox_defconfig
index 3baad0a..1ef5658 100644
--- a/configs/geekbox_defconfig
+++ b/configs/geekbox_defconfig
@@ -10,7 +10,6 @@ CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_RAM=y
CONFIG_DEBUG_UART_BASE=0xFF690000
CONFIG_DEBUG_UART_CLOCK=24000000
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 7af01e2..def9179 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -35,7 +35,6 @@ CONFIG_LED=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3036=y
CONFIG_DM_REGULATOR_FIXED=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_SYSRESET=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 9548b96..a2c230b 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -73,7 +73,6 @@ CONFIG_RGMII=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 3a5ec2d..99057f3 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -50,8 +50,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
CONFIG_REGULATOR_ACT8846=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index 969b0e6..68f7f51 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -54,8 +54,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index 94f4979..b2c73cf 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -50,8 +50,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 8446de7..f0ab359 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -65,7 +65,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3399=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_SPL_DM_REGULATOR=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index 0a95e6a..048863d 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -50,8 +50,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_ACT8846=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index 483f64b..6d5f030 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -35,7 +35,6 @@ CONFIG_LED=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3188=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_ACT8846=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 7efb4eb..e0a7656 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -131,8 +131,6 @@ CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
-CONFIG_PINCTRL_ROCKCHIP_RK3036=y
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_POWER_DOMAIN=y
CONFIG_SANDBOX_POWER_DOMAIN=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 1aa28c7..0a50c04 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -114,8 +114,6 @@ CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
-CONFIG_PINCTRL_ROCKCHIP_RK3036=y
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_POWER_DOMAIN=y
CONFIG_SANDBOX_POWER_DOMAIN=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index b2f55d9..544882f 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -124,8 +124,6 @@ CONFIG_PHY=y
CONFIG_PHY_SANDBOX=y
CONFIG_PINCTRL=y
CONFIG_PINCONF=y
-CONFIG_PINCTRL_ROCKCHIP_RK3036=y
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_PINCTRL_SANDBOX=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_ACT8846=y
diff --git a/configs/sheep-rk3368_defconfig b/configs/sheep-rk3368_defconfig
index f019b68..f0a32b8 100644
--- a/configs/sheep-rk3368_defconfig
+++ b/configs/sheep-rk3368_defconfig
@@ -14,7 +14,6 @@ CONFIG_CLK=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ROCKCHIP_RK3368=y
CONFIG_RAM=y
CONFIG_DEBUG_UART_BASE=0xFF1b0000
CONFIG_DEBUG_UART_CLOCK=24000000
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index a0df3fd..7d35bab 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -53,8 +53,6 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_DM_REGULATOR_FIXED=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 5d8fa22..e5742be 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -47,8 +47,6 @@ CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
-# CONFIG_SPL_PINCTRL_FULL is not set
-CONFIG_PINCTRL_ROCKCHIP_RK3288=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_PMIC_RK8XX=y
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 8/9] pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
` (6 preceding siblings ...)
2018-02-03 6:56 ` [U-Boot] [PATCH 7/9] rockchip: defconfig: Clean the unused pinctrl config David Wu
@ 2018-02-03 6:57 ` David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
2018-02-03 6:57 ` [U-Boot] [PATCH 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration David Wu
8 siblings, 2 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:57 UTC (permalink / raw)
To: u-boot
If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
drivers/pinctrl/rockchip/Makefile | 15 -
drivers/pinctrl/rockchip/pinctrl_rk3036.c | 264 ---------
drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 -------
drivers/pinctrl/rockchip/pinctrl_rk3188.c | 610 --------------------
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 895 ------------------------------
drivers/pinctrl/rockchip/pinctrl_rk3288.c | 870 -----------------------------
drivers/pinctrl/rockchip/pinctrl_rk3328.c | 708 -----------------------
drivers/pinctrl/rockchip/pinctrl_rk3368.c | 742 -------------------------
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 457 ---------------
drivers/pinctrl/rockchip/pinctrl_rv1108.c | 582 -------------------
10 files changed, 5330 deletions(-)
delete mode 100644 drivers/pinctrl/rockchip/Makefile
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3399.c
delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rv1108.c
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
deleted file mode 100644
index f09c6e1..0000000
--- a/drivers/pinctrl/rockchip/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Copyright (c) 2017 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3128) += pinctrl_rk3128.o
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3399) += pinctrl_rk3399.o
-obj-$(CONFIG_PINCTRL_ROCKCHIP_RV1108) += pinctrl_rv1108.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c
deleted file mode 100644
index 94f6d7a..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Pinctrl driver for Rockchip 3036 SoCs
- * (C) Copyright 2015 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3036.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rk3036_pinctrl_priv {
- struct rk3036_grf *grf;
-};
-
-static void pinctrl_rk3036_pwm_config(struct rk3036_grf *grf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
- GPIO0D2_PWM0 << GPIO0D2_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A0_MASK,
- GPIO0A0_PWM1 << GPIO0A0_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0A1_MASK,
- GPIO0A1_PWM2 << GPIO0A1_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio0a_iomux, GPIO0D3_MASK,
- GPIO0D3_PWM3 << GPIO0D3_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3036_i2c_config(struct rk3036_grf *grf, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A1_MASK | GPIO0A0_MASK,
- GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
- GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
-
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A3_MASK | GPIO0A2_MASK,
- GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
- GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C5_MASK | GPIO2C4_MASK,
- GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
- GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
-
- break;
- }
-}
-
-static void pinctrl_rk3036_spi_config(struct rk3036_grf *grf, int cs)
-{
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D6_MASK,
- GPIO1D6_SPI_CSN0 << GPIO1D6_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio1d_iomux, GPIO1D7_MASK,
- GPIO1D7_SPI_CSN1 << GPIO1D7_SHIFT);
- break;
- }
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D5_MASK | GPIO1D4_MASK,
- GPIO1D5_SPI_TXD << GPIO1D5_SHIFT |
- GPIO1D4_SPI_RXD << GPIO1D4_SHIFT);
-
- rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A0_MASK,
- GPIO2A0_SPI_CLK << GPIO2A0_SHIFT);
-}
-
-static void pinctrl_rk3036_uart_config(struct rk3036_grf *grf, int uart_id)
-{
- switch (uart_id) {
- case PERIPH_ID_UART0:
- rk_clrsetreg(&grf->gpio0c_iomux,
- GPIO0C3_MASK | GPIO0C2_MASK |
- GPIO0C1_MASK | GPIO0C0_MASK,
- GPIO0C3_UART0_CTSN << GPIO0C3_SHIFT |
- GPIO0C2_UART0_RTSN << GPIO0C2_SHIFT |
- GPIO0C1_UART0_SIN << GPIO0C1_SHIFT |
- GPIO0C0_UART0_SOUT << GPIO0C0_SHIFT);
- break;
- case PERIPH_ID_UART1:
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C7_MASK | GPIO2C6_MASK,
- GPIO2C7_UART1_SOUT << GPIO2C7_SHIFT |
- GPIO2C6_UART1_SIN << GPIO2C6_SHIFT);
- break;
- case PERIPH_ID_UART2:
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C3_MASK | GPIO1C2_MASK,
- GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT |
- GPIO1C2_UART2_SIN << GPIO1C2_SHIFT);
- break;
- }
-}
-
-static void pinctrl_rk3036_sdmmc_config(struct rk3036_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
- GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
- GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
- GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
- GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
- GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
- GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
- GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
- GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A4_MASK | GPIO2A1_MASK,
- GPIO2A4_EMMC_CMD << GPIO2A4_SHIFT |
- GPIO2A1_EMMC_CLKOUT << GPIO2A1_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio1c_iomux, 0xffff,
- GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
- GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
- GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
- GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
- GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
- GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
- break;
- }
-}
-
-static int rk3036_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- pinctrl_rk3036_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- pinctrl_rk3036_i2c_config(priv->grf, func);
- break;
- case PERIPH_ID_SPI0:
- pinctrl_rk3036_spi_config(priv->grf, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- pinctrl_rk3036_uart_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3036_sdmmc_config(priv->grf, func);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3036_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 14:
- return PERIPH_ID_SDCARD;
- case 16:
- return PERIPH_ID_EMMC;
- case 20:
- return PERIPH_ID_UART0;
- case 21:
- return PERIPH_ID_UART1;
- case 22:
- return PERIPH_ID_UART2;
- case 23:
- return PERIPH_ID_SPI0;
- case 24:
- return PERIPH_ID_I2C0;
- case 25:
- return PERIPH_ID_I2C1;
- case 26:
- return PERIPH_ID_I2C2;
- case 30:
- return PERIPH_ID_PWM0;
- }
- return -ENOENT;
-}
-
-static int rk3036_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3036_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk3036_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3036_pinctrl_ops = {
- .set_state_simple = rk3036_pinctrl_set_state_simple,
- .request = rk3036_pinctrl_request,
- .get_periph_id = rk3036_pinctrl_get_periph_id,
-};
-
-static int rk3036_pinctrl_probe(struct udevice *dev)
-{
- struct rk3036_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- debug("%s: grf=%p\n", __func__, priv->grf);
- return 0;
-}
-
-static const struct udevice_id rk3036_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3036-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3036) = {
- .name = "pinctrl_rk3036",
- .id = UCLASS_PINCTRL,
- .of_match = rk3036_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv),
- .ops = &rk3036_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk3036_pinctrl_probe,
-};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3128.c b/drivers/pinctrl/rockchip/pinctrl_rk3128.c
deleted file mode 100644
index b1c32ac..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rk3128.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Pinctrl driver for Rockchip 3128 SoCs
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3128.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rk3128_pinctrl_priv {
- struct rk3128_grf *grf;
-};
-
-static void pinctrl_rk3128_i2c_config(struct rk3128_grf *grf, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A1_MASK | GPIO0A0_MASK,
- GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
- GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
-
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A3_MASK | GPIO0A2_MASK,
- GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
- GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2c_iomux2,
- GPIO2C5_MASK | GPIO2C4_MASK,
- GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
- GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A7_MASK | GPIO0A6_MASK,
- GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
- GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
-
- break;
- }
-}
-
-static void pinctrl_rk3128_sdmmc_config(struct rk3128_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
- GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
- GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
- GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
- GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
- GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
- GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
- GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
- GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A5_MASK | GPIO2A7_MASK,
- GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
- GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio1c_iomux, 0x0fff,
- GPIO1C5_MMC0_D3 << GPIO1C5_SHIFT |
- GPIO1C4_MMC0_D2 << GPIO1C4_SHIFT |
- GPIO1C3_MMC0_D1 << GPIO1C3_SHIFT |
- GPIO1C2_MMC0_D0 << GPIO1C2_SHIFT |
- GPIO1C1_MMC0_DETN << GPIO1C1_SHIFT |
- GPIO1C0_MMC0_CLKOUT << GPIO1C0_SHIFT);
- break;
- }
-}
-
-static int rk3128_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- pinctrl_rk3128_i2c_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3128_sdmmc_config(priv->grf, func);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3128_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
- "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 14:
- return PERIPH_ID_SDCARD;
- case 16:
- return PERIPH_ID_EMMC;
- case 20:
- return PERIPH_ID_UART0;
- case 21:
- return PERIPH_ID_UART1;
- case 22:
- return PERIPH_ID_UART2;
- case 23:
- return PERIPH_ID_SPI0;
- case 24:
- return PERIPH_ID_I2C0;
- case 25:
- return PERIPH_ID_I2C1;
- case 26:
- return PERIPH_ID_I2C2;
- case 27:
- return PERIPH_ID_I2C3;
- case 30:
- return PERIPH_ID_PWM0;
- }
- return -ENOENT;
-}
-
-static int rk3128_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3128_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk3128_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3128_pinctrl_ops = {
- .set_state_simple = rk3128_pinctrl_set_state_simple,
- .request = rk3128_pinctrl_request,
- .get_periph_id = rk3128_pinctrl_get_periph_id,
-};
-
-static int rk3128_pinctrl_probe(struct udevice *dev)
-{
- struct rk3128_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- debug("%s: grf=%p\n", __func__, priv->grf);
- return 0;
-}
-
-static const struct udevice_id rk3128_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3128-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3128) = {
- .name = "pinctrl_rk3128",
- .id = UCLASS_PINCTRL,
- .of_match = rk3128_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3128_pinctrl_priv),
- .ops = &rk3128_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk3128_pinctrl_probe,
-};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c
deleted file mode 100644
index 692d8e2..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rk3188.c
+++ /dev/null
@@ -1,610 +0,0 @@
-/*
- * Pinctrl driver for Rockchip RK3188 SoCs
- * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3188.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3188.h>
-#include <dm/pinctrl.h>
-#include <dm/root.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rk3188_pinctrl_priv {
- struct rk3188_grf *grf;
- struct rk3188_pmu *pmu;
- int num_banks;
-};
-
-/**
- * Encode variants of iomux registers into a type variable
- */
-#define IOMUX_GPIO_ONLY BIT(0)
-
-/**
- * @type: iomux variant using IOMUX_* constants
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following iomux registers.
- */
-struct rockchip_iomux {
- u8 type;
- s16 offset;
-};
-
-/**
- * @reg: register offset of the gpio bank
- * @nr_pins: number of pins in this bank
- * @bank_num: number of the bank, to account for holes
- * @name: name of the bank
- * @iomux: array describing the 4 iomux sources of the bank
- */
-struct rockchip_pin_bank {
- u16 reg;
- u8 nr_pins;
- u8 bank_num;
- char *name;
- struct rockchip_iomux iomux[4];
-};
-
-#define PIN_BANK(id, pins, label) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .offset = -1 }, \
- { .offset = -1 }, \
- { .offset = -1 }, \
- { .offset = -1 }, \
- }, \
- }
-
-#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .type = iom0, .offset = -1 }, \
- { .type = iom1, .offset = -1 }, \
- { .type = iom2, .offset = -1 }, \
- { .type = iom3, .offset = -1 }, \
- }, \
- }
-
-#ifndef CONFIG_SPL_BUILD
-static struct rockchip_pin_bank rk3188_pin_banks[] = {
- PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
- PIN_BANK(1, 32, "gpio1"),
- PIN_BANK(2, 32, "gpio2"),
- PIN_BANK(3, 32, "gpio3"),
-};
-#endif
-
-static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT,
- GPIO3D3_PWM_0 << GPIO3D3_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT,
- GPIO3D4_PWM_1 << GPIO3D4_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT,
- GPIO3D5_PWM_2 << GPIO3D5_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT,
- GPIO3D6_PWM_3 << GPIO3D6_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf,
- struct rk3188_pmu *pmu, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D1_MASK << GPIO1D1_SHIFT |
- GPIO1D0_MASK << GPIO1D0_SHIFT,
- GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT |
- GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT);
- /* enable new i2c controller */
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT,
- 1 << RKI2C0_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D3_MASK << GPIO1D3_SHIFT |
- GPIO1D2_MASK << GPIO1D2_SHIFT,
- GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT |
- GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT);
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT,
- 1 << RKI2C1_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D5_MASK << GPIO1D5_SHIFT |
- GPIO1D4_MASK << GPIO1D4_SHIFT,
- GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT |
- GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT);
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT,
- 1 << RKI2C2_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio3b_iomux,
- GPIO3B7_MASK << GPIO3B7_SHIFT |
- GPIO3B6_MASK << GPIO3B6_SHIFT,
- GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT |
- GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT);
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT,
- 1 << RKI2C3_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C4:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D7_MASK << GPIO1D7_SHIFT |
- GPIO1D6_MASK << GPIO1D6_SHIFT,
- GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT |
- GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT);
- rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT,
- 1 << RKI2C4_SEL_SHIFT);
- break;
- default:
- debug("i2c id = %d iomux error!\n", i2c_id);
- break;
- }
-}
-
-static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf,
- enum periph_id spi_id, int cs)
-{
- switch (spi_id) {
- case PERIPH_ID_SPI0:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A7_MASK << GPIO1A7_SHIFT,
- GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B7_MASK << GPIO1B7_SHIFT,
- GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A4_MASK << GPIO1A4_SHIFT |
- GPIO1A5_MASK << GPIO1A5_SHIFT |
- GPIO1A6_MASK << GPIO1A6_SHIFT,
- GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT |
- GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT |
- GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT);
- break;
- case PERIPH_ID_SPI1:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D7_MASK << GPIO0D7_SHIFT,
- GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B6_MASK << GPIO1B6_SHIFT,
- GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D4_MASK << GPIO0D4_SHIFT |
- GPIO0D5_MASK << GPIO0D5_SHIFT |
- GPIO0D6_MASK << GPIO0D6_SHIFT,
- GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT |
- GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT |
- GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT);
- break;
- default:
- goto err;
- }
-
- return 0;
-err:
- debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
- return -ENOENT;
-}
-
-static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id)
-{
- switch (uart_id) {
- case PERIPH_ID_UART0:
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A3_MASK << GPIO1A3_SHIFT |
- GPIO1A2_MASK << GPIO1A2_SHIFT |
- GPIO1A1_MASK << GPIO1A1_SHIFT |
- GPIO1A0_MASK << GPIO1A0_SHIFT,
- GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT |
- GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT |
- GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT |
- GPIO1A0_UART0_SIN << GPIO1A0_SHIFT);
- break;
- case PERIPH_ID_UART1:
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A7_MASK << GPIO1A7_SHIFT |
- GPIO1A6_MASK << GPIO1A6_SHIFT |
- GPIO1A5_MASK << GPIO1A5_SHIFT |
- GPIO1A4_MASK << GPIO1A4_SHIFT,
- GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT |
- GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT |
- GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT |
- GPIO1A4_UART1_SIN << GPIO1A4_SHIFT);
- break;
- case PERIPH_ID_UART2:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK << GPIO1B1_SHIFT |
- GPIO1B0_MASK << GPIO1B0_SHIFT,
- GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT |
- GPIO1B0_UART2_SIN << GPIO1B0_SHIFT);
- break;
- case PERIPH_ID_UART3:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B5_MASK << GPIO1B5_SHIFT |
- GPIO1B4_MASK << GPIO1B4_SHIFT |
- GPIO1B3_MASK << GPIO1B3_SHIFT |
- GPIO1B2_MASK << GPIO1B2_SHIFT,
- GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT |
- GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT |
- GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT |
- GPIO1B2_UART3_SIN << GPIO1B2_SHIFT);
- break;
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT,
- 1 << EMMC_FLASH_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D2_MASK << GPIO0D2_SHIFT |
- GPIO0D0_MASK << GPIO0D0_SHIFT,
- GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT |
- GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio3b_iomux,
- GPIO3B0_MASK << GPIO3B0_SHIFT,
- GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT);
- rk_clrsetreg(&grf->gpio3a_iomux,
- GPIO3A7_MASK << GPIO3A7_SHIFT |
- GPIO3A6_MASK << GPIO3A6_SHIFT |
- GPIO3A5_MASK << GPIO3A5_SHIFT |
- GPIO3A4_MASK << GPIO3A4_SHIFT |
- GPIO3A3_MASK << GPIO3A3_SHIFT |
- GPIO3A3_MASK << GPIO3A2_SHIFT,
- GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT |
- GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT |
- GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT |
- GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT |
- GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT |
- GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- pinctrl_rk3188_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- pinctrl_rk3188_spi_config(priv->grf, func, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3188_uart_config(priv->grf, func);
- break;
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3188_sdmmc_config(priv->grf, func);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3188_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 44:
- return PERIPH_ID_SPI0;
- case 45:
- return PERIPH_ID_SPI1;
- case 46:
- return PERIPH_ID_SPI2;
- case 60:
- return PERIPH_ID_I2C0;
- case 62: /* Note strange order */
- return PERIPH_ID_I2C1;
- case 61:
- return PERIPH_ID_I2C2;
- case 63:
- return PERIPH_ID_I2C3;
- case 64:
- return PERIPH_ID_I2C4;
- case 65:
- return PERIPH_ID_I2C5;
- }
-#endif
-
- return -ENOENT;
-}
-
-static int rk3188_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3188_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk3188_pinctrl_request(dev, func, 0);
-}
-
-#ifndef CONFIG_SPL_BUILD
-int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv,
- int banknum, int ind, u32 **addrp, uint *shiftp,
- uint *maskp)
-{
- struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum];
- uint muxnum;
- u32 *addr;
-
- for (muxnum = 0; muxnum < 4; muxnum++) {
- struct rockchip_iomux *mux = &bank->iomux[muxnum];
-
- if (ind >= 8) {
- ind -= 8;
- continue;
- }
-
- addr = &priv->grf->gpio0c_iomux - 2;
- addr += mux->offset;
- *shiftp = ind & 7;
- *maskp = 3;
- *shiftp *= 2;
-
- debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
- *maskp, *shiftp);
- *addrp = addr;
- return 0;
- }
-
- return -EINVAL;
-}
-
-static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
- int index)
-{
- struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
- uint shift;
- uint mask;
- u32 *addr;
- int ret;
-
- ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
- &mask);
- if (ret)
- return ret;
- return (readl(addr) & mask) >> shift;
-}
-
-static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
- int muxval, int flags)
-{
- struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
- uint shift, ind = index;
- uint mask;
- u32 *addr;
- int ret;
-
- debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
- ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
- &mask);
- if (ret)
- return ret;
- rk_clrsetreg(addr, mask << shift, muxval << shift);
-
- /* Handle pullup/pulldown */
- if (flags) {
- uint val = 0;
-
- if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
- val = 1;
- else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
- val = 2;
-
- ind = index >> 3;
-
- if (banknum == 0 && index < 12) {
- addr = &priv->pmu->gpio0_p[ind];
- shift = (index & 7) * 2;
- } else if (banknum == 0 && index >= 12) {
- addr = &priv->grf->gpio0_p[ind - 1];
- /*
- * The bits in the grf-registers have an inverse
- * ordering with the lowest pin being in bits 15:14
- * and the highest pin in bits 1:0 .
- */
- shift = (7 - (index & 7)) * 2;
- } else {
- addr = &priv->grf->gpio1_p[banknum - 1][ind];
- shift = (7 - (index & 7)) * 2;
- }
- debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
- shift);
- rk_clrsetreg(addr, 3 << shift, val << shift);
- }
-
- return 0;
-}
-
-static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config)
-{
- const void *blob = gd->fdt_blob;
- int pcfg_node, ret, flags, count, i;
- u32 cell[60], *ptr;
-
- debug("%s: %s %s\n", __func__, dev->name, config->name);
- ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
- "rockchip,pins", cell,
- ARRAY_SIZE(cell));
- if (ret < 0) {
- debug("%s: bad array %d\n", __func__, ret);
- return -EINVAL;
- }
- count = ret;
- for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
- pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
- if (pcfg_node < 0)
- return -EINVAL;
- flags = pinctrl_decode_pin_config(blob, pcfg_node);
- if (flags < 0)
- return flags;
-
- ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
- flags);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-static struct pinctrl_ops rk3188_pinctrl_ops = {
-#ifndef CONFIG_SPL_BUILD
- .set_state = rk3188_pinctrl_set_state,
- .get_gpio_mux = rk3188_pinctrl_get_gpio_mux,
-#endif
- .set_state_simple = rk3188_pinctrl_set_state_simple,
- .request = rk3188_pinctrl_request,
- .get_periph_id = rk3188_pinctrl_get_periph_id,
-};
-
-#ifndef CONFIG_SPL_BUILD
-static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv,
- struct rockchip_pin_bank *banks,
- int count)
-{
- struct rockchip_pin_bank *bank;
- uint reg, muxnum, banknum;
-
- reg = 0;
- for (banknum = 0; banknum < count; banknum++) {
- bank = &banks[banknum];
- bank->reg = reg;
- debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
- for (muxnum = 0; muxnum < 4; muxnum++) {
- struct rockchip_iomux *mux = &bank->iomux[muxnum];
-
- mux->offset = reg;
- reg += 1;
- }
- }
-
- return 0;
-}
-#endif
-
-static int rk3188_pinctrl_probe(struct udevice *dev)
-{
- struct rk3188_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
- debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
-#ifndef CONFIG_SPL_BUILD
- ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks,
- ARRAY_SIZE(rk3188_pin_banks));
-#endif
-
- return ret;
-}
-
-static const struct udevice_id rk3188_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3188-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3188) = {
- .name = "rockchip_rk3188_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3188_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv),
- .ops = &rk3188_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- .bind = dm_scan_fdt_dev,
-#endif
- .probe = rk3188_pinctrl_probe,
-};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
deleted file mode 100644
index 354fea2..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c
+++ /dev/null
@@ -1,895 +0,0 @@
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk322x.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* GRF_GPIO0A_IOMUX */
-enum {
- GPIO0A7_SHIFT = 14,
- GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
- GPIO0A7_GPIO = 0,
- GPIO0A7_I2C3_SDA,
- GPIO0A7_HDMI_DDCSDA,
-
- GPIO0A6_SHIFT = 12,
- GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
- GPIO0A6_GPIO = 0,
- GPIO0A6_I2C3_SCL,
- GPIO0A6_HDMI_DDCSCL,
-
- GPIO0A3_SHIFT = 6,
- GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
- GPIO0A3_GPIO = 0,
- GPIO0A3_I2C1_SDA,
- GPIO0A3_SDIO_CMD,
-
- GPIO0A2_SHIFT = 4,
- GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
- GPIO0A2_GPIO = 0,
- GPIO0A2_I2C1_SCL,
-
- GPIO0A1_SHIFT = 2,
- GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
- GPIO0A1_GPIO = 0,
- GPIO0A1_I2C0_SDA,
-
- GPIO0A0_SHIFT = 0,
- GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
- GPIO0A0_GPIO = 0,
- GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
- GPIO0B7_SHIFT = 14,
- GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
- GPIO0B7_GPIO = 0,
- GPIO0B7_HDMI_HDP,
-
- GPIO0B6_SHIFT = 12,
- GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
- GPIO0B6_GPIO = 0,
- GPIO0B6_I2S_SDI,
- GPIO0B6_SPI_CSN0,
-
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
- GPIO0B5_GPIO = 0,
- GPIO0B5_I2S_SDO,
- GPIO0B5_SPI_RXD,
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
- GPIO0B3_GPIO = 0,
- GPIO0B3_I2S1_LRCKRX,
- GPIO0B3_SPI_TXD,
-
- GPIO0B1_SHIFT = 2,
- GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
- GPIO0B1_GPIO = 0,
- GPIO0B1_I2S_SCLK,
- GPIO0B1_SPI_CLK,
-
- GPIO0B0_SHIFT = 0,
- GPIO0B0_MASK = 3,
- GPIO0B0_GPIO = 0,
- GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
- GPIO0C4_GPIO = 0,
- GPIO0C4_HDMI_CECSDA,
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
- GPIO0C1_GPIO = 0,
- GPIO0C1_UART0_RSTN,
- GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SDIO_PWREN,
- GPIO0D6_PWM11,
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
- GPIO0D4_GPIO = 0,
- GPIO0D4_PWM2,
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
- GPIO0D3_GPIO = 0,
- GPIO0D3_PWM1,
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
- GPIO0D2_GPIO = 0,
- GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
- GPIO1A7_SHIFT = 14,
- GPIO1A7_MASK = 1,
- GPIO1A7_GPIO = 0,
- GPIO1A7_SDMMC_WRPRT,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_SDMMC_CMD,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO = 0,
- GPIO1B6_SDMMC_PWREN,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO = 0,
- GPIO1B4_SPI_CSN1,
- GPIO1B4_PWM12,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_UART1_RSTN,
- GPIO1B3_PWM13,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_UART1_SIN,
- GPIO1B2_UART21_SIN,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_UART1_SOUT,
- GPIO1B1_UART21_SOUT,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO = 0,
- GPIO1C7_NAND_CS3,
- GPIO1C7_EMMC_RSTNOUT,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO = 0,
- GPIO1C6_NAND_CS2,
- GPIO1C6_EMMC_CMD,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_SDMMC_D3,
- GPIO1C5_JTAG_TMS,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_SDMMC_D2,
- GPIO1C4_JTAG_TCK,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_SDMMC_D1,
- GPIO1C3_UART2_SIN,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO = 0,
- GPIO1C2_SDMMC_D0,
- GPIO1C2_UART2_SOUT,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_SDMMC_DETN,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
- GPIO1C0_GPIO = 0,
- GPIO1C0_SDMMC_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_NAND_D7,
- GPIO1D7_EMMC_D7,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_NAND_D6,
- GPIO1D6_EMMC_D6,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_NAND_D5,
- GPIO1D5_EMMC_D5,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_NAND_D4,
- GPIO1D4_EMMC_D4,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_NAND_D3,
- GPIO1D3_EMMC_D3,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_NAND_D2,
- GPIO1D2_EMMC_D2,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_NAND_D1,
- GPIO1D1_EMMC_D1,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
- GPIO1D0_GPIO = 0,
- GPIO1D0_NAND_D0,
- GPIO1D0_EMMC_D0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_NAND_DQS,
- GPIO2A7_EMMC_CLKOUT,
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
- GPIO2A5_GPIO = 0,
- GPIO2A5_NAND_WP,
- GPIO2A5_EMMC_PWREN,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_NAND_RDY,
- GPIO2A4_EMMC_CMD,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_NAND_RDN,
- GPIO2A4_SPI1_CSN1,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_NAND_WRN,
- GPIO2A4_SPI1_CSN0,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_NAND_CLE,
- GPIO2A1_SPI1_TXD,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_NAND_ALE,
- GPIO2A0_SPI1_RXD,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_GMAC_RXER,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_GMAC_CLK,
- GPIO2B6_MAC_LINK,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_GMAC_TXEN,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_GMAC_MDIO,
-
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
- GPIO2B3_GPIO = 0,
- GPIO2B3_GMAC_RXCLK,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_GMAC_CRS,
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
- GPIO2B1_GPIO = 0,
- GPIO2B1_GMAC_TXCLK,
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
- GPIO2B0_GPIO = 0,
- GPIO2B0_GMAC_RXDV,
- GPIO2B0_MAC_SPEED_IOUT,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
- GPIO2C7_SHIFT = 14,
- GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
- GPIO2C7_GPIO = 0,
- GPIO2C7_GMAC_TXD3,
-
- GPIO2C6_SHIFT = 12,
- GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
- GPIO2C6_GPIO = 0,
- GPIO2C6_GMAC_TXD2,
-
- GPIO2C5_SHIFT = 10,
- GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
- GPIO2C5_GPIO = 0,
- GPIO2C5_I2C2_SCL,
- GPIO2C5_GMAC_RXD2,
-
- GPIO2C4_SHIFT = 8,
- GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
- GPIO2C4_GPIO = 0,
- GPIO2C4_I2C2_SDA,
- GPIO2C4_GMAC_RXD3,
-
- GPIO2C3_SHIFT = 6,
- GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
- GPIO2C3_GPIO = 0,
- GPIO2C3_GMAC_TXD0,
-
- GPIO2C2_SHIFT = 4,
- GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
- GPIO2C2_GPIO = 0,
- GPIO2C2_GMAC_TXD1,
-
- GPIO2C1_SHIFT = 2,
- GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
- GPIO2C1_GPIO = 0,
- GPIO2C1_GMAC_RXD0,
-
- GPIO2C0_SHIFT = 0,
- GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
- GPIO2C0_GPIO = 0,
- GPIO2C0_GMAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_GMAC_MDC,
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3,
- GPIO2D0_GPIO = 0,
- GPIO2D0_GMAC_COL,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
- GPIO3C6_GPIO = 0,
- GPIO3C6_DRV_VBUS1,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
- GPIO3C5_GPIO = 0,
- GPIO3C5_PWM10,
-
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
- GPIO3C1_GPIO = 0,
- GPIO3C1_DRV_VBUS,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
- GPIO3D2_SHIFT = 4,
- GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
- GPIO3D2_GPIO = 0,
- GPIO3D2_PWM3,
-};
-
-/* GRF_CON_IOMUX */
-enum {
- CON_IOMUX_GMACSEL_SHIFT = 15,
- CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT,
- CON_IOMUX_GMACSEL_1 = 1,
- CON_IOMUX_UART1SEL_SHIFT = 11,
- CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
- CON_IOMUX_UART2SEL_SHIFT = 8,
- CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
- CON_IOMUX_UART2SEL_2 = 0,
- CON_IOMUX_UART2SEL_21,
- CON_IOMUX_EMMCSEL_SHIFT = 7,
- CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
- CON_IOMUX_PWM3SEL_SHIFT = 3,
- CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
- CON_IOMUX_PWM2SEL_SHIFT = 2,
- CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
- CON_IOMUX_PWM1SEL_SHIFT = 1,
- CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
- CON_IOMUX_PWM0SEL_SHIFT = 0,
- CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
-};
-
-/* GRF_GPIO2B_E */
-enum {
- GRF_GPIO2B0_E_SHIFT = 0,
- GRF_GPIO2B0_E_MASK = 3 << GRF_GPIO2B0_E_SHIFT,
- GRF_GPIO2B1_E_SHIFT = 2,
- GRF_GPIO2B1_E_MASK = 3 << GRF_GPIO2B1_E_SHIFT,
- GRF_GPIO2B3_E_SHIFT = 6,
- GRF_GPIO2B3_E_MASK = 3 << GRF_GPIO2B3_E_SHIFT,
- GRF_GPIO2B4_E_SHIFT = 8,
- GRF_GPIO2B4_E_MASK = 3 << GRF_GPIO2B4_E_SHIFT,
- GRF_GPIO2B5_E_SHIFT = 10,
- GRF_GPIO2B5_E_MASK = 3 << GRF_GPIO2B5_E_SHIFT,
- GRF_GPIO2B6_E_SHIFT = 12,
- GRF_GPIO2B6_E_MASK = 3 << GRF_GPIO2B6_E_SHIFT,
-};
-
-/* GRF_GPIO2C_E */
-enum {
- GRF_GPIO2C0_E_SHIFT = 0,
- GRF_GPIO2C0_E_MASK = 3 << GRF_GPIO2C0_E_SHIFT,
- GRF_GPIO2C1_E_SHIFT = 2,
- GRF_GPIO2C1_E_MASK = 3 << GRF_GPIO2C1_E_SHIFT,
- GRF_GPIO2C2_E_SHIFT = 4,
- GRF_GPIO2C2_E_MASK = 3 << GRF_GPIO2C2_E_SHIFT,
- GRF_GPIO2C3_E_SHIFT = 6,
- GRF_GPIO2C3_E_MASK = 3 << GRF_GPIO2C3_E_SHIFT,
- GRF_GPIO2C4_E_SHIFT = 8,
- GRF_GPIO2C4_E_MASK = 3 << GRF_GPIO2C4_E_SHIFT,
- GRF_GPIO2C5_E_SHIFT = 10,
- GRF_GPIO2C5_E_MASK = 3 << GRF_GPIO2C5_E_SHIFT,
- GRF_GPIO2C6_E_SHIFT = 12,
- GRF_GPIO2C6_E_MASK = 3 << GRF_GPIO2C6_E_SHIFT,
- GRF_GPIO2C7_E_SHIFT = 14,
- GRF_GPIO2C7_E_MASK = 3 << GRF_GPIO2C7_E_SHIFT,
-};
-
-/* GRF_GPIO2D_E */
-enum {
- GRF_GPIO2D1_E_SHIFT = 2,
- GRF_GPIO2D1_E_MASK = 3 << GRF_GPIO2D1_E_SHIFT,
-};
-
-/* GPIO Bias drive strength settings */
-enum GPIO_BIAS {
- GPIO_BIAS_2MA = 0,
- GPIO_BIAS_4MA,
- GPIO_BIAS_8MA,
- GPIO_BIAS_12MA,
-};
-
-struct rk322x_pinctrl_priv {
- struct rk322x_grf *grf;
-};
-
-static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
-{
- u32 mux_con = readl(&grf->con_iomux);
-
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- if (mux_con & CON_IOMUX_PWM0SEL_MASK)
- rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
- GPIO3C5_PWM10 << GPIO3C5_SHIFT);
- else
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
- GPIO0D2_PWM0 << GPIO0D2_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- if (mux_con & CON_IOMUX_PWM1SEL_MASK)
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
- GPIO0D6_PWM11 << GPIO0D6_SHIFT);
- else
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
- GPIO0D3_PWM1 << GPIO0D3_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- if (mux_con & CON_IOMUX_PWM2SEL_MASK)
- rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
- GPIO1B4_PWM12 << GPIO1B4_SHIFT);
- else
- rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
- GPIO0D4_PWM2 << GPIO0D4_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- if (mux_con & CON_IOMUX_PWM3SEL_MASK)
- rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
- GPIO1B3_PWM13 << GPIO1B3_SHIFT);
- else
- rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
- GPIO3D2_PWM3 << GPIO3D2_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A1_MASK | GPIO0A0_MASK,
- GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
- GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
-
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A3_MASK | GPIO0A2_MASK,
- GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
- GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C5_MASK | GPIO2C4_MASK,
- GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
- GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A7_MASK | GPIO0A6_MASK,
- GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
- GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
-
- break;
- }
-}
-
-static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
-{
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
- GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
- GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
- break;
- }
- rk_clrsetreg(&grf->gpio0b_iomux,
- GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
- GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
- GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
- GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
-}
-
-static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
-{
- u32 mux_con = readl(&grf->con_iomux);
-
- switch (uart_id) {
- case PERIPH_ID_UART1:
- if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK | GPIO1B2_MASK,
- GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
- GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
- break;
- case PERIPH_ID_UART2:
- if (mux_con & CON_IOMUX_UART2SEL_MASK)
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B1_MASK | GPIO1B2_MASK,
- GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
- GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
- else
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C3_MASK | GPIO1C2_MASK,
- GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
- GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
- break;
- }
-}
-
-static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
- GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
- GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
- GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
- GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
- GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
- GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
- GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
- GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A5_MASK | GPIO2A7_MASK,
- GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
- GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C6_MASK | GPIO1C7_MASK,
- GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
- GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B6_MASK | GPIO1B7_MASK,
- GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
- GPIO1B7_SDMMC_CMD << GPIO1B7_SHIFT);
- rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
- GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
- GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
- GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
- GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
- GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
- GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
- break;
- }
-}
-
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id)
-{
- switch (gmac_id) {
- case PERIPH_ID_GMAC:
- /* set rgmii pins mux */
- rk_clrsetreg(&grf->gpio2b_iomux,
- GPIO2B0_MASK |
- GPIO2B1_MASK |
- GPIO2B3_MASK |
- GPIO2B4_MASK |
- GPIO2B5_MASK |
- GPIO2B6_MASK,
- GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT |
- GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT |
- GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT |
- GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT |
- GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT |
- GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT);
-
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C0_MASK |
- GPIO2C1_MASK |
- GPIO2C2_MASK |
- GPIO2C3_MASK |
- GPIO2C4_MASK |
- GPIO2C5_MASK |
- GPIO2C6_MASK |
- GPIO2C7_MASK,
- GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT |
- GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT |
- GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT |
- GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT |
- GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT |
- GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT |
- GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT |
- GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT);
-
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D1_MASK,
- GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT);
-
- /*
- * set rgmii tx pins to 12ma drive-strength,
- * clean others with 2ma.
- */
- rk_clrsetreg(&grf->gpio2_e[1],
- GRF_GPIO2B0_E_MASK |
- GRF_GPIO2B1_E_MASK |
- GRF_GPIO2B3_E_MASK |
- GRF_GPIO2B4_E_MASK |
- GRF_GPIO2B5_E_MASK |
- GRF_GPIO2B6_E_MASK,
- GPIO_BIAS_2MA << GRF_GPIO2B0_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2B1_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2B3_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2B4_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2B5_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2B6_E_SHIFT);
-
- rk_clrsetreg(&grf->gpio2_e[2],
- GRF_GPIO2C0_E_MASK |
- GRF_GPIO2C1_E_MASK |
- GRF_GPIO2C2_E_MASK |
- GRF_GPIO2C3_E_MASK |
- GRF_GPIO2C4_E_MASK |
- GRF_GPIO2C5_E_MASK |
- GRF_GPIO2C6_E_MASK |
- GRF_GPIO2C7_E_MASK,
- GPIO_BIAS_2MA << GRF_GPIO2C0_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2C1_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2C2_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2C3_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2C4_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO2C5_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2C6_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO2C7_E_SHIFT);
-
- rk_clrsetreg(&grf->gpio2_e[3],
- GRF_GPIO2D1_E_MASK,
- GPIO_BIAS_2MA << GRF_GPIO2D1_E_SHIFT);
- break;
- default:
- debug("gmac id = %d iomux error!\n", gmac_id);
- break;
- }
-}
-#endif
-
-static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- pinctrl_rk322x_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- pinctrl_rk322x_i2c_config(priv->grf, func);
- break;
- case PERIPH_ID_SPI0:
- pinctrl_rk322x_spi_config(priv->grf, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- pinctrl_rk322x_uart_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk322x_sdmmc_config(priv->grf, func);
- break;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
- pinctrl_rk322x_gmac_config(priv->grf, func);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
- "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 12:
- return PERIPH_ID_SDCARD;
- case 14:
- return PERIPH_ID_EMMC;
- case 36:
- return PERIPH_ID_I2C0;
- case 37:
- return PERIPH_ID_I2C1;
- case 38:
- return PERIPH_ID_I2C2;
- case 49:
- return PERIPH_ID_SPI0;
- case 50:
- return PERIPH_ID_PWM0;
- case 55:
- return PERIPH_ID_UART0;
- case 56:
- return PERIPH_ID_UART1;
- case 57:
- return PERIPH_ID_UART2;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 24:
- return PERIPH_ID_GMAC;
-#endif
- }
- return -ENOENT;
-}
-
-static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk322x_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk322x_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk322x_pinctrl_ops = {
- .set_state_simple = rk322x_pinctrl_set_state_simple,
- .request = rk322x_pinctrl_request,
- .get_periph_id = rk322x_pinctrl_get_periph_id,
-};
-
-static int rk322x_pinctrl_probe(struct udevice *dev)
-{
- struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- debug("%s: grf=%p\n", __func__, priv->grf);
- return 0;
-}
-
-static const struct udevice_id rk322x_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3228-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3228) = {
- .name = "pinctrl_rk3228",
- .id = UCLASS_PINCTRL,
- .of_match = rk322x_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
- .ops = &rk322x_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk322x_pinctrl_probe,
-};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
deleted file mode 100644
index a21b640..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ /dev/null
@@ -1,870 +0,0 @@
-/*
- * Pinctrl driver for Rockchip SoCs
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rk3288_pinctrl_priv {
- struct rk3288_grf *grf;
- struct rk3288_pmu *pmu;
- int num_banks;
-};
-
-/**
- * Encode variants of iomux registers into a type variable
- */
-#define IOMUX_GPIO_ONLY BIT(0)
-#define IOMUX_WIDTH_4BIT BIT(1)
-#define IOMUX_SOURCE_PMU BIT(2)
-#define IOMUX_UNROUTED BIT(3)
-
-/**
- * @type: iomux variant using IOMUX_* constants
- * @offset: if initialized to -1 it will be autocalculated, by specifying
- * an initial offset value the relevant source offset can be reset
- * to a new value for autocalculating the following iomux registers.
- */
-struct rockchip_iomux {
- u8 type;
- s16 offset;
-};
-
-/**
- * @reg: register offset of the gpio bank
- * @nr_pins: number of pins in this bank
- * @bank_num: number of the bank, to account for holes
- * @name: name of the bank
- * @iomux: array describing the 4 iomux sources of the bank
- */
-struct rockchip_pin_bank {
- u16 reg;
- u8 nr_pins;
- u8 bank_num;
- char *name;
- struct rockchip_iomux iomux[4];
-};
-
-#define PIN_BANK(id, pins, label) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .offset = -1 }, \
- { .offset = -1 }, \
- { .offset = -1 }, \
- { .offset = -1 }, \
- }, \
- }
-
-#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
- { \
- .bank_num = id, \
- .nr_pins = pins, \
- .name = label, \
- .iomux = { \
- { .type = iom0, .offset = -1 }, \
- { .type = iom1, .offset = -1 }, \
- { .type = iom2, .offset = -1 }, \
- { .type = iom3, .offset = -1 }, \
- }, \
- }
-
-#ifndef CONFIG_SPL_BUILD
-static struct rockchip_pin_bank rk3288_pin_banks[] = {
- PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
- IOMUX_SOURCE_PMU,
- IOMUX_SOURCE_PMU,
- IOMUX_UNROUTED
- ),
- PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
- IOMUX_UNROUTED,
- IOMUX_UNROUTED,
- 0
- ),
- PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
- PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
- PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
- IOMUX_WIDTH_4BIT,
- 0,
- 0
- ),
- PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
- 0,
- 0,
- IOMUX_UNROUTED
- ),
- PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
- PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
- 0,
- IOMUX_WIDTH_4BIT,
- IOMUX_UNROUTED
- ),
- PIN_BANK(8, 16, "gpio8"),
-};
-#endif
-
-static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
- GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
- GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
- GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
- GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
- struct rk3288_pmu *pmu, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_B],
- GPIO0_B7_MASK << GPIO0_B7_SHIFT,
- GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
- clrsetbits_le32(&pmu->gpio0_iomux[PMU_GPIO0_C],
- GPIO0_C0_MASK << GPIO0_C0_SHIFT,
- GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
- break;
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio8a_iomux,
- GPIO8A4_MASK << GPIO8A4_SHIFT |
- GPIO8A5_MASK << GPIO8A5_SHIFT,
- GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
- GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio6b_iomux,
- GPIO6B1_MASK << GPIO6B1_SHIFT |
- GPIO6B2_MASK << GPIO6B2_SHIFT,
- GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
- GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio2c_iomux,
- GPIO2C1_MASK << GPIO2C1_SHIFT |
- GPIO2C0_MASK << GPIO2C0_SHIFT,
- GPIO2C1_I2C3CAM_SDA << GPIO2C1_SHIFT |
- GPIO2C0_I2C3CAM_SCL << GPIO2C0_SHIFT);
- break;
- case PERIPH_ID_I2C4:
- rk_clrsetreg(&grf->gpio7cl_iomux,
- GPIO7C1_MASK << GPIO7C1_SHIFT |
- GPIO7C2_MASK << GPIO7C2_SHIFT,
- GPIO7C1_I2C4TP_SDA << GPIO7C1_SHIFT |
- GPIO7C2_I2C4TP_SCL << GPIO7C2_SHIFT);
- break;
- case PERIPH_ID_I2C5:
- rk_clrsetreg(&grf->gpio7cl_iomux,
- GPIO7C3_MASK << GPIO7C3_SHIFT,
- GPIO7C3_I2C5HDMI_SDA << GPIO7C3_SHIFT);
- rk_clrsetreg(&grf->gpio7ch_iomux,
- GPIO7C4_MASK << GPIO7C4_SHIFT,
- GPIO7C4_I2C5HDMI_SCL << GPIO7C4_SHIFT);
- break;
-#endif
- default:
- debug("i2c id = %d iomux error!\n", i2c_id);
- break;
- }
-}
-
-#ifndef CONFIG_SPL_BUILD
-static void pinctrl_rk3288_lcdc_config(struct rk3288_grf *grf, int lcd_id)
-{
- switch (lcd_id) {
- case PERIPH_ID_LCDC0:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D3_MASK << GPIO1D0_SHIFT |
- GPIO1D2_MASK << GPIO1D2_SHIFT |
- GPIO1D1_MASK << GPIO1D1_SHIFT |
- GPIO1D0_MASK << GPIO1D0_SHIFT,
- GPIO1D3_LCDC0_DCLK << GPIO1D3_SHIFT |
- GPIO1D2_LCDC0_DEN << GPIO1D2_SHIFT |
- GPIO1D1_LCDC0_VSYNC << GPIO1D1_SHIFT |
- GPIO1D0_LCDC0_HSYNC << GPIO1D0_SHIFT);
- break;
- default:
- debug("lcdc id = %d iomux error!\n", lcd_id);
- break;
- }
-}
-#endif
-
-static int pinctrl_rk3288_spi_config(struct rk3288_grf *grf,
- enum periph_id spi_id, int cs)
-{
- switch (spi_id) {
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_SPI0:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio5b_iomux,
- GPIO5B5_MASK << GPIO5B5_SHIFT,
- GPIO5B5_SPI0_CSN0 << GPIO5B5_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio5c_iomux,
- GPIO5C0_MASK << GPIO5C0_SHIFT,
- GPIO5C0_SPI0_CSN1 << GPIO5C0_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio5b_iomux,
- GPIO5B7_MASK << GPIO5B7_SHIFT |
- GPIO5B6_MASK << GPIO5B6_SHIFT |
- GPIO5B4_MASK << GPIO5B4_SHIFT,
- GPIO5B7_SPI0_RXD << GPIO5B7_SHIFT |
- GPIO5B6_SPI0_TXD << GPIO5B6_SHIFT |
- GPIO5B4_SPI0_CLK << GPIO5B4_SHIFT);
- break;
- case PERIPH_ID_SPI1:
- if (cs != 0)
- goto err;
- rk_clrsetreg(&grf->gpio7b_iomux,
- GPIO7B6_MASK << GPIO7B6_SHIFT |
- GPIO7B7_MASK << GPIO7B7_SHIFT |
- GPIO7B5_MASK << GPIO7B5_SHIFT |
- GPIO7B4_MASK << GPIO7B4_SHIFT,
- GPIO7B6_SPI1_RXD << GPIO7B6_SHIFT |
- GPIO7B7_SPI1_TXD << GPIO7B7_SHIFT |
- GPIO7B5_SPI1_CSN0 << GPIO7B5_SHIFT |
- GPIO7B4_SPI1_CLK << GPIO7B4_SHIFT);
- break;
-#endif
- case PERIPH_ID_SPI2:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio8a_iomux,
- GPIO8A7_MASK << GPIO8A7_SHIFT,
- GPIO8A7_SPI2_CSN0 << GPIO8A7_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio8a_iomux,
- GPIO8A3_MASK << GPIO8A3_SHIFT,
- GPIO8A3_SPI2_CSN1 << GPIO8A3_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio8b_iomux,
- GPIO8B1_MASK << GPIO8B1_SHIFT |
- GPIO8B0_MASK << GPIO8B0_SHIFT,
- GPIO8B1_SPI2_TXD << GPIO8B1_SHIFT |
- GPIO8B0_SPI2_RXD << GPIO8B0_SHIFT);
- rk_clrsetreg(&grf->gpio8a_iomux,
- GPIO8A6_MASK << GPIO8A6_SHIFT,
- GPIO8A6_SPI2_CLK << GPIO8A6_SHIFT);
- break;
- default:
- goto err;
- }
-
- return 0;
-err:
- debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
- return -ENOENT;
-}
-
-static void pinctrl_rk3288_uart_config(struct rk3288_grf *grf, int uart_id)
-{
- switch (uart_id) {
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_UART_BT:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GPIO4C3_MASK << GPIO4C3_SHIFT |
- GPIO4C2_MASK << GPIO4C2_SHIFT |
- GPIO4C1_MASK << GPIO4C1_SHIFT |
- GPIO4C0_MASK << GPIO4C0_SHIFT,
- GPIO4C3_UART0BT_RTSN << GPIO4C3_SHIFT |
- GPIO4C2_UART0BT_CTSN << GPIO4C2_SHIFT |
- GPIO4C1_UART0BT_SOUT << GPIO4C1_SHIFT |
- GPIO4C0_UART0BT_SIN << GPIO4C0_SHIFT);
- break;
- case PERIPH_ID_UART_BB:
- rk_clrsetreg(&grf->gpio5b_iomux,
- GPIO5B3_MASK << GPIO5B3_SHIFT |
- GPIO5B2_MASK << GPIO5B2_SHIFT |
- GPIO5B1_MASK << GPIO5B1_SHIFT |
- GPIO5B0_MASK << GPIO5B0_SHIFT,
- GPIO5B3_UART1BB_RTSN << GPIO5B3_SHIFT |
- GPIO5B2_UART1BB_CTSN << GPIO5B2_SHIFT |
- GPIO5B1_UART1BB_SOUT << GPIO5B1_SHIFT |
- GPIO5B0_UART1BB_SIN << GPIO5B0_SHIFT);
- break;
-#endif
- case PERIPH_ID_UART_DBG:
- rk_clrsetreg(&grf->gpio7ch_iomux,
- GPIO7C7_MASK << GPIO7C7_SHIFT |
- GPIO7C6_MASK << GPIO7C6_SHIFT,
- GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
- GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
- break;
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_UART_GPS:
- rk_clrsetreg(&grf->gpio7b_iomux,
- GPIO7B2_MASK << GPIO7B2_SHIFT |
- GPIO7B1_MASK << GPIO7B1_SHIFT |
- GPIO7B0_MASK << GPIO7B0_SHIFT,
- GPIO7B2_UART3GPS_RTSN << GPIO7B2_SHIFT |
- GPIO7B1_UART3GPS_CTSN << GPIO7B1_SHIFT |
- GPIO7B0_UART3GPS_SOUT << GPIO7B0_SHIFT);
- rk_clrsetreg(&grf->gpio7a_iomux,
- GPIO7A7_MASK << GPIO7A7_SHIFT,
- GPIO7A7_UART3GPS_SIN << GPIO7A7_SHIFT);
- break;
- case PERIPH_ID_UART_EXP:
- rk_clrsetreg(&grf->gpio5b_iomux,
- GPIO5B5_MASK << GPIO5B5_SHIFT |
- GPIO5B4_MASK << GPIO5B4_SHIFT |
- GPIO5B6_MASK << GPIO5B6_SHIFT |
- GPIO5B7_MASK << GPIO5B7_SHIFT,
- GPIO5B5_UART4EXP_RTSN << GPIO5B5_SHIFT |
- GPIO5B4_UART4EXP_CTSN << GPIO5B4_SHIFT |
- GPIO5B6_UART4EXP_SOUT << GPIO5B6_SHIFT |
- GPIO5B7_UART4EXP_SIN << GPIO5B7_SHIFT);
- break;
-#endif
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio3a_iomux, 0xffff,
- GPIO3A7_EMMC_DATA7 << GPIO3A7_SHIFT |
- GPIO3A6_EMMC_DATA6 << GPIO3A6_SHIFT |
- GPIO3A5_EMMC_DATA5 << GPIO3A5_SHIFT |
- GPIO3A4_EMMC_DATA4 << GPIO3A4_SHIFT |
- GPIO3A3_EMMC_DATA3 << GPIO3A3_SHIFT |
- GPIO3A2_EMMC_DATA2 << GPIO3A2_SHIFT |
- GPIO3A1_EMMC_DATA1 << GPIO3A1_SHIFT |
- GPIO3A0_EMMC_DATA0 << GPIO3A0_SHIFT);
- rk_clrsetreg(&grf->gpio3b_iomux, GPIO3B1_MASK << GPIO3B1_SHIFT,
- GPIO3B1_EMMC_PWREN << GPIO3B1_SHIFT);
- rk_clrsetreg(&grf->gpio3c_iomux,
- GPIO3C0_MASK << GPIO3C0_SHIFT,
- GPIO3C0_EMMC_CMD << GPIO3C0_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio6c_iomux, 0xffff,
- GPIO6C6_SDMMC0_DECTN << GPIO6C6_SHIFT |
- GPIO6C5_SDMMC0_CMD << GPIO6C5_SHIFT |
- GPIO6C4_SDMMC0_CLKOUT << GPIO6C4_SHIFT |
- GPIO6C3_SDMMC0_DATA3 << GPIO6C3_SHIFT |
- GPIO6C2_SDMMC0_DATA2 << GPIO6C2_SHIFT |
- GPIO6C1_SDMMC0_DATA1 << GPIO6C1_SHIFT |
- GPIO6C0_SDMMC0_DATA0 << GPIO6C0_SHIFT);
-
- /* use sdmmc0 io, disable JTAG function */
- rk_clrsetreg(&grf->soc_con0, 1 << GRF_FORCE_JTAG_SHIFT, 0);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-static void pinctrl_rk3288_gmac_config(struct rk3288_grf *grf, int gmac_id)
-{
- switch (gmac_id) {
- case PERIPH_ID_GMAC:
- rk_clrsetreg(&grf->gpio3dl_iomux,
- GPIO3D3_MASK << GPIO3D3_SHIFT |
- GPIO3D2_MASK << GPIO3D2_SHIFT |
- GPIO3D2_MASK << GPIO3D1_SHIFT |
- GPIO3D0_MASK << GPIO3D0_SHIFT,
- GPIO3D3_MAC_RXD3 << GPIO3D3_SHIFT |
- GPIO3D2_MAC_RXD2 << GPIO3D2_SHIFT |
- GPIO3D1_MAC_TXD3 << GPIO3D1_SHIFT |
- GPIO3D0_MAC_TXD2 << GPIO3D0_SHIFT);
-
- rk_clrsetreg(&grf->gpio3dh_iomux,
- GPIO3D7_MASK << GPIO3D7_SHIFT |
- GPIO3D6_MASK << GPIO3D6_SHIFT |
- GPIO3D5_MASK << GPIO3D5_SHIFT |
- GPIO3D4_MASK << GPIO3D4_SHIFT,
- GPIO3D7_MAC_RXD1 << GPIO3D7_SHIFT |
- GPIO3D6_MAC_RXD0 << GPIO3D6_SHIFT |
- GPIO3D5_MAC_TXD1 << GPIO3D5_SHIFT |
- GPIO3D4_MAC_TXD0 << GPIO3D4_SHIFT);
-
- /* switch the Tx pins to 12ma drive-strength */
- rk_clrsetreg(&grf->gpio1_e[2][3],
- GPIO_BIAS_MASK |
- (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1)) |
- (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4)) |
- (GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(5)),
- (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(0)) |
- (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1)) |
- (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4)) |
- (GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(5)));
-
- /* Set normal pull for all GPIO3D pins */
- rk_clrsetreg(&grf->gpio1_p[2][3],
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
-
- rk_clrsetreg(&grf->gpio4al_iomux,
- GPIO4A3_MASK << GPIO4A3_SHIFT |
- GPIO4A1_MASK << GPIO4A1_SHIFT |
- GPIO4A0_MASK << GPIO4A0_SHIFT,
- GPIO4A3_MAC_CLK << GPIO4A3_SHIFT |
- GPIO4A1_MAC_TXDV << GPIO4A1_SHIFT |
- GPIO4A0_MAC_MDC << GPIO4A0_SHIFT);
-
- rk_clrsetreg(&grf->gpio4ah_iomux,
- GPIO4A6_MASK << GPIO4A6_SHIFT |
- GPIO4A5_MASK << GPIO4A5_SHIFT |
- GPIO4A4_MASK << GPIO4A4_SHIFT,
- GPIO4A6_MAC_RXCLK << GPIO4A6_SHIFT |
- GPIO4A5_MAC_MDIO << GPIO4A5_SHIFT |
- GPIO4A4_MAC_TXEN << GPIO4A4_SHIFT);
-
- /* switch GPIO4A4 to 12ma drive-strength */
- rk_clrsetreg(&grf->gpio1_e[3][0],
- GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(4),
- GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(4));
-
- /* Set normal pull for all GPIO4A pins */
- rk_clrsetreg(&grf->gpio1_p[3][0],
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(0)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(2)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(3)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(4)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(7)),
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(0)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(2)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(3)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(4)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(5)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(6)) |
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(7)));
-
- rk_clrsetreg(&grf->gpio4bl_iomux,
- GPIO4B1_MASK << GPIO4B1_SHIFT,
- GPIO4B1_MAC_TXCLK << GPIO4B1_SHIFT);
-
- /* switch GPIO4B1 to 12ma drive-strength */
- rk_clrsetreg(&grf->gpio1_e[3][1],
- GPIO_BIAS_MASK << GPIO_BIAS_SHIFT(1),
- GPIO_BIAS_12MA << GPIO_BIAS_SHIFT(1));
-
- /* Set pull normal for GPIO4B1 */
- rk_clrsetreg(&grf->gpio1_p[3][1],
- (GPIO_PULL_MASK << GPIO_PULL_SHIFT(1)),
- (GPIO_PULL_NORMAL << GPIO_PULL_SHIFT(1)));
-
- break;
- default:
- printf("gmac id = %d iomux error!\n", gmac_id);
- break;
- }
-}
-
-#ifndef CONFIG_SPL_BUILD
-static void pinctrl_rk3288_hdmi_config(struct rk3288_grf *grf, int hdmi_id)
-{
- switch (hdmi_id) {
- case PERIPH_ID_HDMI:
- rk_clrsetreg(&grf->gpio7cl_iomux, GPIO7C3_MASK << GPIO7C3_SHIFT,
- GPIO7C3_EDPHDMII2C_SDA << GPIO7C3_SHIFT);
- rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C4_MASK << GPIO7C4_SHIFT,
- GPIO7C4_EDPHDMII2C_SCL << GPIO7C4_SHIFT);
- break;
- default:
- debug("hdmi id = %d iomux error!\n", hdmi_id);
- break;
- }
-}
-#endif
-
-static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- pinctrl_rk3288_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- pinctrl_rk3288_i2c_config(priv->grf, priv->pmu, func);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- pinctrl_rk3288_spi_config(priv->grf, func, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3288_uart_config(priv->grf, func);
- break;
-#ifndef CONFIG_SPL_BUILD
- case PERIPH_ID_LCDC0:
- case PERIPH_ID_LCDC1:
- pinctrl_rk3288_lcdc_config(priv->grf, func);
- break;
- case PERIPH_ID_HDMI:
- pinctrl_rk3288_hdmi_config(priv->grf, func);
- break;
-#endif
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3288_sdmmc_config(priv->grf, func);
- break;
- case PERIPH_ID_GMAC:
- pinctrl_rk3288_gmac_config(priv->grf, func);
- break;
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3288_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 27:
- return PERIPH_ID_GMAC;
- case 44:
- return PERIPH_ID_SPI0;
- case 45:
- return PERIPH_ID_SPI1;
- case 46:
- return PERIPH_ID_SPI2;
- case 60:
- return PERIPH_ID_I2C0;
- case 62: /* Note strange order */
- return PERIPH_ID_I2C1;
- case 61:
- return PERIPH_ID_I2C2;
- case 63:
- return PERIPH_ID_I2C3;
- case 64:
- return PERIPH_ID_I2C4;
- case 65:
- return PERIPH_ID_I2C5;
- case 103:
- return PERIPH_ID_HDMI;
- }
-#endif
-
- return -ENOENT;
-}
-
-static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3288_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
- return rk3288_pinctrl_request(dev, func, 0);
-}
-
-#ifndef CONFIG_SPL_BUILD
-int rk3288_pinctrl_get_pin_info(struct rk3288_pinctrl_priv *priv,
- int banknum, int ind, u32 **addrp, uint *shiftp,
- uint *maskp)
-{
- struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
- uint muxnum;
- u32 *addr;
-
- for (muxnum = 0; muxnum < 4; muxnum++) {
- struct rockchip_iomux *mux = &bank->iomux[muxnum];
-
- if (ind >= 8) {
- ind -= 8;
- continue;
- }
-
- if (mux->type & IOMUX_SOURCE_PMU)
- addr = priv->pmu->gpio0_iomux;
- else
- addr = (u32 *)priv->grf - 4;
- addr += mux->offset;
- *shiftp = ind & 7;
- if (mux->type & IOMUX_WIDTH_4BIT) {
- *maskp = 0xf;
- *shiftp *= 4;
- if (*shiftp >= 16) {
- *shiftp -= 16;
- addr++;
- }
- } else {
- *maskp = 3;
- *shiftp *= 2;
- }
-
- debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
- *maskp, *shiftp);
- *addrp = addr;
- return 0;
- }
-
- return -EINVAL;
-}
-
-static int rk3288_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
- int index)
-{
- struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
- uint shift;
- uint mask;
- u32 *addr;
- int ret;
-
- ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
- &mask);
- if (ret)
- return ret;
- return (readl(addr) & mask) >> shift;
-}
-
-static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
- int muxval, int flags)
-{
- struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
- uint shift, ind = index;
- uint mask;
- uint value;
- u32 *addr;
- int ret;
-
- debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
- ret = rk3288_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift,
- &mask);
- if (ret)
- return ret;
-
- /*
- * PMU_GPIO0 registers cannot be selectively written so we cannot use
- * rk_clrsetreg() here. However, the upper 16 bits are reserved and
- * are ignored when written, so we can use the same code as for the
- * other GPIO banks providing that we preserve the value of the other
- * bits.
- */
- value = readl(addr);
- value &= ~(mask << shift);
- value |= (mask << (shift + 16)) | (muxval << shift);
- writel(value, addr);
-
- /* Handle pullup/pulldown/drive-strength */
- if (flags) {
- uint val = 0;
-
- if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
- val = 1;
- else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
- val = 2;
- else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
- val = 3;
-
- shift = (index & 7) * 2;
- ind = index >> 3;
- if (banknum == 0)
- addr = &priv->pmu->gpio0pull[ind];
- else if (flags & (1 << PIN_CONFIG_DRIVE_STRENGTH))
- addr = &priv->grf->gpio1_e[banknum - 1][ind];
- else
- addr = &priv->grf->gpio1_p[banknum - 1][ind];
- debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
- shift);
-
- /* As above, rk_clrsetreg() cannot be used here. */
- value = readl(addr);
- value &= ~(mask << shift);
- value |= (3 << (shift + 16)) | (val << shift);
- writel(value, addr);
- }
-
- return 0;
-}
-
-static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
-{
- const void *blob = gd->fdt_blob;
- int pcfg_node, ret, flags, count, i;
- u32 cell[60], *ptr;
-
- debug("%s: %s %s\n", __func__, dev->name, config->name);
- ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
- "rockchip,pins", cell,
- ARRAY_SIZE(cell));
- if (ret < 0) {
- debug("%s: bad array %d\n", __func__, ret);
- return -EINVAL;
- }
- count = ret;
- for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
- pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
- if (pcfg_node < 0)
- return -EINVAL;
- flags = pinctrl_decode_pin_config(blob, pcfg_node);
- if (flags < 0)
- return flags;
-
- if (fdtdec_get_int(blob, pcfg_node, "drive-strength", 0) == 12)
- flags |= 1 << PIN_CONFIG_DRIVE_STRENGTH;
-
- ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
- flags);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-#endif
-
-static struct pinctrl_ops rk3288_pinctrl_ops = {
-#ifndef CONFIG_SPL_BUILD
- .set_state = rk3288_pinctrl_set_state,
- .get_gpio_mux = rk3288_pinctrl_get_gpio_mux,
-#endif
- .set_state_simple = rk3288_pinctrl_set_state_simple,
- .request = rk3288_pinctrl_request,
- .get_periph_id = rk3288_pinctrl_get_periph_id,
-};
-
-#ifndef CONFIG_SPL_BUILD
-static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
- struct rockchip_pin_bank *banks,
- int count)
-{
- struct rockchip_pin_bank *bank;
- uint reg, muxnum, banknum;
-
- reg = 0;
- for (banknum = 0; banknum < count; banknum++) {
- bank = &banks[banknum];
- bank->reg = reg;
- debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
- for (muxnum = 0; muxnum < 4; muxnum++) {
- struct rockchip_iomux *mux = &bank->iomux[muxnum];
-
- if (!(mux->type & IOMUX_UNROUTED))
- mux->offset = reg;
- if (mux->type & IOMUX_WIDTH_4BIT)
- reg += 2;
- else
- reg += 1;
- }
- }
-
- return 0;
-}
-#endif
-
-static int rk3288_pinctrl_probe(struct udevice *dev)
-{
- struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
- debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
-#ifndef CONFIG_SPL_BUILD
- ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
- ARRAY_SIZE(rk3288_pin_banks));
-#endif
-
- return ret;
-}
-
-static const struct udevice_id rk3288_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3288-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3288) = {
- .name = "rockchip_rk3288_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3288_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv),
- .ops = &rk3288_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- .bind = dm_scan_fdt_dev,
-#endif
- .probe = rk3288_pinctrl_probe,
-};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c
deleted file mode 100644
index fa2356a..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c
+++ /dev/null
@@ -1,708 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk3328.h>
-#include <asm/arch/periph.h>
-#include <asm/io.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-enum {
- /* GPIO0A_IOMUX */
- GPIO0A5_SEL_SHIFT = 10,
- GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT,
- GPIO0A5_I2C3_SCL = 2,
-
- GPIO0A6_SEL_SHIFT = 12,
- GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT,
- GPIO0A6_I2C3_SDA = 2,
-
- GPIO0A7_SEL_SHIFT = 14,
- GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT,
- GPIO0A7_EMMC_DATA0 = 2,
-
- /* GPIO0B_IOMUX*/
- GPIO0B0_SEL_SHIFT = 0,
- GPIO0B0_SEL_MASK = 3 << GPIO0B0_SEL_SHIFT,
- GPIO0B0_GAMC_CLKTXM0 = 1,
-
- GPIO0B4_SEL_SHIFT = 8,
- GPIO0B4_SEL_MASK = 3 << GPIO0B4_SEL_SHIFT,
- GPIO0B4_GAMC_TXENM0 = 1,
-
- /* GPIO0C_IOMUX*/
- GPIO0C0_SEL_SHIFT = 0,
- GPIO0C0_SEL_MASK = 3 << GPIO0C0_SEL_SHIFT,
- GPIO0C0_GAMC_TXD1M0 = 1,
-
- GPIO0C1_SEL_SHIFT = 2,
- GPIO0C1_SEL_MASK = 3 << GPIO0C1_SEL_SHIFT,
- GPIO0C1_GAMC_TXD0M0 = 1,
-
- GPIO0C6_SEL_SHIFT = 12,
- GPIO0C6_SEL_MASK = 3 << GPIO0C6_SEL_SHIFT,
- GPIO0C6_GAMC_TXD2M0 = 1,
-
- GPIO0C7_SEL_SHIFT = 14,
- GPIO0C7_SEL_MASK = 3 << GPIO0C7_SEL_SHIFT,
- GPIO0C7_GAMC_TXD3M0 = 1,
-
- /* GPIO0D_IOMUX*/
- GPIO0D0_SEL_SHIFT = 0,
- GPIO0D0_SEL_MASK = 3 << GPIO0D0_SEL_SHIFT,
- GPIO0D0_GMAC_CLKM0 = 1,
-
- GPIO0D6_SEL_SHIFT = 12,
- GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT,
- GPIO0D6_GPIO = 0,
- GPIO0D6_SDMMC0_PWRENM1 = 3,
-
- /* GPIO1A_IOMUX */
- GPIO1A0_SEL_SHIFT = 0,
- GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT,
- GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555,
-
- /* GPIO1B_IOMUX */
- GPIO1B0_SEL_SHIFT = 0,
- GPIO1B0_SEL_MASK = 3 << GPIO1B0_SEL_SHIFT,
- GPIO1B0_GMAC_TXD1M1 = 2,
-
- GPIO1B1_SEL_SHIFT = 2,
- GPIO1B1_SEL_MASK = 3 << GPIO1B1_SEL_SHIFT,
- GPIO1B1_GMAC_TXD0M1 = 2,
-
- GPIO1B2_SEL_SHIFT = 4,
- GPIO1B2_SEL_MASK = 3 << GPIO1B2_SEL_SHIFT,
- GPIO1B2_GMAC_RXD1M1 = 2,
-
- GPIO1B3_SEL_SHIFT = 6,
- GPIO1B3_SEL_MASK = 3 << GPIO1B3_SEL_SHIFT,
- GPIO1B3_GMAC_RXD0M1 = 2,
-
- GPIO1B4_SEL_SHIFT = 8,
- GPIO1B4_SEL_MASK = 3 << GPIO1B4_SEL_SHIFT,
- GPIO1B4_GMAC_TXCLKM1 = 2,
-
- GPIO1B5_SEL_SHIFT = 10,
- GPIO1B5_SEL_MASK = 3 << GPIO1B5_SEL_SHIFT,
- GPIO1B5_GMAC_RXCLKM1 = 2,
-
- GPIO1B6_SEL_SHIFT = 12,
- GPIO1B6_SEL_MASK = 3 << GPIO1B6_SEL_SHIFT,
- GPIO1B6_GMAC_RXD3M1 = 2,
-
- GPIO1B7_SEL_SHIFT = 14,
- GPIO1B7_SEL_MASK = 3 << GPIO1B7_SEL_SHIFT,
- GPIO1B7_GMAC_RXD2M1 = 2,
-
- /* GPIO1C_IOMUX */
- GPIO1C0_SEL_SHIFT = 0,
- GPIO1C0_SEL_MASK = 3 << GPIO1C0_SEL_SHIFT,
- GPIO1C0_GMAC_TXD3M1 = 2,
-
- GPIO1C1_SEL_SHIFT = 2,
- GPIO1C1_SEL_MASK = 3 << GPIO1C1_SEL_SHIFT,
- GPIO1C1_GMAC_TXD2M1 = 2,
-
- GPIO1C3_SEL_SHIFT = 6,
- GPIO1C3_SEL_MASK = 3 << GPIO1C3_SEL_SHIFT,
- GPIO1C3_GMAC_MDIOM1 = 2,
-
- GPIO1C5_SEL_SHIFT = 10,
- GPIO1C5_SEL_MASK = 3 << GPIO1C5_SEL_SHIFT,
- GPIO1C5_GMAC_CLKM1 = 2,
-
- GPIO1C6_SEL_SHIFT = 12,
- GPIO1C6_SEL_MASK = 3 << GPIO1C6_SEL_SHIFT,
- GPIO1C6_GMAC_RXDVM1 = 2,
-
- GPIO1C7_SEL_SHIFT = 14,
- GPIO1C7_SEL_MASK = 3 << GPIO1C7_SEL_SHIFT,
- GPIO1C7_GMAC_MDCM1 = 2,
-
- /* GPIO1D_IOMUX */
- GPIO1D1_SEL_SHIFT = 2,
- GPIO1D1_SEL_MASK = 3 << GPIO1D1_SEL_SHIFT,
- GPIO1D1_GMAC_TXENM1 = 2,
-
- /* GPIO2A_IOMUX */
- GPIO2A0_SEL_SHIFT = 0,
- GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
- GPIO2A0_UART2_TX_M1 = 1,
-
- GPIO2A1_SEL_SHIFT = 2,
- GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
- GPIO2A1_UART2_RX_M1 = 1,
-
- GPIO2A2_SEL_SHIFT = 4,
- GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT,
- GPIO2A2_PWM_IR = 1,
-
- GPIO2A4_SEL_SHIFT = 8,
- GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT,
- GPIO2A4_PWM_0 = 1,
- GPIO2A4_I2C1_SDA,
-
- GPIO2A5_SEL_SHIFT = 10,
- GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT,
- GPIO2A5_PWM_1 = 1,
- GPIO2A5_I2C1_SCL,
-
- GPIO2A6_SEL_SHIFT = 12,
- GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT,
- GPIO2A6_PWM_2 = 1,
-
- GPIO2A7_SEL_SHIFT = 14,
- GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_SDMMC0_PWRENM0,
-
- /* GPIO2BL_IOMUX */
- GPIO2BL0_SEL_SHIFT = 0,
- GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT,
- GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15,
-
- GPIO2BL3_SEL_SHIFT = 6,
- GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT,
- GPIO2BL3_SPI_CSN0_M0 = 1,
-
- GPIO2BL4_SEL_SHIFT = 8,
- GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT,
- GPIO2BL4_SPI_CSN1_M0 = 1,
-
- GPIO2BL5_SEL_SHIFT = 10,
- GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT,
- GPIO2BL5_I2C2_SDA = 1,
-
- GPIO2BL6_SEL_SHIFT = 12,
- GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT,
- GPIO2BL6_I2C2_SCL = 1,
-
- /* GPIO2D_IOMUX */
- GPIO2D0_SEL_SHIFT = 0,
- GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT,
- GPIO2D0_I2C0_SCL = 1,
-
- GPIO2D1_SEL_SHIFT = 2,
- GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT,
- GPIO2D1_I2C0_SDA = 1,
-
- GPIO2D4_SEL_SHIFT = 8,
- GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT,
- GPIO2D4_EMMC_DATA1234 = 0xaa,
-
- /* GPIO3C_IOMUX */
- GPIO3C0_SEL_SHIFT = 0,
- GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT,
- GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa,
-
- /* COM_IOMUX */
- IOMUX_SEL_UART2_SHIFT = 0,
- IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
- IOMUX_SEL_UART2_M0 = 0,
- IOMUX_SEL_UART2_M1,
-
- IOMUX_SEL_GMAC_SHIFT = 2,
- IOMUX_SEL_GMAC_MASK = 1 << IOMUX_SEL_GMAC_SHIFT,
- IOMUX_SEL_GMAC_M0 = 0,
- IOMUX_SEL_GMAC_M1,
-
- IOMUX_SEL_SPI_SHIFT = 4,
- IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT,
- IOMUX_SEL_SPI_M0 = 0,
- IOMUX_SEL_SPI_M1,
- IOMUX_SEL_SPI_M2,
-
- IOMUX_SEL_SDMMC_SHIFT = 7,
- IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT,
- IOMUX_SEL_SDMMC_M0 = 0,
- IOMUX_SEL_SDMMC_M1,
-
- IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10,
- IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = 1 << IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT,
- IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0,
- IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER,
-
- /* GRF_GPIO1B_E */
- GRF_GPIO1B0_E_SHIFT = 0,
- GRF_GPIO1B0_E_MASK = 3 << GRF_GPIO1B0_E_SHIFT,
- GRF_GPIO1B1_E_SHIFT = 2,
- GRF_GPIO1B1_E_MASK = 3 << GRF_GPIO1B1_E_SHIFT,
- GRF_GPIO1B2_E_SHIFT = 4,
- GRF_GPIO1B2_E_MASK = 3 << GRF_GPIO1B2_E_SHIFT,
- GRF_GPIO1B3_E_SHIFT = 6,
- GRF_GPIO1B3_E_MASK = 3 << GRF_GPIO1B3_E_SHIFT,
- GRF_GPIO1B4_E_SHIFT = 8,
- GRF_GPIO1B4_E_MASK = 3 << GRF_GPIO1B4_E_SHIFT,
- GRF_GPIO1B5_E_SHIFT = 10,
- GRF_GPIO1B5_E_MASK = 3 << GRF_GPIO1B5_E_SHIFT,
- GRF_GPIO1B6_E_SHIFT = 12,
- GRF_GPIO1B6_E_MASK = 3 << GRF_GPIO1B6_E_SHIFT,
- GRF_GPIO1B7_E_SHIFT = 14,
- GRF_GPIO1B7_E_MASK = 3 << GRF_GPIO1B7_E_SHIFT,
-
- /* GRF_GPIO1C_E */
- GRF_GPIO1C0_E_SHIFT = 0,
- GRF_GPIO1C0_E_MASK = 3 << GRF_GPIO1C0_E_SHIFT,
- GRF_GPIO1C1_E_SHIFT = 2,
- GRF_GPIO1C1_E_MASK = 3 << GRF_GPIO1C1_E_SHIFT,
- GRF_GPIO1C3_E_SHIFT = 6,
- GRF_GPIO1C3_E_MASK = 3 << GRF_GPIO1C3_E_SHIFT,
- GRF_GPIO1C5_E_SHIFT = 10,
- GRF_GPIO1C5_E_MASK = 3 << GRF_GPIO1C5_E_SHIFT,
- GRF_GPIO1C6_E_SHIFT = 12,
- GRF_GPIO1C6_E_MASK = 3 << GRF_GPIO1C6_E_SHIFT,
- GRF_GPIO1C7_E_SHIFT = 14,
- GRF_GPIO1C7_E_MASK = 3 << GRF_GPIO1C7_E_SHIFT,
-
- /* GRF_GPIO1D_E */
- GRF_GPIO1D1_E_SHIFT = 2,
- GRF_GPIO1D1_E_MASK = 3 << GRF_GPIO1D1_E_SHIFT,
-};
-
-/* GPIO Bias drive strength settings */
-enum GPIO_BIAS {
- GPIO_BIAS_2MA = 0,
- GPIO_BIAS_4MA,
- GPIO_BIAS_8MA,
- GPIO_BIAS_12MA,
-};
-
-struct rk3328_pinctrl_priv {
- struct rk3328_grf_regs *grf;
-};
-
-static void pinctrl_rk3328_pwm_config(struct rk3328_grf_regs *grf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A4_SEL_MASK,
- GPIO2A4_PWM_0 << GPIO2A4_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A5_SEL_MASK,
- GPIO2A5_PWM_1 << GPIO2A5_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A6_SEL_MASK,
- GPIO2A6_PWM_2 << GPIO2A6_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A2_SEL_MASK,
- GPIO2A2_PWM_IR << GPIO2A2_SEL_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3328_i2c_config(struct rk3328_grf_regs *grf, int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D0_SEL_MASK | GPIO2D1_SEL_MASK,
- GPIO2D0_I2C0_SCL << GPIO2D0_SEL_SHIFT |
- GPIO2D1_I2C0_SDA << GPIO2D1_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C1:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A4_SEL_MASK | GPIO2A5_SEL_MASK,
- GPIO2A5_I2C1_SCL << GPIO2A5_SEL_SHIFT |
- GPIO2A4_I2C1_SDA << GPIO2A4_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C2:
- rk_clrsetreg(&grf->gpio2bl_iomux,
- GPIO2BL5_SEL_MASK | GPIO2BL6_SEL_MASK,
- GPIO2BL6_I2C2_SCL << GPIO2BL6_SEL_SHIFT |
- GPIO2BL5_I2C2_SDA << GPIO2BL5_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C3:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A5_SEL_MASK | GPIO0A6_SEL_MASK,
- GPIO0A5_I2C3_SCL << GPIO0A5_SEL_SHIFT |
- GPIO0A6_I2C3_SDA << GPIO0A6_SEL_SHIFT);
- break;
- default:
- debug("i2c id = %d iomux error!\n", i2c_id);
- break;
- }
-}
-
-static void pinctrl_rk3328_lcdc_config(struct rk3328_grf_regs *grf, int lcd_id)
-{
- switch (lcd_id) {
- case PERIPH_ID_LCDC0:
- break;
- default:
- debug("lcdc id = %d iomux error!\n", lcd_id);
- break;
- }
-}
-
-static int pinctrl_rk3328_spi_config(struct rk3328_grf_regs *grf,
- enum periph_id spi_id, int cs)
-{
- u32 com_iomux = readl(&grf->com_iomux);
-
- if ((com_iomux & IOMUX_SEL_SPI_MASK) !=
- IOMUX_SEL_SPI_M0 << IOMUX_SEL_SPI_SHIFT) {
- debug("driver do not support iomux other than m0\n");
- goto err;
- }
-
- switch (spi_id) {
- case PERIPH_ID_SPI0:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio2bl_iomux,
- GPIO2BL3_SEL_MASK,
- GPIO2BL3_SPI_CSN0_M0
- << GPIO2BL3_SEL_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio2bl_iomux,
- GPIO2BL4_SEL_MASK,
- GPIO2BL4_SPI_CSN1_M0
- << GPIO2BL4_SEL_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio2bl_iomux,
- GPIO2BL0_SEL_MASK,
- GPIO2BL0_SPI_CLK_TX_RX_M0 << GPIO2BL0_SEL_SHIFT);
- break;
- default:
- goto err;
- }
-
- return 0;
-err:
- debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
- return -ENOENT;
-}
-
-static void pinctrl_rk3328_uart_config(struct rk3328_grf_regs *grf, int uart_id)
-{
- u32 com_iomux = readl(&grf->com_iomux);
-
- switch (uart_id) {
- case PERIPH_ID_UART2:
- break;
- if (com_iomux & IOMUX_SEL_UART2_MASK)
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A0_SEL_MASK | GPIO2A1_SEL_MASK,
- GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT |
- GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
-
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf,
- int mmc_id)
-{
- u32 com_iomux = readl(&grf->com_iomux);
-
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- rk_clrsetreg(&grf->gpio0a_iomux,
- GPIO0A7_SEL_MASK,
- GPIO0A7_EMMC_DATA0 << GPIO0A7_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D4_SEL_MASK,
- GPIO2D4_EMMC_DATA1234 << GPIO2D4_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio3c_iomux,
- GPIO3C0_SEL_MASK,
- GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD
- << GPIO3C0_SEL_SHIFT);
- break;
- case PERIPH_ID_SDCARD:
- /* SDMMC_PWREN use GPIO and init as regulator-fiexed */
- if (com_iomux & IOMUX_SEL_SDMMC_MASK)
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D6_SEL_MASK,
- GPIO0D6_GPIO << GPIO0D6_SEL_SHIFT);
- else
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A7_SEL_MASK,
- GPIO2A7_GPIO << GPIO2A7_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio1a_iomux,
- GPIO1A0_SEL_MASK,
- GPIO1A0_CARD_DATA_CLK_CMD_DETN
- << GPIO1A0_SEL_SHIFT);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id)
-{
- switch (gmac_id) {
- case PERIPH_ID_GMAC:
- /* set rgmii m1 pins mux */
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B0_SEL_MASK |
- GPIO1B1_SEL_MASK |
- GPIO1B2_SEL_MASK |
- GPIO1B3_SEL_MASK |
- GPIO1B4_SEL_MASK |
- GPIO1B5_SEL_MASK |
- GPIO1B6_SEL_MASK |
- GPIO1B7_SEL_MASK,
- GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT |
- GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT |
- GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT |
- GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT |
- GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT |
- GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT |
- GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT |
- GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT);
-
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C0_SEL_MASK |
- GPIO1C1_SEL_MASK |
- GPIO1C3_SEL_MASK |
- GPIO1C5_SEL_MASK |
- GPIO1C6_SEL_MASK |
- GPIO1C7_SEL_MASK,
- GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT |
- GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT |
- GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT |
- GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT |
- GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT |
- GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT);
-
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D1_SEL_MASK,
- GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT);
-
- /* set rgmii m0 tx pins mux */
- rk_clrsetreg(&grf->gpio0b_iomux,
- GPIO0B0_SEL_MASK |
- GPIO0B4_SEL_MASK,
- GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT |
- GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT);
-
- rk_clrsetreg(&grf->gpio0c_iomux,
- GPIO0C0_SEL_MASK |
- GPIO0C1_SEL_MASK |
- GPIO0C6_SEL_MASK |
- GPIO0C7_SEL_MASK,
- GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT |
- GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT |
- GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT |
- GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT);
-
- rk_clrsetreg(&grf->gpio0d_iomux,
- GPIO0D0_SEL_MASK,
- GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT);
-
- /* set com mux */
- rk_clrsetreg(&grf->com_iomux,
- IOMUX_SEL_GMAC_MASK |
- IOMUX_SEL_GMACM1_OPTIMIZATION_MASK,
- IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT |
- IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER <<
- IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT);
-
- /*
- * set rgmii m1 tx pins to 12ma drive-strength,
- * and clean others to 2ma.
- */
- rk_clrsetreg(&grf->gpio1b_e,
- GRF_GPIO1B0_E_MASK |
- GRF_GPIO1B1_E_MASK |
- GRF_GPIO1B2_E_MASK |
- GRF_GPIO1B3_E_MASK |
- GRF_GPIO1B4_E_MASK |
- GRF_GPIO1B5_E_MASK |
- GRF_GPIO1B6_E_MASK |
- GRF_GPIO1B7_E_MASK,
- GPIO_BIAS_12MA << GRF_GPIO1B0_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO1B1_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B2_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B3_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO1B4_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B5_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B6_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1B7_E_SHIFT);
-
- rk_clrsetreg(&grf->gpio1c_e,
- GRF_GPIO1C0_E_MASK |
- GRF_GPIO1C1_E_MASK |
- GRF_GPIO1C3_E_MASK |
- GRF_GPIO1C5_E_MASK |
- GRF_GPIO1C6_E_MASK |
- GRF_GPIO1C7_E_MASK,
- GPIO_BIAS_12MA << GRF_GPIO1C0_E_SHIFT |
- GPIO_BIAS_12MA << GRF_GPIO1C1_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1C3_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1C5_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1C6_E_SHIFT |
- GPIO_BIAS_2MA << GRF_GPIO1C7_E_SHIFT);
-
- rk_clrsetreg(&grf->gpio1d_e,
- GRF_GPIO1D1_E_MASK,
- GPIO_BIAS_12MA << GRF_GPIO1D1_E_SHIFT);
- break;
- default:
- debug("gmac id = %d iomux error!\n", gmac_id);
- break;
- }
-}
-#endif
-
-static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- pinctrl_rk3328_pwm_config(priv->grf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- pinctrl_rk3328_i2c_config(priv->grf, func);
- break;
- case PERIPH_ID_SPI0:
- pinctrl_rk3328_spi_config(priv->grf, func, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3328_uart_config(priv->grf, func);
- break;
- case PERIPH_ID_LCDC0:
- case PERIPH_ID_LCDC1:
- pinctrl_rk3328_lcdc_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3328_sdmmc_config(priv->grf, func);
- break;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
- pinctrl_rk3328_gmac_config(priv->grf, func);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3328_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 49:
- return PERIPH_ID_SPI0;
- case 50:
- return PERIPH_ID_PWM0;
- case 36:
- return PERIPH_ID_I2C0;
- case 37: /* Note strange order */
- return PERIPH_ID_I2C1;
- case 38:
- return PERIPH_ID_I2C2;
- case 39:
- return PERIPH_ID_I2C3;
- case 12:
- return PERIPH_ID_SDCARD;
- case 14:
- return PERIPH_ID_EMMC;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 24:
- return PERIPH_ID_GMAC;
-#endif
- }
-
- return -ENOENT;
-}
-
-static int rk3328_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3328_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
-
- return rk3328_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3328_pinctrl_ops = {
- .set_state_simple = rk3328_pinctrl_set_state_simple,
- .request = rk3328_pinctrl_request,
- .get_periph_id = rk3328_pinctrl_get_periph_id,
-};
-
-static int rk3328_pinctrl_probe(struct udevice *dev)
-{
- struct rk3328_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- debug("%s: grf=%p\n", __func__, priv->grf);
-
- return ret;
-}
-
-static const struct udevice_id rk3328_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3328-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3328) = {
- .name = "rockchip_rk3328_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3328_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3328_pinctrl_priv),
- .ops = &rk3328_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk3328_pinctrl_probe,
-};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3368.c b/drivers/pinctrl/rockchip/pinctrl_rk3368.c
deleted file mode 100644
index 25249e3..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rk3368.c
+++ /dev/null
@@ -1,742 +0,0 @@
-/*
- * (C) Copyright 2017 Rockchip Electronics Co., Ltd
- * Author: Andy Yan <andy.yan@rock-chips.com>
- * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/grf_rk3368.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* PMUGRF_GPIO0B_IOMUX */
-enum {
- GPIO0B5_SHIFT = 10,
- GPIO0B5_MASK = GENMASK(GPIO0B5_SHIFT + 1, GPIO0B5_SHIFT),
- GPIO0B5_GPIO = 0,
- GPIO0B5_SPI2_CSN0 = (2 << GPIO0B5_SHIFT),
-
- GPIO0B4_SHIFT = 8,
- GPIO0B4_MASK = GENMASK(GPIO0B4_SHIFT + 1, GPIO0B4_SHIFT),
- GPIO0B4_GPIO = 0,
- GPIO0B4_SPI2_CLK = (2 << GPIO0B4_SHIFT),
-
- GPIO0B3_SHIFT = 6,
- GPIO0B3_MASK = GENMASK(GPIO0B3_SHIFT + 1, GPIO0B3_SHIFT),
- GPIO0B3_GPIO = 0,
- GPIO0B3_SPI2_TXD = (2 << GPIO0B3_SHIFT),
-
- GPIO0B2_SHIFT = 4,
- GPIO0B2_MASK = GENMASK(GPIO0B2_SHIFT + 1, GPIO0B2_SHIFT),
- GPIO0B2_GPIO = 0,
- GPIO0B2_SPI2_RXD = (2 << GPIO0B2_SHIFT),
-};
-
-/*GRF_GPIO0C_IOMUX*/
-enum {
- GPIO0C7_SHIFT = 14,
- GPIO0C7_MASK = GENMASK(GPIO0C7_SHIFT + 1, GPIO0C7_SHIFT),
- GPIO0C7_GPIO = 0,
- GPIO0C7_LCDC_D19 = (1 << GPIO0C7_SHIFT),
- GPIO0C7_TRACE_D9 = (2 << GPIO0C7_SHIFT),
- GPIO0C7_UART1_RTSN = (3 << GPIO0C7_SHIFT),
-
- GPIO0C6_SHIFT = 12,
- GPIO0C6_MASK = GENMASK(GPIO0C6_SHIFT + 1, GPIO0C6_SHIFT),
- GPIO0C6_GPIO = 0,
- GPIO0C6_LCDC_D18 = (1 << GPIO0C6_SHIFT),
- GPIO0C6_TRACE_D8 = (2 << GPIO0C6_SHIFT),
- GPIO0C6_UART1_CTSN = (3 << GPIO0C6_SHIFT),
-
- GPIO0C5_SHIFT = 10,
- GPIO0C5_MASK = GENMASK(GPIO0C5_SHIFT + 1, GPIO0C5_SHIFT),
- GPIO0C5_GPIO = 0,
- GPIO0C5_LCDC_D17 = (1 << GPIO0C5_SHIFT),
- GPIO0C5_TRACE_D7 = (2 << GPIO0C5_SHIFT),
- GPIO0C5_UART1_SOUT = (3 << GPIO0C5_SHIFT),
-
- GPIO0C4_SHIFT = 8,
- GPIO0C4_MASK = GENMASK(GPIO0C4_SHIFT + 1, GPIO0C4_SHIFT),
- GPIO0C4_GPIO = 0,
- GPIO0C4_LCDC_D16 = (1 << GPIO0C4_SHIFT),
- GPIO0C4_TRACE_D6 = (2 << GPIO0C4_SHIFT),
- GPIO0C4_UART1_SIN = (3 << GPIO0C4_SHIFT),
-
- GPIO0C3_SHIFT = 6,
- GPIO0C3_MASK = GENMASK(GPIO0C3_SHIFT + 1, GPIO0C3_SHIFT),
- GPIO0C3_GPIO = 0,
- GPIO0C3_LCDC_D15 = (1 << GPIO0C3_SHIFT),
- GPIO0C3_TRACE_D5 = (2 << GPIO0C3_SHIFT),
- GPIO0C3_MCU_JTAG_TDO = (3 << GPIO0C3_SHIFT),
-
- GPIO0C2_SHIFT = 4,
- GPIO0C2_MASK = GENMASK(GPIO0C2_SHIFT + 1, GPIO0C2_SHIFT),
- GPIO0C2_GPIO = 0,
- GPIO0C2_LCDC_D14 = (1 << GPIO0C2_SHIFT),
- GPIO0C2_TRACE_D4 = (2 << GPIO0C2_SHIFT),
- GPIO0C2_MCU_JTAG_TDI = (3 << GPIO0C2_SHIFT),
-
- GPIO0C1_SHIFT = 2,
- GPIO0C1_MASK = GENMASK(GPIO0C1_SHIFT + 1, GPIO0C1_SHIFT),
- GPIO0C1_GPIO = 0,
- GPIO0C1_LCDC_D13 = (1 << GPIO0C1_SHIFT),
- GPIO0C1_TRACE_D3 = (2 << GPIO0C1_SHIFT),
- GPIO0C1_MCU_JTAG_TRTSN = (3 << GPIO0C1_SHIFT),
-
- GPIO0C0_SHIFT = 0,
- GPIO0C0_MASK = GENMASK(GPIO0C0_SHIFT + 1, GPIO0C0_SHIFT),
- GPIO0C0_GPIO = 0,
- GPIO0C0_LCDC_D12 = (1 << GPIO0C0_SHIFT),
- GPIO0C0_TRACE_D2 = (2 << GPIO0C0_SHIFT),
- GPIO0C0_MCU_JTAG_TDO = (3 << GPIO0C0_SHIFT),
-};
-
-/*GRF_GPIO0D_IOMUX*/
-enum {
- GPIO0D7_SHIFT = 14,
- GPIO0D7_MASK = GENMASK(GPIO0D7_SHIFT + 1, GPIO0D7_SHIFT),
- GPIO0D7_GPIO = 0,
- GPIO0D7_LCDC_DCLK = (1 << GPIO0D7_SHIFT),
- GPIO0D7_TRACE_CTL = (2 << GPIO0D7_SHIFT),
- GPIO0D7_PMU_DEBUG5 = (3 << GPIO0D7_SHIFT),
-
- GPIO0D6_SHIFT = 12,
- GPIO0D6_MASK = GENMASK(GPIO0D6_SHIFT + 1, GPIO0D6_SHIFT),
- GPIO0D6_GPIO = 0,
- GPIO0D6_LCDC_DEN = (1 << GPIO0D6_SHIFT),
- GPIO0D6_TRACE_CLK = (2 << GPIO0D6_SHIFT),
- GPIO0D6_PMU_DEBUG4 = (3 << GPIO0D6_SHIFT),
-
- GPIO0D5_SHIFT = 10,
- GPIO0D5_MASK = GENMASK(GPIO0D5_SHIFT + 1, GPIO0D5_SHIFT),
- GPIO0D5_GPIO = 0,
- GPIO0D5_LCDC_VSYNC = (1 << GPIO0D5_SHIFT),
- GPIO0D5_TRACE_D15 = (2 << GPIO0D5_SHIFT),
- GPIO0D5_PMU_DEBUG3 = (3 << GPIO0D5_SHIFT),
-
- GPIO0D4_SHIFT = 8,
- GPIO0D4_MASK = GENMASK(GPIO0D4_SHIFT + 1, GPIO0D4_SHIFT),
- GPIO0D4_GPIO = 0,
- GPIO0D4_LCDC_HSYNC = (1 << GPIO0D4_SHIFT),
- GPIO0D4_TRACE_D14 = (2 << GPIO0D4_SHIFT),
- GPIO0D4_PMU_DEBUG2 = (3 << GPIO0D4_SHIFT),
-
- GPIO0D3_SHIFT = 6,
- GPIO0D3_MASK = GENMASK(GPIO0D3_SHIFT + 1, GPIO0D3_SHIFT),
- GPIO0D3_GPIO = 0,
- GPIO0D3_LCDC_D23 = (1 << GPIO0D3_SHIFT),
- GPIO0D3_TRACE_D13 = (2 << GPIO0D3_SHIFT),
- GPIO0D3_UART4_SIN = (3 << GPIO0D3_SHIFT),
-
- GPIO0D2_SHIFT = 4,
- GPIO0D2_MASK = GENMASK(GPIO0D2_SHIFT + 1, GPIO0D2_SHIFT),
- GPIO0D2_GPIO = 0,
- GPIO0D2_LCDC_D22 = (1 << GPIO0D2_SHIFT),
- GPIO0D2_TRACE_D12 = (2 << GPIO0D2_SHIFT),
- GPIO0D2_UART4_SOUT = (3 << GPIO0D2_SHIFT),
-
- GPIO0D1_SHIFT = 2,
- GPIO0D1_MASK = GENMASK(GPIO0D1_SHIFT + 1, GPIO0D1_SHIFT),
- GPIO0D1_GPIO = 0,
- GPIO0D1_LCDC_D21 = (1 << GPIO0D1_SHIFT),
- GPIO0D1_TRACE_D11 = (2 << GPIO0D1_SHIFT),
- GPIO0D1_UART4_RTSN = (3 << GPIO0D1_SHIFT),
-
- GPIO0D0_SHIFT = 0,
- GPIO0D0_MASK = GENMASK(GPIO0D0_SHIFT + 1, GPIO0D0_SHIFT),
- GPIO0D0_GPIO = 0,
- GPIO0D0_LCDC_D20 = (1 << GPIO0D0_SHIFT),
- GPIO0D0_TRACE_D10 = (2 << GPIO0D0_SHIFT),
- GPIO0D0_UART4_CTSN = (3 << GPIO0D0_SHIFT),
-};
-
-/*GRF_GPIO2A_IOMUX*/
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = GENMASK(GPIO2A7_SHIFT + 1, GPIO2A7_SHIFT),
- GPIO2A7_GPIO = 0,
- GPIO2A7_SDMMC0_D2 = (1 << GPIO2A7_SHIFT),
- GPIO2A7_JTAG_TCK = (2 << GPIO2A7_SHIFT),
-
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = GENMASK(GPIO2A6_SHIFT + 1, GPIO2A6_SHIFT),
- GPIO2A6_GPIO = 0,
- GPIO2A6_SDMMC0_D1 = (1 << GPIO2A6_SHIFT),
- GPIO2A6_UART2_SIN = (2 << GPIO2A6_SHIFT),
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = GENMASK(GPIO2A5_SHIFT + 1, GPIO2A5_SHIFT),
- GPIO2A5_GPIO = 0,
- GPIO2A5_SDMMC0_D0 = (1 << GPIO2A5_SHIFT),
- GPIO2A5_UART2_SOUT = (2 << GPIO2A5_SHIFT),
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = GENMASK(GPIO2A4_SHIFT + 1, GPIO2A4_SHIFT),
- GPIO2A4_GPIO = 0,
- GPIO2A4_FLASH_DQS = (1 << GPIO2A4_SHIFT),
- GPIO2A4_EMMC_CLKOUT = (2 << GPIO2A4_SHIFT),
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = GENMASK(GPIO2A3_SHIFT + 1, GPIO2A3_SHIFT),
- GPIO2A3_GPIO = 0,
- GPIO2A3_FLASH_CSN3 = (1 << GPIO2A3_SHIFT),
- GPIO2A3_EMMC_RSTNOUT = (2 << GPIO2A3_SHIFT),
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = GENMASK(GPIO2A2_SHIFT + 1, GPIO2A2_SHIFT),
- GPIO2A2_GPIO = 0,
- GPIO2A2_FLASH_CSN2 = (1 << GPIO2A2_SHIFT),
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = GENMASK(GPIO2A1_SHIFT + 1, GPIO2A1_SHIFT),
- GPIO2A1_GPIO = 0,
- GPIO2A1_FLASH_CSN1 = (1 << GPIO2A1_SHIFT),
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = GENMASK(GPIO2A0_SHIFT + 1, GPIO2A0_SHIFT),
- GPIO2A0_GPIO = 0,
- GPIO2A0_FLASH_CSN0 = (1 << GPIO2A0_SHIFT),
-};
-
-/*GRF_GPIO2B_IOMUX*/
-enum {
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = GENMASK(GPIO2B3_SHIFT + 1, GPIO2B3_SHIFT),
- GPIO2B3_GPIO = 0,
- GPIO2B3_SDMMC0_DTECTN = (1 << GPIO2B3_SHIFT),
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = GENMASK(GPIO2B2_SHIFT + 1, GPIO2B2_SHIFT),
- GPIO2B2_GPIO = 0,
- GPIO2B2_SDMMC0_CMD = (1 << GPIO2B2_SHIFT),
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = GENMASK(GPIO2B1_SHIFT + 1, GPIO2B1_SHIFT),
- GPIO2B1_GPIO = 0,
- GPIO2B1_SDMMC0_CLKOUT = (1 << GPIO2B1_SHIFT),
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = GENMASK(GPIO2B0_SHIFT + 1, GPIO2B0_SHIFT),
- GPIO2B0_GPIO = 0,
- GPIO2B0_SDMMC0_D3 = (1 << GPIO2B0_SHIFT),
-};
-
-/*GRF_GPIO2D_IOMUX*/
-enum {
- GPIO2D7_SHIFT = 14,
- GPIO2D7_MASK = GENMASK(GPIO2D7_SHIFT + 1, GPIO2D7_SHIFT),
- GPIO2D7_GPIO = 0,
- GPIO2D7_SDIO0_D3 = (1 << GPIO2D7_SHIFT),
-
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = GENMASK(GPIO2D6_SHIFT + 1, GPIO2D6_SHIFT),
- GPIO2D6_GPIO = 0,
- GPIO2D6_SDIO0_D2 = (1 << GPIO2D6_SHIFT),
-
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = GENMASK(GPIO2D5_SHIFT + 1, GPIO2D5_SHIFT),
- GPIO2D5_GPIO = 0,
- GPIO2D5_SDIO0_D1 = (1 << GPIO2D5_SHIFT),
-
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = GENMASK(GPIO2D4_SHIFT + 1, GPIO2D4_SHIFT),
- GPIO2D4_GPIO = 0,
- GPIO2D4_SDIO0_D0 = (1 << GPIO2D4_SHIFT),
-
- GPIO2D3_SHIFT = 6,
- GPIO2D3_MASK = GENMASK(GPIO2D3_SHIFT + 1, GPIO2D3_SHIFT),
- GPIO2D3_GPIO = 0,
- GPIO2D3_UART0_RTS0 = (1 << GPIO2D3_SHIFT),
-
- GPIO2D2_SHIFT = 4,
- GPIO2D2_MASK = GENMASK(GPIO2D2_SHIFT + 1, GPIO2D2_SHIFT),
- GPIO2D2_GPIO = 0,
- GPIO2D2_UART0_CTS0 = (1 << GPIO2D2_SHIFT),
-
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = GENMASK(GPIO2D1_SHIFT + 1, GPIO2D1_SHIFT),
- GPIO2D1_GPIO = 0,
- GPIO2D1_UART0_SOUT = (1 << GPIO2D1_SHIFT),
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = GENMASK(GPIO2D0_SHIFT + 1, GPIO2D0_SHIFT),
- GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_SIN = (1 << GPIO2D0_SHIFT),
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = GENMASK(GPIO1B7_SHIFT + 1, GPIO1B7_SHIFT),
- GPIO1B7_GPIO = 0,
- GPIO1B7_SPI1_CSN0 = (2 << GPIO1B7_SHIFT),
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = GENMASK(GPIO1B6_SHIFT + 1, GPIO1B6_SHIFT),
- GPIO1B6_GPIO = 0,
- GPIO1B6_SPI1_CLK = (2 << GPIO1B6_SHIFT),
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = GENMASK(GPIO1C7_SHIFT + 1, GPIO1C7_SHIFT),
- GPIO1C7_GPIO = 0,
- GPIO1C7_EMMC_DATA5 = (2 << GPIO1C7_SHIFT),
- GPIO1C7_SPI0_TXD = (3 << GPIO1C7_SHIFT),
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = GENMASK(GPIO1C6_SHIFT + 1, GPIO1C6_SHIFT),
- GPIO1C6_GPIO = 0,
- GPIO1C6_EMMC_DATA4 = (2 << GPIO1C6_SHIFT),
- GPIO1C6_SPI0_RXD = (3 << GPIO1C6_SHIFT),
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = GENMASK(GPIO1C5_SHIFT + 1, GPIO1C5_SHIFT),
- GPIO1C5_GPIO = 0,
- GPIO1C5_EMMC_DATA3 = (2 << GPIO1C5_SHIFT),
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = GENMASK(GPIO1C4_SHIFT + 1, GPIO1C4_SHIFT),
- GPIO1C4_GPIO = 0,
- GPIO1C4_EMMC_DATA2 = (2 << GPIO1C4_SHIFT),
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = GENMASK(GPIO1C3_SHIFT + 1, GPIO1C3_SHIFT),
- GPIO1C3_GPIO = 0,
- GPIO1C3_EMMC_DATA1 = (2 << GPIO1C3_SHIFT),
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = GENMASK(GPIO1C2_SHIFT + 1, GPIO1C2_SHIFT),
- GPIO1C2_GPIO = 0,
- GPIO1C2_EMMC_DATA0 = (2 << GPIO1C2_SHIFT),
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = GENMASK(GPIO1C1_SHIFT + 1, GPIO1C1_SHIFT),
- GPIO1C1_GPIO = 0,
- GPIO1C1_SPI1_RXD = (2 << GPIO1C1_SHIFT),
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = GENMASK(GPIO1C0_SHIFT + 1, GPIO1C0_SHIFT),
- GPIO1C0_GPIO = 0,
- GPIO1C0_SPI1_TXD = (2 << GPIO1C0_SHIFT),
-};
-
-/* GRF_GPIO1D_IOMUX*/
-enum {
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = GENMASK(GPIO1D5_SHIFT + 1, GPIO1D5_SHIFT),
- GPIO1D5_GPIO = 0,
- GPIO1D5_SPI0_CLK = (2 << GPIO1D5_SHIFT),
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = GENMASK(GPIO1D3_SHIFT + 1, GPIO1D3_SHIFT),
- GPIO1D3_GPIO = 0,
- GPIO1D3_EMMC_PWREN = (2 << GPIO1D3_SHIFT),
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = GENMASK(GPIO1D2_SHIFT + 1, GPIO1D2_SHIFT),
- GPIO1D2_GPIO = 0,
- GPIO1D2_EMMC_CMD = (2 << GPIO1D2_SHIFT),
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = GENMASK(GPIO1D1_SHIFT + 1, GPIO1D1_SHIFT),
- GPIO1D1_GPIO = 0,
- GPIO1D1_EMMC_DATA7 = (2 << GPIO1D1_SHIFT),
- GPIO1D1_SPI0_CSN1 = (3 << GPIO1D1_SHIFT),
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = GENMASK(GPIO1D0_SHIFT + 1, GPIO1D0_SHIFT),
- GPIO1D0_GPIO = 0,
- GPIO1D0_EMMC_DATA6 = (2 << GPIO1D0_SHIFT),
- GPIO1D0_SPI0_CSN0 = (3 << GPIO1D0_SHIFT),
-};
-
-
-/*GRF_GPIO3B_IOMUX*/
-enum {
- GPIO3B7_SHIFT = 14,
- GPIO3B7_MASK = GENMASK(GPIO3B7_SHIFT + 1, GPIO3B7_SHIFT),
- GPIO3B7_GPIO = 0,
- GPIO3B7_MAC_RXD0 = (1 << GPIO3B7_SHIFT),
-
- GPIO3B6_SHIFT = 12,
- GPIO3B6_MASK = GENMASK(GPIO3B6_SHIFT + 1, GPIO3B6_SHIFT),
- GPIO3B6_GPIO = 0,
- GPIO3B6_MAC_TXD3 = (1 << GPIO3B6_SHIFT),
-
- GPIO3B5_SHIFT = 10,
- GPIO3B5_MASK = GENMASK(GPIO3B5_SHIFT + 1, GPIO3B5_SHIFT),
- GPIO3B5_GPIO = 0,
- GPIO3B5_MAC_TXEN = (1 << GPIO3B5_SHIFT),
-
- GPIO3B4_SHIFT = 8,
- GPIO3B4_MASK = GENMASK(GPIO3B4_SHIFT + 1, GPIO3B4_SHIFT),
- GPIO3B4_GPIO = 0,
- GPIO3B4_MAC_COL = (1 << GPIO3B4_SHIFT),
-
- GPIO3B3_SHIFT = 6,
- GPIO3B3_MASK = GENMASK(GPIO3B3_SHIFT + 1, GPIO3B3_SHIFT),
- GPIO3B3_GPIO = 0,
- GPIO3B3_MAC_CRS = (1 << GPIO3B3_SHIFT),
-
- GPIO3B2_SHIFT = 4,
- GPIO3B2_MASK = GENMASK(GPIO3B2_SHIFT + 1, GPIO3B2_SHIFT),
- GPIO3B2_GPIO = 0,
- GPIO3B2_MAC_TXD2 = (1 << GPIO3B2_SHIFT),
-
- GPIO3B1_SHIFT = 2,
- GPIO3B1_MASK = GENMASK(GPIO3B1_SHIFT + 1, GPIO3B1_SHIFT),
- GPIO3B1_GPIO = 0,
- GPIO3B1_MAC_TXD1 = (1 << GPIO3B1_SHIFT),
-
- GPIO3B0_SHIFT = 0,
- GPIO3B0_MASK = GENMASK(GPIO3B0_SHIFT + 1, GPIO3B0_SHIFT),
- GPIO3B0_GPIO = 0,
- GPIO3B0_MAC_TXD0 = (1 << GPIO3B0_SHIFT),
- GPIO3B0_PWM0 = (2 << GPIO3B0_SHIFT),
-};
-
-/*GRF_GPIO3C_IOMUX*/
-enum {
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = GENMASK(GPIO3C6_SHIFT + 1, GPIO3C6_SHIFT),
- GPIO3C6_GPIO = 0,
- GPIO3C6_MAC_CLK = (1 << GPIO3C6_SHIFT),
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = GENMASK(GPIO3C5_SHIFT + 1, GPIO3C5_SHIFT),
- GPIO3C5_GPIO = 0,
- GPIO3C5_MAC_RXEN = (1 << GPIO3C5_SHIFT),
-
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = GENMASK(GPIO3C4_SHIFT + 1, GPIO3C4_SHIFT),
- GPIO3C4_GPIO = 0,
- GPIO3C4_MAC_RXDV = (1 << GPIO3C4_SHIFT),
-
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = GENMASK(GPIO3C3_SHIFT + 1, GPIO3C3_SHIFT),
- GPIO3C3_GPIO = 0,
- GPIO3C3_MAC_MDC = (1 << GPIO3C3_SHIFT),
-
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = GENMASK(GPIO3C2_SHIFT + 1, GPIO3C2_SHIFT),
- GPIO3C2_GPIO = 0,
- GPIO3C2_MAC_RXD3 = (1 << GPIO3C2_SHIFT),
-
- GPIO3C1_SHIFT = 2,
- GPIO3C1_MASK = GENMASK(GPIO3C1_SHIFT + 1, GPIO3C1_SHIFT),
- GPIO3C1_GPIO = 0,
- GPIO3C1_MAC_RXD2 = (1 << GPIO3C1_SHIFT),
-
- GPIO3C0_SHIFT = 0,
- GPIO3C0_MASK = GENMASK(GPIO3C0_SHIFT + 1, GPIO3C0_SHIFT),
- GPIO3C0_GPIO = 0,
- GPIO3C0_MAC_RXD1 = (1 << GPIO3C0_SHIFT),
-};
-
-/*GRF_GPIO3D_IOMUX*/
-enum {
- GPIO3D4_SHIFT = 8,
- GPIO3D4_MASK = GENMASK(GPIO3D4_SHIFT + 1, GPIO3D4_SHIFT),
- GPIO3D4_GPIO = 0,
- GPIO3D4_MAC_TXCLK = (1 << GPIO3D4_SHIFT),
- GPIO3D4_SPI1_CNS1 = (2 << GPIO3D4_SHIFT),
-
- GPIO3D1_SHIFT = 2,
- GPIO3D1_MASK = GENMASK(GPIO3D1_SHIFT + 1, GPIO3D1_SHIFT),
- GPIO3D1_GPIO = 0,
- GPIO3D1_MAC_RXCLK = (1 << GPIO3D1_SHIFT),
-
- GPIO3D0_SHIFT = 0,
- GPIO3D0_MASK = GENMASK(GPIO3D0_SHIFT + 1, GPIO3D0_SHIFT),
- GPIO3D0_GPIO = 0,
- GPIO3D0_MAC_MDIO = (1 << GPIO3D0_SHIFT),
-};
-
-struct rk3368_pinctrl_priv {
- struct rk3368_grf *grf;
- struct rk3368_pmu_grf *pmugrf;
-};
-
-static void pinctrl_rk3368_uart_config(struct rk3368_pinctrl_priv *priv,
- int uart_id)
-{
- struct rk3368_grf *grf = priv->grf;
- struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
-
- switch (uart_id) {
- case PERIPH_ID_UART2:
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A6_MASK | GPIO2A5_MASK,
- GPIO2A6_UART2_SIN | GPIO2A5_UART2_SOUT);
- break;
- case PERIPH_ID_UART0:
- break;
- case PERIPH_ID_UART1:
- break;
- case PERIPH_ID_UART3:
- break;
- case PERIPH_ID_UART4:
- rk_clrsetreg(&pmugrf->gpio0d_iomux,
- GPIO0D0_MASK | GPIO0D1_MASK |
- GPIO0D2_MASK | GPIO0D3_MASK,
- GPIO0D0_GPIO | GPIO0D1_GPIO |
- GPIO0D2_UART4_SOUT | GPIO0D3_UART4_SIN);
- break;
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3368_spi_config(struct rk3368_pinctrl_priv *priv,
- int spi_id)
-{
- struct rk3368_grf *grf = priv->grf;
- struct rk3368_pmu_grf *pmugrf = priv->pmugrf;
-
- switch (spi_id) {
- case PERIPH_ID_SPI0:
- /*
- * eMMC can only be connected with 4 bits, when SPI0 is used.
- * This is all-or-nothing, so we assume that if someone asks us
- * to configure SPI0, that their eMMC interface is unused or
- * configured appropriately.
- */
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D0_MASK | GPIO1D1_MASK |
- GPIO1D5_MASK,
- GPIO1D0_SPI0_CSN0 | GPIO1D1_SPI0_CSN1 |
- GPIO1D5_SPI0_CLK);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C6_MASK | GPIO1C7_MASK,
- GPIO1C6_SPI0_RXD | GPIO1C7_SPI0_TXD);
- break;
- case PERIPH_ID_SPI1:
- /*
- * We don't implement support for configuring SPI1_CSN#1, as it
- * conflicts with the GMAC (MAC TX clk-out).
- */
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B6_MASK | GPIO1B7_MASK,
- GPIO1B6_SPI1_CLK | GPIO1B7_SPI1_CSN0);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C0_MASK | GPIO1C1_MASK,
- GPIO1C0_SPI1_TXD | GPIO1C1_SPI1_RXD);
- break;
- case PERIPH_ID_SPI2:
- rk_clrsetreg(&pmugrf->gpio0b_iomux,
- GPIO0B2_MASK | GPIO0B3_MASK |
- GPIO0B4_MASK | GPIO0B5_MASK,
- GPIO0B2_SPI2_RXD | GPIO0B3_SPI2_TXD |
- GPIO0B4_SPI2_CLK | GPIO0B5_SPI2_CSN0);
- break;
- default:
- debug("%s: spi id = %d iomux error!\n", __func__, spi_id);
- break;
- }
-}
-
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static void pinctrl_rk3368_gmac_config(struct rk3368_grf *grf, int gmac_id)
-{
- rk_clrsetreg(&grf->gpio3b_iomux,
- GPIO3B0_MASK | GPIO3B1_MASK |
- GPIO3B2_MASK | GPIO3B5_MASK |
- GPIO3B6_MASK | GPIO3B7_MASK,
- GPIO3B0_MAC_TXD0 | GPIO3B1_MAC_TXD1 |
- GPIO3B2_MAC_TXD2 | GPIO3B5_MAC_TXEN |
- GPIO3B6_MAC_TXD3 | GPIO3B7_MAC_RXD0);
- rk_clrsetreg(&grf->gpio3c_iomux,
- GPIO3C0_MASK | GPIO3C1_MASK |
- GPIO3C2_MASK | GPIO3C3_MASK |
- GPIO3C4_MASK | GPIO3C5_MASK |
- GPIO3C6_MASK,
- GPIO3C0_MAC_RXD1 | GPIO3C1_MAC_RXD2 |
- GPIO3C2_MAC_RXD3 | GPIO3C3_MAC_MDC |
- GPIO3C4_MAC_RXDV | GPIO3C5_MAC_RXEN |
- GPIO3C6_MAC_CLK);
- rk_clrsetreg(&grf->gpio3d_iomux,
- GPIO3D0_MASK | GPIO3D1_MASK |
- GPIO3D4_MASK,
- GPIO3D0_MAC_MDIO | GPIO3D1_MAC_RXCLK |
- GPIO3D4_MAC_TXCLK);
-}
-#endif
-
-static void pinctrl_rk3368_sdmmc_config(struct rk3368_grf *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- debug("mmc id = %d setting registers!\n", mmc_id);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C2_MASK | GPIO1C3_MASK |
- GPIO1C4_MASK | GPIO1C5_MASK |
- GPIO1C6_MASK | GPIO1C7_MASK,
- GPIO1C2_EMMC_DATA0 |
- GPIO1C3_EMMC_DATA1 |
- GPIO1C4_EMMC_DATA2 |
- GPIO1C5_EMMC_DATA3 |
- GPIO1C6_EMMC_DATA4 |
- GPIO1C7_EMMC_DATA5);
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D0_MASK | GPIO1D1_MASK |
- GPIO1D2_MASK | GPIO1D3_MASK,
- GPIO1D0_EMMC_DATA6 |
- GPIO1D1_EMMC_DATA7 |
- GPIO1D2_EMMC_CMD |
- GPIO1D3_EMMC_PWREN);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A3_MASK | GPIO2A4_MASK,
- GPIO2A3_EMMC_RSTNOUT |
- GPIO2A4_EMMC_CLKOUT);
- break;
- case PERIPH_ID_SDCARD:
- debug("mmc id = %d setting registers!\n", mmc_id);
- rk_clrsetreg(&grf->gpio2a_iomux,
- GPIO2A5_MASK | GPIO2A7_MASK |
- GPIO2A7_MASK,
- GPIO2A5_SDMMC0_D0 | GPIO2A6_SDMMC0_D1 |
- GPIO2A7_SDMMC0_D2);
- rk_clrsetreg(&grf->gpio2b_iomux,
- GPIO2B0_MASK | GPIO2B1_MASK |
- GPIO2B2_MASK | GPIO2B3_MASK,
- GPIO2B0_SDMMC0_D3 | GPIO2B1_SDMMC0_CLKOUT |
- GPIO2B2_SDMMC0_CMD | GPIO2B3_SDMMC0_DTECTN);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-static int rk3368_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%d, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3368_uart_config(priv, func);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- pinctrl_rk3368_spi_config(priv, func);
- break;
- case PERIPH_ID_EMMC:
- case PERIPH_ID_SDCARD:
- pinctrl_rk3368_sdmmc_config(priv->grf, func);
- break;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
- pinctrl_rk3368_gmac_config(priv->grf, func);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3368_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 59:
- return PERIPH_ID_UART4;
- case 58:
- return PERIPH_ID_UART3;
- case 57:
- return PERIPH_ID_UART2;
- case 56:
- return PERIPH_ID_UART1;
- case 55:
- return PERIPH_ID_UART0;
- case 44:
- return PERIPH_ID_SPI0;
- case 45:
- return PERIPH_ID_SPI1;
- case 41:
- return PERIPH_ID_SPI2;
- case 35:
- return PERIPH_ID_EMMC;
- case 32:
- return PERIPH_ID_SDCARD;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 27:
- return PERIPH_ID_GMAC;
-#endif
- }
-
- return -ENOENT;
-}
-
-static int rk3368_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3368_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
-
- return rk3368_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3368_pinctrl_ops = {
- .set_state_simple = rk3368_pinctrl_set_state_simple,
- .request = rk3368_pinctrl_request,
- .get_periph_id = rk3368_pinctrl_get_periph_id,
-};
-
-static int rk3368_pinctrl_probe(struct udevice *dev)
-{
- struct rk3368_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
-
- debug("%s: grf=%p pmugrf:%p\n", __func__, priv->grf, priv->pmugrf);
-
- return ret;
-}
-
-static const struct udevice_id rk3368_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3368-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3368) = {
- .name = "rockchip_rk3368_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3368_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3368_pinctrl_priv),
- .ops = &rk3368_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rk3368_pinctrl_probe,
-};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c
deleted file mode 100644
index 19a7415..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/grf_rk3399.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/clock.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rk3399_pinctrl_priv {
- struct rk3399_grf_regs *grf;
- struct rk3399_pmugrf_regs *pmugrf;
-};
-
-static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs *grf,
- struct rk3399_pmugrf_regs *pmugrf, int pwm_id)
-{
- switch (pwm_id) {
- case PERIPH_ID_PWM0:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C2_SEL_MASK,
- GRF_PWM_0 << GRF_GPIO4C2_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM1:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C6_SEL_MASK,
- GRF_PWM_1 << GRF_GPIO4C6_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM2:
- rk_clrsetreg(&pmugrf->gpio1c_iomux,
- PMUGRF_GPIO1C3_SEL_MASK,
- PMUGRF_PWM_2 << PMUGRF_GPIO1C3_SEL_SHIFT);
- break;
- case PERIPH_ID_PWM3:
- if (readl(&pmugrf->soc_con0) & (1 << 5))
- rk_clrsetreg(&pmugrf->gpio1b_iomux,
- PMUGRF_GPIO1B6_SEL_MASK,
- PMUGRF_PWM_3B << PMUGRF_GPIO1B6_SEL_SHIFT);
- else
- rk_clrsetreg(&pmugrf->gpio0a_iomux,
- PMUGRF_GPIO0A6_SEL_MASK,
- PMUGRF_PWM_3A << PMUGRF_GPIO0A6_SEL_SHIFT);
- break;
- default:
- debug("pwm id = %d iomux error!\n", pwm_id);
- break;
- }
-}
-
-static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs *grf,
- struct rk3399_pmugrf_regs *pmugrf,
- int i2c_id)
-{
- switch (i2c_id) {
- case PERIPH_ID_I2C0:
- rk_clrsetreg(&pmugrf->gpio1b_iomux,
- PMUGRF_GPIO1B7_SEL_MASK,
- PMUGRF_I2C0PMU_SDA << PMUGRF_GPIO1B7_SEL_SHIFT);
- rk_clrsetreg(&pmugrf->gpio1c_iomux,
- PMUGRF_GPIO1C0_SEL_MASK,
- PMUGRF_I2C0PMU_SCL << PMUGRF_GPIO1C0_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C8:
- rk_clrsetreg(&pmugrf->gpio1c_iomux,
- PMUGRF_GPIO1C4_SEL_MASK,
- PMUGRF_I2C8PMU_SDA << PMUGRF_GPIO1C4_SEL_SHIFT);
- rk_clrsetreg(&pmugrf->gpio1c_iomux,
- PMUGRF_GPIO1C5_SEL_MASK,
- PMUGRF_I2C8PMU_SCL << PMUGRF_GPIO1C5_SEL_SHIFT);
- break;
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- default:
- debug("i2c id = %d iomux error!\n", i2c_id);
- break;
- }
-}
-
-static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs *grf, int lcd_id)
-{
- switch (lcd_id) {
- case PERIPH_ID_LCDC0:
- break;
- default:
- debug("lcdc id = %d iomux error!\n", lcd_id);
- break;
- }
-}
-
-static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
- struct rk3399_pmugrf_regs *pmugrf,
- enum periph_id spi_id, int cs)
-{
- switch (spi_id) {
- case PERIPH_ID_SPI0:
- switch (cs) {
- case 0:
- rk_clrsetreg(&grf->gpio3a_iomux,
- GRF_GPIO3A7_SEL_MASK,
- GRF_SPI0NORCODEC_CSN0
- << GRF_GPIO3A7_SEL_SHIFT);
- break;
- case 1:
- rk_clrsetreg(&grf->gpio3b_iomux,
- GRF_GPIO3B0_SEL_MASK,
- GRF_SPI0NORCODEC_CSN1
- << GRF_GPIO3B0_SEL_SHIFT);
- break;
- default:
- goto err;
- }
- rk_clrsetreg(&grf->gpio3a_iomux,
- GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_SHIFT
- | GRF_GPIO3A6_SEL_SHIFT,
- GRF_SPI0NORCODEC_RXD << GRF_GPIO3A4_SEL_SHIFT
- | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A5_SEL_SHIFT
- | GRF_SPI0NORCODEC_RXD << GRF_GPIO3A6_SEL_SHIFT);
- break;
- case PERIPH_ID_SPI1:
- if (cs != 0)
- goto err;
- rk_clrsetreg(&pmugrf->gpio1a_iomux,
- PMUGRF_GPIO1A7_SEL_MASK,
- PMUGRF_SPI1EC_RXD << PMUGRF_GPIO1A7_SEL_SHIFT);
- rk_clrsetreg(&pmugrf->gpio1b_iomux,
- PMUGRF_GPIO1B0_SEL_MASK | PMUGRF_GPIO1B1_SEL_MASK
- | PMUGRF_GPIO1B2_SEL_MASK,
- PMUGRF_SPI1EC_TXD << PMUGRF_GPIO1B0_SEL_SHIFT
- | PMUGRF_SPI1EC_CLK << PMUGRF_GPIO1B1_SEL_SHIFT
- | PMUGRF_SPI1EC_CSN0 << PMUGRF_GPIO1B2_SEL_SHIFT);
- break;
- case PERIPH_ID_SPI2:
- if (cs != 0)
- goto err;
- rk_clrsetreg(&grf->gpio2b_iomux,
- GRF_GPIO2B1_SEL_MASK | GRF_GPIO2B2_SEL_MASK
- | GRF_GPIO2B3_SEL_MASK | GRF_GPIO2B4_SEL_MASK,
- GRF_SPI2TPM_RXD << GRF_GPIO2B1_SEL_SHIFT
- | GRF_SPI2TPM_TXD << GRF_GPIO2B2_SEL_SHIFT
- | GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
- | GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
- break;
- case PERIPH_ID_SPI5:
- if (cs != 0)
- goto err;
- rk_clrsetreg(&grf->gpio2c_iomux,
- GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
- | GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
- GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
- | GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
- | GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
- | GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
- break;
- default:
- printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
- goto err;
- }
-
- return 0;
-err:
- debug("rkspi: periph%d cs=%d not supported", spi_id, cs);
- return -ENOENT;
-}
-
-static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs *grf,
- struct rk3399_pmugrf_regs *pmugrf,
- int uart_id)
-{
- switch (uart_id) {
- case PERIPH_ID_UART2:
- /* Using channel-C by default */
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C3_SEL_MASK,
- GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C4_SEL_MASK,
- GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- default:
- debug("uart id = %d iomux error!\n", uart_id);
- break;
- }
-}
-
-static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id)
-{
- switch (mmc_id) {
- case PERIPH_ID_EMMC:
- break;
- case PERIPH_ID_SDCARD:
- rk_clrsetreg(&grf->gpio4b_iomux,
- GRF_GPIO4B0_SEL_MASK | GRF_GPIO4B1_SEL_MASK
- | GRF_GPIO4B2_SEL_MASK | GRF_GPIO4B3_SEL_MASK
- | GRF_GPIO4B4_SEL_MASK | GRF_GPIO4B5_SEL_MASK,
- GRF_SDMMC_DATA0 << GRF_GPIO4B0_SEL_SHIFT
- | GRF_SDMMC_DATA1 << GRF_GPIO4B1_SEL_SHIFT
- | GRF_SDMMC_DATA2 << GRF_GPIO4B2_SEL_SHIFT
- | GRF_SDMMC_DATA3 << GRF_GPIO4B3_SEL_SHIFT
- | GRF_SDMMC_CLKOUT << GRF_GPIO4B4_SEL_SHIFT
- | GRF_SDMMC_CMD << GRF_GPIO4B5_SEL_SHIFT);
- break;
- default:
- debug("mmc id = %d iomux error!\n", mmc_id);
- break;
- }
-}
-
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
-static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
-{
- rk_clrsetreg(&grf->gpio3a_iomux,
- GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK |
- GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK |
- GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK |
- GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK,
- GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT |
- GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT |
- GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT |
- GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT |
- GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT |
- GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT |
- GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT |
- GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio3b_iomux,
- GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK |
- GRF_GPIO3B3_SEL_MASK |
- GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK |
- GRF_GPIO3B6_SEL_MASK,
- GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT |
- GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT |
- GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT |
- GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT |
- GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT |
- GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT);
- rk_clrsetreg(&grf->gpio3c_iomux,
- GRF_GPIO3C1_SEL_MASK,
- GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
-
- /* Set drive strength for GMAC tx io, value 3 means 13mA */
- rk_clrsetreg(&grf->gpio3_e[0],
- GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
- GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
- 3 << GRF_GPIO3A0_E_SHIFT |
- 3 << GRF_GPIO3A1_E_SHIFT |
- 3 << GRF_GPIO3A4_E_SHIFT |
- 1 << GRF_GPIO3A5_E0_SHIFT);
- rk_clrsetreg(&grf->gpio3_e[1],
- GRF_GPIO3A5_E12_MASK,
- 1 << GRF_GPIO3A5_E12_SHIFT);
- rk_clrsetreg(&grf->gpio3_e[2],
- GRF_GPIO3B4_E_MASK,
- 3 << GRF_GPIO3B4_E_SHIFT);
- rk_clrsetreg(&grf->gpio3_e[4],
- GRF_GPIO3C1_E_MASK,
- 3 << GRF_GPIO3C1_E_SHIFT);
-}
-#endif
-
-#if !defined(CONFIG_SPL_BUILD)
-static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id)
-{
- switch (hdmi_id) {
- case PERIPH_ID_HDMI:
- rk_clrsetreg(&grf->gpio4c_iomux,
- GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK,
- (GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) |
- (GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT));
- break;
- default:
- debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id);
- break;
- }
-}
-#endif
-
-static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
-
- debug("%s: func=%x, flags=%x\n", __func__, func, flags);
- switch (func) {
- case PERIPH_ID_PWM0:
- case PERIPH_ID_PWM1:
- case PERIPH_ID_PWM2:
- case PERIPH_ID_PWM3:
- case PERIPH_ID_PWM4:
- pinctrl_rk3399_pwm_config(priv->grf, priv->pmugrf, func);
- break;
- case PERIPH_ID_I2C0:
- case PERIPH_ID_I2C1:
- case PERIPH_ID_I2C2:
- case PERIPH_ID_I2C3:
- case PERIPH_ID_I2C4:
- case PERIPH_ID_I2C5:
- case PERIPH_ID_I2C6:
- case PERIPH_ID_I2C7:
- case PERIPH_ID_I2C8:
- pinctrl_rk3399_i2c_config(priv->grf, priv->pmugrf, func);
- break;
- case PERIPH_ID_SPI0:
- case PERIPH_ID_SPI1:
- case PERIPH_ID_SPI2:
- case PERIPH_ID_SPI3:
- case PERIPH_ID_SPI4:
- case PERIPH_ID_SPI5:
- pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
- break;
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- case PERIPH_ID_UART3:
- case PERIPH_ID_UART4:
- pinctrl_rk3399_uart_config(priv->grf, priv->pmugrf, func);
- break;
- case PERIPH_ID_LCDC0:
- case PERIPH_ID_LCDC1:
- pinctrl_rk3399_lcdc_config(priv->grf, func);
- break;
- case PERIPH_ID_SDMMC0:
- case PERIPH_ID_SDMMC1:
- pinctrl_rk3399_sdmmc_config(priv->grf, func);
- break;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case PERIPH_ID_GMAC:
- pinctrl_rk3399_gmac_config(priv->grf, func);
- break;
-#endif
-#if !defined(CONFIG_SPL_BUILD)
- case PERIPH_ID_HDMI:
- pinctrl_rk3399_hdmi_config(priv->grf, func);
- break;
-#endif
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 68:
- return PERIPH_ID_SPI0;
- case 53:
- return PERIPH_ID_SPI1;
- case 52:
- return PERIPH_ID_SPI2;
- case 132:
- return PERIPH_ID_SPI5;
- case 57:
- return PERIPH_ID_I2C0;
- case 59: /* Note strange order */
- return PERIPH_ID_I2C1;
- case 35:
- return PERIPH_ID_I2C2;
- case 34:
- return PERIPH_ID_I2C3;
- case 56:
- return PERIPH_ID_I2C4;
- case 38:
- return PERIPH_ID_I2C5;
- case 37:
- return PERIPH_ID_I2C6;
- case 36:
- return PERIPH_ID_I2C7;
- case 58:
- return PERIPH_ID_I2C8;
- case 65:
- return PERIPH_ID_SDMMC1;
-#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
- case 12:
- return PERIPH_ID_GMAC;
-#endif
-#if !defined(CONFIG_SPL_BUILD)
- case 23:
- return PERIPH_ID_HDMI;
-#endif
- }
-#endif
- return -ENOENT;
-}
-
-static int rk3399_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rk3399_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
-
- return rk3399_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rk3399_pinctrl_ops = {
- .set_state_simple = rk3399_pinctrl_set_state_simple,
- .request = rk3399_pinctrl_request,
- .get_periph_id = rk3399_pinctrl_get_periph_id,
-};
-
-static int rk3399_pinctrl_probe(struct udevice *dev)
-{
- struct rk3399_pinctrl_priv *priv = dev_get_priv(dev);
- int ret = 0;
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
- debug("%s: grf=%p, pmugrf=%p\n", __func__, priv->grf, priv->pmugrf);
-
- return ret;
-}
-
-static const struct udevice_id rk3399_pinctrl_ids[] = {
- { .compatible = "rockchip,rk3399-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rk3399) = {
- .name = "rockchip_rk3399_pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = rk3399_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rk3399_pinctrl_priv),
- .ops = &rk3399_pinctrl_ops,
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
- .bind = dm_scan_fdt_dev,
-#endif
- .probe = rk3399_pinctrl_probe,
-};
diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c
deleted file mode 100644
index 035f01a..0000000
--- a/drivers/pinctrl/rockchip/pinctrl_rv1108.c
+++ /dev/null
@@ -1,582 +0,0 @@
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- * Author: Andy Yan <andy.yan@rock-chips.com>
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rv1108.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <dm/pinctrl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct rv1108_pinctrl_priv {
- struct rv1108_grf *grf;
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
- GPIO1B7_SHIFT = 14,
- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
- GPIO1B7_GPIO = 0,
- GPIO1B7_LCDC_D12,
- GPIO1B7_I2S_SDIO2_M0,
- GPIO1B7_GMAC_RXDV,
-
- GPIO1B6_SHIFT = 12,
- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
- GPIO1B6_GPIO = 0,
- GPIO1B6_LCDC_D13,
- GPIO1B6_I2S_LRCLKTX_M0,
- GPIO1B6_GMAC_RXD1,
-
- GPIO1B5_SHIFT = 10,
- GPIO1B5_MASK = 3 << GPIO1B5_SHIFT,
- GPIO1B5_GPIO = 0,
- GPIO1B5_LCDC_D14,
- GPIO1B5_I2S_SDIO1_M0,
- GPIO1B5_GMAC_RXD0,
-
- GPIO1B4_SHIFT = 8,
- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
- GPIO1B4_GPIO = 0,
- GPIO1B4_LCDC_D15,
- GPIO1B4_I2S_MCLK_M0,
- GPIO1B4_GMAC_TXEN,
-
- GPIO1B3_SHIFT = 6,
- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
- GPIO1B3_GPIO = 0,
- GPIO1B3_LCDC_D16,
- GPIO1B3_I2S_SCLK_M0,
- GPIO1B3_GMAC_TXD1,
-
- GPIO1B2_SHIFT = 4,
- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
- GPIO1B2_GPIO = 0,
- GPIO1B2_LCDC_D17,
- GPIO1B2_I2S_SDIO_M0,
- GPIO1B2_GMAC_TXD0,
-
- GPIO1B1_SHIFT = 2,
- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
- GPIO1B1_GPIO = 0,
- GPIO1B1_LCDC_D9,
- GPIO1B1_PWM7,
-
- GPIO1B0_SHIFT = 0,
- GPIO1B0_MASK = 3,
- GPIO1B0_GPIO = 0,
- GPIO1B0_LCDC_D8,
- GPIO1B0_PWM6,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
- GPIO1C7_SHIFT = 14,
- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
- GPIO1C7_GPIO = 0,
- GPIO1C7_CIF_D5,
- GPIO1C7_I2S_SDIO2_M1,
-
- GPIO1C6_SHIFT = 12,
- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
- GPIO1C6_GPIO = 0,
- GPIO1C6_CIF_D4,
- GPIO1C6_I2S_LRCLKTX_M1,
-
- GPIO1C5_SHIFT = 10,
- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
- GPIO1C5_GPIO = 0,
- GPIO1C5_LCDC_CLK,
- GPIO1C5_GMAC_CLK,
-
- GPIO1C4_SHIFT = 8,
- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
- GPIO1C4_GPIO = 0,
- GPIO1C4_LCDC_HSYNC,
- GPIO1C4_GMAC_MDC,
-
- GPIO1C3_SHIFT = 6,
- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
- GPIO1C3_GPIO = 0,
- GPIO1C3_LCDC_VSYNC,
- GPIO1C3_GMAC_MDIO,
-
- GPIO1C2_SHIFT = 4,
- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
- GPIO1C2_GPIO = 0,
- GPIO1C2_LCDC_EN,
- GPIO1C2_I2S_SDIO3_M0,
- GPIO1C2_GMAC_RXER,
-
- GPIO1C1_SHIFT = 2,
- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
- GPIO1C1_GPIO = 0,
- GPIO1C1_LCDC_D10,
- GPIO1C1_I2S_SDI_M0,
- GPIO1C1_PWM4,
-
- GPIO1C0_SHIFT = 0,
- GPIO1C0_MASK = 3,
- GPIO1C0_GPIO = 0,
- GPIO1C0_LCDC_D11,
- GPIO1C0_I2S_LRCLKRX_M0,
-};
-
-/* GRF_GPIO1D_OIMUX */
-enum {
- GPIO1D7_SHIFT = 14,
- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
- GPIO1D7_GPIO = 0,
- GPIO1D7_HDMI_CEC,
- GPIO1D7_DSP_RTCK,
-
- GPIO1D6_SHIFT = 12,
- GPIO1D6_MASK = 1 << GPIO1D6_SHIFT,
- GPIO1D6_GPIO = 0,
- GPIO1D6_HDMI_HPD_M0,
-
- GPIO1D5_SHIFT = 10,
- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
- GPIO1D5_GPIO = 0,
- GPIO1D5_UART2_RTSN,
- GPIO1D5_HDMI_SDA_M0,
-
- GPIO1D4_SHIFT = 8,
- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
- GPIO1D4_GPIO = 0,
- GPIO1D4_UART2_CTSN,
- GPIO1D4_HDMI_SCL_M0,
-
- GPIO1D3_SHIFT = 6,
- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
- GPIO1D3_GPIO = 0,
- GPIO1D3_UART0_SOUT,
- GPIO1D3_SPI_TXD_M0,
-
- GPIO1D2_SHIFT = 4,
- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
- GPIO1D2_GPIO = 0,
- GPIO1D2_UART0_SIN,
- GPIO1D2_SPI_RXD_M0,
- GPIO1D2_DSP_TDI,
-
- GPIO1D1_SHIFT = 2,
- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
- GPIO1D1_GPIO = 0,
- GPIO1D1_UART0_RTSN,
- GPIO1D1_SPI_CSN0_M0,
- GPIO1D1_DSP_TMS,
-
- GPIO1D0_SHIFT = 0,
- GPIO1D0_MASK = 3,
- GPIO1D0_GPIO = 0,
- GPIO1D0_UART0_CTSN,
- GPIO1D0_SPI_CLK_M0,
- GPIO1D0_DSP_TCK,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
- GPIO2A7_SHIFT = 14,
- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
- GPIO2A7_GPIO = 0,
- GPIO2A7_FLASH_D7,
- GPIO2A7_EMMC_D7,
-
- GPIO2A6_SHIFT = 12,
- GPIO2A6_MASK = 3 << GPIO2A6_SHIFT,
- GPIO2A6_GPIO = 0,
- GPIO2A6_FLASH_D6,
- GPIO2A6_EMMC_D6,
-
- GPIO2A5_SHIFT = 10,
- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
- GPIO2A5_GPIO = 0,
- GPIO2A5_FLASH_D5,
- GPIO2A5_EMMC_D5,
-
- GPIO2A4_SHIFT = 8,
- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
- GPIO2A4_GPIO = 0,
- GPIO2A4_FLASH_D4,
- GPIO2A4_EMMC_D4,
-
- GPIO2A3_SHIFT = 6,
- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
- GPIO2A3_GPIO = 0,
- GPIO2A3_FLASH_D3,
- GPIO2A3_EMMC_D3,
- GPIO2A3_SFC_HOLD_IO3,
-
- GPIO2A2_SHIFT = 4,
- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
- GPIO2A2_GPIO = 0,
- GPIO2A2_FLASH_D2,
- GPIO2A2_EMMC_D2,
- GPIO2A2_SFC_WP_IO2,
-
- GPIO2A1_SHIFT = 2,
- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
- GPIO2A1_GPIO = 0,
- GPIO2A1_FLASH_D1,
- GPIO2A1_EMMC_D1,
- GPIO2A1_SFC_SO_IO1,
-
- GPIO2A0_SHIFT = 0,
- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
- GPIO2A0_GPIO = 0,
- GPIO2A0_FLASH_D0,
- GPIO2A0_EMMC_D0,
- GPIO2A0_SFC_SI_IO0,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2B7_SHIFT = 14,
- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
- GPIO2B7_GPIO = 0,
- GPIO2B7_FLASH_CS1,
- GPIO2B7_SFC_CLK,
-
- GPIO2B6_SHIFT = 12,
- GPIO2B6_MASK = 1 << GPIO2B6_SHIFT,
- GPIO2B6_GPIO = 0,
- GPIO2B6_EMMC_CLKO,
-
- GPIO2B5_SHIFT = 10,
- GPIO2B5_MASK = 1 << GPIO2B5_SHIFT,
- GPIO2B5_GPIO = 0,
- GPIO2B5_FLASH_CS0,
-
- GPIO2B4_SHIFT = 8,
- GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
- GPIO2B4_GPIO = 0,
- GPIO2B4_FLASH_RDY,
- GPIO2B4_EMMC_CMD,
- GPIO2B4_SFC_CSN0,
-
- GPIO2B3_SHIFT = 6,
- GPIO2B3_MASK = 1 << GPIO2B3_SHIFT,
- GPIO2B3_GPIO = 0,
- GPIO2B3_FLASH_RDN,
-
- GPIO2B2_SHIFT = 4,
- GPIO2B2_MASK = 1 << GPIO2B2_SHIFT,
- GPIO2B2_GPIO = 0,
- GPIO2B2_FLASH_WRN,
-
- GPIO2B1_SHIFT = 2,
- GPIO2B1_MASK = 1 << GPIO2B1_SHIFT,
- GPIO2B1_GPIO = 0,
- GPIO2B1_FLASH_CLE,
-
- GPIO2B0_SHIFT = 0,
- GPIO2B0_MASK = 1 << GPIO2B0_SHIFT,
- GPIO2B0_GPIO = 0,
- GPIO2B0_FLASH_ALE,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
- GPIO2D7_SHIFT = 14,
- GPIO2D7_MASK = 1 << GPIO2D7_SHIFT,
- GPIO2D7_GPIO = 0,
- GPIO2D7_SDIO_D0,
-
- GPIO2D6_SHIFT = 12,
- GPIO2D6_MASK = 1 << GPIO2D6_SHIFT,
- GPIO2D6_GPIO = 0,
- GPIO2D6_SDIO_CMD,
-
- GPIO2D5_SHIFT = 10,
- GPIO2D5_MASK = 1 << GPIO2D5_SHIFT,
- GPIO2D5_GPIO = 0,
- GPIO2D5_SDIO_CLKO,
-
- GPIO2D4_SHIFT = 8,
- GPIO2D4_MASK = 1 << GPIO2D4_SHIFT,
- GPIO2D4_GPIO = 0,
- GPIO2D4_I2C1_SCL,
-
- GPIO2D3_SHIFT = 6,
- GPIO2D3_MASK = 1 << GPIO2D3_SHIFT,
- GPIO2D3_GPIO = 0,
- GPIO2D3_I2C1_SDA,
-
- GPIO2D2_SHIFT = 4,
- GPIO2D2_MASK = 3 << GPIO2D2_SHIFT,
- GPIO2D2_GPIO = 0,
- GPIO2D2_UART2_SOUT_M0,
- GPIO2D2_JTAG_TCK,
-
- GPIO2D1_SHIFT = 2,
- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
- GPIO2D1_GPIO = 0,
- GPIO2D1_UART2_SIN_M0,
- GPIO2D1_JTAG_TMS,
- GPIO2D1_DSP_TMS,
-
- GPIO2D0_SHIFT = 0,
- GPIO2D0_MASK = 3,
- GPIO2D0_GPIO = 0,
- GPIO2D0_UART0_CTSN,
- GPIO2D0_SPI_CLK_M0,
- GPIO2D0_DSP_TCK,
-};
-
-/* GRF_GPIO3A_IOMUX */
-enum {
- GPIO3A7_SHIFT = 14,
- GPIO3A7_MASK = 1 << GPIO3A7_SHIFT,
- GPIO3A7_GPIO = 0,
-
- GPIO3A6_SHIFT = 12,
- GPIO3A6_MASK = 1 << GPIO3A6_SHIFT,
- GPIO3A6_GPIO = 0,
- GPIO3A6_UART1_SOUT,
-
- GPIO3A5_SHIFT = 10,
- GPIO3A5_MASK = 1 << GPIO3A5_SHIFT,
- GPIO3A5_GPIO = 0,
- GPIO3A5_UART1_SIN,
-
- GPIO3A4_SHIFT = 8,
- GPIO3A4_MASK = 1 << GPIO3A4_SHIFT,
- GPIO3A4_GPIO = 0,
- GPIO3A4_UART1_CTSN,
-
- GPIO3A3_SHIFT = 6,
- GPIO3A3_MASK = 1 << GPIO3A3_SHIFT,
- GPIO3A3_GPIO = 0,
- GPIO3A3_UART1_RTSN,
-
- GPIO3A2_SHIFT = 4,
- GPIO3A2_MASK = 1 << GPIO3A2_SHIFT,
- GPIO3A2_GPIO = 0,
- GPIO3A2_SDIO_D3,
-
- GPIO3A1_SHIFT = 2,
- GPIO3A1_MASK = 1 << GPIO3A1_SHIFT,
- GPIO3A1_GPIO = 0,
- GPIO3A1_SDIO_D2,
-
- GPIO3A0_SHIFT = 0,
- GPIO3A0_MASK = 1,
- GPIO3A0_GPIO = 0,
- GPIO3A0_SDIO_D1,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
- GPIO3C7_SHIFT = 14,
- GPIO3C7_MASK = 1 << GPIO3C7_SHIFT,
- GPIO3C7_GPIO = 0,
- GPIO3C7_CIF_CLKI,
-
- GPIO3C6_SHIFT = 12,
- GPIO3C6_MASK = 1 << GPIO3C6_SHIFT,
- GPIO3C6_GPIO = 0,
- GPIO3C6_CIF_VSYNC,
-
- GPIO3C5_SHIFT = 10,
- GPIO3C5_MASK = 1 << GPIO3C5_SHIFT,
- GPIO3C5_GPIO = 0,
- GPIO3C5_SDMMC_CMD,
-
- GPIO3C4_SHIFT = 8,
- GPIO3C4_MASK = 1 << GPIO3C4_SHIFT,
- GPIO3C4_GPIO = 0,
- GPIO3C4_SDMMC_CLKO,
-
- GPIO3C3_SHIFT = 6,
- GPIO3C3_MASK = 3 << GPIO3C3_SHIFT,
- GPIO3C3_GPIO = 0,
- GPIO3C3_SDMMC_D0,
- GPIO3C3_UART2_SOUT_M1,
-
- GPIO3C2_SHIFT = 4,
- GPIO3C2_MASK = 3 << GPIO3C2_SHIFT,
- GPIO3C2_GPIO = 0,
- GPIO3C2_SDMMC_D1,
- GPIO3C2_UART2_SIN_M1,
-
- GPIOC1_SHIFT = 2,
- GPIOC1_MASK = 1 << GPIOC1_SHIFT,
- GPIOC1_GPIO = 0,
- GPIOC1_SDMMC_D2,
-
- GPIOC0_SHIFT = 0,
- GPIOC0_MASK = 1,
- GPIO3C0_GPIO = 0,
- GPIO3C0_SDMMC_D3,
-};
-
-static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id)
-{
- switch (uart_id) {
- case PERIPH_ID_UART0:
- rk_clrsetreg(&grf->gpio3a_iomux,
- GPIO3A6_MASK | GPIO3A5_MASK,
- GPIO3A6_UART1_SOUT << GPIO3A6_SHIFT |
- GPIO3A5_UART1_SIN << GPIO3A5_SHIFT);
- break;
- case PERIPH_ID_UART1:
- rk_clrsetreg(&grf->gpio1d_iomux,
- GPIO1D3_MASK | GPIO1D2_MASK | GPIO1D1_MASK |
- GPIO1D0_MASK,
- GPIO1D3_UART0_SOUT << GPIO1D3_SHIFT |
- GPIO1D2_UART0_SIN << GPIO1D2_SHIFT |
- GPIO1D1_UART0_RTSN << GPIO1D1_SHIFT |
- GPIO1D0_UART0_CTSN << GPIO1D0_SHIFT);
- break;
- case PERIPH_ID_UART2:
- rk_clrsetreg(&grf->gpio2d_iomux,
- GPIO2D2_MASK | GPIO2D1_MASK,
- GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT |
- GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT);
- break;
- }
-}
-
-static void pinctrl_rv1108_gmac_config(struct rv1108_grf *grf, int func)
-{
- rk_clrsetreg(&grf->gpio1b_iomux,
- GPIO1B7_MASK | GPIO1B6_MASK | GPIO1B5_MASK |
- GPIO1B4_MASK | GPIO1B3_MASK | GPIO1B2_MASK,
- GPIO1B7_GMAC_RXDV << GPIO1B7_SHIFT |
- GPIO1B6_GMAC_RXD1 << GPIO1B6_SHIFT |
- GPIO1B5_GMAC_RXD0 << GPIO1B5_SHIFT |
- GPIO1B4_GMAC_TXEN << GPIO1B4_SHIFT |
- GPIO1B3_GMAC_TXD1 << GPIO1B3_SHIFT |
- GPIO1B2_GMAC_TXD0 << GPIO1B2_SHIFT);
- rk_clrsetreg(&grf->gpio1c_iomux,
- GPIO1C5_MASK | GPIO1C4_MASK |
- GPIO1C3_MASK | GPIO1C2_MASK,
- GPIO1C5_GMAC_CLK << GPIO1C5_SHIFT |
- GPIO1C4_GMAC_MDC << GPIO1C4_SHIFT |
- GPIO1C3_GMAC_MDIO << GPIO1C3_SHIFT |
- GPIO1C2_GMAC_RXER << GPIO1C2_SHIFT);
- writel(0xffff57f5, &grf->gpio1b_drv);
-}
-
-static void pinctrl_rv1108_sfc_config(struct rv1108_grf *grf)
-{
- rk_clrsetreg(&grf->gpio2a_iomux, GPIO2A3_MASK | GPIO2A2_MASK |
- GPIO2A1_MASK | GPIO2A0_MASK,
- GPIO2A3_SFC_HOLD_IO3 << GPIO2A3_SHIFT |
- GPIO2A2_SFC_WP_IO2 << GPIO2A2_SHIFT |
- GPIO2A1_SFC_SO_IO1 << GPIO2A1_SHIFT |
- GPIO2A0_SFC_SI_IO0 << GPIO2A0_SHIFT);
- rk_clrsetreg(&grf->gpio2b_iomux, GPIO2B7_MASK | GPIO2B4_MASK,
- GPIO2B7_SFC_CLK << GPIO2B7_SHIFT |
- GPIO2B4_SFC_CSN0 << GPIO2B4_SHIFT);
-}
-
-static int rv1108_pinctrl_request(struct udevice *dev, int func, int flags)
-{
- struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
-
- switch (func) {
- case PERIPH_ID_UART0:
- case PERIPH_ID_UART1:
- case PERIPH_ID_UART2:
- pinctrl_rv1108_uart_config(priv->grf, func);
- break;
- case PERIPH_ID_GMAC:
- pinctrl_rv1108_gmac_config(priv->grf, func);
- case PERIPH_ID_SFC:
- pinctrl_rv1108_sfc_config(priv->grf);
- default:
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int rv1108_pinctrl_get_periph_id(struct udevice *dev,
- struct udevice *periph)
-{
- u32 cell[3];
- int ret;
-
- ret = dev_read_u32_array(periph, "interrupts", cell, ARRAY_SIZE(cell));
- if (ret < 0)
- return -EINVAL;
-
- switch (cell[1]) {
- case 11:
- return PERIPH_ID_SDCARD;
- case 13:
- return PERIPH_ID_EMMC;
- case 19:
- return PERIPH_ID_GMAC;
- case 30:
- return PERIPH_ID_I2C0;
- case 31:
- return PERIPH_ID_I2C1;
- case 32:
- return PERIPH_ID_I2C2;
- case 39:
- return PERIPH_ID_PWM0;
- case 44:
- return PERIPH_ID_UART0;
- case 45:
- return PERIPH_ID_UART1;
- case 46:
- return PERIPH_ID_UART2;
- case 56:
- return PERIPH_ID_SFC;
- }
-
- return -ENOENT;
-}
-
-static int rv1108_pinctrl_set_state_simple(struct udevice *dev,
- struct udevice *periph)
-{
- int func;
-
- func = rv1108_pinctrl_get_periph_id(dev, periph);
- if (func < 0)
- return func;
-
- return rv1108_pinctrl_request(dev, func, 0);
-}
-
-static struct pinctrl_ops rv1108_pinctrl_ops = {
- .set_state_simple = rv1108_pinctrl_set_state_simple,
- .request = rv1108_pinctrl_request,
- .get_periph_id = rv1108_pinctrl_get_periph_id,
-};
-
-static int rv1108_pinctrl_probe(struct udevice *dev)
-{
- struct rv1108_pinctrl_priv *priv = dev_get_priv(dev);
-
- priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
-
- return 0;
-}
-
-static const struct udevice_id rv1108_pinctrl_ids[] = {
- {.compatible = "rockchip,rv1108-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(pinctrl_rv1108) = {
- .name = "pinctrl_rv1108",
- .id = UCLASS_PINCTRL,
- .of_match = rv1108_pinctrl_ids,
- .priv_auto_alloc_size = sizeof(struct rv1108_pinctrl_priv),
- .ops = &rv1108_pinctrl_ops,
- .bind = dm_scan_fdt_dev,
- .probe = rv1108_pinctrl_probe,
-};
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
` (7 preceding siblings ...)
2018-02-03 6:57 ` [U-Boot] [PATCH 8/9] pinctrl: rockchip: Clean the unused rockchip pinctrl drivers David Wu
@ 2018-02-03 6:57 ` David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
8 siblings, 2 replies; 31+ messages in thread
From: David Wu @ 2018-02-03 6:57 UTC (permalink / raw)
To: u-boot
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.
Signed-off-by: David Wu <david.wu@rock-chips.com>
---
arch/arm/dts/rk322x.dtsi | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 22324f9..023ced6 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -207,7 +207,7 @@
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
pinctrl-names = "default";
- pinctrl-0 = <&uart2_xfer>;
+ pinctrl-0 = <&uart21_xfer>;
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@@ -749,7 +749,7 @@
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+ rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>,
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
};
@@ -761,6 +761,13 @@
rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
};
};
+
+ uart2-1 {
+ uart21_xfer: uart21-xfer {
+ rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
+ <1 9 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
};
dmc: dmc at 11200000 {
--
2.7.4
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
2018-02-03 6:56 ` [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip " David Wu
@ 2018-02-04 7:45 ` Kever Yang
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-18 19:20 ` Philipp Tomsich
2 siblings, 0 replies; 31+ messages in thread
From: Kever Yang @ 2018-02-04 7:45 UTC (permalink / raw)
To: u-boot
Hi David,
On 02/03/2018 02:56 PM, David Wu wrote:
> Use this driver to fit all Rockchip SOCs and to support
> the desired pinctrl configuration via DTS.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
>
> drivers/pinctrl/Kconfig | 98 +-
> drivers/pinctrl/Makefile | 2 +-
> drivers/pinctrl/pinctrl-rockchip.c | 2440 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 2454 insertions(+), 86 deletions(-)
> create mode 100644 drivers/pinctrl/pinctrl-rockchip.c
>
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 7e8e4b0..6177e7c 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -158,95 +158,23 @@ config PINCTRL_QCA953X
> the GPIO definitions and pin control functions for each available
> multiplex function.
>
> -config PINCTRL_ROCKCHIP_RK3036
> - bool "Rockchip rk3036 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3036 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3128
> - bool "Rockchip rk3128 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3128 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3188
> - bool "Rockchip rk3188 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3188 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK322X
> - bool "Rockchip rk322x pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk322x SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3288
> - bool "Rockchip rk3288 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3288 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3328
> - bool "Rockchip rk3328 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3328 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3368
> - bool "Rockchip RK3368 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3368 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3399
> - bool "Rockchip rk3399 pin control driver"
> - depends on DM
> +config PINCTRL_ROCKCHIP
> + bool "Rockchip pin control driver"
> + depends on PINCTRL_FULL
> + default y
> help
> - Support pin multiplexing control on Rockchip rk3399 SoCs.
> + Support pin multiplexing control on Rockchip SoCs.
>
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> + The driver is controlled by a device tree node which contains pin
> + control functions for each available multiplex function.
>
> -config PINCTRL_ROCKCHIP_RV1108
> - bool "Rockchip rv1108 pin control driver"
> - depends on DM
> +config SPL_PINCTRL_ROCKCHIP
> + bool "Support Rockchip pin controllers in SPL"
> + depends on SPL_PINCTRL_FULL
> + default y
> help
> - Support pin multiplexing control on Rockchip rv1108 SoC.
> -
> - The driver is controlled by a device tree node which contains
> - both the GPIO definitions and pin control functions for each
> - available multiplex function.
> + This option is an SPL-variant of the PINCTRL_ROCKCHIP option.
> + See the help of PINCTRL_ROCKCHIP for details.
>
> config PINCTRL_SANDBOX
> bool "Sandbox pinctrl driver"
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index 8c04028..2429eb9 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -11,7 +11,7 @@ obj-y += nxp/
> obj-$(CONFIG_ARCH_ASPEED) += aspeed/
> obj-$(CONFIG_ARCH_ATH79) += ath79/
> obj-$(CONFIG_ARCH_RMOBILE) += renesas/
> -obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> +obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
> obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
>
> obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> new file mode 100644
> index 0000000..68bf30d
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -0,0 +1,2440 @@
> +/*
> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +
> +#define MAX_ROCKCHIP_GPIO_PER_BANK 32
> +#define RK_FUNC_GPIO 0
> +#define MAX_ROCKCHIP_PINS_ENTRIES 20
> +
> +enum rockchip_pinctrl_type {
> + PX30,
> + RV1108,
> + RK2928,
> + RK3066B,
> + RK3128,
> + RK3188,
> + RK3288,
> + RK3368,
> + RK3399,
> +};
> +
> +/**
> + * Encode variants of iomux registers into a type variable
> + */
> +#define IOMUX_GPIO_ONLY BIT(0)
> +#define IOMUX_WIDTH_4BIT BIT(1)
> +#define IOMUX_SOURCE_PMU BIT(2)
> +#define IOMUX_UNROUTED BIT(3)
> +#define IOMUX_WIDTH_3BIT BIT(4)
> +
> +/**
> + * @type: iomux variant using IOMUX_* constants
> + * @offset: if initialized to -1 it will be autocalculated, by specifying
> + * an initial offset value the relevant source offset can be reset
> + * to a new value for autocalculating the following iomux registers.
> + */
> +struct rockchip_iomux {
> + int type;
> + int offset;
> +};
> +
> +/**
> + * enum type index corresponding to rockchip_perpin_drv_list arrays index.
> + */
> +enum rockchip_pin_drv_type {
> + DRV_TYPE_IO_DEFAULT = 0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_ONLY,
> + DRV_TYPE_IO_1V8_3V0_AUTO,
> + DRV_TYPE_IO_3V3_ONLY,
> + DRV_TYPE_MAX
> +};
> +
> +/**
> + * enum type index corresponding to rockchip_pull_list arrays index.
> + */
> +enum rockchip_pin_pull_type {
> + PULL_TYPE_IO_DEFAULT = 0,
> + PULL_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_MAX
> +};
> +
> +/**
> + * @drv_type: drive strength variant using rockchip_perpin_drv_type
> + * @offset: if initialized to -1 it will be autocalculated, by specifying
> + * an initial offset value the relevant source offset can be reset
> + * to a new value for autocalculating the following drive strength
> + * registers. if used chips own cal_drv func instead to calculate
> + * registers offset, the variant could be ignored.
> + */
> +struct rockchip_drv {
> + enum rockchip_pin_drv_type drv_type;
> + int offset;
> +};
> +
> +/**
> + * @priv: common pinctrl private basedata
> + * @pin_base: first pin number
> + * @nr_pins: number of pins in this bank
> + * @name: name of the bank
> + * @bank_num: number of the bank, to account for holes
> + * @iomux: array describing the 4 iomux sources of the bank
> + * @drv: array describing the 4 drive strength sources of the bank
> + * @pull_type: array describing the 4 pull type sources of the bank
> + * @recalced_mask: bits describing the mux recalced pins of per bank
> + * @route_mask: bits describing the routing pins of per bank
> + */
> +struct rockchip_pin_bank {
> + struct rockchip_pinctrl_priv *priv;
> + u32 pin_base;
> + u8 nr_pins;
> + char *name;
> + u8 bank_num;
> + struct rockchip_iomux iomux[4];
> + struct rockchip_drv drv[4];
> + enum rockchip_pin_pull_type pull_type[4];
> + u32 recalced_mask;
> + u32 route_mask;
> +};
> +
> +#define PIN_BANK(id, pins, label) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + }, \
> + }
> +
> +#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .type = iom0, .offset = -1 }, \
> + { .type = iom1, .offset = -1 }, \
> + { .type = iom2, .offset = -1 }, \
> + { .type = iom3, .offset = -1 }, \
> + }, \
> + }
> +
> +#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + }, \
> + .drv = { \
> + { .drv_type = type0, .offset = -1 }, \
> + { .drv_type = type1, .offset = -1 }, \
> + { .drv_type = type2, .offset = -1 }, \
> + { .drv_type = type3, .offset = -1 }, \
> + }, \
> + }
> +
> +#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
> + drv2, drv3, pull0, pull1, \
> + pull2, pull3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + }, \
> + .drv = { \
> + { .drv_type = drv0, .offset = -1 }, \
> + { .drv_type = drv1, .offset = -1 }, \
> + { .drv_type = drv2, .offset = -1 }, \
> + { .drv_type = drv3, .offset = -1 }, \
> + }, \
> + .pull_type[0] = pull0, \
> + .pull_type[1] = pull1, \
> + .pull_type[2] = pull2, \
> + .pull_type[3] = pull3, \
> + }
> +
> +#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
> + iom2, iom3, drv0, drv1, drv2, \
> + drv3, offset0, offset1, \
> + offset2, offset3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .type = iom0, .offset = -1 }, \
> + { .type = iom1, .offset = -1 }, \
> + { .type = iom2, .offset = -1 }, \
> + { .type = iom3, .offset = -1 }, \
> + }, \
> + .drv = { \
> + { .drv_type = drv0, .offset = offset0 }, \
> + { .drv_type = drv1, .offset = offset1 }, \
> + { .drv_type = drv2, .offset = offset2 }, \
> + { .drv_type = drv3, .offset = offset3 }, \
> + }, \
> + }
> +
> +#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
> + label, iom0, iom1, iom2, \
> + iom3, drv0, drv1, drv2, \
> + drv3, offset0, offset1, \
> + offset2, offset3, pull0, \
> + pull1, pull2, pull3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .type = iom0, .offset = -1 }, \
> + { .type = iom1, .offset = -1 }, \
> + { .type = iom2, .offset = -1 }, \
> + { .type = iom3, .offset = -1 }, \
> + }, \
> + .drv = { \
> + { .drv_type = drv0, .offset = offset0 }, \
> + { .drv_type = drv1, .offset = offset1 }, \
> + { .drv_type = drv2, .offset = offset2 }, \
> + { .drv_type = drv3, .offset = offset3 }, \
> + }, \
> + .pull_type[0] = pull0, \
> + .pull_type[1] = pull1, \
> + .pull_type[2] = pull2, \
> + .pull_type[3] = pull3, \
> + }
> +
> +/**
> + * struct rockchip_mux_recalced_data: represent a pin iomux data.
> + * @num: bank number.
> + * @pin: pin number.
> + * @bit: index at register.
> + * @reg: register offset.
> + * @mask: mask bit
> + */
> +struct rockchip_mux_recalced_data {
> + u8 num;
> + u8 pin;
> + u32 reg;
> + u8 bit;
> + u8 mask;
> +};
> +
> +/**
> + * struct rockchip_mux_recalced_data: represent a pin iomux data.
> + * @bank_num: bank number.
> + * @pin: index at register or used to calc index.
> + * @func: the min pin.
> + * @route_offset: the max pin.
> + * @route_val: the register offset.
> + */
> +struct rockchip_mux_route_data {
> + u8 bank_num;
> + u8 pin;
> + u8 func;
> + u32 route_offset;
> + u32 route_val;
> +};
> +
> +/**
> + */
> +struct rockchip_pin_ctrl {
> + struct rockchip_pin_bank *pin_banks;
> + u32 nr_banks;
> + u32 nr_pins;
> + char *label;
> + enum rockchip_pinctrl_type type;
> + int grf_mux_offset;
> + int pmu_mux_offset;
> + int grf_drv_offset;
> + int pmu_drv_offset;
> + struct rockchip_mux_recalced_data *iomux_recalced;
> + u32 niomux_recalced;
> + struct rockchip_mux_route_data *iomux_routes;
> + u32 niomux_routes;
> +
> + void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit);
> + void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit);
> + int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit);
> +};
> +
> +/**
> + */
> +struct rockchip_pinctrl_priv {
> + struct rockchip_pin_ctrl *ctrl;
> + struct regmap *regmap_base;
> + struct regmap *regmap_pmu;
> +
> +};
> +
> +static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
> +{
> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> +
> + if (bank >= ctrl->nr_banks) {
> + debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
> + return -EINVAL;
> + }
> +
> + if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
> + debug("pin conf pin %d >= %d\n", pin,
> + MAX_ROCKCHIP_GPIO_PER_BANK);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
> + {
> + .num = 1,
> + .pin = 0,
> + .reg = 0x418,
> + .bit = 0,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 1,
> + .reg = 0x418,
> + .bit = 2,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 2,
> + .reg = 0x418,
> + .bit = 4,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 3,
> + .reg = 0x418,
> + .bit = 6,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 4,
> + .reg = 0x418,
> + .bit = 8,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 5,
> + .reg = 0x418,
> + .bit = 10,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 6,
> + .reg = 0x418,
> + .bit = 12,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 7,
> + .reg = 0x418,
> + .bit = 14,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 8,
> + .reg = 0x41c,
> + .bit = 0,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 9,
> + .reg = 0x41c,
> + .bit = 2,
> + .mask = 0x3
> + },
> +};
> +
> +static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
> + {
> + .num = 2,
> + .pin = 20,
> + .reg = 0xe8,
> + .bit = 0,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 21,
> + .reg = 0xe8,
> + .bit = 4,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 22,
> + .reg = 0xe8,
> + .bit = 8,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 23,
> + .reg = 0xe8,
> + .bit = 12,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 24,
> + .reg = 0xd4,
> + .bit = 12,
> + .mask = 0x7
> + },
> +};
> +
> +static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
> + {
> + .num = 2,
> + .pin = 12,
> + .reg = 0x24,
> + .bit = 8,
> + .mask = 0x3
> + }, {
> + .num = 2,
> + .pin = 15,
> + .reg = 0x28,
> + .bit = 0,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 23,
> + .reg = 0x30,
> + .bit = 14,
> + .mask = 0x3
> + },
> +};
> +
> +static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
> + int *reg, u8 *bit, int *mask)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct rockchip_mux_recalced_data *data;
> + int i;
> +
> + for (i = 0; i < ctrl->niomux_recalced; i++) {
> + data = &ctrl->iomux_recalced[i];
> + if (data->num == bank->bank_num &&
> + data->pin == pin)
> + break;
> + }
> +
> + if (i >= ctrl->niomux_recalced)
> + return;
> +
> + *reg = data->reg;
> + *mask = data->mask;
> + *bit = data->bit;
> +}
> +
> +static struct rockchip_mux_route_data px30_mux_route_data[] = {
> + {
> + /* cif-d2m0 */
> + .bank_num = 2,
> + .pin = 0,
> + .func = 1,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 7),
> + }, {
> + /* cif-d2m1 */
> + .bank_num = 3,
> + .pin = 3,
> + .func = 3,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 7) | BIT(7),
> + }, {
> + /* pdm-m0 */
> + .bank_num = 3,
> + .pin = 22,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 8),
> + }, {
> + /* pdm-m1 */
> + .bank_num = 2,
> + .pin = 22,
> + .func = 1,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 8) | BIT(8),
> + }, {
> + /* uart2-rxm0 */
> + .bank_num = 1,
> + .pin = 26,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 9),
> + }, {
> + /* uart2-rxm1 */
> + .bank_num = 2,
> + .pin = 14,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 9) | BIT(9),
> + }, {
> + /* uart3-rxm0 */
> + .bank_num = 0,
> + .pin = 17,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 10),
> + }, {
> + /* uart3-rxm1 */
> + .bank_num = 1,
> + .pin = 13,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 10) | BIT(10),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
> + {
> + /* spi-0 */
> + .bank_num = 1,
> + .pin = 10,
> + .func = 1,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 3) | BIT(16 + 4),
> + }, {
> + /* spi-1 */
> + .bank_num = 1,
> + .pin = 27,
> + .func = 3,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
> + }, {
> + /* spi-2 */
> + .bank_num = 0,
> + .pin = 13,
> + .func = 2,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
> + }, {
> + /* i2s-0 */
> + .bank_num = 1,
> + .pin = 5,
> + .func = 1,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 5),
> + }, {
> + /* i2s-1 */
> + .bank_num = 0,
> + .pin = 14,
> + .func = 1,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 5) | BIT(5),
> + }, {
> + /* emmc-0 */
> + .bank_num = 1,
> + .pin = 22,
> + .func = 2,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 6),
> + }, {
> + /* emmc-1 */
> + .bank_num = 2,
> + .pin = 4,
> + .func = 2,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 6) | BIT(6),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
> + {
> + /* pwm0-0 */
> + .bank_num = 0,
> + .pin = 26,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16),
> + }, {
> + /* pwm0-1 */
> + .bank_num = 3,
> + .pin = 21,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16) | BIT(0),
> + }, {
> + /* pwm1-0 */
> + .bank_num = 0,
> + .pin = 27,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 1),
> + }, {
> + /* pwm1-1 */
> + .bank_num = 0,
> + .pin = 30,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 1) | BIT(1),
> + }, {
> + /* pwm2-0 */
> + .bank_num = 0,
> + .pin = 28,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 2),
> + }, {
> + /* pwm2-1 */
> + .bank_num = 1,
> + .pin = 12,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 2) | BIT(2),
> + }, {
> + /* pwm3-0 */
> + .bank_num = 3,
> + .pin = 26,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 3),
> + }, {
> + /* pwm3-1 */
> + .bank_num = 1,
> + .pin = 11,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 3) | BIT(3),
> + }, {
> + /* sdio-0_d0 */
> + .bank_num = 1,
> + .pin = 1,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 4),
> + }, {
> + /* sdio-1_d0 */
> + .bank_num = 3,
> + .pin = 2,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 4) | BIT(4),
> + }, {
> + /* spi-0_rx */
> + .bank_num = 0,
> + .pin = 13,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 5),
> + }, {
> + /* spi-1_rx */
> + .bank_num = 2,
> + .pin = 0,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 5) | BIT(5),
> + }, {
> + /* emmc-0_cmd */
> + .bank_num = 1,
> + .pin = 22,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 7),
> + }, {
> + /* emmc-1_cmd */
> + .bank_num = 2,
> + .pin = 4,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 7) | BIT(7),
> + }, {
> + /* uart2-0_rx */
> + .bank_num = 1,
> + .pin = 19,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 8),
> + }, {
> + /* uart2-1_rx */
> + .bank_num = 1,
> + .pin = 10,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 8) | BIT(8),
> + }, {
> + /* uart1-0_rx */
> + .bank_num = 1,
> + .pin = 10,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 11),
> + }, {
> + /* uart1-1_rx */
> + .bank_num = 3,
> + .pin = 13,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 11) | BIT(11),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
> + {
> + /* edphdmi_cecinoutt1 */
> + .bank_num = 7,
> + .pin = 16,
> + .func = 2,
> + .route_offset = 0x264,
> + .route_val = BIT(16 + 12) | BIT(12),
> + }, {
> + /* edphdmi_cecinout */
> + .bank_num = 7,
> + .pin = 23,
> + .func = 4,
> + .route_offset = 0x264,
> + .route_val = BIT(16 + 12),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
> + {
> + /* uart2dbg_rxm0 */
> + .bank_num = 1,
> + .pin = 1,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16) | BIT(16 + 1),
> + }, {
> + /* uart2dbg_rxm1 */
> + .bank_num = 2,
> + .pin = 1,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
> + }, {
> + /* gmac-m1_rxd0 */
> + .bank_num = 1,
> + .pin = 11,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 2) | BIT(2),
> + }, {
> + /* gmac-m1-optimized_rxd3 */
> + .bank_num = 1,
> + .pin = 14,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 10) | BIT(10),
> + }, {
> + /* pdm_sdi0m0 */
> + .bank_num = 2,
> + .pin = 19,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 3),
> + }, {
> + /* pdm_sdi0m1 */
> + .bank_num = 1,
> + .pin = 23,
> + .func = 3,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 3) | BIT(3),
> + }, {
> + /* spi_rxdm2 */
> + .bank_num = 3,
> + .pin = 2,
> + .func = 4,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
> + }, {
> + /* i2s2_sdim0 */
> + .bank_num = 1,
> + .pin = 24,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 6),
> + }, {
> + /* i2s2_sdim1 */
> + .bank_num = 3,
> + .pin = 2,
> + .func = 6,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 6) | BIT(6),
> + }, {
> + /* card_iom1 */
> + .bank_num = 2,
> + .pin = 22,
> + .func = 3,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 7) | BIT(7),
> + }, {
> + /* tsp_d5m1 */
> + .bank_num = 2,
> + .pin = 16,
> + .func = 3,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 8) | BIT(8),
> + }, {
> + /* cif_data5m1 */
> + .bank_num = 2,
> + .pin = 16,
> + .func = 4,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 9) | BIT(9),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
> + {
> + /* uart2dbga_rx */
> + .bank_num = 4,
> + .pin = 8,
> + .func = 2,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 10) | BIT(16 + 11),
> + }, {
> + /* uart2dbgb_rx */
> + .bank_num = 4,
> + .pin = 16,
> + .func = 2,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
> + }, {
> + /* uart2dbgc_rx */
> + .bank_num = 4,
> + .pin = 19,
> + .func = 1,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
> + }, {
> + /* pcie_clkreqn */
> + .bank_num = 2,
> + .pin = 26,
> + .func = 2,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 14),
> + }, {
> + /* pcie_clkreqnb */
> + .bank_num = 4,
> + .pin = 24,
> + .func = 1,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 14) | BIT(14),
> + },
> +};
> +
> +static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
> + int mux, u32 *reg, u32 *value)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct rockchip_mux_route_data *data;
> + int i;
> +
> + for (i = 0; i < ctrl->niomux_routes; i++) {
> + data = &ctrl->iomux_routes[i];
> + if ((data->bank_num == bank->bank_num) &&
> + (data->pin == pin) && (data->func == mux))
> + break;
> + }
> +
> + if (i >= ctrl->niomux_routes)
> + return false;
> +
> + *reg = data->route_offset;
> + *value = data->route_val;
> +
> + return true;
> +}
> +
> +static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + unsigned int val;
> + int reg, ret, mask, mux_type;
> + u8 bit;
> +
> + if (iomux_num > 3)
> + return -EINVAL;
> +
> + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
> + debug("pin %d is unrouted\n", pin);
> + return -EINVAL;
> + }
> +
> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
> + return RK_FUNC_GPIO;
> +
> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + ? priv->regmap_pmu : priv->regmap_base;
> +
> + /* get basic quadrupel of mux registers and the correct reg inside */
> + mux_type = bank->iomux[iomux_num].type;
> + reg = bank->iomux[iomux_num].offset;
> + if (mux_type & IOMUX_WIDTH_4BIT) {
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> + } else if (mux_type & IOMUX_WIDTH_3BIT) {
> + if ((pin % 8) >= 5)
> + reg += 0x4;
> + bit = (pin % 8 % 5) * 3;
> + mask = 0x7;
> + } else {
> + bit = (pin % 8) * 2;
> + mask = 0x3;
> + }
> +
> + if (bank->recalced_mask & BIT(pin))
> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
> +
> + ret = regmap_read(regmap, reg, &val);
> + if (ret)
> + return ret;
> +
> + return ((val >> bit) & mask);
> +}
> +
> +static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
> + int index)
> +{ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> +
> + return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
> +}
> +
> +static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
> + int pin, int mux)
> +{
> + int iomux_num = (pin / 8);
> +
> + if (iomux_num > 3)
> + return -EINVAL;
> +
> + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
> + debug("pin %d is unrouted\n", pin);
> + return -EINVAL;
> + }
> +
> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
> + if (mux != IOMUX_GPIO_ONLY) {
> + debug("pin %d only supports a gpio mux\n", pin);
> + return -ENOTSUPP;
> + }
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Set a new mux function for a pin.
> + *
> + * The register is divided into the upper and lower 16 bit. When changing
> + * a value, the previous register value is not read and changed. Instead
> + * it seems the changed bits are marked in the upper 16 bit, while the
> + * changed value gets set in the same offset in the lower 16 bit.
> + * All pin settings seem to be 2 bit wide in both the upper and lower
> + * parts.
> + * @bank: pin bank to change
> + * @pin: pin to change
> + * @mux: new mux function to set
> + */
> +static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask, mux_type;
> + u8 bit;
> + u32 data, route_reg, route_val;
> +
> + ret = rockchip_verify_mux(bank, pin, mux);
> + if (ret < 0)
> + return ret;
> +
> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
> + return 0;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
> +
> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + ? priv->regmap_pmu : priv->regmap_base;
> +
> + /* get basic quadrupel of mux registers and the correct reg inside */
> + mux_type = bank->iomux[iomux_num].type;
> + reg = bank->iomux[iomux_num].offset;
> + if (mux_type & IOMUX_WIDTH_4BIT) {
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> + } else if (mux_type & IOMUX_WIDTH_3BIT) {
> + if ((pin % 8) >= 5)
> + reg += 0x4;
> + bit = (pin % 8 % 5) * 3;
> + mask = 0x7;
> + } else {
> + bit = (pin % 8) * 2;
> + mask = 0x3;
> + }
> +
> + if (bank->recalced_mask & BIT(pin))
> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
> +
> + if (bank->route_mask & BIT(pin)) {
> + if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
> + &route_val)) {
> + ret = regmap_write(regmap, route_reg, route_val);
> + if (ret)
> + return ret;
> + }
> + }
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define PX30_PULL_PMU_OFFSET 0x10
> +#define PX30_PULL_GRF_OFFSET 0x60
> +#define PX30_PULL_BITS_PER_PIN 2
> +#define PX30_PULL_PINS_PER_REG 8
> +#define PX30_PULL_BANK_STRIDE 16
> +
> +static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = PX30_PULL_PMU_OFFSET;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = PX30_PULL_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % PX30_PULL_PINS_PER_REG);
> + *bit *= PX30_PULL_BITS_PER_PIN;
> +}
> +
> +#define PX30_DRV_PMU_OFFSET 0x20
> +#define PX30_DRV_GRF_OFFSET 0xf0
> +#define PX30_DRV_BITS_PER_PIN 2
> +#define PX30_DRV_PINS_PER_REG 8
> +#define PX30_DRV_BANK_STRIDE 16
> +
> +static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = PX30_DRV_PMU_OFFSET;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = PX30_DRV_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
> + *bit = (pin_num % PX30_DRV_PINS_PER_REG);
> + *bit *= PX30_DRV_BITS_PER_PIN;
> +}
> +
> +#define PX30_SCHMITT_PMU_OFFSET 0x38
> +#define PX30_SCHMITT_GRF_OFFSET 0xc0
> +#define PX30_SCHMITT_PINS_PER_PMU_REG 16
> +#define PX30_SCHMITT_BANK_STRIDE 16
> +#define PX30_SCHMITT_PINS_PER_GRF_REG 8
> +
> +static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num,
> + struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int pins_per_reg;
> +
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = PX30_SCHMITT_PMU_OFFSET;
> + pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = PX30_SCHMITT_GRF_OFFSET;
> + pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
> + *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
> + }
> + *reg += ((pin_num / pins_per_reg) * 4);
> + *bit = pin_num % pins_per_reg;
> +
> + return 0;
> +}
> +
> +#define RV1108_PULL_PMU_OFFSET 0x10
> +#define RV1108_PULL_OFFSET 0x110
> +#define RV1108_PULL_PINS_PER_REG 8
> +#define RV1108_PULL_BITS_PER_PIN 2
> +#define RV1108_PULL_BANK_STRIDE 16
> +
> +static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 24 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RV1108_PULL_PMU_OFFSET;
> + } else {
> + *reg = RV1108_PULL_OFFSET;
> + *regmap = priv->regmap_base;
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
> + *bit *= RV1108_PULL_BITS_PER_PIN;
> +}
> +
> +#define RV1108_DRV_PMU_OFFSET 0x20
> +#define RV1108_DRV_GRF_OFFSET 0x210
> +#define RV1108_DRV_BITS_PER_PIN 2
> +#define RV1108_DRV_PINS_PER_REG 8
> +#define RV1108_DRV_BANK_STRIDE 16
> +
> +static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 24 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RV1108_DRV_PMU_OFFSET;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RV1108_DRV_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
> + *bit = pin_num % RV1108_DRV_PINS_PER_REG;
> + *bit *= RV1108_DRV_BITS_PER_PIN;
> +}
> +
> +#define RV1108_SCHMITT_PMU_OFFSET 0x30
> +#define RV1108_SCHMITT_GRF_OFFSET 0x388
> +#define RV1108_SCHMITT_BANK_STRIDE 8
> +#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
> +#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
> +
> +static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num,
> + struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int pins_per_reg;
> +
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RV1108_SCHMITT_PMU_OFFSET;
> + pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RV1108_SCHMITT_GRF_OFFSET;
> + pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
> + *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
> + }
> + *reg += ((pin_num / pins_per_reg) * 4);
> + *bit = pin_num % pins_per_reg;
> +
> + return 0;
> +}
> +
> +#define RK2928_PULL_OFFSET 0x118
> +#define RK2928_PULL_PINS_PER_REG 16
> +#define RK2928_PULL_BANK_STRIDE 8
> +
> +static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK2928_PULL_OFFSET;
> + *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
> + *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
> +
> + *bit = pin_num % RK2928_PULL_PINS_PER_REG;
> +};
> +
> +#define RK3128_PULL_OFFSET 0x118
> +
> +static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK3128_PULL_OFFSET;
> + *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
> +
> + *bit = pin_num % RK2928_PULL_PINS_PER_REG;
> +}
> +
> +#define RK3188_PULL_OFFSET 0x164
> +#define RK3188_PULL_BITS_PER_PIN 2
> +#define RK3188_PULL_PINS_PER_REG 8
> +#define RK3188_PULL_BANK_STRIDE 16
> +#define RK3188_PULL_PMU_OFFSET 0x64
> +
> +static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 12 pins of the first bank are located elsewhere */
> + if (bank->bank_num == 0 && pin_num < 12) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3188_PULL_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3188_PULL_OFFSET;
> +
> + /* correct the offset, as it is the 2nd pull register */
> + *reg -= 4;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + /*
> + * The bits in these registers have an inverse ordering
> + * with the lowest pin being in bits 15:14 and the highest
> + * pin in bits 1:0
> + */
> + *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3288_PULL_OFFSET 0x140
> +static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 24 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3188_PULL_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3288_PULL_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3288_DRV_PMU_OFFSET 0x70
> +#define RK3288_DRV_GRF_OFFSET 0x1c0
> +#define RK3288_DRV_BITS_PER_PIN 2
> +#define RK3288_DRV_PINS_PER_REG 8
> +#define RK3288_DRV_BANK_STRIDE 16
> +
> +static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 24 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3288_DRV_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3288_DRV_PINS_PER_REG;
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3288_DRV_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3228_PULL_OFFSET 0x100
> +
> +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK3228_PULL_OFFSET;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> +}
> +
> +#define RK3228_DRV_GRF_OFFSET 0x200
> +
> +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK3228_DRV_GRF_OFFSET;
> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> +}
> +
> +#define RK3368_PULL_GRF_OFFSET 0x100
> +#define RK3368_PULL_PMU_OFFSET 0x10
> +
> +static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3368_PULL_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3368_PULL_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3368_DRV_PMU_OFFSET 0x20
> +#define RK3368_DRV_GRF_OFFSET 0x200
> +
> +static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3368_DRV_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3288_DRV_PINS_PER_REG;
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3368_DRV_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3399_PULL_GRF_OFFSET 0xe040
> +#define RK3399_PULL_PMU_OFFSET 0x40
> +#define RK3399_DRV_3BITS_PER_PIN 3
> +
> +static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The bank0:16 and bank1:32 pins are located in PMU */
> + if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3399_PULL_PMU_OFFSET;
> +
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> +
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3399_PULL_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 3rd bank */
> + *reg -= 0x20;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + }
> +}
> +
> +static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int drv_num = (pin_num / 8);
> +
> + /* The bank0:16 and bank1:32 pins are located in PMU */
> + if ((bank->bank_num == 0) || (bank->bank_num == 1))
> + *regmap = priv->regmap_pmu;
> + else
> + *regmap = priv->regmap_base;
> +
> + *reg = bank->drv[drv_num].offset;
> + if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
> + (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
> + *bit = (pin_num % 8) * 3;
> + else
> + *bit = (pin_num % 8) * 2;
> +}
> +
> +static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
> + { 2, 4, 8, 12, -1, -1, -1, -1 },
> + { 3, 6, 9, 12, -1, -1, -1, -1 },
> + { 5, 10, 15, 20, -1, -1, -1, -1 },
> + { 4, 6, 8, 10, 12, 14, 16, 18 },
> + { 4, 7, 10, 13, 16, 19, 22, 26 }
> +};
> +
> +static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct regmap *regmap;
> + int reg, ret, i;
> + u32 data, rmask_bits, temp;
> + u8 bit;
> + int drv_type = bank->drv[pin_num / 8].drv_type;
> +
> + debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
> + pin_num, strength);
> +
> + ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
> +
> + ret = -EINVAL;
> + for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
> + if (rockchip_perpin_drv_list[drv_type][i] == strength) {
> + ret = i;
> + break;
> + } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
> + ret = rockchip_perpin_drv_list[drv_type][i];
> + break;
> + }
> + }
> +
> + if (ret < 0) {
> + debug("unsupported driver strength %d\n", strength);
> + return ret;
> + }
> +
> + switch (drv_type) {
> + case DRV_TYPE_IO_1V8_3V0_AUTO:
> + case DRV_TYPE_IO_3V3_ONLY:
> + rmask_bits = RK3399_DRV_3BITS_PER_PIN;
> + switch (bit) {
> + case 0 ... 12:
> + /* regular case, nothing to do */
> + break;
> + case 15:
> + /*
> + * drive-strength offset is special, as it is spread
> + * over 2 registers, the bit data[15] contains bit 0
> + * of the value while temp[1:0] contains bits 2 and 1
> + */
> + data = (ret & 0x1) << 15;
> + temp = (ret >> 0x1) & 0x3;
> +
> + data |= BIT(31);
> + ret = regmap_write(regmap, reg, data);
> + if (ret)
> + return ret;
> +
> + temp |= (0x3 << 16);
> + reg += 0x4;
> + ret = regmap_write(regmap, reg, temp);
> +
> + return ret;
> + case 18 ... 21:
> + /* setting fully enclosed in the second register */
> + reg += 4;
> + bit -= 16;
> + break;
> + default:
> + debug("unsupported bit: %d for pinctrl drive type: %d\n",
> + bit, drv_type);
> + return -EINVAL;
> + }
> + break;
> + case DRV_TYPE_IO_DEFAULT:
> + case DRV_TYPE_IO_1V8_OR_3V0:
> + case DRV_TYPE_IO_1V8_ONLY:
> + rmask_bits = RK3288_DRV_BITS_PER_PIN;
> + break;
> + default:
> + debug("unsupported pinctrl drive type: %d\n",
> + drv_type);
> + return -EINVAL;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << rmask_bits) - 1) << (bit + 16);
> + data |= (ret << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + return ret;
> +}
> +
> +static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
> + {
> + PIN_CONFIG_BIAS_DISABLE,
> + PIN_CONFIG_BIAS_PULL_UP,
> + PIN_CONFIG_BIAS_PULL_DOWN,
> + PIN_CONFIG_BIAS_BUS_HOLD
> + },
> + {
> + PIN_CONFIG_BIAS_DISABLE,
> + PIN_CONFIG_BIAS_PULL_DOWN,
> + PIN_CONFIG_BIAS_DISABLE,
> + PIN_CONFIG_BIAS_PULL_UP
> + },
> +};
> +
> +static int rockchip_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct regmap *regmap;
> + int reg, ret, i, pull_type;
> + u8 bit;
> + u32 data;
> +
> + debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
> + pin_num, pull);
> +
> + /* rk3066b does support any pulls */
> + if (ctrl->type == RK3066B)
> + return pull ? -EINVAL : 0;
> +
> + ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
> +
> + switch (ctrl->type) {
> + case RK2928:
> + case RK3128:
> + data = BIT(bit + 16);
> + if (pull == PIN_CONFIG_BIAS_DISABLE)
> + data |= BIT(bit);
> + ret = regmap_write(regmap, reg, data);
> + break;
> + case PX30:
> + case RV1108:
> + case RK3188:
> + case RK3288:
> + case RK3368:
> + case RK3399:
> + pull_type = bank->pull_type[pin_num / 8];
> + ret = -EINVAL;
> + for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
> + i++) {
> + if (rockchip_pull_list[pull_type][i] == pull) {
> + ret = i;
> + break;
> + }
> + }
> +
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (ret << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + break;
> + default:
> + debug("unsupported pinctrl type\n");
> + return -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +#define RK3328_SCHMITT_BITS_PER_PIN 1
> +#define RK3328_SCHMITT_PINS_PER_REG 16
> +#define RK3328_SCHMITT_BANK_STRIDE 8
> +#define RK3328_SCHMITT_GRF_OFFSET 0x380
> +
> +static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num,
> + struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK3328_SCHMITT_GRF_OFFSET;
> +
> + *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
> + *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
> +
> + return 0;
> +}
> +
> +static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit;
> + u32 data;
> +
> + debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
> + pin_num, enable);
> +
> + ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
> + if (ret)
> + return ret;
> +
> + /* enable the write to the equivalent lower bits */
> + data = BIT(bit + 16) | (enable << bit);
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +/*
> + * Pinconf_ops handling
> + */
> +static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
> + unsigned int pull)
> +{
> + switch (ctrl->type) {
> + case RK2928:
> + case RK3128:
> + return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
> + pull == PIN_CONFIG_BIAS_DISABLE);
> + case RK3066B:
> + return pull ? false : true;
> + case PX30:
> + case RV1108:
> + case RK3188:
> + case RK3288:
> + case RK3368:
> + case RK3399:
> + return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
> + }
> +
> + return false;
> +}
> +
> +/* set the pin config settings for a specified pin */
> +static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
> + u32 pin, u32 param, u32 arg)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + int rc;
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + rc = rockchip_set_pull(bank, pin, param);
> + if (rc)
> + return rc;
> + break;
> +
> + case PIN_CONFIG_BIAS_PULL_UP:
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
> + case PIN_CONFIG_BIAS_BUS_HOLD:
> + if (!rockchip_pinconf_pull_valid(ctrl, param))
> + return -ENOTSUPP;
> +
> + if (!arg)
> + return -EINVAL;
> +
> + rc = rockchip_set_pull(bank, pin, param);
> + if (rc)
> + return rc;
> + break;
> +
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + if (!ctrl->drv_calc_reg)
> + return -ENOTSUPP;
> +
> + rc = rockchip_set_drive_perpin(bank, pin, arg);
> + if (rc < 0)
> + return rc;
> + break;
> +
> + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
> + if (!ctrl->schmitt_calc_reg)
> + return -ENOTSUPP;
> +
> + rc = rockchip_set_schmitt(bank, pin, arg);
> + if (rc < 0)
> + return rc;
> + break;
> +
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static const struct pinconf_param rockchip_conf_params[] = {
> + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
> + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
> + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
> + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
> + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
> + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
> + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
> + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
> + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
> +};
> +
> +static int rockchip_pinconf_prop_name_to_param(const char *property,
> + u32 *default_value)
> +{
> + const struct pinconf_param *p, *end;
> +
> + p = rockchip_conf_params;
> + end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
> +
> + /* See if this pctldev supports this parameter */
> + for (; p < end; p++) {
> + if (!strcmp(property, p->property)) {
> + *default_value = p->default_value;
> + return p->param;
> + }
> + }
> +
> + *default_value = 0;
> + return -EPERM;
> +}
> +
> +static int rockchip_pinctrl_set_state(struct udevice *dev,
> + struct udevice *config)
> +{
> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + const void *blob = gd->fdt_blob;
> + int node = dev_of_offset(config);
> + u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
> + u32 bank, pin, mux, conf, arg, default_val;
> + int ret, count, i;
> + const char *prop_name;
> + int pcfg_node, property_offset, prop_len, param;
> + const void *value;
> +
> + count = fdtdec_get_int_array_count(blob, node, "rockchip,pins",
> + cells, ARRAY_SIZE(cells));
> + if (count < 0) {
> + debug("%s: bad array %d\n", __func__, count);
> + return -EINVAL;
> + }
> +
> + if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
> + debug("%s: unsupported pins array count %d\n",
> + __func__, count);
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < (count >> 2); i++) {
> + bank = cells[4 * i + 0];
> + pin = cells[4 * i + 1];
> + mux = cells[4 * i + 2];
> + conf = cells[4 * i + 3];
> +
> + ret = rockchip_verify_config(dev, bank, pin);
> + if (ret)
> + return ret;
> +
> + ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
> + if (ret)
> + return ret;
> +
> + pcfg_node = fdt_node_offset_by_phandle(blob, conf);
> + if (pcfg_node < 0)
> + return -ENODEV;
> +
> + fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
> + value = fdt_getprop_by_offset(blob, property_offset,
> + &prop_name, &prop_len);
> + if (!value)
> + return -ENOENT;
> +
> + param = rockchip_pinconf_prop_name_to_param(prop_name,
> + &default_val);
> + if (param < 0)
> + break;
> +
> + if (prop_len >= sizeof(fdt32_t))
> + arg = fdt32_to_cpu(*(fdt32_t *)value);
> + else
> + arg = default_val;
> +
> + ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
> + param, arg);
> + if (ret) {
> + debug("%s: rockchip_pinconf_set fail: %d\n",
> + __func__, ret);
> + return ret;
> + }
> + }
> + }
> +
> + return 0;
> +}
> +
> +static struct pinctrl_ops rockchip_pinctrl_ops = {
> + .set_state = rockchip_pinctrl_set_state,
> + .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
> +};
> +
> +/* retrieve the soc specific data */
> +static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
> +{
> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl =
> + (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
> + struct rockchip_pin_bank *bank;
> + int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
> +
> + grf_offs = ctrl->grf_mux_offset;
> + pmu_offs = ctrl->pmu_mux_offset;
> + drv_pmu_offs = ctrl->pmu_drv_offset;
> + drv_grf_offs = ctrl->grf_drv_offset;
> + bank = ctrl->pin_banks;
> +
> + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
> + int bank_pins = 0;
> +
> + bank->priv = priv;
> + bank->pin_base = ctrl->nr_pins;
> + ctrl->nr_pins += bank->nr_pins;
> +
> + /* calculate iomux and drv offsets */
> + for (j = 0; j < 4; j++) {
> + struct rockchip_iomux *iom = &bank->iomux[j];
> + struct rockchip_drv *drv = &bank->drv[j];
> + int inc;
> +
> + if (bank_pins >= bank->nr_pins)
> + break;
> +
> + /* preset iomux offset value, set new start value */
> + if (iom->offset >= 0) {
> + if (iom->type & IOMUX_SOURCE_PMU)
> + pmu_offs = iom->offset;
> + else
> + grf_offs = iom->offset;
> + } else { /* set current iomux offset */
> + iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> + pmu_offs : grf_offs;
> + }
> +
> + /* preset drv offset value, set new start value */
> + if (drv->offset >= 0) {
> + if (iom->type & IOMUX_SOURCE_PMU)
> + drv_pmu_offs = drv->offset;
> + else
> + drv_grf_offs = drv->offset;
> + } else { /* set current drv offset */
> + drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> + drv_pmu_offs : drv_grf_offs;
> + }
> +
> + debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
> + i, j, iom->offset, drv->offset);
> +
> + /*
> + * Increase offset according to iomux width.
> + * 4bit iomux'es are spread over two registers.
> + */
> + inc = (iom->type & (IOMUX_WIDTH_4BIT |
> + IOMUX_WIDTH_3BIT)) ? 8 : 4;
> + if (iom->type & IOMUX_SOURCE_PMU)
> + pmu_offs += inc;
> + else
> + grf_offs += inc;
> +
> + /*
> + * Increase offset according to drv width.
> + * 3bit drive-strenth'es are spread over two registers.
> + */
> + if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
> + (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
> + inc = 8;
> + else
> + inc = 4;
> +
> + if (iom->type & IOMUX_SOURCE_PMU)
> + drv_pmu_offs += inc;
> + else
> + drv_grf_offs += inc;
> +
> + bank_pins += 8;
> + }
> +
> + /* calculate the per-bank recalced_mask */
> + for (j = 0; j < ctrl->niomux_recalced; j++) {
> + int pin = 0;
> +
> + if (ctrl->iomux_recalced[j].num == bank->bank_num) {
> + pin = ctrl->iomux_recalced[j].pin;
> + bank->recalced_mask |= BIT(pin);
> + }
> + }
> +
> + /* calculate the per-bank route_mask */
> + for (j = 0; j < ctrl->niomux_routes; j++) {
> + int pin = 0;
> +
> + if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
> + pin = ctrl->iomux_routes[j].pin;
> + bank->route_mask |= BIT(pin);
> + }
> + }
> + }
> +
> + return ctrl;
> +}
> +
> +static int rockchip_pinctrl_probe(struct udevice *dev)
> +{
> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl;
> + struct udevice *syscon;
> + struct regmap *regmap;
> + int ret = 0;
> +
> + /* get rockchip grf syscon phandle */
> + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
> + &syscon);
> + if (ret) {
> + debug("unable to find rockchip,grf syscon device (%d)\n", ret);
> + return ret;
> + }
> +
> + /* get grf-reg base address */
> + regmap = syscon_get_regmap(syscon);
> + if (!regmap) {
> + debug("unable to find rockchip grf regmap\n");
> + return -ENODEV;
> + }
> + priv->regmap_base = regmap;
> +
> + /* option: get pmu-reg base address */
> + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
> + &syscon);
> + if (!ret) {
> + /* get pmugrf-reg base address */
> + regmap = syscon_get_regmap(syscon);
> + if (!regmap) {
> + debug("unable to find rockchip pmu regmap\n");
> + return -ENODEV;
> + }
> + priv->regmap_pmu = regmap;
> + }
> +
> + ctrl = rockchip_pinctrl_get_soc_data(dev);
> + if (!ctrl) {
> + debug("driver data not available\n");
> + return -EINVAL;
> + }
> +
> + priv->ctrl = ctrl;
> + return 0;
> +}
> +
> +static struct rockchip_pin_bank px30_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU
> + ),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT
> + ),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT
> + ),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT
> + ),
> +};
> +
> +static struct rockchip_pin_ctrl px30_pin_ctrl = {
> + .pin_banks = px30_pin_banks,
> + .nr_banks = ARRAY_SIZE(px30_pin_banks),
> + .label = "PX30-GPIO",
> + .type = PX30,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .iomux_routes = px30_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
> + .pull_calc_reg = px30_calc_pull_reg_and_bit,
> + .drv_calc_reg = px30_calc_drv_reg_and_bit,
> + .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rv1108_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
> +};
> +
> +static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
> + .pin_banks = rv1108_pin_banks,
> + .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
> + .label = "RV1108-GPIO",
> + .type = RV1108,
> + .grf_mux_offset = 0x10,
> + .pmu_mux_offset = 0x0,
> + .iomux_recalced = rv1108_mux_recalced_data,
> + .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
> + .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
> + .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
> + .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk2928_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
> + .pin_banks = rk2928_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
> + .label = "RK2928-GPIO",
> + .type = RK2928,
> + .grf_mux_offset = 0xa8,
> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3036_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
> + .pin_banks = rk3036_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
> + .label = "RK3036-GPIO",
> + .type = RK2928,
> + .grf_mux_offset = 0xa8,
> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3066a_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> + PIN_BANK(4, 32, "gpio4"),
> + PIN_BANK(6, 16, "gpio6"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
> + .pin_banks = rk3066a_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
> + .label = "RK3066a-GPIO",
> + .type = RK2928,
> + .grf_mux_offset = 0xa8,
> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3066b_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
> + .pin_banks = rk3066b_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
> + .label = "RK3066b-GPIO",
> + .type = RK3066B,
> + .grf_mux_offset = 0x60,
> +};
> +
> +static struct rockchip_pin_bank rk3128_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
> + .pin_banks = rk3128_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
> + .label = "RK3128-GPIO",
> + .type = RK3128,
> + .grf_mux_offset = 0xa8,
> + .iomux_recalced = rk3128_mux_recalced_data,
> + .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
> + .iomux_routes = rk3128_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
> + .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3188_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
> + .pin_banks = rk3188_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
> + .label = "RK3188-GPIO",
> + .type = RK3188,
> + .grf_mux_offset = 0x60,
> + .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3228_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
> + .pin_banks = rk3228_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
> + .label = "RK3228-GPIO",
> + .type = RK3288,
> + .grf_mux_offset = 0x0,
> + .iomux_routes = rk3228_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
> + .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3288_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_UNROUTED
> + ),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
> + IOMUX_UNROUTED,
> + IOMUX_UNROUTED,
> + 0
> + ),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0,
> + 0
> + ),
> + PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
> + 0,
> + 0,
> + IOMUX_UNROUTED
> + ),
> + PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
> + PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
> + 0,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_UNROUTED
> + ),
> + PIN_BANK(8, 16, "gpio8"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
> + .pin_banks = rk3288_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
> + .label = "RK3288-GPIO",
> + .type = RK3288,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x84,
> + .iomux_routes = rk3288_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
> + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3328_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
> + IOMUX_WIDTH_3BIT,
> + IOMUX_WIDTH_3BIT,
> + 0),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
> + IOMUX_WIDTH_3BIT,
> + IOMUX_WIDTH_3BIT,
> + 0,
> + 0),
> +};
> +
> +static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
> + .pin_banks = rk3328_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
> + .label = "RK3328-GPIO",
> + .type = RK3288,
> + .grf_mux_offset = 0x0,
> + .iomux_recalced = rk3328_mux_recalced_data,
> + .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
> + .iomux_routes = rk3328_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
> + .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
> + .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3368_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU
> + ),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
> + .pin_banks = rk3368_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
> + .label = "RK3368-GPIO",
> + .type = RK3368,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3399_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + DRV_TYPE_IO_1V8_ONLY,
> + DRV_TYPE_IO_1V8_ONLY,
> + DRV_TYPE_IO_DEFAULT,
> + DRV_TYPE_IO_DEFAULT,
> + 0x80,
> + 0x88,
> + -1,
> + -1,
> + PULL_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_IO_DEFAULT,
> + PULL_TYPE_IO_DEFAULT
> + ),
> + PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + 0xa0,
> + 0xa8,
> + 0xb0,
> + 0xb8
> + ),
> + PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_ONLY,
> + DRV_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_IO_DEFAULT,
> + PULL_TYPE_IO_DEFAULT,
> + PULL_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_IO_1V8_ONLY
> + ),
> + PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
> + DRV_TYPE_IO_3V3_ONLY,
> + DRV_TYPE_IO_3V3_ONLY,
> + DRV_TYPE_IO_1V8_OR_3V0
> + ),
> + PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_3V0_AUTO,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0
> + ),
> +};
> +
> +static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
> + .pin_banks = rk3399_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
> + .label = "RK3399-GPIO",
> + .type = RK3399,
> + .grf_mux_offset = 0xe000,
> + .pmu_mux_offset = 0x0,
> + .grf_drv_offset = 0xe100,
> + .pmu_drv_offset = 0x80,
> + .iomux_routes = rk3399_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
> + .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
> +};
> +
> +static const struct udevice_id rockchip_pinctrl_dt_match[] = {
> + { .compatible = "rockchip,px30-pinctrl",
> + .data = (ulong)&px30_pin_ctrl },
> + { .compatible = "rockchip,rv1108-pinctrl",
> + .data = (ulong)&rv1108_pin_ctrl },
> + { .compatible = "rockchip,rk2928-pinctrl",
> + .data = (ulong)&rk2928_pin_ctrl },
> + { .compatible = "rockchip,rk3036-pinctrl",
> + .data = (ulong)&rk3036_pin_ctrl },
> + { .compatible = "rockchip,rk3066a-pinctrl",
> + .data = (ulong)&rk3066a_pin_ctrl },
> + { .compatible = "rockchip,rk3066b-pinctrl",
> + .data = (ulong)&rk3066b_pin_ctrl },
> + { .compatible = "rockchip,rk3128-pinctrl",
> + .data = (ulong)&rk3128_pin_ctrl },
> + { .compatible = "rockchip,rk3188-pinctrl",
> + .data = (ulong)&rk3188_pin_ctrl },
> + { .compatible = "rockchip,rk3228-pinctrl",
> + .data = (ulong)&rk3228_pin_ctrl },
> + { .compatible = "rockchip,rk3288-pinctrl",
> + .data = (ulong)&rk3288_pin_ctrl },
> + { .compatible = "rockchip,rk3328-pinctrl",
> + .data = (ulong)&rk3328_pin_ctrl },
> + { .compatible = "rockchip,rk3368-pinctrl",
> + .data = (ulong)&rk3368_pin_ctrl },
> + { .compatible = "rockchip,rk3399-pinctrl",
> + .data = (ulong)&rk3399_pin_ctrl },
> + {},
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rockchip) = {
> + .name = "rockchip_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rockchip_pinctrl_dt_match,
> + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver
2018-02-03 6:51 ` [U-Boot] [PATCH 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-18 18:57 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
> to make fdedesc be built in.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> configs/evb-rk3399_defconfig | 1 -
> 1 file changed, 1 deletion(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
2018-02-03 6:51 ` [U-Boot] [PATCH 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL David Wu
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-18 19:00 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> When the boot ROM sets up MMC we don't need to do it again. Remove the
> MMC setup code entirely, but we also need to enable uart for debug message.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/rk3188-board-spl.c | 42 +++----------------------------
> 1 file changed, 3 insertions(+), 39 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver
2018-02-03 6:55 ` [U-Boot] [PATCH 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-18 19:01 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
> to make fdedesc be built in.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> configs/chromebit_mickey_defconfig | 2 --
> configs/chromebook_jerry_defconfig | 2 --
> configs/chromebook_minnie_defconfig | 2 --
> 3 files changed, 6 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
2018-02-03 6:51 ` [U-Boot] [PATCH 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl David Wu
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> If we use the new pinctrl driver, the pinctrl setup will be done
> by device probe. Remove the pinctrl setup at rk3288-board-spl.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/rk3288-board-spl.c | 79 -------------------------------
> 1 file changed, 79 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
2018-02-03 6:51 ` [U-Boot] [PATCH 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 David Wu
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> It seems that pinctrl is not requested for rk3188 SPL, remove it so
> that can save more space for SPL image size.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/Kconfig | 1 -
> 1 file changed, 1 deletion(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
2018-02-03 6:56 ` [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip " David Wu
2018-02-04 7:45 ` Kever Yang
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-18 19:20 ` Philipp Tomsich
2 siblings, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> Use this driver to fit all Rockchip SOCs and to support
> the desired pinctrl configuration via DTS.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> Tested-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> drivers/pinctrl/Kconfig | 98 +-
> drivers/pinctrl/Makefile | 2 +-
> drivers/pinctrl/pinctrl-rockchip.c | 2440 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 2454 insertions(+), 86 deletions(-)
> create mode 100644 drivers/pinctrl/pinctrl-rockchip.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 7/9] rockchip: defconfig: Clean the unused pinctrl config
2018-02-03 6:56 ` [U-Boot] [PATCH 7/9] rockchip: defconfig: Clean the unused pinctrl config David Wu
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> If we used the pinctrl-rockchip driver, these config is not needed,
> so remove them.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> configs/chromebit_mickey_defconfig | 2 --
> configs/chromebook_jerry_defconfig | 2 --
> configs/chromebook_minnie_defconfig | 2 --
> configs/evb-px5_defconfig | 1 -
> configs/evb-rk3128_defconfig | 1 -
> configs/evb-rk3229_defconfig | 1 -
> configs/evb-rk3288_defconfig | 2 --
> configs/evb-rk3399_defconfig | 1 -
> configs/evb-rv1108_defconfig | 1 -
> configs/fennec-rk3288_defconfig | 2 --
> configs/firefly-rk3288_defconfig | 2 --
> configs/firefly-rk3399_defconfig | 1 -
> configs/geekbox_defconfig | 1 -
> configs/kylin-rk3036_defconfig | 1 -
> configs/lion-rk3368_defconfig | 1 -
> configs/miqi-rk3288_defconfig | 2 --
> configs/phycore-rk3288_defconfig | 2 --
> configs/popmetal-rk3288_defconfig | 2 --
> configs/puma-rk3399_defconfig | 1 -
> configs/rock2_defconfig | 2 --
> configs/rock_defconfig | 1 -
> configs/sandbox_defconfig | 2 --
> configs/sandbox_flattree_defconfig | 2 --
> configs/sandbox_noblk_defconfig | 2 --
> configs/sheep-rk3368_defconfig | 1 -
> configs/tinker-rk3288_defconfig | 2 --
> configs/vyasa-rk3288_defconfig | 2 --
> 27 files changed, 42 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 8/9] pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
2018-02-03 6:57 ` [U-Boot] [PATCH 8/9] pinctrl: rockchip: Clean the unused rockchip pinctrl drivers David Wu
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> If we used the pinctrl-rockchip driver, these code is not needed,
> so remove them.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> drivers/pinctrl/rockchip/Makefile | 15 -
> drivers/pinctrl/rockchip/pinctrl_rk3036.c | 264 ---------
> drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 -------
> drivers/pinctrl/rockchip/pinctrl_rk3188.c | 610 --------------------
> drivers/pinctrl/rockchip/pinctrl_rk322x.c | 895 ------------------------------
> drivers/pinctrl/rockchip/pinctrl_rk3288.c | 870 -----------------------------
> drivers/pinctrl/rockchip/pinctrl_rk3328.c | 708 -----------------------
> drivers/pinctrl/rockchip/pinctrl_rk3368.c | 742 -------------------------
> drivers/pinctrl/rockchip/pinctrl_rk3399.c | 457 ---------------
> drivers/pinctrl/rockchip/pinctrl_rv1108.c | 582 -------------------
> 10 files changed, 5330 deletions(-)
> delete mode 100644 drivers/pinctrl/rockchip/Makefile
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3399.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rv1108.c
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration
2018-02-03 6:57 ` [U-Boot] [PATCH 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration David Wu
@ 2018-02-09 10:13 ` Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:13 UTC (permalink / raw)
To: u-boot
> To match the iomux setting of uart2 at SPL, correct the uart2
> default pin configuration, if not changed, the evb-rk3229 can't
> output the log message.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> arch/arm/dts/rk322x.dtsi | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188
2018-02-03 6:51 ` [U-Boot] [PATCH 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:15 UTC (permalink / raw)
To: u-boot
> It seems that pinctrl is not requested for rk3188 SPL, remove it so
> that can save more space for SPL image size.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/Kconfig | 1 -
> 1 file changed, 1 deletion(-)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl
2018-02-03 6:51 ` [U-Boot] [PATCH 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:15 UTC (permalink / raw)
To: u-boot
> If we use the new pinctrl driver, the pinctrl setup will be done
> by device probe. Remove the pinctrl setup at rk3288-board-spl.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/rk3288-board-spl.c | 79 -------------------------------
> 1 file changed, 79 deletions(-)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 7/9] rockchip: defconfig: Clean the unused pinctrl config
2018-02-03 6:56 ` [U-Boot] [PATCH 7/9] rockchip: defconfig: Clean the unused pinctrl config David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:15 UTC (permalink / raw)
To: u-boot
> If we used the pinctrl-rockchip driver, these config is not needed,
> so remove them.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> configs/chromebit_mickey_defconfig | 2 --
> configs/chromebook_jerry_defconfig | 2 --
> configs/chromebook_minnie_defconfig | 2 --
> configs/evb-px5_defconfig | 1 -
> configs/evb-rk3128_defconfig | 1 -
> configs/evb-rk3229_defconfig | 1 -
> configs/evb-rk3288_defconfig | 2 --
> configs/evb-rk3399_defconfig | 1 -
> configs/evb-rv1108_defconfig | 1 -
> configs/fennec-rk3288_defconfig | 2 --
> configs/firefly-rk3288_defconfig | 2 --
> configs/firefly-rk3399_defconfig | 1 -
> configs/geekbox_defconfig | 1 -
> configs/kylin-rk3036_defconfig | 1 -
> configs/lion-rk3368_defconfig | 1 -
> configs/miqi-rk3288_defconfig | 2 --
> configs/phycore-rk3288_defconfig | 2 --
> configs/popmetal-rk3288_defconfig | 2 --
> configs/puma-rk3399_defconfig | 1 -
> configs/rock2_defconfig | 2 --
> configs/rock_defconfig | 1 -
> configs/sandbox_defconfig | 2 --
> configs/sandbox_flattree_defconfig | 2 --
> configs/sandbox_noblk_defconfig | 2 --
> configs/sheep-rk3368_defconfig | 1 -
> configs/tinker-rk3288_defconfig | 2 --
> configs/vyasa-rk3288_defconfig | 2 --
> 27 files changed, 42 deletions(-)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 8/9] pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
2018-02-03 6:57 ` [U-Boot] [PATCH 8/9] pinctrl: rockchip: Clean the unused rockchip pinctrl drivers David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:15 UTC (permalink / raw)
To: u-boot
> If we used the pinctrl-rockchip driver, these code is not needed,
> so remove them.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> drivers/pinctrl/rockchip/Makefile | 15 -
> drivers/pinctrl/rockchip/pinctrl_rk3036.c | 264 ---------
> drivers/pinctrl/rockchip/pinctrl_rk3128.c | 187 -------
> drivers/pinctrl/rockchip/pinctrl_rk3188.c | 610 --------------------
> drivers/pinctrl/rockchip/pinctrl_rk322x.c | 895 ------------------------------
> drivers/pinctrl/rockchip/pinctrl_rk3288.c | 870 -----------------------------
> drivers/pinctrl/rockchip/pinctrl_rk3328.c | 708 -----------------------
> drivers/pinctrl/rockchip/pinctrl_rk3368.c | 742 -------------------------
> drivers/pinctrl/rockchip/pinctrl_rk3399.c | 457 ---------------
> drivers/pinctrl/rockchip/pinctrl_rv1108.c | 582 -------------------
> 10 files changed, 5330 deletions(-)
> delete mode 100644 drivers/pinctrl/rockchip/Makefile
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3036.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3128.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3328.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3368.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3399.c
> delete mode 100644 drivers/pinctrl/rockchip/pinctrl_rv1108.c
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration
2018-02-03 6:57 ` [U-Boot] [PATCH 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-09 10:15 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-09 10:15 UTC (permalink / raw)
To: u-boot
> To match the iomux setting of uart2 at SPL, correct the uart2
> default pin configuration, if not changed, the evb-rk3229 can't
> output the log message.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
>
> arch/arm/dts/rk322x.dtsi | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver
2018-02-03 6:51 ` [U-Boot] [PATCH 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-18 18:57 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-18 18:57 UTC (permalink / raw)
To: u-boot
On Sat, 3 Feb 2018, David Wu wrote:
> The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
> to make fdedesc be built in.
You should reword this, as "fdedesc" ist not how the device-tree is
usually referred to.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> configs/evb-rk3399_defconfig | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
> index e8e52c3..54eb703 100644
> --- a/configs/evb-rk3399_defconfig
> +++ b/configs/evb-rk3399_defconfig
> @@ -22,7 +22,6 @@ CONFIG_CMD_USB=y
> CONFIG_CMD_TIME=y
> CONFIG_SPL_OF_CONTROL=y
> CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> -CONFIG_SPL_OF_PLATDATA=y
> CONFIG_ENV_IS_IN_MMC=y
> CONFIG_NET_RANDOM_ETHADDR=y
> CONFIG_REGMAP=y
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
2018-02-03 6:51 ` [U-Boot] [PATCH 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-18 19:00 ` Philipp Tomsich
2018-03-05 11:36 ` David Wu
1 sibling, 1 reply; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-18 19:00 UTC (permalink / raw)
To: u-boot
On Sat, 3 Feb 2018, David Wu wrote:
> When the boot ROM sets up MMC we don't need to do it again. Remove the
> MMC setup code entirely, but we also need to enable uart for debug message.
If the MMC always set up correctly for all configurations (e.g. bus-width)
or should some of the setup be duplicated there to ensure that we catch
all corner cases?
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> arch/arm/mach-rockchip/rk3188-board-spl.c | 42 +++----------------------------
> 1 file changed, 3 insertions(+), 39 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c
> index 8e3b8ae..8371a31 100644
> --- a/arch/arm/mach-rockchip/rk3188-board-spl.c
> +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
> @@ -100,10 +100,11 @@ static int setup_arm_clock(void)
>
> void board_init_f(ulong dummy)
> {
> - struct udevice *pinctrl, *dev;
> + struct udevice *dev;
> int ret;
>
> /* Example code showing how to enable the debug UART on RK3188 */
> +#define EARLY_UART
> #ifdef EARLY_UART
> #include <asm/arch/grf_rk3188.h>
> /* Enable early UART on the RK3188 */
> @@ -124,10 +125,7 @@ void board_init_f(ulong dummy)
> * printascii("string");
> */
> debug_uart_init();
> - printch('s');
> - printch('p');
> - printch('l');
> - printch('\n');
> + printascii("U-Boot SPL board init");
> #endif
>
> ret = spl_early_init();
> @@ -144,12 +142,6 @@ void board_init_f(ulong dummy)
> return;
> }
>
> - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> - if (ret) {
> - debug("Pinctrl init failed: %d\n", ret);
> - return;
> - }
> -
> ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> if (ret) {
> debug("DRAM init failed: %d\n", ret);
> @@ -187,7 +179,6 @@ static int setup_led(void)
>
> void spl_board_init(void)
> {
> - struct udevice *pinctrl;
> int ret;
>
> ret = setup_led();
> @@ -196,36 +187,9 @@ void spl_board_init(void)
> hang();
> }
>
> - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
> - if (ret) {
> - debug("%s: Cannot find pinctrl device\n", __func__);
> - goto err;
> - }
> -
> -#ifdef CONFIG_SPL_MMC_SUPPORT
> - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
> - if (ret) {
> - debug("%s: Failed to set up SD card\n", __func__);
> - goto err;
> - }
> -#endif
> -
> - /* Enable debug UART */
> - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
> - if (ret) {
> - debug("%s: Failed to set up console UART\n", __func__);
> - goto err;
> - }
> -
> preloader_console_init();
> #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
> back_to_bootrom(BROM_BOOT_NEXTSTAGE);
> #endif
> return;
> -
> -err:
> - printf("spl_board_init: Error %d\n", ret);
> -
> - /* No way to report error here */
> - hang();
> }
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver
2018-02-03 6:55 ` [U-Boot] [PATCH 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-18 19:01 ` Philipp Tomsich
1 sibling, 0 replies; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-18 19:01 UTC (permalink / raw)
To: u-boot
On Sat, 3 Feb 2018, David Wu wrote:
> The fdedesc is requested for new pinctrl driver, disable SPL_OF_PLATDATA
> to make fdedesc be built in.
Again, please reword: I don't see "fdedesc" used anywhere else in U-Boot
to refer to the device tree.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> configs/chromebit_mickey_defconfig | 2 --
> configs/chromebook_jerry_defconfig | 2 --
> configs/chromebook_minnie_defconfig | 2 --
> 3 files changed, 6 deletions(-)
>
> diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
> index b350811..93c5c4e 100644
> --- a/configs/chromebit_mickey_defconfig
> +++ b/configs/chromebit_mickey_defconfig
> @@ -34,7 +34,6 @@ CONFIG_CMD_REGULATOR=y
> CONFIG_SPL_PARTITION_UUIDS=y
> CONFIG_SPL_OF_CONTROL=y
> CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> -CONFIG_SPL_OF_PLATDATA=y
> CONFIG_REGMAP=y
> CONFIG_SPL_REGMAP=y
> CONFIG_SYSCON=y
> @@ -88,7 +87,6 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y
> CONFIG_USE_TINY_PRINTF=y
> CONFIG_CMD_DHRYSTONE=y
> CONFIG_ERRNO_STR=y
> -# CONFIG_SPL_OF_LIBFDT is not set
> CONFIG_USB_GADGET_DOWNLOAD=y
> CONFIG_USB_GADGET_VBUS_DRAW=0
> CONFIG_G_DNL_MANUFACTURER="Rockchip"
> diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
> index f80faae..57d35e9 100644
> --- a/configs/chromebook_jerry_defconfig
> +++ b/configs/chromebook_jerry_defconfig
> @@ -36,7 +36,6 @@ CONFIG_CMD_REGULATOR=y
> CONFIG_SPL_PARTITION_UUIDS=y
> CONFIG_SPL_OF_CONTROL=y
> CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> -CONFIG_SPL_OF_PLATDATA=y
> CONFIG_REGMAP=y
> CONFIG_SPL_REGMAP=y
> CONFIG_SYSCON=y
> @@ -90,7 +89,6 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y
> CONFIG_USE_TINY_PRINTF=y
> CONFIG_CMD_DHRYSTONE=y
> CONFIG_ERRNO_STR=y
> -# CONFIG_SPL_OF_LIBFDT is not set
> CONFIG_USB_GADGET_DOWNLOAD=y
> CONFIG_USB_GADGET_VBUS_DRAW=0
> CONFIG_G_DNL_MANUFACTURER="Rockchip"
> diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
> index ff94a4d..529444a 100644
> --- a/configs/chromebook_minnie_defconfig
> +++ b/configs/chromebook_minnie_defconfig
> @@ -35,7 +35,6 @@ CONFIG_CMD_REGULATOR=y
> CONFIG_SPL_PARTITION_UUIDS=y
> CONFIG_SPL_OF_CONTROL=y
> CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> -CONFIG_SPL_OF_PLATDATA=y
> CONFIG_REGMAP=y
> CONFIG_SPL_REGMAP=y
> CONFIG_SYSCON=y
> @@ -90,7 +89,6 @@ CONFIG_CONSOLE_SCROLL_LINES=10
> CONFIG_USE_TINY_PRINTF=y
> CONFIG_CMD_DHRYSTONE=y
> CONFIG_ERRNO_STR=y
> -# CONFIG_SPL_OF_LIBFDT is not set
> CONFIG_USB_GADGET_DOWNLOAD=y
> CONFIG_USB_GADGET_VBUS_DRAW=0
> CONFIG_G_DNL_MANUFACTURER="Rockchip"
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
2018-02-03 6:56 ` [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip " David Wu
2018-02-04 7:45 ` Kever Yang
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
@ 2018-02-18 19:20 ` Philipp Tomsich
2018-03-05 11:23 ` David Wu
2 siblings, 1 reply; 31+ messages in thread
From: Philipp Tomsich @ 2018-02-18 19:20 UTC (permalink / raw)
To: u-boot
On Sat, 3 Feb 2018, David Wu wrote:
> Use this driver to fit all Rockchip SOCs and to support
> the desired pinctrl configuration via DTS.
Please split this into multiple comments (and possibly multiple files) for
the relevant per-SoC data structures. I'd like this to be multiple
commits to add the individual data structures for each of the SOCs.
We had the fundamental discussion of how to deal with drivers that require
additional config-structures and code for some SOCs in the HDMI/VOP
context and we should follow the same here.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> Tested-by: Kever Yang <kever.yang@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
>
> drivers/pinctrl/Kconfig | 98 +-
> drivers/pinctrl/Makefile | 2 +-
> drivers/pinctrl/pinctrl-rockchip.c | 2440 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 2454 insertions(+), 86 deletions(-)
> create mode 100644 drivers/pinctrl/pinctrl-rockchip.c
>
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 7e8e4b0..6177e7c 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -158,95 +158,23 @@ config PINCTRL_QCA953X
> the GPIO definitions and pin control functions for each available
> multiplex function.
>
> -config PINCTRL_ROCKCHIP_RK3036
> - bool "Rockchip rk3036 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3036 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3128
> - bool "Rockchip rk3128 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3128 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3188
> - bool "Rockchip rk3188 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3188 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK322X
> - bool "Rockchip rk322x pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk322x SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3288
> - bool "Rockchip rk3288 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3288 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3328
> - bool "Rockchip rk3328 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3328 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3368
> - bool "Rockchip RK3368 pin control driver"
> - depends on DM
> - help
> - Support pin multiplexing control on Rockchip rk3368 SoCs.
> -
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> -
> -config PINCTRL_ROCKCHIP_RK3399
> - bool "Rockchip rk3399 pin control driver"
> - depends on DM
> +config PINCTRL_ROCKCHIP
> + bool "Rockchip pin control driver"
> + depends on PINCTRL_FULL
> + default y
> help
> - Support pin multiplexing control on Rockchip rk3399 SoCs.
> + Support pin multiplexing control on Rockchip SoCs.
>
> - The driver is controlled by a device tree node which contains both
> - the GPIO definitions and pin control functions for each available
> - multiplex function.
> + The driver is controlled by a device tree node which contains pin
> + control functions for each available multiplex function.
>
> -config PINCTRL_ROCKCHIP_RV1108
> - bool "Rockchip rv1108 pin control driver"
> - depends on DM
> +config SPL_PINCTRL_ROCKCHIP
> + bool "Support Rockchip pin controllers in SPL"
> + depends on SPL_PINCTRL_FULL
> + default y
> help
> - Support pin multiplexing control on Rockchip rv1108 SoC.
> -
> - The driver is controlled by a device tree node which contains
> - both the GPIO definitions and pin control functions for each
> - available multiplex function.
> + This option is an SPL-variant of the PINCTRL_ROCKCHIP option.
> + See the help of PINCTRL_ROCKCHIP for details.
>
> config PINCTRL_SANDBOX
> bool "Sandbox pinctrl driver"
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index 8c04028..2429eb9 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -11,7 +11,7 @@ obj-y += nxp/
> obj-$(CONFIG_ARCH_ASPEED) += aspeed/
> obj-$(CONFIG_ARCH_ATH79) += ath79/
> obj-$(CONFIG_ARCH_RMOBILE) += renesas/
> -obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
> +obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
> obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
>
> obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> new file mode 100644
> index 0000000..68bf30d
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -0,0 +1,2440 @@
> +/*
> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +
> +#define MAX_ROCKCHIP_GPIO_PER_BANK 32
> +#define RK_FUNC_GPIO 0
> +#define MAX_ROCKCHIP_PINS_ENTRIES 20
> +
> +enum rockchip_pinctrl_type {
> + PX30,
PX30 support has not been added to U-Boot. This should only be added, once
the PX30 support is added.
> + RV1108,
> + RK2928,
RK2928 support is not present in U-Boot.
> + RK3066B,
> + RK3128,
> + RK3188,
> + RK3288,
> + RK3368,
> + RK3399,
> +};
> +
> +/**
> + * Encode variants of iomux registers into a type variable
> + */
> +#define IOMUX_GPIO_ONLY BIT(0)
> +#define IOMUX_WIDTH_4BIT BIT(1)
> +#define IOMUX_SOURCE_PMU BIT(2)
> +#define IOMUX_UNROUTED BIT(3)
> +#define IOMUX_WIDTH_3BIT BIT(4)
> +
> +/**
> + * @type: iomux variant using IOMUX_* constants
> + * @offset: if initialized to -1 it will be autocalculated, by specifying
> + * an initial offset value the relevant source offset can be reset
> + * to a new value for autocalculating the following iomux registers.
> + */
> +struct rockchip_iomux {
> + int type;
> + int offset;
> +};
> +
> +/**
> + * enum type index corresponding to rockchip_perpin_drv_list arrays index.
> + */
> +enum rockchip_pin_drv_type {
> + DRV_TYPE_IO_DEFAULT = 0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_ONLY,
> + DRV_TYPE_IO_1V8_3V0_AUTO,
> + DRV_TYPE_IO_3V3_ONLY,
> + DRV_TYPE_MAX
> +};
> +
> +/**
> + * enum type index corresponding to rockchip_pull_list arrays index.
> + */
> +enum rockchip_pin_pull_type {
> + PULL_TYPE_IO_DEFAULT = 0,
> + PULL_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_MAX
> +};
> +
> +/**
> + * @drv_type: drive strength variant using rockchip_perpin_drv_type
> + * @offset: if initialized to -1 it will be autocalculated, by specifying
> + * an initial offset value the relevant source offset can be reset
> + * to a new value for autocalculating the following drive strength
> + * registers. if used chips own cal_drv func instead to calculate
> + * registers offset, the variant could be ignored.
> + */
> +struct rockchip_drv {
> + enum rockchip_pin_drv_type drv_type;
> + int offset;
> +};
> +
> +/**
> + * @priv: common pinctrl private basedata
> + * @pin_base: first pin number
> + * @nr_pins: number of pins in this bank
> + * @name: name of the bank
> + * @bank_num: number of the bank, to account for holes
> + * @iomux: array describing the 4 iomux sources of the bank
> + * @drv: array describing the 4 drive strength sources of the bank
> + * @pull_type: array describing the 4 pull type sources of the bank
> + * @recalced_mask: bits describing the mux recalced pins of per bank
> + * @route_mask: bits describing the routing pins of per bank
> + */
> +struct rockchip_pin_bank {
> + struct rockchip_pinctrl_priv *priv;
> + u32 pin_base;
> + u8 nr_pins;
> + char *name;
> + u8 bank_num;
> + struct rockchip_iomux iomux[4];
> + struct rockchip_drv drv[4];
> + enum rockchip_pin_pull_type pull_type[4];
> + u32 recalced_mask;
> + u32 route_mask;
> +};
> +
> +#define PIN_BANK(id, pins, label) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + }, \
> + }
> +
> +#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .type = iom0, .offset = -1 }, \
> + { .type = iom1, .offset = -1 }, \
> + { .type = iom2, .offset = -1 }, \
> + { .type = iom3, .offset = -1 }, \
> + }, \
> + }
> +
> +#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + }, \
> + .drv = { \
> + { .drv_type = type0, .offset = -1 }, \
> + { .drv_type = type1, .offset = -1 }, \
> + { .drv_type = type2, .offset = -1 }, \
> + { .drv_type = type3, .offset = -1 }, \
> + }, \
> + }
> +
> +#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
> + drv2, drv3, pull0, pull1, \
> + pull2, pull3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + { .offset = -1 }, \
> + }, \
> + .drv = { \
> + { .drv_type = drv0, .offset = -1 }, \
> + { .drv_type = drv1, .offset = -1 }, \
> + { .drv_type = drv2, .offset = -1 }, \
> + { .drv_type = drv3, .offset = -1 }, \
> + }, \
> + .pull_type[0] = pull0, \
> + .pull_type[1] = pull1, \
> + .pull_type[2] = pull2, \
> + .pull_type[3] = pull3, \
> + }
> +
> +#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
> + iom2, iom3, drv0, drv1, drv2, \
> + drv3, offset0, offset1, \
> + offset2, offset3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .type = iom0, .offset = -1 }, \
> + { .type = iom1, .offset = -1 }, \
> + { .type = iom2, .offset = -1 }, \
> + { .type = iom3, .offset = -1 }, \
> + }, \
> + .drv = { \
> + { .drv_type = drv0, .offset = offset0 }, \
> + { .drv_type = drv1, .offset = offset1 }, \
> + { .drv_type = drv2, .offset = offset2 }, \
> + { .drv_type = drv3, .offset = offset3 }, \
> + }, \
> + }
> +
> +#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
> + label, iom0, iom1, iom2, \
> + iom3, drv0, drv1, drv2, \
> + drv3, offset0, offset1, \
> + offset2, offset3, pull0, \
> + pull1, pull2, pull3) \
> + { \
> + .bank_num = id, \
> + .nr_pins = pins, \
> + .name = label, \
> + .iomux = { \
> + { .type = iom0, .offset = -1 }, \
> + { .type = iom1, .offset = -1 }, \
> + { .type = iom2, .offset = -1 }, \
> + { .type = iom3, .offset = -1 }, \
> + }, \
> + .drv = { \
> + { .drv_type = drv0, .offset = offset0 }, \
> + { .drv_type = drv1, .offset = offset1 }, \
> + { .drv_type = drv2, .offset = offset2 }, \
> + { .drv_type = drv3, .offset = offset3 }, \
> + }, \
> + .pull_type[0] = pull0, \
> + .pull_type[1] = pull1, \
> + .pull_type[2] = pull2, \
> + .pull_type[3] = pull3, \
> + }
> +
> +/**
> + * struct rockchip_mux_recalced_data: represent a pin iomux data.
Why is this 'recalced'? This sounds more like a table describing each
chip's IOMUX.
> + * @num: bank number.
> + * @pin: pin number.
> + * @bit: index at register.
> + * @reg: register offset.
> + * @mask: mask bit
> + */
> +struct rockchip_mux_recalced_data {
> + u8 num;
> + u8 pin;
> + u32 reg;
> + u8 bit;
> + u8 mask;
> +};
> +
> +/**
> + * struct rockchip_mux_recalced_data: represent a pin iomux data.
> + * @bank_num: bank number.
> + * @pin: index at register or used to calc index.
> + * @func: the min pin.
> + * @route_offset: the max pin.
> + * @route_val: the register offset.
> + */
> +struct rockchip_mux_route_data {
> + u8 bank_num;
> + u8 pin;
> + u8 func;
> + u32 route_offset;
> + u32 route_val;
> +};
> +
> +/**
> + */
> +struct rockchip_pin_ctrl {
> + struct rockchip_pin_bank *pin_banks;
> + u32 nr_banks;
> + u32 nr_pins;
> + char *label;
> + enum rockchip_pinctrl_type type;
> + int grf_mux_offset;
> + int pmu_mux_offset;
> + int grf_drv_offset;
> + int pmu_drv_offset;
> + struct rockchip_mux_recalced_data *iomux_recalced;
> + u32 niomux_recalced;
> + struct rockchip_mux_route_data *iomux_routes;
> + u32 niomux_routes;
> +
> + void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit);
> + void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit);
> + int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit);
> +};
> +
> +/**
> + */
> +struct rockchip_pinctrl_priv {
> + struct rockchip_pin_ctrl *ctrl;
> + struct regmap *regmap_base;
> + struct regmap *regmap_pmu;
> +
> +};
> +
> +static int rockchip_verify_config(struct udevice *dev, u32 bank, u32 pin)
> +{
> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> +
> + if (bank >= ctrl->nr_banks) {
> + debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
> + return -EINVAL;
> + }
> +
> + if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
> + debug("pin conf pin %d >= %d\n", pin,
> + MAX_ROCKCHIP_GPIO_PER_BANK);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
> + {
> + .num = 1,
> + .pin = 0,
> + .reg = 0x418,
I assume this is a register offset. If so, I'd appreciate this to not be
hard-coded, but to be either (a) a symbolic constant or (b) preferrably
even an offsetof(...).
This applies for all uses throughout the file.
> + .bit = 0,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 1,
> + .reg = 0x418,
> + .bit = 2,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 2,
> + .reg = 0x418,
> + .bit = 4,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 3,
> + .reg = 0x418,
> + .bit = 6,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 4,
> + .reg = 0x418,
> + .bit = 8,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 5,
> + .reg = 0x418,
> + .bit = 10,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 6,
> + .reg = 0x418,
> + .bit = 12,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 7,
> + .reg = 0x418,
> + .bit = 14,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 8,
> + .reg = 0x41c,
> + .bit = 0,
> + .mask = 0x3
> + }, {
> + .num = 1,
> + .pin = 9,
> + .reg = 0x41c,
> + .bit = 2,
> + .mask = 0x3
> + },
> +};
> +
> +static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
> + {
> + .num = 2,
> + .pin = 20,
> + .reg = 0xe8,
> + .bit = 0,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 21,
> + .reg = 0xe8,
> + .bit = 4,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 22,
> + .reg = 0xe8,
> + .bit = 8,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 23,
> + .reg = 0xe8,
> + .bit = 12,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 24,
> + .reg = 0xd4,
> + .bit = 12,
> + .mask = 0x7
> + },
> +};
> +
> +static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
> + {
> + .num = 2,
> + .pin = 12,
> + .reg = 0x24,
> + .bit = 8,
> + .mask = 0x3
> + }, {
> + .num = 2,
> + .pin = 15,
> + .reg = 0x28,
> + .bit = 0,
> + .mask = 0x7
> + }, {
> + .num = 2,
> + .pin = 23,
> + .reg = 0x30,
> + .bit = 14,
> + .mask = 0x3
> + },
> +};
> +
> +static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
> + int *reg, u8 *bit, int *mask)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct rockchip_mux_recalced_data *data;
> + int i;
> +
> + for (i = 0; i < ctrl->niomux_recalced; i++) {
> + data = &ctrl->iomux_recalced[i];
> + if (data->num == bank->bank_num &&
> + data->pin == pin)
> + break;
> + }
> +
> + if (i >= ctrl->niomux_recalced)
> + return;
> +
> + *reg = data->reg;
> + *mask = data->mask;
> + *bit = data->bit;
> +}
> +
> +static struct rockchip_mux_route_data px30_mux_route_data[] = {
The PX30-specific structures should be added together with the PX30
enablement series. It doesn't make sense to have them here now, as U-Boot
doesn't know about the PX30 yet.
> + {
> + /* cif-d2m0 */
> + .bank_num = 2,
> + .pin = 0,
> + .func = 1,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 7),
> + }, {
> + /* cif-d2m1 */
> + .bank_num = 3,
> + .pin = 3,
> + .func = 3,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 7) | BIT(7),
> + }, {
> + /* pdm-m0 */
> + .bank_num = 3,
> + .pin = 22,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 8),
> + }, {
> + /* pdm-m1 */
> + .bank_num = 2,
> + .pin = 22,
> + .func = 1,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 8) | BIT(8),
> + }, {
> + /* uart2-rxm0 */
> + .bank_num = 1,
> + .pin = 26,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 9),
> + }, {
> + /* uart2-rxm1 */
> + .bank_num = 2,
> + .pin = 14,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 9) | BIT(9),
> + }, {
> + /* uart3-rxm0 */
> + .bank_num = 0,
> + .pin = 17,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 10),
> + }, {
> + /* uart3-rxm1 */
> + .bank_num = 1,
> + .pin = 13,
> + .func = 2,
> + .route_offset = 0x184,
> + .route_val = BIT(16 + 10) | BIT(10),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
> + {
> + /* spi-0 */
> + .bank_num = 1,
> + .pin = 10,
> + .func = 1,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 3) | BIT(16 + 4),
> + }, {
> + /* spi-1 */
> + .bank_num = 1,
> + .pin = 27,
> + .func = 3,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
> + }, {
> + /* spi-2 */
> + .bank_num = 0,
> + .pin = 13,
> + .func = 2,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
> + }, {
> + /* i2s-0 */
> + .bank_num = 1,
> + .pin = 5,
> + .func = 1,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 5),
> + }, {
> + /* i2s-1 */
> + .bank_num = 0,
> + .pin = 14,
> + .func = 1,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 5) | BIT(5),
> + }, {
> + /* emmc-0 */
> + .bank_num = 1,
> + .pin = 22,
> + .func = 2,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 6),
> + }, {
> + /* emmc-1 */
> + .bank_num = 2,
> + .pin = 4,
> + .func = 2,
> + .route_offset = 0x144,
> + .route_val = BIT(16 + 6) | BIT(6),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
> + {
> + /* pwm0-0 */
> + .bank_num = 0,
> + .pin = 26,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16),
> + }, {
> + /* pwm0-1 */
> + .bank_num = 3,
> + .pin = 21,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16) | BIT(0),
> + }, {
> + /* pwm1-0 */
> + .bank_num = 0,
> + .pin = 27,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 1),
> + }, {
> + /* pwm1-1 */
> + .bank_num = 0,
> + .pin = 30,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 1) | BIT(1),
> + }, {
> + /* pwm2-0 */
> + .bank_num = 0,
> + .pin = 28,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 2),
> + }, {
> + /* pwm2-1 */
> + .bank_num = 1,
> + .pin = 12,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 2) | BIT(2),
> + }, {
> + /* pwm3-0 */
> + .bank_num = 3,
> + .pin = 26,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 3),
> + }, {
> + /* pwm3-1 */
> + .bank_num = 1,
> + .pin = 11,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 3) | BIT(3),
> + }, {
> + /* sdio-0_d0 */
> + .bank_num = 1,
> + .pin = 1,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 4),
> + }, {
> + /* sdio-1_d0 */
> + .bank_num = 3,
> + .pin = 2,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 4) | BIT(4),
> + }, {
> + /* spi-0_rx */
> + .bank_num = 0,
> + .pin = 13,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 5),
> + }, {
> + /* spi-1_rx */
> + .bank_num = 2,
> + .pin = 0,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 5) | BIT(5),
> + }, {
> + /* emmc-0_cmd */
> + .bank_num = 1,
> + .pin = 22,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 7),
> + }, {
> + /* emmc-1_cmd */
> + .bank_num = 2,
> + .pin = 4,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 7) | BIT(7),
> + }, {
> + /* uart2-0_rx */
> + .bank_num = 1,
> + .pin = 19,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 8),
> + }, {
> + /* uart2-1_rx */
> + .bank_num = 1,
> + .pin = 10,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 8) | BIT(8),
> + }, {
> + /* uart1-0_rx */
> + .bank_num = 1,
> + .pin = 10,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 11),
> + }, {
> + /* uart1-1_rx */
> + .bank_num = 3,
> + .pin = 13,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 11) | BIT(11),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
> + {
> + /* edphdmi_cecinoutt1 */
> + .bank_num = 7,
> + .pin = 16,
> + .func = 2,
> + .route_offset = 0x264,
> + .route_val = BIT(16 + 12) | BIT(12),
> + }, {
> + /* edphdmi_cecinout */
> + .bank_num = 7,
> + .pin = 23,
> + .func = 4,
> + .route_offset = 0x264,
> + .route_val = BIT(16 + 12),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
> + {
> + /* uart2dbg_rxm0 */
> + .bank_num = 1,
> + .pin = 1,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16) | BIT(16 + 1),
> + }, {
> + /* uart2dbg_rxm1 */
> + .bank_num = 2,
> + .pin = 1,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
> + }, {
> + /* gmac-m1_rxd0 */
> + .bank_num = 1,
> + .pin = 11,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 2) | BIT(2),
> + }, {
> + /* gmac-m1-optimized_rxd3 */
> + .bank_num = 1,
> + .pin = 14,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 10) | BIT(10),
> + }, {
> + /* pdm_sdi0m0 */
> + .bank_num = 2,
> + .pin = 19,
> + .func = 2,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 3),
> + }, {
> + /* pdm_sdi0m1 */
> + .bank_num = 1,
> + .pin = 23,
> + .func = 3,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 3) | BIT(3),
> + }, {
> + /* spi_rxdm2 */
> + .bank_num = 3,
> + .pin = 2,
> + .func = 4,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
> + }, {
> + /* i2s2_sdim0 */
> + .bank_num = 1,
> + .pin = 24,
> + .func = 1,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 6),
> + }, {
> + /* i2s2_sdim1 */
> + .bank_num = 3,
> + .pin = 2,
> + .func = 6,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 6) | BIT(6),
> + }, {
> + /* card_iom1 */
> + .bank_num = 2,
> + .pin = 22,
> + .func = 3,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 7) | BIT(7),
> + }, {
> + /* tsp_d5m1 */
> + .bank_num = 2,
> + .pin = 16,
> + .func = 3,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 8) | BIT(8),
> + }, {
> + /* cif_data5m1 */
> + .bank_num = 2,
> + .pin = 16,
> + .func = 4,
> + .route_offset = 0x50,
> + .route_val = BIT(16 + 9) | BIT(9),
> + },
> +};
> +
> +static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
> + {
> + /* uart2dbga_rx */
> + .bank_num = 4,
> + .pin = 8,
> + .func = 2,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 10) | BIT(16 + 11),
> + }, {
> + /* uart2dbgb_rx */
> + .bank_num = 4,
> + .pin = 16,
> + .func = 2,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
> + }, {
> + /* uart2dbgc_rx */
> + .bank_num = 4,
> + .pin = 19,
> + .func = 1,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
> + }, {
> + /* pcie_clkreqn */
> + .bank_num = 2,
> + .pin = 26,
> + .func = 2,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 14),
> + }, {
> + /* pcie_clkreqnb */
> + .bank_num = 4,
> + .pin = 24,
> + .func = 1,
> + .route_offset = 0xe21c,
> + .route_val = BIT(16 + 14) | BIT(14),
> + },
> +};
> +
> +static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
> + int mux, u32 *reg, u32 *value)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct rockchip_mux_route_data *data;
> + int i;
> +
> + for (i = 0; i < ctrl->niomux_routes; i++) {
> + data = &ctrl->iomux_routes[i];
> + if ((data->bank_num == bank->bank_num) &&
> + (data->pin == pin) && (data->func == mux))
> + break;
> + }
> +
> + if (i >= ctrl->niomux_routes)
> + return false;
> +
> + *reg = data->route_offset;
> + *value = data->route_val;
> +
> + return true;
> +}
> +
> +static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + unsigned int val;
> + int reg, ret, mask, mux_type;
> + u8 bit;
> +
> + if (iomux_num > 3)
> + return -EINVAL;
> +
> + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
> + debug("pin %d is unrouted\n", pin);
> + return -EINVAL;
> + }
> +
> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
> + return RK_FUNC_GPIO;
> +
> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + ? priv->regmap_pmu : priv->regmap_base;
> +
> + /* get basic quadrupel of mux registers and the correct reg inside */
> + mux_type = bank->iomux[iomux_num].type;
> + reg = bank->iomux[iomux_num].offset;
> + if (mux_type & IOMUX_WIDTH_4BIT) {
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> + } else if (mux_type & IOMUX_WIDTH_3BIT) {
> + if ((pin % 8) >= 5)
> + reg += 0x4;
> + bit = (pin % 8 % 5) * 3;
"(pin % 8 % 5)" ... really? This just begs for trouble down the road (and
it's not self-explanatory at all)... please restructure.
> + mask = 0x7;
> + } else {
> + bit = (pin % 8) * 2;
> + mask = 0x3;
> + }
Given that this is not self-explanatory: please add a comment, so people
can follow it. And it wouldn't hurt if the magic calculations were a bit
less magic...
> +
> + if (bank->recalced_mask & BIT(pin))
> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
> +
> + ret = regmap_read(regmap, reg, &val);
> + if (ret)
> + return ret;
> +
> + return ((val >> bit) & mask);
> +}
> +
> +static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int banknum,
> + int index)
> +{ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> +
> + return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
> +}
> +
> +static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
> + int pin, int mux)
> +{
> + int iomux_num = (pin / 8);
> +
> + if (iomux_num > 3)
> + return -EINVAL;
Why is iomux_num limited to 3? If this is a configurable constant for the
driver, please make it at least a symbolic constant... if this is a
SOC-specific limit, then you should go through the driver-data to access
it and check against this limit.
> +
> + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
> + debug("pin %d is unrouted\n", pin);
> + return -EINVAL;
> + }
> +
> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
> + if (mux != IOMUX_GPIO_ONLY) {
> + debug("pin %d only supports a gpio mux\n", pin);
> + return -ENOTSUPP;
> + }
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * Set a new mux function for a pin.
> + *
> + * The register is divided into the upper and lower 16 bit. When changing
> + * a value, the previous register value is not read and changed. Instead
> + * it seems the changed bits are marked in the upper 16 bit, while the
> + * changed value gets set in the same offset in the lower 16 bit.
> + * All pin settings seem to be 2 bit wide in both the upper and lower
> + * parts.
> + * @bank: pin bank to change
> + * @pin: pin to change
> + * @mux: new mux function to set
> + */
> +static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask, mux_type;
> + u8 bit;
> + u32 data, route_reg, route_val;
> +
> + ret = rockchip_verify_mux(bank, pin, mux);
> + if (ret < 0)
> + return ret;
> +
> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
> + return 0;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
> +
> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
> + ? priv->regmap_pmu : priv->regmap_base;
> +
> + /* get basic quadrupel of mux registers and the correct reg inside */
> + mux_type = bank->iomux[iomux_num].type;
> + reg = bank->iomux[iomux_num].offset;
> + if (mux_type & IOMUX_WIDTH_4BIT) {
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> + } else if (mux_type & IOMUX_WIDTH_3BIT) {
> + if ((pin % 8) >= 5)
> + reg += 0x4;
> + bit = (pin % 8 % 5) * 3;
> + mask = 0x7;
> + } else {
> + bit = (pin % 8) * 2;
> + mask = 0x3;
> + }
The same magic as above.
Note, that if you perform the same calculations in multiple places, you
should create a helper function and call it multiple times.
> +
> + if (bank->recalced_mask & BIT(pin))
> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
> +
> + if (bank->route_mask & BIT(pin)) {
> + if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
> + &route_val)) {
> + ret = regmap_write(regmap, route_reg, route_val);
> + if (ret)
> + return ret;
> + }
> + }
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> + ret = regmap_write(regmap, reg, data);
> +
> + return ret;
> +}
> +
> +#define PX30_PULL_PMU_OFFSET 0x10
> +#define PX30_PULL_GRF_OFFSET 0x60
> +#define PX30_PULL_BITS_PER_PIN 2
> +#define PX30_PULL_PINS_PER_REG 8
> +#define PX30_PULL_BANK_STRIDE 16
Anything PX30-related needs to come in with the PX30 enablement series.
Thanks.
> +
> +static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = PX30_PULL_PMU_OFFSET;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = PX30_PULL_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % PX30_PULL_PINS_PER_REG);
> + *bit *= PX30_PULL_BITS_PER_PIN;
> +}
> +
> +#define PX30_DRV_PMU_OFFSET 0x20
> +#define PX30_DRV_GRF_OFFSET 0xf0
> +#define PX30_DRV_BITS_PER_PIN 2
> +#define PX30_DRV_PINS_PER_REG 8
> +#define PX30_DRV_BANK_STRIDE 16
> +
> +static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = PX30_DRV_PMU_OFFSET;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = PX30_DRV_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
> + *bit = (pin_num % PX30_DRV_PINS_PER_REG);
> + *bit *= PX30_DRV_BITS_PER_PIN;
> +}
> +
> +#define PX30_SCHMITT_PMU_OFFSET 0x38
> +#define PX30_SCHMITT_GRF_OFFSET 0xc0
> +#define PX30_SCHMITT_PINS_PER_PMU_REG 16
> +#define PX30_SCHMITT_BANK_STRIDE 16
> +#define PX30_SCHMITT_PINS_PER_GRF_REG 8
> +
> +static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num,
> + struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int pins_per_reg;
> +
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = PX30_SCHMITT_PMU_OFFSET;
> + pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = PX30_SCHMITT_GRF_OFFSET;
> + pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
> + *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
> + }
> + *reg += ((pin_num / pins_per_reg) * 4);
> + *bit = pin_num % pins_per_reg;
> +
> + return 0;
> +}
> +
> +#define RV1108_PULL_PMU_OFFSET 0x10
> +#define RV1108_PULL_OFFSET 0x110
> +#define RV1108_PULL_PINS_PER_REG 8
> +#define RV1108_PULL_BITS_PER_PIN 2
> +#define RV1108_PULL_BANK_STRIDE 16
> +
> +static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 24 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RV1108_PULL_PMU_OFFSET;
> + } else {
> + *reg = RV1108_PULL_OFFSET;
> + *regmap = priv->regmap_base;
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
> + *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
> + *bit *= RV1108_PULL_BITS_PER_PIN;
> +}
> +
> +#define RV1108_DRV_PMU_OFFSET 0x20
> +#define RV1108_DRV_GRF_OFFSET 0x210
> +#define RV1108_DRV_BITS_PER_PIN 2
> +#define RV1108_DRV_PINS_PER_REG 8
> +#define RV1108_DRV_BANK_STRIDE 16
> +
> +static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 24 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RV1108_DRV_PMU_OFFSET;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RV1108_DRV_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
> + }
> +
> + *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
> + *bit = pin_num % RV1108_DRV_PINS_PER_REG;
> + *bit *= RV1108_DRV_BITS_PER_PIN;
> +}
> +
> +#define RV1108_SCHMITT_PMU_OFFSET 0x30
> +#define RV1108_SCHMITT_GRF_OFFSET 0x388
> +#define RV1108_SCHMITT_BANK_STRIDE 8
> +#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
> +#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
> +
> +static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num,
> + struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int pins_per_reg;
> +
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RV1108_SCHMITT_PMU_OFFSET;
> + pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RV1108_SCHMITT_GRF_OFFSET;
> + pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
> + *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
> + }
> + *reg += ((pin_num / pins_per_reg) * 4);
> + *bit = pin_num % pins_per_reg;
> +
> + return 0;
> +}
> +
> +#define RK2928_PULL_OFFSET 0x118
> +#define RK2928_PULL_PINS_PER_REG 16
> +#define RK2928_PULL_BANK_STRIDE 8
> +
> +static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK2928_PULL_OFFSET;
> + *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
> + *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
> +
> + *bit = pin_num % RK2928_PULL_PINS_PER_REG;
> +};
> +
> +#define RK3128_PULL_OFFSET 0x118
> +
> +static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK3128_PULL_OFFSET;
> + *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
> +
> + *bit = pin_num % RK2928_PULL_PINS_PER_REG;
> +}
> +
> +#define RK3188_PULL_OFFSET 0x164
> +#define RK3188_PULL_BITS_PER_PIN 2
> +#define RK3188_PULL_PINS_PER_REG 8
> +#define RK3188_PULL_BANK_STRIDE 16
> +#define RK3188_PULL_PMU_OFFSET 0x64
> +
> +static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 12 pins of the first bank are located elsewhere */
> + if (bank->bank_num == 0 && pin_num < 12) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3188_PULL_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3188_PULL_OFFSET;
> +
> + /* correct the offset, as it is the 2nd pull register */
> + *reg -= 4;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + /*
> + * The bits in these registers have an inverse ordering
> + * with the lowest pin being in bits 15:14 and the highest
> + * pin in bits 1:0
> + */
> + *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3288_PULL_OFFSET 0x140
> +static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 24 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3188_PULL_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3288_PULL_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3288_DRV_PMU_OFFSET 0x70
> +#define RK3288_DRV_GRF_OFFSET 0x1c0
> +#define RK3288_DRV_BITS_PER_PIN 2
> +#define RK3288_DRV_PINS_PER_REG 8
> +#define RK3288_DRV_BANK_STRIDE 16
> +
> +static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 24 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3288_DRV_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3288_DRV_PINS_PER_REG;
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3288_DRV_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3228_PULL_OFFSET 0x100
> +
> +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK3228_PULL_OFFSET;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> +}
> +
> +#define RK3228_DRV_GRF_OFFSET 0x200
> +
> +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK3228_DRV_GRF_OFFSET;
> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> +}
> +
> +#define RK3368_PULL_GRF_OFFSET 0x100
> +#define RK3368_PULL_PMU_OFFSET 0x10
> +
> +static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3368_PULL_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3368_PULL_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + }
> +}
> +
> +#define RK3368_DRV_PMU_OFFSET 0x20
> +#define RK3368_DRV_GRF_OFFSET 0x200
> +
> +static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The first 32 pins of the first bank are located in PMU */
> + if (bank->bank_num == 0) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3368_DRV_PMU_OFFSET;
> +
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3288_DRV_PINS_PER_REG;
> + *bit *= RK3288_DRV_BITS_PER_PIN;
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3368_DRV_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 2nd bank */
> + *reg -= 0x10;
> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
> + *bit *= RK3288_DRV_BITS_PER_PIN;
Why suddenly RK3288_ symbolic constants? This is the RK3368 setup code.
> + }
> +}
> +
> +#define RK3399_PULL_GRF_OFFSET 0xe040
> +#define RK3399_PULL_PMU_OFFSET 0x40
> +#define RK3399_DRV_3BITS_PER_PIN 3
> +
> +static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + /* The bank0:16 and bank1:32 pins are located in PMU */
> + if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
> + *regmap = priv->regmap_pmu;
> + *reg = RK3399_PULL_PMU_OFFSET;
> +
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> +
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
> + *bit *= RK3188_PULL_BITS_PER_PIN;
Why are these RK3188_ symbolic constants in the RK3399 path?
> + } else {
> + *regmap = priv->regmap_base;
> + *reg = RK3399_PULL_GRF_OFFSET;
> +
> + /* correct the offset, as we're starting with the 3rd bank */
> + *reg -= 0x20;
> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
> +
> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
> + *bit *= RK3188_PULL_BITS_PER_PIN;
> + }
> +}
> +
> +static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int drv_num = (pin_num / 8);
> +
> + /* The bank0:16 and bank1:32 pins are located in PMU */
> + if ((bank->bank_num == 0) || (bank->bank_num == 1))
> + *regmap = priv->regmap_pmu;
> + else
> + *regmap = priv->regmap_base;
> +
> + *reg = bank->drv[drv_num].offset;
> + if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
> + (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
> + *bit = (pin_num % 8) * 3;
> + else
> + *bit = (pin_num % 8) * 2;
> +}
> +
> +static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
> + { 2, 4, 8, 12, -1, -1, -1, -1 },
> + { 3, 6, 9, 12, -1, -1, -1, -1 },
> + { 5, 10, 15, 20, -1, -1, -1, -1 },
> + { 4, 6, 8, 10, 12, 14, 16, 18 },
> + { 4, 7, 10, 13, 16, 19, 22, 26 }
> +};
Please rewrite this (and add a comment), so it isn't a magic array.
> +
> +static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct regmap *regmap;
> + int reg, ret, i;
> + u32 data, rmask_bits, temp;
> + u8 bit;
> + int drv_type = bank->drv[pin_num / 8].drv_type;
> +
> + debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
> + pin_num, strength);
> +
> + ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
> +
> + ret = -EINVAL;
> + for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
> + if (rockchip_perpin_drv_list[drv_type][i] == strength) {
> + ret = i;
> + break;
> + } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
> + ret = rockchip_perpin_drv_list[drv_type][i];
> + break;
> + }
> + }
> +
> + if (ret < 0) {
> + debug("unsupported driver strength %d\n", strength);
> + return ret;
> + }
> +
> + switch (drv_type) {
> + case DRV_TYPE_IO_1V8_3V0_AUTO:
> + case DRV_TYPE_IO_3V3_ONLY:
> + rmask_bits = RK3399_DRV_3BITS_PER_PIN;
> + switch (bit) {
> + case 0 ... 12:
> + /* regular case, nothing to do */
> + break;
> + case 15:
> + /*
> + * drive-strength offset is special, as it is spread
> + * over 2 registers, the bit data[15] contains bit 0
> + * of the value while temp[1:0] contains bits 2 and 1
> + */
> + data = (ret & 0x1) << 15;
> + temp = (ret >> 0x1) & 0x3;
> +
> + data |= BIT(31);
> + ret = regmap_write(regmap, reg, data);
> + if (ret)
> + return ret;
> +
> + temp |= (0x3 << 16);
> + reg += 0x4;
> + ret = regmap_write(regmap, reg, temp);
> +
> + return ret;
> + case 18 ... 21:
> + /* setting fully enclosed in the second register */
> + reg += 4;
> + bit -= 16;
> + break;
> + default:
> + debug("unsupported bit: %d for pinctrl drive type: %d\n",
> + bit, drv_type);
> + return -EINVAL;
> + }
> + break;
> + case DRV_TYPE_IO_DEFAULT:
> + case DRV_TYPE_IO_1V8_OR_3V0:
> + case DRV_TYPE_IO_1V8_ONLY:
> + rmask_bits = RK3288_DRV_BITS_PER_PIN;
> + break;
> + default:
> + debug("unsupported pinctrl drive type: %d\n",
> + drv_type);
> + return -EINVAL;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << rmask_bits) - 1) << (bit + 16);
> + data |= (ret << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + return ret;
> +}
> +
> +static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
> + {
> + PIN_CONFIG_BIAS_DISABLE,
> + PIN_CONFIG_BIAS_PULL_UP,
> + PIN_CONFIG_BIAS_PULL_DOWN,
> + PIN_CONFIG_BIAS_BUS_HOLD
> + },
> + {
> + PIN_CONFIG_BIAS_DISABLE,
> + PIN_CONFIG_BIAS_PULL_DOWN,
> + PIN_CONFIG_BIAS_DISABLE,
> + PIN_CONFIG_BIAS_PULL_UP
> + },
> +};
> +
> +static int rockchip_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct regmap *regmap;
> + int reg, ret, i, pull_type;
> + u8 bit;
> + u32 data;
> +
> + debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
> + pin_num, pull);
> +
> + /* rk3066b does support any pulls */
> + if (ctrl->type == RK3066B)
> + return pull ? -EINVAL : 0;
> +
> + ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
> +
> + switch (ctrl->type) {
> + case RK2928:
No RK2928 in U-Boot...
> + case RK3128:
> + data = BIT(bit + 16);
> + if (pull == PIN_CONFIG_BIAS_DISABLE)
> + data |= BIT(bit);
> + ret = regmap_write(regmap, reg, data);
> + break;
> + case PX30:
...and neither a PX30 in U-Boot as of now.
> + case RV1108:
> + case RK3188:
> + case RK3288:
> + case RK3368:
> + case RK3399:
> + pull_type = bank->pull_type[pin_num / 8];
> + ret = -EINVAL;
> + for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
> + i++) {
> + if (rockchip_pull_list[pull_type][i] == pull) {
> + ret = i;
> + break;
> + }
> + }
> +
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> + data |= (ret << bit);
> +
> + ret = regmap_write(regmap, reg, data);
> + break;
> + default:
> + debug("unsupported pinctrl type\n");
> + return -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +#define RK3328_SCHMITT_BITS_PER_PIN 1
> +#define RK3328_SCHMITT_PINS_PER_REG 16
> +#define RK3328_SCHMITT_BANK_STRIDE 8
> +#define RK3328_SCHMITT_GRF_OFFSET 0x380
> +
> +static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num,
> + struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> + *reg = RK3328_SCHMITT_GRF_OFFSET;
> +
> + *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
> + *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
> +
> + return 0;
> +}
> +
> +static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit;
> + u32 data;
> +
> + debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
> + pin_num, enable);
> +
> + ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
> + if (ret)
> + return ret;
> +
> + /* enable the write to the equivalent lower bits */
> + data = BIT(bit + 16) | (enable << bit);
> +
> + return regmap_write(regmap, reg, data);
> +}
> +
> +/*
> + * Pinconf_ops handling
> + */
> +static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
> + unsigned int pull)
> +{
> + switch (ctrl->type) {
> + case RK2928:
> + case RK3128:
> + return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
> + pull == PIN_CONFIG_BIAS_DISABLE);
> + case RK3066B:
> + return pull ? false : true;
> + case PX30:
> + case RV1108:
> + case RK3188:
> + case RK3288:
> + case RK3368:
> + case RK3399:
> + return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
> + }
> +
> + return false;
> +}
> +
> +/* set the pin config settings for a specified pin */
> +static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
> + u32 pin, u32 param, u32 arg)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + int rc;
> +
> + switch (param) {
> + case PIN_CONFIG_BIAS_DISABLE:
> + rc = rockchip_set_pull(bank, pin, param);
> + if (rc)
> + return rc;
> + break;
> +
> + case PIN_CONFIG_BIAS_PULL_UP:
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
> + case PIN_CONFIG_BIAS_BUS_HOLD:
> + if (!rockchip_pinconf_pull_valid(ctrl, param))
> + return -ENOTSUPP;
> +
> + if (!arg)
> + return -EINVAL;
> +
> + rc = rockchip_set_pull(bank, pin, param);
> + if (rc)
> + return rc;
> + break;
> +
> + case PIN_CONFIG_DRIVE_STRENGTH:
> + if (!ctrl->drv_calc_reg)
> + return -ENOTSUPP;
> +
> + rc = rockchip_set_drive_perpin(bank, pin, arg);
> + if (rc < 0)
> + return rc;
> + break;
> +
> + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
> + if (!ctrl->schmitt_calc_reg)
> + return -ENOTSUPP;
> +
> + rc = rockchip_set_schmitt(bank, pin, arg);
> + if (rc < 0)
> + return rc;
> + break;
> +
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static const struct pinconf_param rockchip_conf_params[] = {
> + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
> + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
> + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
> + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
> + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
> + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
> + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
> + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
> + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
> +};
> +
> +static int rockchip_pinconf_prop_name_to_param(const char *property,
> + u32 *default_value)
> +{
> + const struct pinconf_param *p, *end;
> +
> + p = rockchip_conf_params;
> + end = p + sizeof(rockchip_conf_params) / sizeof(struct pinconf_param);
> +
> + /* See if this pctldev supports this parameter */
> + for (; p < end; p++) {
> + if (!strcmp(property, p->property)) {
> + *default_value = p->default_value;
> + return p->param;
> + }
> + }
> +
> + *default_value = 0;
> + return -EPERM;
> +}
> +
> +static int rockchip_pinctrl_set_state(struct udevice *dev,
> + struct udevice *config)
> +{
> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
> + const void *blob = gd->fdt_blob;
> + int node = dev_of_offset(config);
> + u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
> + u32 bank, pin, mux, conf, arg, default_val;
> + int ret, count, i;
> + const char *prop_name;
> + int pcfg_node, property_offset, prop_len, param;
> + const void *value;
> +
> + count = fdtdec_get_int_array_count(blob, node, "rockchip,pins",
> + cells, ARRAY_SIZE(cells));
> + if (count < 0) {
> + debug("%s: bad array %d\n", __func__, count);
> + return -EINVAL;
> + }
> +
> + if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
> + debug("%s: unsupported pins array count %d\n",
> + __func__, count);
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < (count >> 2); i++) {
> + bank = cells[4 * i + 0];
> + pin = cells[4 * i + 1];
> + mux = cells[4 * i + 2];
> + conf = cells[4 * i + 3];
> +
> + ret = rockchip_verify_config(dev, bank, pin);
> + if (ret)
> + return ret;
> +
> + ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
> + if (ret)
> + return ret;
> +
> + pcfg_node = fdt_node_offset_by_phandle(blob, conf);
> + if (pcfg_node < 0)
> + return -ENODEV;
> +
> + fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
> + value = fdt_getprop_by_offset(blob, property_offset,
> + &prop_name, &prop_len);
> + if (!value)
> + return -ENOENT;
> +
> + param = rockchip_pinconf_prop_name_to_param(prop_name,
> + &default_val);
> + if (param < 0)
> + break;
> +
> + if (prop_len >= sizeof(fdt32_t))
> + arg = fdt32_to_cpu(*(fdt32_t *)value);
> + else
> + arg = default_val;
> +
> + ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
> + param, arg);
> + if (ret) {
> + debug("%s: rockchip_pinconf_set fail: %d\n",
> + __func__, ret);
> + return ret;
> + }
> + }
> + }
> +
> + return 0;
> +}
> +
> +static struct pinctrl_ops rockchip_pinctrl_ops = {
> + .set_state = rockchip_pinctrl_set_state,
> + .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
> +};
> +
> +/* retrieve the soc specific data */
> +static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *dev)
> +{
> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl =
> + (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
> + struct rockchip_pin_bank *bank;
> + int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
> +
> + grf_offs = ctrl->grf_mux_offset;
> + pmu_offs = ctrl->pmu_mux_offset;
> + drv_pmu_offs = ctrl->pmu_drv_offset;
> + drv_grf_offs = ctrl->grf_drv_offset;
> + bank = ctrl->pin_banks;
> +
> + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
> + int bank_pins = 0;
> +
> + bank->priv = priv;
> + bank->pin_base = ctrl->nr_pins;
> + ctrl->nr_pins += bank->nr_pins;
> +
> + /* calculate iomux and drv offsets */
> + for (j = 0; j < 4; j++) {
> + struct rockchip_iomux *iom = &bank->iomux[j];
> + struct rockchip_drv *drv = &bank->drv[j];
> + int inc;
> +
> + if (bank_pins >= bank->nr_pins)
> + break;
> +
> + /* preset iomux offset value, set new start value */
> + if (iom->offset >= 0) {
> + if (iom->type & IOMUX_SOURCE_PMU)
> + pmu_offs = iom->offset;
> + else
> + grf_offs = iom->offset;
> + } else { /* set current iomux offset */
> + iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> + pmu_offs : grf_offs;
> + }
> +
> + /* preset drv offset value, set new start value */
> + if (drv->offset >= 0) {
> + if (iom->type & IOMUX_SOURCE_PMU)
> + drv_pmu_offs = drv->offset;
> + else
> + drv_grf_offs = drv->offset;
> + } else { /* set current drv offset */
> + drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
> + drv_pmu_offs : drv_grf_offs;
> + }
> +
> + debug("bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
> + i, j, iom->offset, drv->offset);
> +
> + /*
> + * Increase offset according to iomux width.
> + * 4bit iomux'es are spread over two registers.
> + */
> + inc = (iom->type & (IOMUX_WIDTH_4BIT |
> + IOMUX_WIDTH_3BIT)) ? 8 : 4;
> + if (iom->type & IOMUX_SOURCE_PMU)
> + pmu_offs += inc;
> + else
> + grf_offs += inc;
> +
> + /*
> + * Increase offset according to drv width.
> + * 3bit drive-strenth'es are spread over two registers.
> + */
> + if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
> + (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
> + inc = 8;
> + else
> + inc = 4;
> +
> + if (iom->type & IOMUX_SOURCE_PMU)
> + drv_pmu_offs += inc;
> + else
> + drv_grf_offs += inc;
> +
> + bank_pins += 8;
> + }
> +
> + /* calculate the per-bank recalced_mask */
> + for (j = 0; j < ctrl->niomux_recalced; j++) {
> + int pin = 0;
> +
> + if (ctrl->iomux_recalced[j].num == bank->bank_num) {
> + pin = ctrl->iomux_recalced[j].pin;
> + bank->recalced_mask |= BIT(pin);
> + }
> + }
> +
> + /* calculate the per-bank route_mask */
> + for (j = 0; j < ctrl->niomux_routes; j++) {
> + int pin = 0;
> +
> + if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
> + pin = ctrl->iomux_routes[j].pin;
> + bank->route_mask |= BIT(pin);
> + }
> + }
> + }
> +
> + return ctrl;
> +}
> +
> +static int rockchip_pinctrl_probe(struct udevice *dev)
> +{
> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
> + struct rockchip_pin_ctrl *ctrl;
> + struct udevice *syscon;
> + struct regmap *regmap;
> + int ret = 0;
> +
> + /* get rockchip grf syscon phandle */
> + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,grf",
> + &syscon);
> + if (ret) {
> + debug("unable to find rockchip,grf syscon device (%d)\n", ret);
> + return ret;
> + }
> +
> + /* get grf-reg base address */
> + regmap = syscon_get_regmap(syscon);
> + if (!regmap) {
> + debug("unable to find rockchip grf regmap\n");
> + return -ENODEV;
> + }
> + priv->regmap_base = regmap;
> +
> + /* option: get pmu-reg base address */
> + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "rockchip,pmu",
> + &syscon);
> + if (!ret) {
> + /* get pmugrf-reg base address */
> + regmap = syscon_get_regmap(syscon);
> + if (!regmap) {
> + debug("unable to find rockchip pmu regmap\n");
> + return -ENODEV;
> + }
> + priv->regmap_pmu = regmap;
> + }
> +
> + ctrl = rockchip_pinctrl_get_soc_data(dev);
> + if (!ctrl) {
> + debug("driver data not available\n");
> + return -EINVAL;
> + }
> +
> + priv->ctrl = ctrl;
> + return 0;
> +}
> +
> +static struct rockchip_pin_bank px30_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU
> + ),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT
> + ),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT
> + ),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT
> + ),
> +};
> +
> +static struct rockchip_pin_ctrl px30_pin_ctrl = {
> + .pin_banks = px30_pin_banks,
> + .nr_banks = ARRAY_SIZE(px30_pin_banks),
> + .label = "PX30-GPIO",
> + .type = PX30,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .iomux_routes = px30_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
> + .pull_calc_reg = px30_calc_pull_reg_and_bit,
> + .drv_calc_reg = px30_calc_drv_reg_and_bit,
> + .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rv1108_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
> +};
> +
> +static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
> + .pin_banks = rv1108_pin_banks,
> + .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
> + .label = "RV1108-GPIO",
> + .type = RV1108,
> + .grf_mux_offset = 0x10,
> + .pmu_mux_offset = 0x0,
> + .iomux_recalced = rv1108_mux_recalced_data,
> + .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
> + .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
> + .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
> + .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk2928_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
> + .pin_banks = rk2928_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
> + .label = "RK2928-GPIO",
> + .type = RK2928,
> + .grf_mux_offset = 0xa8,
> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3036_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
> + .pin_banks = rk3036_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
> + .label = "RK3036-GPIO",
> + .type = RK2928,
> + .grf_mux_offset = 0xa8,
> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3066a_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> + PIN_BANK(4, 32, "gpio4"),
> + PIN_BANK(6, 16, "gpio6"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
> + .pin_banks = rk3066a_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
> + .label = "RK3066a-GPIO",
> + .type = RK2928,
> + .grf_mux_offset = 0xa8,
> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3066b_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
> + .pin_banks = rk3066b_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
> + .label = "RK3066b-GPIO",
> + .type = RK3066B,
> + .grf_mux_offset = 0x60,
> +};
> +
> +static struct rockchip_pin_bank rk3128_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
> + .pin_banks = rk3128_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
> + .label = "RK3128-GPIO",
> + .type = RK3128,
> + .grf_mux_offset = 0xa8,
> + .iomux_recalced = rk3128_mux_recalced_data,
> + .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
> + .iomux_routes = rk3128_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
> + .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3188_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
> + .pin_banks = rk3188_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
> + .label = "RK3188-GPIO",
> + .type = RK3188,
> + .grf_mux_offset = 0x60,
> + .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3228_pin_banks[] = {
> + PIN_BANK(0, 32, "gpio0"),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
> + .pin_banks = rk3228_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
> + .label = "RK3228-GPIO",
> + .type = RK3288,
> + .grf_mux_offset = 0x0,
> + .iomux_routes = rk3228_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
> + .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3288_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_UNROUTED
> + ),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
> + IOMUX_UNROUTED,
> + IOMUX_UNROUTED,
> + 0
> + ),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
> + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0,
> + 0
> + ),
> + PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
> + 0,
> + 0,
> + IOMUX_UNROUTED
> + ),
> + PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
> + PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
> + 0,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_UNROUTED
> + ),
> + PIN_BANK(8, 16, "gpio8"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
> + .pin_banks = rk3288_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
> + .label = "RK3288-GPIO",
> + .type = RK3288,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x84,
> + .iomux_routes = rk3288_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
> + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3328_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
> + IOMUX_WIDTH_3BIT,
> + IOMUX_WIDTH_3BIT,
> + 0),
> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
> + IOMUX_WIDTH_3BIT,
> + IOMUX_WIDTH_3BIT,
> + 0,
> + 0),
> +};
> +
> +static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
> + .pin_banks = rk3328_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
> + .label = "RK3328-GPIO",
> + .type = RK3288,
> + .grf_mux_offset = 0x0,
> + .iomux_recalced = rk3328_mux_recalced_data,
> + .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
> + .iomux_routes = rk3328_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
> + .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
> + .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3368_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU
> + ),
> + PIN_BANK(1, 32, "gpio1"),
> + PIN_BANK(2, 32, "gpio2"),
> + PIN_BANK(3, 32, "gpio3"),
> +};
> +
> +static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
> + .pin_banks = rk3368_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
> + .label = "RK3368-GPIO",
> + .type = RK3368,
> + .grf_mux_offset = 0x0,
> + .pmu_mux_offset = 0x0,
> + .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
> +};
> +
> +static struct rockchip_pin_bank rk3399_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + DRV_TYPE_IO_1V8_ONLY,
> + DRV_TYPE_IO_1V8_ONLY,
> + DRV_TYPE_IO_DEFAULT,
> + DRV_TYPE_IO_DEFAULT,
> + 0x80,
> + 0x88,
> + -1,
> + -1,
> + PULL_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_IO_DEFAULT,
> + PULL_TYPE_IO_DEFAULT
> + ),
> + PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + IOMUX_SOURCE_PMU,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + 0xa0,
> + 0xa8,
> + 0xb0,
> + 0xb8
> + ),
> + PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_ONLY,
> + DRV_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_IO_DEFAULT,
> + PULL_TYPE_IO_DEFAULT,
> + PULL_TYPE_IO_1V8_ONLY,
> + PULL_TYPE_IO_1V8_ONLY
> + ),
> + PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
> + DRV_TYPE_IO_3V3_ONLY,
> + DRV_TYPE_IO_3V3_ONLY,
> + DRV_TYPE_IO_1V8_OR_3V0
> + ),
> + PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_3V0_AUTO,
> + DRV_TYPE_IO_1V8_OR_3V0,
> + DRV_TYPE_IO_1V8_OR_3V0
> + ),
> +};
> +
> +static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
> + .pin_banks = rk3399_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
> + .label = "RK3399-GPIO",
> + .type = RK3399,
> + .grf_mux_offset = 0xe000,
> + .pmu_mux_offset = 0x0,
> + .grf_drv_offset = 0xe100,
> + .pmu_drv_offset = 0x80,
> + .iomux_routes = rk3399_mux_route_data,
> + .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
> + .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
> + .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
> +};
> +
> +static const struct udevice_id rockchip_pinctrl_dt_match[] = {
> + { .compatible = "rockchip,px30-pinctrl",
> + .data = (ulong)&px30_pin_ctrl },
> + { .compatible = "rockchip,rv1108-pinctrl",
> + .data = (ulong)&rv1108_pin_ctrl },
> + { .compatible = "rockchip,rk2928-pinctrl",
> + .data = (ulong)&rk2928_pin_ctrl },
> + { .compatible = "rockchip,rk3036-pinctrl",
> + .data = (ulong)&rk3036_pin_ctrl },
> + { .compatible = "rockchip,rk3066a-pinctrl",
> + .data = (ulong)&rk3066a_pin_ctrl },
> + { .compatible = "rockchip,rk3066b-pinctrl",
> + .data = (ulong)&rk3066b_pin_ctrl },
> + { .compatible = "rockchip,rk3128-pinctrl",
> + .data = (ulong)&rk3128_pin_ctrl },
> + { .compatible = "rockchip,rk3188-pinctrl",
> + .data = (ulong)&rk3188_pin_ctrl },
> + { .compatible = "rockchip,rk3228-pinctrl",
> + .data = (ulong)&rk3228_pin_ctrl },
> + { .compatible = "rockchip,rk3288-pinctrl",
> + .data = (ulong)&rk3288_pin_ctrl },
> + { .compatible = "rockchip,rk3328-pinctrl",
> + .data = (ulong)&rk3328_pin_ctrl },
> + { .compatible = "rockchip,rk3368-pinctrl",
> + .data = (ulong)&rk3368_pin_ctrl },
> + { .compatible = "rockchip,rk3399-pinctrl",
> + .data = (ulong)&rk3399_pin_ctrl },
> + {},
> +};
No point in always adding all possible SOC support in U-Boot. Given that
users may be space-sensitive, we should only pull in support for those
chips that are needed.
Furthermore, we've had the decision on how to structure such drivers
earlier (last time I remember was for HDMI): there should be a common
driver infrastructure and multiple mini-drivers that reference it (see
drivers/video/rockchip/*_{vop,hmdi}.[ch]) and that can be selectively
pulled in.
> +
> +U_BOOT_DRIVER(pinctrl_rockchip) = {
> + .name = "rockchip_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rockchip_pinctrl_dt_match,
> + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 6/9] pinctrl: rockchip: Add common rockchip pinctrl driver
2018-02-18 19:20 ` Philipp Tomsich
@ 2018-03-05 11:23 ` David Wu
0 siblings, 0 replies; 31+ messages in thread
From: David Wu @ 2018-03-05 11:23 UTC (permalink / raw)
To: u-boot
Hi Philipp,
Okay, each SOC should have its own file, which include private data
structure, and probe(). Can reduce driver size.
在 2018年02月19日 03:20, Philipp Tomsich 写道:
>
>
> On Sat, 3 Feb 2018, David Wu wrote:
>
>> Use this driver to fit all Rockchip SOCs and to support
>> the desired pinctrl configuration via DTS.
>
> Please split this into multiple comments (and possibly multiple files)
> for the relevant per-SoC data structures. I'd like this to be multiple
> commits to add the individual data structures for each of the SOCs.
>
> We had the fundamental discussion of how to deal with drivers that
> require additional config-structures and code for some SOCs in the
> HDMI/VOP context and we should follow the same here.
>
>>
>> Signed-off-by: David Wu <david.wu@rock-chips.com>
>> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
>> Tested-by: Kever Yang <kever.yang@rock-chips.com>
>> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> ---
>>
>> drivers/pinctrl/Kconfig | 98 +-
>> drivers/pinctrl/Makefile | 2 +-
>> drivers/pinctrl/pinctrl-rockchip.c | 2440
>> ++++++++++++++++++++++++++++++++++++
>> 3 files changed, 2454 insertions(+), 86 deletions(-)
>> create mode 100644 drivers/pinctrl/pinctrl-rockchip.c
>>
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> index 7e8e4b0..6177e7c 100644
>> --- a/drivers/pinctrl/Kconfig
>> +++ b/drivers/pinctrl/Kconfig
>> @@ -158,95 +158,23 @@ config PINCTRL_QCA953X
>> the GPIO definitions and pin control functions for each available
>> multiplex function.
>>
>> -config PINCTRL_ROCKCHIP_RK3036
>> - bool "Rockchip rk3036 pin control driver"
>> - depends on DM
>> - help
>> - Support pin multiplexing control on Rockchip rk3036 SoCs.
>> -
>> - The driver is controlled by a device tree node which contains both
>> - the GPIO definitions and pin control functions for each available
>> - multiplex function.
>> -
>> -config PINCTRL_ROCKCHIP_RK3128
>> - bool "Rockchip rk3128 pin control driver"
>> - depends on DM
>> - help
>> - Support pin multiplexing control on Rockchip rk3128 SoCs.
>> -
>> - The driver is controlled by a device tree node which contains both
>> - the GPIO definitions and pin control functions for each available
>> - multiplex function.
>> -
>> -config PINCTRL_ROCKCHIP_RK3188
>> - bool "Rockchip rk3188 pin control driver"
>> - depends on DM
>> - help
>> - Support pin multiplexing control on Rockchip rk3188 SoCs.
>> -
>> - The driver is controlled by a device tree node which contains both
>> - the GPIO definitions and pin control functions for each available
>> - multiplex function.
>> -
>> -config PINCTRL_ROCKCHIP_RK322X
>> - bool "Rockchip rk322x pin control driver"
>> - depends on DM
>> - help
>> - Support pin multiplexing control on Rockchip rk322x SoCs.
>> -
>> - The driver is controlled by a device tree node which contains both
>> - the GPIO definitions and pin control functions for each available
>> - multiplex function.
>> -
>> -config PINCTRL_ROCKCHIP_RK3288
>> - bool "Rockchip rk3288 pin control driver"
>> - depends on DM
>> - help
>> - Support pin multiplexing control on Rockchip rk3288 SoCs.
>> -
>> - The driver is controlled by a device tree node which contains both
>> - the GPIO definitions and pin control functions for each available
>> - multiplex function.
>> -
>> -config PINCTRL_ROCKCHIP_RK3328
>> - bool "Rockchip rk3328 pin control driver"
>> - depends on DM
>> - help
>> - Support pin multiplexing control on Rockchip rk3328 SoCs.
>> -
>> - The driver is controlled by a device tree node which contains both
>> - the GPIO definitions and pin control functions for each available
>> - multiplex function.
>> -
>> -config PINCTRL_ROCKCHIP_RK3368
>> - bool "Rockchip RK3368 pin control driver"
>> - depends on DM
>> - help
>> - Support pin multiplexing control on Rockchip rk3368 SoCs.
>> -
>> - The driver is controlled by a device tree node which contains both
>> - the GPIO definitions and pin control functions for each available
>> - multiplex function.
>> -
>> -config PINCTRL_ROCKCHIP_RK3399
>> - bool "Rockchip rk3399 pin control driver"
>> - depends on DM
>> +config PINCTRL_ROCKCHIP
>> + bool "Rockchip pin control driver"
>> + depends on PINCTRL_FULL
>> + default y
>> help
>> - Support pin multiplexing control on Rockchip rk3399 SoCs.
>> + Support pin multiplexing control on Rockchip SoCs.
>>
>> - The driver is controlled by a device tree node which contains both
>> - the GPIO definitions and pin control functions for each available
>> - multiplex function.
>> + The driver is controlled by a device tree node which contains pin
>> + control functions for each available multiplex function.
>>
>> -config PINCTRL_ROCKCHIP_RV1108
>> - bool "Rockchip rv1108 pin control driver"
>> - depends on DM
>> +config SPL_PINCTRL_ROCKCHIP
>> + bool "Support Rockchip pin controllers in SPL"
>> + depends on SPL_PINCTRL_FULL
>> + default y
>> help
>> - Support pin multiplexing control on Rockchip rv1108 SoC.
>> -
>> - The driver is controlled by a device tree node which contains
>> - both the GPIO definitions and pin control functions for each
>> - available multiplex function.
>> + This option is an SPL-variant of the PINCTRL_ROCKCHIP option.
>> + See the help of PINCTRL_ROCKCHIP for details.
>>
>> config PINCTRL_SANDBOX
>> bool "Sandbox pinctrl driver"
>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>> index 8c04028..2429eb9 100644
>> --- a/drivers/pinctrl/Makefile
>> +++ b/drivers/pinctrl/Makefile
>> @@ -11,7 +11,7 @@ obj-y += nxp/
>> obj-$(CONFIG_ARCH_ASPEED) += aspeed/
>> obj-$(CONFIG_ARCH_ATH79) += ath79/
>> obj-$(CONFIG_ARCH_RMOBILE) += renesas/
>> -obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
>> +obj-$(CONFIG_$(SPL_)PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
>> obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
>>
>> obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/
>> diff --git a/drivers/pinctrl/pinctrl-rockchip.c
>> b/drivers/pinctrl/pinctrl-rockchip.c
>> new file mode 100644
>> index 0000000..68bf30d
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl-rockchip.c
>> @@ -0,0 +1,2440 @@
>> +/*
>> + * (C) Copyright 2018 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <dm/pinctrl.h>
>> +#include <regmap.h>
>> +#include <syscon.h>
>> +
>> +#define MAX_ROCKCHIP_GPIO_PER_BANK 32
>> +#define RK_FUNC_GPIO 0
>> +#define MAX_ROCKCHIP_PINS_ENTRIES 20
>> +
>> +enum rockchip_pinctrl_type {
>> + PX30,
>
> PX30 support has not been added to U-Boot. This should only be added,
> once the PX30 support is added.
>
>> + RV1108,
>> + RK2928,
>
> RK2928 support is not present in U-Boot.
>
>> + RK3066B,
>> + RK3128,
>> + RK3188,
>> + RK3288,
>> + RK3368,
>> + RK3399,
>> +};
>> +
>> +/**
>> + * Encode variants of iomux registers into a type variable
>> + */
>> +#define IOMUX_GPIO_ONLY BIT(0)
>> +#define IOMUX_WIDTH_4BIT BIT(1)
>> +#define IOMUX_SOURCE_PMU BIT(2)
>> +#define IOMUX_UNROUTED BIT(3)
>> +#define IOMUX_WIDTH_3BIT BIT(4)
>> +
>> +/**
>> + * @type: iomux variant using IOMUX_* constants
>> + * @offset: if initialized to -1 it will be autocalculated, by
>> specifying
>> + * an initial offset value the relevant source offset can be
>> reset
>> + * to a new value for autocalculating the following iomux
>> registers.
>> + */
>> +struct rockchip_iomux {
>> + int type;
>> + int offset;
>> +};
>> +
>> +/**
>> + * enum type index corresponding to rockchip_perpin_drv_list arrays
>> index.
>> + */
>> +enum rockchip_pin_drv_type {
>> + DRV_TYPE_IO_DEFAULT = 0,
>> + DRV_TYPE_IO_1V8_OR_3V0,
>> + DRV_TYPE_IO_1V8_ONLY,
>> + DRV_TYPE_IO_1V8_3V0_AUTO,
>> + DRV_TYPE_IO_3V3_ONLY,
>> + DRV_TYPE_MAX
>> +};
>> +
>> +/**
>> + * enum type index corresponding to rockchip_pull_list arrays index.
>> + */
>> +enum rockchip_pin_pull_type {
>> + PULL_TYPE_IO_DEFAULT = 0,
>> + PULL_TYPE_IO_1V8_ONLY,
>> + PULL_TYPE_MAX
>> +};
>> +
>> +/**
>> + * @drv_type: drive strength variant using rockchip_perpin_drv_type
>> + * @offset: if initialized to -1 it will be autocalculated, by
>> specifying
>> + * an initial offset value the relevant source offset can be
>> reset
>> + * to a new value for autocalculating the following drive
>> strength
>> + * registers. if used chips own cal_drv func instead to calculate
>> + * registers offset, the variant could be ignored.
>> + */
>> +struct rockchip_drv {
>> + enum rockchip_pin_drv_type drv_type;
>> + int offset;
>> +};
>> +
>> +/**
>> + * @priv: common pinctrl private basedata
>> + * @pin_base: first pin number
>> + * @nr_pins: number of pins in this bank
>> + * @name: name of the bank
>> + * @bank_num: number of the bank, to account for holes
>> + * @iomux: array describing the 4 iomux sources of the bank
>> + * @drv: array describing the 4 drive strength sources of the bank
>> + * @pull_type: array describing the 4 pull type sources of the bank
>> + * @recalced_mask: bits describing the mux recalced pins of per bank
>> + * @route_mask: bits describing the routing pins of per bank
>> + */
>> +struct rockchip_pin_bank {
>> + struct rockchip_pinctrl_priv *priv;
>> + u32 pin_base;
>> + u8 nr_pins;
>> + char *name;
>> + u8 bank_num;
>> + struct rockchip_iomux iomux[4];
>> + struct rockchip_drv drv[4];
>> + enum rockchip_pin_pull_type pull_type[4];
>> + u32 recalced_mask;
>> + u32 route_mask;
>> +};
>> +
>> +#define PIN_BANK(id, pins, label) \
>> + { \
>> + .bank_num = id, \
>> + .nr_pins = pins, \
>> + .name = label, \
>> + .iomux = { \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + }, \
>> + }
>> +
>> +#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2,
>> iom3) \
>> + { \
>> + .bank_num = id, \
>> + .nr_pins = pins, \
>> + .name = label, \
>> + .iomux = { \
>> + { .type = iom0, .offset = -1 }, \
>> + { .type = iom1, .offset = -1 }, \
>> + { .type = iom2, .offset = -1 }, \
>> + { .type = iom3, .offset = -1 }, \
>> + }, \
>> + }
>> +
>> +#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2,
>> type3) \
>> + { \
>> + .bank_num = id, \
>> + .nr_pins = pins, \
>> + .name = label, \
>> + .iomux = { \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + }, \
>> + .drv = { \
>> + { .drv_type = type0, .offset = -1 }, \
>> + { .drv_type = type1, .offset = -1 }, \
>> + { .drv_type = type2, .offset = -1 }, \
>> + { .drv_type = type3, .offset = -1 }, \
>> + }, \
>> + }
>> +
>> +#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
>> + drv2, drv3, pull0, pull1, \
>> + pull2, pull3) \
>> + { \
>> + .bank_num = id, \
>> + .nr_pins = pins, \
>> + .name = label, \
>> + .iomux = { \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + { .offset = -1 }, \
>> + }, \
>> + .drv = { \
>> + { .drv_type = drv0, .offset = -1 }, \
>> + { .drv_type = drv1, .offset = -1 }, \
>> + { .drv_type = drv2, .offset = -1 }, \
>> + { .drv_type = drv3, .offset = -1 }, \
>> + }, \
>> + .pull_type[0] = pull0, \
>> + .pull_type[1] = pull1, \
>> + .pull_type[2] = pull2, \
>> + .pull_type[3] = pull3, \
>> + }
>> +
>> +#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0,
>> iom1, \
>> + iom2, iom3, drv0, drv1, drv2, \
>> + drv3, offset0, offset1, \
>> + offset2, offset3) \
>> + { \
>> + .bank_num = id, \
>> + .nr_pins = pins, \
>> + .name = label, \
>> + .iomux = { \
>> + { .type = iom0, .offset = -1 }, \
>> + { .type = iom1, .offset = -1 }, \
>> + { .type = iom2, .offset = -1 }, \
>> + { .type = iom3, .offset = -1 }, \
>> + }, \
>> + .drv = { \
>> + { .drv_type = drv0, .offset = offset0 }, \
>> + { .drv_type = drv1, .offset = offset1 }, \
>> + { .drv_type = drv2, .offset = offset2 }, \
>> + { .drv_type = drv3, .offset = offset3 }, \
>> + }, \
>> + }
>> +
>> +#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
>> + label, iom0, iom1, iom2, \
>> + iom3, drv0, drv1, drv2, \
>> + drv3, offset0, offset1, \
>> + offset2, offset3, pull0, \
>> + pull1, pull2, pull3) \
>> + { \
>> + .bank_num = id, \
>> + .nr_pins = pins, \
>> + .name = label, \
>> + .iomux = { \
>> + { .type = iom0, .offset = -1 }, \
>> + { .type = iom1, .offset = -1 }, \
>> + { .type = iom2, .offset = -1 }, \
>> + { .type = iom3, .offset = -1 }, \
>> + }, \
>> + .drv = { \
>> + { .drv_type = drv0, .offset = offset0 }, \
>> + { .drv_type = drv1, .offset = offset1 }, \
>> + { .drv_type = drv2, .offset = offset2 }, \
>> + { .drv_type = drv3, .offset = offset3 }, \
>> + }, \
>> + .pull_type[0] = pull0, \
>> + .pull_type[1] = pull1, \
>> + .pull_type[2] = pull2, \
>> + .pull_type[3] = pull3, \
>> + }
>> +
>> +/**
>> + * struct rockchip_mux_recalced_data: represent a pin iomux data.
>
> Why is this 'recalced'? This sounds more like a table describing each
> chip's IOMUX.
>
>> + * @num: bank number.
>> + * @pin: pin number.
>> + * @bit: index at register.
>> + * @reg: register offset.
>> + * @mask: mask bit
>> + */
>> +struct rockchip_mux_recalced_data {
>> + u8 num;
>> + u8 pin;
>> + u32 reg;
>> + u8 bit;
>> + u8 mask;
>> +};
>> +
>> +/**
>> + * struct rockchip_mux_recalced_data: represent a pin iomux data.
>> + * @bank_num: bank number.
>> + * @pin: index at register or used to calc index.
>> + * @func: the min pin.
>> + * @route_offset: the max pin.
>> + * @route_val: the register offset.
>> + */
>> +struct rockchip_mux_route_data {
>> + u8 bank_num;
>> + u8 pin;
>> + u8 func;
>> + u32 route_offset;
>> + u32 route_val;
>> +};
>> +
>> +/**
>> + */
>> +struct rockchip_pin_ctrl {
>> + struct rockchip_pin_bank *pin_banks;
>> + u32 nr_banks;
>> + u32 nr_pins;
>> + char *label;
>> + enum rockchip_pinctrl_type type;
>> + int grf_mux_offset;
>> + int pmu_mux_offset;
>> + int grf_drv_offset;
>> + int pmu_drv_offset;
>> + struct rockchip_mux_recalced_data *iomux_recalced;
>> + u32 niomux_recalced;
>> + struct rockchip_mux_route_data *iomux_routes;
>> + u32 niomux_routes;
>> +
>> + void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit);
>> + void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit);
>> + int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit);
>> +};
>> +
>> +/**
>> + */
>> +struct rockchip_pinctrl_priv {
>> + struct rockchip_pin_ctrl *ctrl;
>> + struct regmap *regmap_base;
>> + struct regmap *regmap_pmu;
>> +
>> +};
>> +
>> +static int rockchip_verify_config(struct udevice *dev, u32 bank, u32
>> pin)
>> +{
>> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> +
>> + if (bank >= ctrl->nr_banks) {
>> + debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
>> + return -EINVAL;
>> + }
>> +
>> + if (pin >= MAX_ROCKCHIP_GPIO_PER_BANK) {
>> + debug("pin conf pin %d >= %d\n", pin,
>> + MAX_ROCKCHIP_GPIO_PER_BANK);
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
>> + {
>> + .num = 1,
>> + .pin = 0,
>> + .reg = 0x418,
>
> I assume this is a register offset. If so, I'd appreciate this to not be
> hard-coded, but to be either (a) a symbolic constant or (b) preferrably
> even an offsetof(...).
>
> This applies for all uses throughout the file.
>
>> + .bit = 0,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 1,
>> + .reg = 0x418,
>> + .bit = 2,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 2,
>> + .reg = 0x418,
>> + .bit = 4,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 3,
>> + .reg = 0x418,
>> + .bit = 6,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 4,
>> + .reg = 0x418,
>> + .bit = 8,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 5,
>> + .reg = 0x418,
>> + .bit = 10,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 6,
>> + .reg = 0x418,
>> + .bit = 12,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 7,
>> + .reg = 0x418,
>> + .bit = 14,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 8,
>> + .reg = 0x41c,
>> + .bit = 0,
>> + .mask = 0x3
>> + }, {
>> + .num = 1,
>> + .pin = 9,
>> + .reg = 0x41c,
>> + .bit = 2,
>> + .mask = 0x3
>> + },
>> +};
>> +
>> +static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
>> + {
>> + .num = 2,
>> + .pin = 20,
>> + .reg = 0xe8,
>> + .bit = 0,
>> + .mask = 0x7
>> + }, {
>> + .num = 2,
>> + .pin = 21,
>> + .reg = 0xe8,
>> + .bit = 4,
>> + .mask = 0x7
>> + }, {
>> + .num = 2,
>> + .pin = 22,
>> + .reg = 0xe8,
>> + .bit = 8,
>> + .mask = 0x7
>> + }, {
>> + .num = 2,
>> + .pin = 23,
>> + .reg = 0xe8,
>> + .bit = 12,
>> + .mask = 0x7
>> + }, {
>> + .num = 2,
>> + .pin = 24,
>> + .reg = 0xd4,
>> + .bit = 12,
>> + .mask = 0x7
>> + },
>> +};
>> +
>> +static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
>> + {
>> + .num = 2,
>> + .pin = 12,
>> + .reg = 0x24,
>> + .bit = 8,
>> + .mask = 0x3
>> + }, {
>> + .num = 2,
>> + .pin = 15,
>> + .reg = 0x28,
>> + .bit = 0,
>> + .mask = 0x7
>> + }, {
>> + .num = 2,
>> + .pin = 23,
>> + .reg = 0x30,
>> + .bit = 14,
>> + .mask = 0x3
>> + },
>> +};
>> +
>> +static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank,
>> int pin,
>> + int *reg, u8 *bit, int *mask)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> + struct rockchip_mux_recalced_data *data;
>> + int i;
>> +
>> + for (i = 0; i < ctrl->niomux_recalced; i++) {
>> + data = &ctrl->iomux_recalced[i];
>> + if (data->num == bank->bank_num &&
>> + data->pin == pin)
>> + break;
>> + }
>> +
>> + if (i >= ctrl->niomux_recalced)
>> + return;
>> +
>> + *reg = data->reg;
>> + *mask = data->mask;
>> + *bit = data->bit;
>> +}
>> +
>> +static struct rockchip_mux_route_data px30_mux_route_data[] = {
>
> The PX30-specific structures should be added together with the PX30
> enablement series. It doesn't make sense to have them here now, as
> U-Boot doesn't know about the PX30 yet.
>
>> + {
>> + /* cif-d2m0 */
>> + .bank_num = 2,
>> + .pin = 0,
>> + .func = 1,
>> + .route_offset = 0x184,
>> + .route_val = BIT(16 + 7),
>> + }, {
>> + /* cif-d2m1 */
>> + .bank_num = 3,
>> + .pin = 3,
>> + .func = 3,
>> + .route_offset = 0x184,
>> + .route_val = BIT(16 + 7) | BIT(7),
>> + }, {
>> + /* pdm-m0 */
>> + .bank_num = 3,
>> + .pin = 22,
>> + .func = 2,
>> + .route_offset = 0x184,
>> + .route_val = BIT(16 + 8),
>> + }, {
>> + /* pdm-m1 */
>> + .bank_num = 2,
>> + .pin = 22,
>> + .func = 1,
>> + .route_offset = 0x184,
>> + .route_val = BIT(16 + 8) | BIT(8),
>> + }, {
>> + /* uart2-rxm0 */
>> + .bank_num = 1,
>> + .pin = 26,
>> + .func = 2,
>> + .route_offset = 0x184,
>> + .route_val = BIT(16 + 9),
>> + }, {
>> + /* uart2-rxm1 */
>> + .bank_num = 2,
>> + .pin = 14,
>> + .func = 2,
>> + .route_offset = 0x184,
>> + .route_val = BIT(16 + 9) | BIT(9),
>> + }, {
>> + /* uart3-rxm0 */
>> + .bank_num = 0,
>> + .pin = 17,
>> + .func = 2,
>> + .route_offset = 0x184,
>> + .route_val = BIT(16 + 10),
>> + }, {
>> + /* uart3-rxm1 */
>> + .bank_num = 1,
>> + .pin = 13,
>> + .func = 2,
>> + .route_offset = 0x184,
>> + .route_val = BIT(16 + 10) | BIT(10),
>> + },
>> +};
>> +
>> +static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
>> + {
>> + /* spi-0 */
>> + .bank_num = 1,
>> + .pin = 10,
>> + .func = 1,
>> + .route_offset = 0x144,
>> + .route_val = BIT(16 + 3) | BIT(16 + 4),
>> + }, {
>> + /* spi-1 */
>> + .bank_num = 1,
>> + .pin = 27,
>> + .func = 3,
>> + .route_offset = 0x144,
>> + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
>> + }, {
>> + /* spi-2 */
>> + .bank_num = 0,
>> + .pin = 13,
>> + .func = 2,
>> + .route_offset = 0x144,
>> + .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
>> + }, {
>> + /* i2s-0 */
>> + .bank_num = 1,
>> + .pin = 5,
>> + .func = 1,
>> + .route_offset = 0x144,
>> + .route_val = BIT(16 + 5),
>> + }, {
>> + /* i2s-1 */
>> + .bank_num = 0,
>> + .pin = 14,
>> + .func = 1,
>> + .route_offset = 0x144,
>> + .route_val = BIT(16 + 5) | BIT(5),
>> + }, {
>> + /* emmc-0 */
>> + .bank_num = 1,
>> + .pin = 22,
>> + .func = 2,
>> + .route_offset = 0x144,
>> + .route_val = BIT(16 + 6),
>> + }, {
>> + /* emmc-1 */
>> + .bank_num = 2,
>> + .pin = 4,
>> + .func = 2,
>> + .route_offset = 0x144,
>> + .route_val = BIT(16 + 6) | BIT(6),
>> + },
>> +};
>> +
>> +static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
>> + {
>> + /* pwm0-0 */
>> + .bank_num = 0,
>> + .pin = 26,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16),
>> + }, {
>> + /* pwm0-1 */
>> + .bank_num = 3,
>> + .pin = 21,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16) | BIT(0),
>> + }, {
>> + /* pwm1-0 */
>> + .bank_num = 0,
>> + .pin = 27,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 1),
>> + }, {
>> + /* pwm1-1 */
>> + .bank_num = 0,
>> + .pin = 30,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 1) | BIT(1),
>> + }, {
>> + /* pwm2-0 */
>> + .bank_num = 0,
>> + .pin = 28,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 2),
>> + }, {
>> + /* pwm2-1 */
>> + .bank_num = 1,
>> + .pin = 12,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 2) | BIT(2),
>> + }, {
>> + /* pwm3-0 */
>> + .bank_num = 3,
>> + .pin = 26,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 3),
>> + }, {
>> + /* pwm3-1 */
>> + .bank_num = 1,
>> + .pin = 11,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 3) | BIT(3),
>> + }, {
>> + /* sdio-0_d0 */
>> + .bank_num = 1,
>> + .pin = 1,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 4),
>> + }, {
>> + /* sdio-1_d0 */
>> + .bank_num = 3,
>> + .pin = 2,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 4) | BIT(4),
>> + }, {
>> + /* spi-0_rx */
>> + .bank_num = 0,
>> + .pin = 13,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 5),
>> + }, {
>> + /* spi-1_rx */
>> + .bank_num = 2,
>> + .pin = 0,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 5) | BIT(5),
>> + }, {
>> + /* emmc-0_cmd */
>> + .bank_num = 1,
>> + .pin = 22,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 7),
>> + }, {
>> + /* emmc-1_cmd */
>> + .bank_num = 2,
>> + .pin = 4,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 7) | BIT(7),
>> + }, {
>> + /* uart2-0_rx */
>> + .bank_num = 1,
>> + .pin = 19,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 8),
>> + }, {
>> + /* uart2-1_rx */
>> + .bank_num = 1,
>> + .pin = 10,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 8) | BIT(8),
>> + }, {
>> + /* uart1-0_rx */
>> + .bank_num = 1,
>> + .pin = 10,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 11),
>> + }, {
>> + /* uart1-1_rx */
>> + .bank_num = 3,
>> + .pin = 13,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 11) | BIT(11),
>> + },
>> +};
>> +
>> +static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
>> + {
>> + /* edphdmi_cecinoutt1 */
>> + .bank_num = 7,
>> + .pin = 16,
>> + .func = 2,
>> + .route_offset = 0x264,
>> + .route_val = BIT(16 + 12) | BIT(12),
>> + }, {
>> + /* edphdmi_cecinout */
>> + .bank_num = 7,
>> + .pin = 23,
>> + .func = 4,
>> + .route_offset = 0x264,
>> + .route_val = BIT(16 + 12),
>> + },
>> +};
>> +
>> +static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
>> + {
>> + /* uart2dbg_rxm0 */
>> + .bank_num = 1,
>> + .pin = 1,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16) | BIT(16 + 1),
>> + }, {
>> + /* uart2dbg_rxm1 */
>> + .bank_num = 2,
>> + .pin = 1,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
>> + }, {
>> + /* gmac-m1_rxd0 */
>> + .bank_num = 1,
>> + .pin = 11,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 2) | BIT(2),
>> + }, {
>> + /* gmac-m1-optimized_rxd3 */
>> + .bank_num = 1,
>> + .pin = 14,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 10) | BIT(10),
>> + }, {
>> + /* pdm_sdi0m0 */
>> + .bank_num = 2,
>> + .pin = 19,
>> + .func = 2,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 3),
>> + }, {
>> + /* pdm_sdi0m1 */
>> + .bank_num = 1,
>> + .pin = 23,
>> + .func = 3,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 3) | BIT(3),
>> + }, {
>> + /* spi_rxdm2 */
>> + .bank_num = 3,
>> + .pin = 2,
>> + .func = 4,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
>> + }, {
>> + /* i2s2_sdim0 */
>> + .bank_num = 1,
>> + .pin = 24,
>> + .func = 1,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 6),
>> + }, {
>> + /* i2s2_sdim1 */
>> + .bank_num = 3,
>> + .pin = 2,
>> + .func = 6,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 6) | BIT(6),
>> + }, {
>> + /* card_iom1 */
>> + .bank_num = 2,
>> + .pin = 22,
>> + .func = 3,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 7) | BIT(7),
>> + }, {
>> + /* tsp_d5m1 */
>> + .bank_num = 2,
>> + .pin = 16,
>> + .func = 3,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 8) | BIT(8),
>> + }, {
>> + /* cif_data5m1 */
>> + .bank_num = 2,
>> + .pin = 16,
>> + .func = 4,
>> + .route_offset = 0x50,
>> + .route_val = BIT(16 + 9) | BIT(9),
>> + },
>> +};
>> +
>> +static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
>> + {
>> + /* uart2dbga_rx */
>> + .bank_num = 4,
>> + .pin = 8,
>> + .func = 2,
>> + .route_offset = 0xe21c,
>> + .route_val = BIT(16 + 10) | BIT(16 + 11),
>> + }, {
>> + /* uart2dbgb_rx */
>> + .bank_num = 4,
>> + .pin = 16,
>> + .func = 2,
>> + .route_offset = 0xe21c,
>> + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
>> + }, {
>> + /* uart2dbgc_rx */
>> + .bank_num = 4,
>> + .pin = 19,
>> + .func = 1,
>> + .route_offset = 0xe21c,
>> + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
>> + }, {
>> + /* pcie_clkreqn */
>> + .bank_num = 2,
>> + .pin = 26,
>> + .func = 2,
>> + .route_offset = 0xe21c,
>> + .route_val = BIT(16 + 14),
>> + }, {
>> + /* pcie_clkreqnb */
>> + .bank_num = 4,
>> + .pin = 24,
>> + .func = 1,
>> + .route_offset = 0xe21c,
>> + .route_val = BIT(16 + 14) | BIT(14),
>> + },
>> +};
>> +
>> +static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank,
>> int pin,
>> + int mux, u32 *reg, u32 *value)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> + struct rockchip_mux_route_data *data;
>> + int i;
>> +
>> + for (i = 0; i < ctrl->niomux_routes; i++) {
>> + data = &ctrl->iomux_routes[i];
>> + if ((data->bank_num == bank->bank_num) &&
>> + (data->pin == pin) && (data->func == mux))
>> + break;
>> + }
>> +
>> + if (i >= ctrl->niomux_routes)
>> + return false;
>> +
>> + *reg = data->route_offset;
>> + *value = data->route_val;
>> +
>> + return true;
>> +}
>> +
>> +static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + unsigned int val;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> +
>> + if (iomux_num > 3)
>> + return -EINVAL;
>> +
>> + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
>> + debug("pin %d is unrouted\n", pin);
>> + return -EINVAL;
>> + }
>> +
>> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
>> + return RK_FUNC_GPIO;
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg
>> inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + if (mux_type & IOMUX_WIDTH_4BIT) {
>> + if ((pin % 8) >= 4)
>> + reg += 0x4;
>> + bit = (pin % 4) * 4;
>> + mask = 0xf;
>> + } else if (mux_type & IOMUX_WIDTH_3BIT) {
>> + if ((pin % 8) >= 5)
>> + reg += 0x4;
>> + bit = (pin % 8 % 5) * 3;
>
> "(pin % 8 % 5)" ... really? This just begs for trouble down the road
> (and it's not self-explanatory at all)... please restructure.
>
>> + mask = 0x7;
>> + } else {
>> + bit = (pin % 8) * 2;
>> + mask = 0x3;
>> + }
>
> Given that this is not self-explanatory: please add a comment, so people
> can follow it. And it wouldn't hurt if the magic calculations were a
> bit less magic...
>
>> +
>> + if (bank->recalced_mask & BIT(pin))
>> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
>> +
>> + ret = regmap_read(regmap, reg, &val);
>> + if (ret)
>> + return ret;
>> +
>> + return ((val >> bit) & mask);
>> +}
>> +
>> +static int rockchip_pinctrl_get_gpio_mux(struct udevice *dev, int
>> banknum,
>> + int index)
>> +{ struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> +
>> + return rockchip_get_mux(&ctrl->pin_banks[banknum], index);
>> +}
>> +
>> +static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
>> + int pin, int mux)
>> +{
>> + int iomux_num = (pin / 8);
>> +
>> + if (iomux_num > 3)
>> + return -EINVAL;
>
> Why is iomux_num limited to 3? If this is a configurable constant for
> the driver, please make it at least a symbolic constant... if this is a
> SOC-specific limit, then you should go through the driver-data to access
> it and check against this limit.
>
>> +
>> + if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
>> + debug("pin %d is unrouted\n", pin);
>> + return -EINVAL;
>> + }
>> +
>> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
>> + if (mux != IOMUX_GPIO_ONLY) {
>> + debug("pin %d only supports a gpio mux\n", pin);
>> + return -ENOTSUPP;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Set a new mux function for a pin.
>> + *
>> + * The register is divided into the upper and lower 16 bit. When
>> changing
>> + * a value, the previous register value is not read and changed. Instead
>> + * it seems the changed bits are marked in the upper 16 bit, while the
>> + * changed value gets set in the same offset in the lower 16 bit.
>> + * All pin settings seem to be 2 bit wide in both the upper and lower
>> + * parts.
>> + * @bank: pin bank to change
>> + * @pin: pin to change
>> + * @mux: new mux function to set
>> + */
>> +static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin,
>> int mux)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int iomux_num = (pin / 8);
>> + struct regmap *regmap;
>> + int reg, ret, mask, mux_type;
>> + u8 bit;
>> + u32 data, route_reg, route_val;
>> +
>> + ret = rockchip_verify_mux(bank, pin, mux);
>> + if (ret < 0)
>> + return ret;
>> +
>> + if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
>> + return 0;
>> +
>> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
>> +
>> + regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
>> + ? priv->regmap_pmu : priv->regmap_base;
>> +
>> + /* get basic quadrupel of mux registers and the correct reg
>> inside */
>> + mux_type = bank->iomux[iomux_num].type;
>> + reg = bank->iomux[iomux_num].offset;
>> + if (mux_type & IOMUX_WIDTH_4BIT) {
>> + if ((pin % 8) >= 4)
>> + reg += 0x4;
>> + bit = (pin % 4) * 4;
>> + mask = 0xf;
>> + } else if (mux_type & IOMUX_WIDTH_3BIT) {
>> + if ((pin % 8) >= 5)
>> + reg += 0x4;
>> + bit = (pin % 8 % 5) * 3;
>> + mask = 0x7;
>> + } else {
>> + bit = (pin % 8) * 2;
>> + mask = 0x3;
>> + }
>
> The same magic as above.
> Note, that if you perform the same calculations in multiple places, you
> should create a helper function and call it multiple times.
>
>> +
>> + if (bank->recalced_mask & BIT(pin))
>> + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
>> +
>> + if (bank->route_mask & BIT(pin)) {
>> + if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
>> + &route_val)) {
>> + ret = regmap_write(regmap, route_reg, route_val);
>> + if (ret)
>> + return ret;
>> + }
>> + }
>> +
>> + data = (mask << (bit + 16));
>> + data |= (mux & mask) << bit;
>> + ret = regmap_write(regmap, reg, data);
>> +
>> + return ret;
>> +}
>> +
>> +#define PX30_PULL_PMU_OFFSET 0x10
>> +#define PX30_PULL_GRF_OFFSET 0x60
>> +#define PX30_PULL_BITS_PER_PIN 2
>> +#define PX30_PULL_PINS_PER_REG 8
>> +#define PX30_PULL_BANK_STRIDE 16
>
> Anything PX30-related needs to come in with the PX30 enablement series.
> Thanks.
>
>> +
>> +static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 32 pins of the first bank are located in PMU */
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = PX30_PULL_PMU_OFFSET;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = PX30_PULL_GRF_OFFSET;
>> +
>> + /* correct the offset, as we're starting with the 2nd bank */
>> + *reg -= 0x10;
>> + *reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
>> + }
>> +
>> + *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
>> + *bit = (pin_num % PX30_PULL_PINS_PER_REG);
>> + *bit *= PX30_PULL_BITS_PER_PIN;
>> +}
>> +
>> +#define PX30_DRV_PMU_OFFSET 0x20
>> +#define PX30_DRV_GRF_OFFSET 0xf0
>> +#define PX30_DRV_BITS_PER_PIN 2
>> +#define PX30_DRV_PINS_PER_REG 8
>> +#define PX30_DRV_BANK_STRIDE 16
>> +
>> +static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 32 pins of the first bank are located in PMU */
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = PX30_DRV_PMU_OFFSET;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = PX30_DRV_GRF_OFFSET;
>> +
>> + /* correct the offset, as we're starting with the 2nd bank */
>> + *reg -= 0x10;
>> + *reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
>> + }
>> +
>> + *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
>> + *bit = (pin_num % PX30_DRV_PINS_PER_REG);
>> + *bit *= PX30_DRV_BITS_PER_PIN;
>> +}
>> +
>> +#define PX30_SCHMITT_PMU_OFFSET 0x38
>> +#define PX30_SCHMITT_GRF_OFFSET 0xc0
>> +#define PX30_SCHMITT_PINS_PER_PMU_REG 16
>> +#define PX30_SCHMITT_BANK_STRIDE 16
>> +#define PX30_SCHMITT_PINS_PER_GRF_REG 8
>> +
>> +static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num,
>> + struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int pins_per_reg;
>> +
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = PX30_SCHMITT_PMU_OFFSET;
>> + pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = PX30_SCHMITT_GRF_OFFSET;
>> + pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
>> + *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
>> + }
>> + *reg += ((pin_num / pins_per_reg) * 4);
>> + *bit = pin_num % pins_per_reg;
>> +
>> + return 0;
>> +}
>> +
>> +#define RV1108_PULL_PMU_OFFSET 0x10
>> +#define RV1108_PULL_OFFSET 0x110
>> +#define RV1108_PULL_PINS_PER_REG 8
>> +#define RV1108_PULL_BITS_PER_PIN 2
>> +#define RV1108_PULL_BANK_STRIDE 16
>> +
>> +static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 24 pins of the first bank are located in PMU */
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RV1108_PULL_PMU_OFFSET;
>> + } else {
>> + *reg = RV1108_PULL_OFFSET;
>> + *regmap = priv->regmap_base;
>> + /* correct the offset, as we're starting with the 2nd bank */
>> + *reg -= 0x10;
>> + *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
>> + }
>> +
>> + *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
>> + *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
>> + *bit *= RV1108_PULL_BITS_PER_PIN;
>> +}
>> +
>> +#define RV1108_DRV_PMU_OFFSET 0x20
>> +#define RV1108_DRV_GRF_OFFSET 0x210
>> +#define RV1108_DRV_BITS_PER_PIN 2
>> +#define RV1108_DRV_PINS_PER_REG 8
>> +#define RV1108_DRV_BANK_STRIDE 16
>> +
>> +static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 24 pins of the first bank are located in PMU */
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RV1108_DRV_PMU_OFFSET;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = RV1108_DRV_GRF_OFFSET;
>> +
>> + /* correct the offset, as we're starting with the 2nd bank */
>> + *reg -= 0x10;
>> + *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
>> + }
>> +
>> + *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
>> + *bit = pin_num % RV1108_DRV_PINS_PER_REG;
>> + *bit *= RV1108_DRV_BITS_PER_PIN;
>> +}
>> +
>> +#define RV1108_SCHMITT_PMU_OFFSET 0x30
>> +#define RV1108_SCHMITT_GRF_OFFSET 0x388
>> +#define RV1108_SCHMITT_BANK_STRIDE 8
>> +#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
>> +#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
>> +
>> +static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank
>> *bank,
>> + int pin_num,
>> + struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int pins_per_reg;
>> +
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RV1108_SCHMITT_PMU_OFFSET;
>> + pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = RV1108_SCHMITT_GRF_OFFSET;
>> + pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
>> + *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
>> + }
>> + *reg += ((pin_num / pins_per_reg) * 4);
>> + *bit = pin_num % pins_per_reg;
>> +
>> + return 0;
>> +}
>> +
>> +#define RK2928_PULL_OFFSET 0x118
>> +#define RK2928_PULL_PINS_PER_REG 16
>> +#define RK2928_PULL_BANK_STRIDE 8
>> +
>> +static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + *regmap = priv->regmap_base;
>> + *reg = RK2928_PULL_OFFSET;
>> + *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
>> + *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
>> +
>> + *bit = pin_num % RK2928_PULL_PINS_PER_REG;
>> +};
>> +
>> +#define RK3128_PULL_OFFSET 0x118
>> +
>> +static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + *regmap = priv->regmap_base;
>> + *reg = RK3128_PULL_OFFSET;
>> + *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
>> + *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
>> +
>> + *bit = pin_num % RK2928_PULL_PINS_PER_REG;
>> +}
>> +
>> +#define RK3188_PULL_OFFSET 0x164
>> +#define RK3188_PULL_BITS_PER_PIN 2
>> +#define RK3188_PULL_PINS_PER_REG 8
>> +#define RK3188_PULL_BANK_STRIDE 16
>> +#define RK3188_PULL_PMU_OFFSET 0x64
>> +
>> +static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 12 pins of the first bank are located elsewhere */
>> + if (bank->bank_num == 0 && pin_num < 12) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RK3188_PULL_PMU_OFFSET;
>> +
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = RK3188_PULL_OFFSET;
>> +
>> + /* correct the offset, as it is the 2nd pull register */
>> + *reg -= 4;
>> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> +
>> + /*
>> + * The bits in these registers have an inverse ordering
>> + * with the lowest pin being in bits 15:14 and the highest
>> + * pin in bits 1:0
>> + */
>> + *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>> + }
>> +}
>> +
>> +#define RK3288_PULL_OFFSET 0x140
>> +static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 24 pins of the first bank are located in PMU */
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RK3188_PULL_PMU_OFFSET;
>> +
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = RK3288_PULL_OFFSET;
>> +
>> + /* correct the offset, as we're starting with the 2nd bank */
>> + *reg -= 0x10;
>> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>> + }
>> +}
>> +
>> +#define RK3288_DRV_PMU_OFFSET 0x70
>> +#define RK3288_DRV_GRF_OFFSET 0x1c0
>> +#define RK3288_DRV_BITS_PER_PIN 2
>> +#define RK3288_DRV_PINS_PER_REG 8
>> +#define RK3288_DRV_BANK_STRIDE 16
>> +
>> +static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 24 pins of the first bank are located in PMU */
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RK3288_DRV_PMU_OFFSET;
>> +
>> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
>> + *bit = pin_num % RK3288_DRV_PINS_PER_REG;
>> + *bit *= RK3288_DRV_BITS_PER_PIN;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = RK3288_DRV_GRF_OFFSET;
>> +
>> + /* correct the offset, as we're starting with the 2nd bank */
>> + *reg -= 0x10;
>> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
>> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
>> + *bit *= RK3288_DRV_BITS_PER_PIN;
>> + }
>> +}
>> +
>> +#define RK3228_PULL_OFFSET 0x100
>> +
>> +static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + *regmap = priv->regmap_base;
>> + *reg = RK3228_PULL_OFFSET;
>> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>> +}
>> +
>> +#define RK3228_DRV_GRF_OFFSET 0x200
>> +
>> +static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + *regmap = priv->regmap_base;
>> + *reg = RK3228_DRV_GRF_OFFSET;
>> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
>> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
>> + *bit *= RK3288_DRV_BITS_PER_PIN;
>> +}
>> +
>> +#define RK3368_PULL_GRF_OFFSET 0x100
>> +#define RK3368_PULL_PMU_OFFSET 0x10
>> +
>> +static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 32 pins of the first bank are located in PMU */
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RK3368_PULL_PMU_OFFSET;
>> +
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = RK3368_PULL_GRF_OFFSET;
>> +
>> + /* correct the offset, as we're starting with the 2nd bank */
>> + *reg -= 0x10;
>> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>> + }
>> +}
>> +
>> +#define RK3368_DRV_PMU_OFFSET 0x20
>> +#define RK3368_DRV_GRF_OFFSET 0x200
>> +
>> +static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The first 32 pins of the first bank are located in PMU */
>> + if (bank->bank_num == 0) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RK3368_DRV_PMU_OFFSET;
>> +
>> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
>> + *bit = pin_num % RK3288_DRV_PINS_PER_REG;
>> + *bit *= RK3288_DRV_BITS_PER_PIN;
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = RK3368_DRV_GRF_OFFSET;
>> +
>> + /* correct the offset, as we're starting with the 2nd bank */
>> + *reg -= 0x10;
>> + *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
>> + *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
>> + *bit *= RK3288_DRV_BITS_PER_PIN;
>
> Why suddenly RK3288_ symbolic constants? This is the RK3368 setup code.
>
>> + }
>> +}
>> +
>> +#define RK3399_PULL_GRF_OFFSET 0xe040
>> +#define RK3399_PULL_PMU_OFFSET 0x40
>> +#define RK3399_DRV_3BITS_PER_PIN 3
>> +
>> +static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + /* The bank0:16 and bank1:32 pins are located in PMU */
>> + if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
>> + *regmap = priv->regmap_pmu;
>> + *reg = RK3399_PULL_PMU_OFFSET;
>> +
>> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
>> +
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> + *bit = pin_num % RK3188_PULL_PINS_PER_REG;
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>
> Why are these RK3188_ symbolic constants in the RK3399 path?
>
>> + } else {
>> + *regmap = priv->regmap_base;
>> + *reg = RK3399_PULL_GRF_OFFSET;
>> +
>> + /* correct the offset, as we're starting with the 3rd bank */
>> + *reg -= 0x20;
>> + *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
>> + *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
>> +
>> + *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
>> + *bit *= RK3188_PULL_BITS_PER_PIN;
>> + }
>> +}
>> +
>> +static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
>> + int pin_num, struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + int drv_num = (pin_num / 8);
>> +
>> + /* The bank0:16 and bank1:32 pins are located in PMU */
>> + if ((bank->bank_num == 0) || (bank->bank_num == 1))
>> + *regmap = priv->regmap_pmu;
>> + else
>> + *regmap = priv->regmap_base;
>> +
>> + *reg = bank->drv[drv_num].offset;
>> + if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
>> + (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
>> + *bit = (pin_num % 8) * 3;
>> + else
>> + *bit = (pin_num % 8) * 2;
>> +}
>> +
>> +static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
>> + { 2, 4, 8, 12, -1, -1, -1, -1 },
>> + { 3, 6, 9, 12, -1, -1, -1, -1 },
>> + { 5, 10, 15, 20, -1, -1, -1, -1 },
>> + { 4, 6, 8, 10, 12, 14, 16, 18 },
>> + { 4, 7, 10, 13, 16, 19, 22, 26 }
>> +};
>
> Please rewrite this (and add a comment), so it isn't a magic array.
>
>> +
>> +static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
>> + int pin_num, int strength)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> + struct regmap *regmap;
>> + int reg, ret, i;
>> + u32 data, rmask_bits, temp;
>> + u8 bit;
>> + int drv_type = bank->drv[pin_num / 8].drv_type;
>> +
>> + debug("setting drive of GPIO%d-%d to %d\n", bank->bank_num,
>> + pin_num, strength);
>> +
>> + ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
>> +
>> + ret = -EINVAL;
>> + for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]);
>> i++) {
>> + if (rockchip_perpin_drv_list[drv_type][i] == strength) {
>> + ret = i;
>> + break;
>> + } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
>> + ret = rockchip_perpin_drv_list[drv_type][i];
>> + break;
>> + }
>> + }
>> +
>> + if (ret < 0) {
>> + debug("unsupported driver strength %d\n", strength);
>> + return ret;
>> + }
>> +
>> + switch (drv_type) {
>> + case DRV_TYPE_IO_1V8_3V0_AUTO:
>> + case DRV_TYPE_IO_3V3_ONLY:
>> + rmask_bits = RK3399_DRV_3BITS_PER_PIN;
>> + switch (bit) {
>> + case 0 ... 12:
>> + /* regular case, nothing to do */
>> + break;
>> + case 15:
>> + /*
>> + * drive-strength offset is special, as it is spread
>> + * over 2 registers, the bit data[15] contains bit 0
>> + * of the value while temp[1:0] contains bits 2 and 1
>> + */
>> + data = (ret & 0x1) << 15;
>> + temp = (ret >> 0x1) & 0x3;
>> +
>> + data |= BIT(31);
>> + ret = regmap_write(regmap, reg, data);
>> + if (ret)
>> + return ret;
>> +
>> + temp |= (0x3 << 16);
>> + reg += 0x4;
>> + ret = regmap_write(regmap, reg, temp);
>> +
>> + return ret;
>> + case 18 ... 21:
>> + /* setting fully enclosed in the second register */
>> + reg += 4;
>> + bit -= 16;
>> + break;
>> + default:
>> + debug("unsupported bit: %d for pinctrl drive type: %d\n",
>> + bit, drv_type);
>> + return -EINVAL;
>> + }
>> + break;
>> + case DRV_TYPE_IO_DEFAULT:
>> + case DRV_TYPE_IO_1V8_OR_3V0:
>> + case DRV_TYPE_IO_1V8_ONLY:
>> + rmask_bits = RK3288_DRV_BITS_PER_PIN;
>> + break;
>> + default:
>> + debug("unsupported pinctrl drive type: %d\n",
>> + drv_type);
>> + return -EINVAL;
>> + }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << rmask_bits) - 1) << (bit + 16);
>> + data |= (ret << bit);
>> +
>> + ret = regmap_write(regmap, reg, data);
>> + return ret;
>> +}
>> +
>> +static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
>> + {
>> + PIN_CONFIG_BIAS_DISABLE,
>> + PIN_CONFIG_BIAS_PULL_UP,
>> + PIN_CONFIG_BIAS_PULL_DOWN,
>> + PIN_CONFIG_BIAS_BUS_HOLD
>> + },
>> + {
>> + PIN_CONFIG_BIAS_DISABLE,
>> + PIN_CONFIG_BIAS_PULL_DOWN,
>> + PIN_CONFIG_BIAS_DISABLE,
>> + PIN_CONFIG_BIAS_PULL_UP
>> + },
>> +};
>> +
>> +static int rockchip_set_pull(struct rockchip_pin_bank *bank,
>> + int pin_num, int pull)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> + struct regmap *regmap;
>> + int reg, ret, i, pull_type;
>> + u8 bit;
>> + u32 data;
>> +
>> + debug("setting pull of GPIO%d-%d to %d\n", bank->bank_num,
>> + pin_num, pull);
>> +
>> + /* rk3066b does support any pulls */
>> + if (ctrl->type == RK3066B)
>> + return pull ? -EINVAL : 0;
>> +
>> + ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
>> +
>> + switch (ctrl->type) {
>> + case RK2928:
>
> No RK2928 in U-Boot...
>
>> + case RK3128:
>> + data = BIT(bit + 16);
>> + if (pull == PIN_CONFIG_BIAS_DISABLE)
>> + data |= BIT(bit);
>> + ret = regmap_write(regmap, reg, data);
>> + break;
>> + case PX30:
>
> ...and neither a PX30 in U-Boot as of now.
>
>> + case RV1108:
>> + case RK3188:
>> + case RK3288:
>> + case RK3368:
>> + case RK3399:
>> + pull_type = bank->pull_type[pin_num / 8];
>> + ret = -EINVAL;
>> + for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
>> + i++) {
>> + if (rockchip_pull_list[pull_type][i] == pull) {
>> + ret = i;
>> + break;
>> + }
>> + }
>> +
>> + if (ret < 0) {
>> + debug("unsupported pull setting %d\n", pull);
>> + return ret;
>> + }
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
>> + data |= (ret << bit);
>> +
>> + ret = regmap_write(regmap, reg, data);
>> + break;
>> + default:
>> + debug("unsupported pinctrl type\n");
>> + return -EINVAL;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +#define RK3328_SCHMITT_BITS_PER_PIN 1
>> +#define RK3328_SCHMITT_PINS_PER_REG 16
>> +#define RK3328_SCHMITT_BANK_STRIDE 8
>> +#define RK3328_SCHMITT_GRF_OFFSET 0x380
>> +
>> +static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank
>> *bank,
>> + int pin_num,
>> + struct regmap **regmap,
>> + int *reg, u8 *bit)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> +
>> + *regmap = priv->regmap_base;
>> + *reg = RK3328_SCHMITT_GRF_OFFSET;
>> +
>> + *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
>> + *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
>> + *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
>> +
>> + return 0;
>> +}
>> +
>> +static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
>> + int pin_num, int enable)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> + struct regmap *regmap;
>> + int reg, ret;
>> + u8 bit;
>> + u32 data;
>> +
>> + debug("setting input schmitt of GPIO%d-%d to %d\n", bank->bank_num,
>> + pin_num, enable);
>> +
>> + ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
>> + if (ret)
>> + return ret;
>> +
>> + /* enable the write to the equivalent lower bits */
>> + data = BIT(bit + 16) | (enable << bit);
>> +
>> + return regmap_write(regmap, reg, data);
>> +}
>> +
>> +/*
>> + * Pinconf_ops handling
>> + */
>> +static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
>> + unsigned int pull)
>> +{
>> + switch (ctrl->type) {
>> + case RK2928:
>> + case RK3128:
>> + return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
>> + pull == PIN_CONFIG_BIAS_DISABLE);
>> + case RK3066B:
>> + return pull ? false : true;
>> + case PX30:
>> + case RV1108:
>> + case RK3188:
>> + case RK3288:
>> + case RK3368:
>> + case RK3399:
>> + return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
>> + }
>> +
>> + return false;
>> +}
>> +
>> +/* set the pin config settings for a specified pin */
>> +static int rockchip_pinconf_set(struct rockchip_pin_bank *bank,
>> + u32 pin, u32 param, u32 arg)
>> +{
>> + struct rockchip_pinctrl_priv *priv = bank->priv;
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> + int rc;
>> +
>> + switch (param) {
>> + case PIN_CONFIG_BIAS_DISABLE:
>> + rc = rockchip_set_pull(bank, pin, param);
>> + if (rc)
>> + return rc;
>> + break;
>> +
>> + case PIN_CONFIG_BIAS_PULL_UP:
>> + case PIN_CONFIG_BIAS_PULL_DOWN:
>> + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
>> + case PIN_CONFIG_BIAS_BUS_HOLD:
>> + if (!rockchip_pinconf_pull_valid(ctrl, param))
>> + return -ENOTSUPP;
>> +
>> + if (!arg)
>> + return -EINVAL;
>> +
>> + rc = rockchip_set_pull(bank, pin, param);
>> + if (rc)
>> + return rc;
>> + break;
>> +
>> + case PIN_CONFIG_DRIVE_STRENGTH:
>> + if (!ctrl->drv_calc_reg)
>> + return -ENOTSUPP;
>> +
>> + rc = rockchip_set_drive_perpin(bank, pin, arg);
>> + if (rc < 0)
>> + return rc;
>> + break;
>> +
>> + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
>> + if (!ctrl->schmitt_calc_reg)
>> + return -ENOTSUPP;
>> +
>> + rc = rockchip_set_schmitt(bank, pin, arg);
>> + if (rc < 0)
>> + return rc;
>> + break;
>> +
>> + default:
>> + break;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct pinconf_param rockchip_conf_params[] = {
>> + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
>> + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0 },
>> + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
>> + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
>> + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
>> + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
>> + { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
>> + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
>> + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
>> +};
>> +
>> +static int rockchip_pinconf_prop_name_to_param(const char *property,
>> + u32 *default_value)
>> +{
>> + const struct pinconf_param *p, *end;
>> +
>> + p = rockchip_conf_params;
>> + end = p + sizeof(rockchip_conf_params) / sizeof(struct
>> pinconf_param);
>> +
>> + /* See if this pctldev supports this parameter */
>> + for (; p < end; p++) {
>> + if (!strcmp(property, p->property)) {
>> + *default_value = p->default_value;
>> + return p->param;
>> + }
>> + }
>> +
>> + *default_value = 0;
>> + return -EPERM;
>> +}
>> +
>> +static int rockchip_pinctrl_set_state(struct udevice *dev,
>> + struct udevice *config)
>> +{
>> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
>> + struct rockchip_pin_ctrl *ctrl = priv->ctrl;
>> + const void *blob = gd->fdt_blob;
>> + int node = dev_of_offset(config);
>> + u32 cells[MAX_ROCKCHIP_PINS_ENTRIES * 4];
>> + u32 bank, pin, mux, conf, arg, default_val;
>> + int ret, count, i;
>> + const char *prop_name;
>> + int pcfg_node, property_offset, prop_len, param;
>> + const void *value;
>> +
>> + count = fdtdec_get_int_array_count(blob, node, "rockchip,pins",
>> + cells, ARRAY_SIZE(cells));
>> + if (count < 0) {
>> + debug("%s: bad array %d\n", __func__, count);
>> + return -EINVAL;
>> + }
>> +
>> + if (count > MAX_ROCKCHIP_PINS_ENTRIES * 4) {
>> + debug("%s: unsupported pins array count %d\n",
>> + __func__, count);
>> + return -EINVAL;
>> + }
>> +
>> + for (i = 0; i < (count >> 2); i++) {
>> + bank = cells[4 * i + 0];
>> + pin = cells[4 * i + 1];
>> + mux = cells[4 * i + 2];
>> + conf = cells[4 * i + 3];
>> +
>> + ret = rockchip_verify_config(dev, bank, pin);
>> + if (ret)
>> + return ret;
>> +
>> + ret = rockchip_set_mux(&ctrl->pin_banks[bank], pin, mux);
>> + if (ret)
>> + return ret;
>> +
>> + pcfg_node = fdt_node_offset_by_phandle(blob, conf);
>> + if (pcfg_node < 0)
>> + return -ENODEV;
>> +
>> + fdt_for_each_property_offset(property_offset, blob, pcfg_node) {
>> + value = fdt_getprop_by_offset(blob, property_offset,
>> + &prop_name, &prop_len);
>> + if (!value)
>> + return -ENOENT;
>> +
>> + param = rockchip_pinconf_prop_name_to_param(prop_name,
>> + &default_val);
>> + if (param < 0)
>> + break;
>> +
>> + if (prop_len >= sizeof(fdt32_t))
>> + arg = fdt32_to_cpu(*(fdt32_t *)value);
>> + else
>> + arg = default_val;
>> +
>> + ret = rockchip_pinconf_set(&ctrl->pin_banks[bank], pin,
>> + param, arg);
>> + if (ret) {
>> + debug("%s: rockchip_pinconf_set fail: %d\n",
>> + __func__, ret);
>> + return ret;
>> + }
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static struct pinctrl_ops rockchip_pinctrl_ops = {
>> + .set_state = rockchip_pinctrl_set_state,
>> + .get_gpio_mux = rockchip_pinctrl_get_gpio_mux,
>> +};
>> +
>> +/* retrieve the soc specific data */
>> +static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct
>> udevice *dev)
>> +{
>> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
>> + struct rockchip_pin_ctrl *ctrl =
>> + (struct rockchip_pin_ctrl *)dev_get_driver_data(dev);
>> + struct rockchip_pin_bank *bank;
>> + int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
>> +
>> + grf_offs = ctrl->grf_mux_offset;
>> + pmu_offs = ctrl->pmu_mux_offset;
>> + drv_pmu_offs = ctrl->pmu_drv_offset;
>> + drv_grf_offs = ctrl->grf_drv_offset;
>> + bank = ctrl->pin_banks;
>> +
>> + for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
>> + int bank_pins = 0;
>> +
>> + bank->priv = priv;
>> + bank->pin_base = ctrl->nr_pins;
>> + ctrl->nr_pins += bank->nr_pins;
>> +
>> + /* calculate iomux and drv offsets */
>> + for (j = 0; j < 4; j++) {
>> + struct rockchip_iomux *iom = &bank->iomux[j];
>> + struct rockchip_drv *drv = &bank->drv[j];
>> + int inc;
>> +
>> + if (bank_pins >= bank->nr_pins)
>> + break;
>> +
>> + /* preset iomux offset value, set new start value */
>> + if (iom->offset >= 0) {
>> + if (iom->type & IOMUX_SOURCE_PMU)
>> + pmu_offs = iom->offset;
>> + else
>> + grf_offs = iom->offset;
>> + } else { /* set current iomux offset */
>> + iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
>> + pmu_offs : grf_offs;
>> + }
>> +
>> + /* preset drv offset value, set new start value */
>> + if (drv->offset >= 0) {
>> + if (iom->type & IOMUX_SOURCE_PMU)
>> + drv_pmu_offs = drv->offset;
>> + else
>> + drv_grf_offs = drv->offset;
>> + } else { /* set current drv offset */
>> + drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
>> + drv_pmu_offs : drv_grf_offs;
>> + }
>> +
>> + debug("bank %d, iomux %d has iom_offset 0x%x drv_offset
>> 0x%x\n",
>> + i, j, iom->offset, drv->offset);
>> +
>> + /*
>> + * Increase offset according to iomux width.
>> + * 4bit iomux'es are spread over two registers.
>> + */
>> + inc = (iom->type & (IOMUX_WIDTH_4BIT |
>> + IOMUX_WIDTH_3BIT)) ? 8 : 4;
>> + if (iom->type & IOMUX_SOURCE_PMU)
>> + pmu_offs += inc;
>> + else
>> + grf_offs += inc;
>> +
>> + /*
>> + * Increase offset according to drv width.
>> + * 3bit drive-strenth'es are spread over two registers.
>> + */
>> + if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
>> + (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
>> + inc = 8;
>> + else
>> + inc = 4;
>> +
>> + if (iom->type & IOMUX_SOURCE_PMU)
>> + drv_pmu_offs += inc;
>> + else
>> + drv_grf_offs += inc;
>> +
>> + bank_pins += 8;
>> + }
>> +
>> + /* calculate the per-bank recalced_mask */
>> + for (j = 0; j < ctrl->niomux_recalced; j++) {
>> + int pin = 0;
>> +
>> + if (ctrl->iomux_recalced[j].num == bank->bank_num) {
>> + pin = ctrl->iomux_recalced[j].pin;
>> + bank->recalced_mask |= BIT(pin);
>> + }
>> + }
>> +
>> + /* calculate the per-bank route_mask */
>> + for (j = 0; j < ctrl->niomux_routes; j++) {
>> + int pin = 0;
>> +
>> + if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
>> + pin = ctrl->iomux_routes[j].pin;
>> + bank->route_mask |= BIT(pin);
>> + }
>> + }
>> + }
>> +
>> + return ctrl;
>> +}
>> +
>> +static int rockchip_pinctrl_probe(struct udevice *dev)
>> +{
>> + struct rockchip_pinctrl_priv *priv = dev_get_priv(dev);
>> + struct rockchip_pin_ctrl *ctrl;
>> + struct udevice *syscon;
>> + struct regmap *regmap;
>> + int ret = 0;
>> +
>> + /* get rockchip grf syscon phandle */
>> + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
>> "rockchip,grf",
>> + &syscon);
>> + if (ret) {
>> + debug("unable to find rockchip,grf syscon device (%d)\n", ret);
>> + return ret;
>> + }
>> +
>> + /* get grf-reg base address */
>> + regmap = syscon_get_regmap(syscon);
>> + if (!regmap) {
>> + debug("unable to find rockchip grf regmap\n");
>> + return -ENODEV;
>> + }
>> + priv->regmap_base = regmap;
>> +
>> + /* option: get pmu-reg base address */
>> + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
>> "rockchip,pmu",
>> + &syscon);
>> + if (!ret) {
>> + /* get pmugrf-reg base address */
>> + regmap = syscon_get_regmap(syscon);
>> + if (!regmap) {
>> + debug("unable to find rockchip pmu regmap\n");
>> + return -ENODEV;
>> + }
>> + priv->regmap_pmu = regmap;
>> + }
>> +
>> + ctrl = rockchip_pinctrl_get_soc_data(dev);
>> + if (!ctrl) {
>> + debug("driver data not available\n");
>> + return -EINVAL;
>> + }
>> +
>> + priv->ctrl = ctrl;
>> + return 0;
>> +}
>> +
>> +static struct rockchip_pin_bank px30_pin_banks[] = {
>> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU
>> + ),
>> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT
>> + ),
>> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT
>> + ),
>> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT
>> + ),
>> +};
>> +
>> +static struct rockchip_pin_ctrl px30_pin_ctrl = {
>> + .pin_banks = px30_pin_banks,
>> + .nr_banks = ARRAY_SIZE(px30_pin_banks),
>> + .label = "PX30-GPIO",
>> + .type = PX30,
>> + .grf_mux_offset = 0x0,
>> + .pmu_mux_offset = 0x0,
>> + .iomux_routes = px30_mux_route_data,
>> + .niomux_routes = ARRAY_SIZE(px30_mux_route_data),
>> + .pull_calc_reg = px30_calc_pull_reg_and_bit,
>> + .drv_calc_reg = px30_calc_drv_reg_and_bit,
>> + .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rv1108_pin_banks[] = {
>> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU),
>> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
>> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
>> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
>> + .pin_banks = rv1108_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
>> + .label = "RV1108-GPIO",
>> + .type = RV1108,
>> + .grf_mux_offset = 0x10,
>> + .pmu_mux_offset = 0x0,
>> + .iomux_recalced = rv1108_mux_recalced_data,
>> + .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
>> + .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
>> + .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
>> + .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk2928_pin_banks[] = {
>> + PIN_BANK(0, 32, "gpio0"),
>> + PIN_BANK(1, 32, "gpio1"),
>> + PIN_BANK(2, 32, "gpio2"),
>> + PIN_BANK(3, 32, "gpio3"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
>> + .pin_banks = rk2928_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
>> + .label = "RK2928-GPIO",
>> + .type = RK2928,
>> + .grf_mux_offset = 0xa8,
>> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3036_pin_banks[] = {
>> + PIN_BANK(0, 32, "gpio0"),
>> + PIN_BANK(1, 32, "gpio1"),
>> + PIN_BANK(2, 32, "gpio2"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
>> + .pin_banks = rk3036_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
>> + .label = "RK3036-GPIO",
>> + .type = RK2928,
>> + .grf_mux_offset = 0xa8,
>> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3066a_pin_banks[] = {
>> + PIN_BANK(0, 32, "gpio0"),
>> + PIN_BANK(1, 32, "gpio1"),
>> + PIN_BANK(2, 32, "gpio2"),
>> + PIN_BANK(3, 32, "gpio3"),
>> + PIN_BANK(4, 32, "gpio4"),
>> + PIN_BANK(6, 16, "gpio6"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
>> + .pin_banks = rk3066a_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
>> + .label = "RK3066a-GPIO",
>> + .type = RK2928,
>> + .grf_mux_offset = 0xa8,
>> + .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3066b_pin_banks[] = {
>> + PIN_BANK(0, 32, "gpio0"),
>> + PIN_BANK(1, 32, "gpio1"),
>> + PIN_BANK(2, 32, "gpio2"),
>> + PIN_BANK(3, 32, "gpio3"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
>> + .pin_banks = rk3066b_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
>> + .label = "RK3066b-GPIO",
>> + .type = RK3066B,
>> + .grf_mux_offset = 0x60,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3128_pin_banks[] = {
>> + PIN_BANK(0, 32, "gpio0"),
>> + PIN_BANK(1, 32, "gpio1"),
>> + PIN_BANK(2, 32, "gpio2"),
>> + PIN_BANK(3, 32, "gpio3"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
>> + .pin_banks = rk3128_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
>> + .label = "RK3128-GPIO",
>> + .type = RK3128,
>> + .grf_mux_offset = 0xa8,
>> + .iomux_recalced = rk3128_mux_recalced_data,
>> + .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
>> + .iomux_routes = rk3128_mux_route_data,
>> + .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
>> + .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3188_pin_banks[] = {
>> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
>> + PIN_BANK(1, 32, "gpio1"),
>> + PIN_BANK(2, 32, "gpio2"),
>> + PIN_BANK(3, 32, "gpio3"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
>> + .pin_banks = rk3188_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
>> + .label = "RK3188-GPIO",
>> + .type = RK3188,
>> + .grf_mux_offset = 0x60,
>> + .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3228_pin_banks[] = {
>> + PIN_BANK(0, 32, "gpio0"),
>> + PIN_BANK(1, 32, "gpio1"),
>> + PIN_BANK(2, 32, "gpio2"),
>> + PIN_BANK(3, 32, "gpio3"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
>> + .pin_banks = rk3228_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
>> + .label = "RK3228-GPIO",
>> + .type = RK3288,
>> + .grf_mux_offset = 0x0,
>> + .iomux_routes = rk3228_mux_route_data,
>> + .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
>> + .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
>> + .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3288_pin_banks[] = {
>> + PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_UNROUTED
>> + ),
>> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
>> + IOMUX_UNROUTED,
>> + IOMUX_UNROUTED,
>> + 0
>> + ),
>> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
>> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
>> + PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
>> + IOMUX_WIDTH_4BIT,
>> + 0,
>> + 0
>> + ),
>> + PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
>> + 0,
>> + 0,
>> + IOMUX_UNROUTED
>> + ),
>> + PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
>> + PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
>> + 0,
>> + IOMUX_WIDTH_4BIT,
>> + IOMUX_UNROUTED
>> + ),
>> + PIN_BANK(8, 16, "gpio8"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
>> + .pin_banks = rk3288_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
>> + .label = "RK3288-GPIO",
>> + .type = RK3288,
>> + .grf_mux_offset = 0x0,
>> + .pmu_mux_offset = 0x84,
>> + .iomux_routes = rk3288_mux_route_data,
>> + .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
>> + .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
>> + .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3328_pin_banks[] = {
>> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
>> + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
>> + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
>> + IOMUX_WIDTH_3BIT,
>> + IOMUX_WIDTH_3BIT,
>> + 0),
>> + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
>> + IOMUX_WIDTH_3BIT,
>> + IOMUX_WIDTH_3BIT,
>> + 0,
>> + 0),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
>> + .pin_banks = rk3328_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
>> + .label = "RK3328-GPIO",
>> + .type = RK3288,
>> + .grf_mux_offset = 0x0,
>> + .iomux_recalced = rk3328_mux_recalced_data,
>> + .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
>> + .iomux_routes = rk3328_mux_route_data,
>> + .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
>> + .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
>> + .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
>> + .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3368_pin_banks[] = {
>> + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU
>> + ),
>> + PIN_BANK(1, 32, "gpio1"),
>> + PIN_BANK(2, 32, "gpio2"),
>> + PIN_BANK(3, 32, "gpio3"),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
>> + .pin_banks = rk3368_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
>> + .label = "RK3368-GPIO",
>> + .type = RK3368,
>> + .grf_mux_offset = 0x0,
>> + .pmu_mux_offset = 0x0,
>> + .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
>> + .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
>> +};
>> +
>> +static struct rockchip_pin_bank rk3399_pin_banks[] = {
>> + PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + DRV_TYPE_IO_1V8_ONLY,
>> + DRV_TYPE_IO_1V8_ONLY,
>> + DRV_TYPE_IO_DEFAULT,
>> + DRV_TYPE_IO_DEFAULT,
>> + 0x80,
>> + 0x88,
>> + -1,
>> + -1,
>> + PULL_TYPE_IO_1V8_ONLY,
>> + PULL_TYPE_IO_1V8_ONLY,
>> + PULL_TYPE_IO_DEFAULT,
>> + PULL_TYPE_IO_DEFAULT
>> + ),
>> + PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + IOMUX_SOURCE_PMU,
>> + DRV_TYPE_IO_1V8_OR_3V0,
>> + DRV_TYPE_IO_1V8_OR_3V0,
>> + DRV_TYPE_IO_1V8_OR_3V0,
>> + DRV_TYPE_IO_1V8_OR_3V0,
>> + 0xa0,
>> + 0xa8,
>> + 0xb0,
>> + 0xb8
>> + ),
>> + PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2",
>> DRV_TYPE_IO_1V8_OR_3V0,
>> + DRV_TYPE_IO_1V8_OR_3V0,
>> + DRV_TYPE_IO_1V8_ONLY,
>> + DRV_TYPE_IO_1V8_ONLY,
>> + PULL_TYPE_IO_DEFAULT,
>> + PULL_TYPE_IO_DEFAULT,
>> + PULL_TYPE_IO_1V8_ONLY,
>> + PULL_TYPE_IO_1V8_ONLY
>> + ),
>> + PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
>> + DRV_TYPE_IO_3V3_ONLY,
>> + DRV_TYPE_IO_3V3_ONLY,
>> + DRV_TYPE_IO_1V8_OR_3V0
>> + ),
>> + PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
>> + DRV_TYPE_IO_1V8_3V0_AUTO,
>> + DRV_TYPE_IO_1V8_OR_3V0,
>> + DRV_TYPE_IO_1V8_OR_3V0
>> + ),
>> +};
>> +
>> +static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
>> + .pin_banks = rk3399_pin_banks,
>> + .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
>> + .label = "RK3399-GPIO",
>> + .type = RK3399,
>> + .grf_mux_offset = 0xe000,
>> + .pmu_mux_offset = 0x0,
>> + .grf_drv_offset = 0xe100,
>> + .pmu_drv_offset = 0x80,
>> + .iomux_routes = rk3399_mux_route_data,
>> + .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
>> + .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
>> + .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
>> +};
>> +
>> +static const struct udevice_id rockchip_pinctrl_dt_match[] = {
>> + { .compatible = "rockchip,px30-pinctrl",
>> + .data = (ulong)&px30_pin_ctrl },
>> + { .compatible = "rockchip,rv1108-pinctrl",
>> + .data = (ulong)&rv1108_pin_ctrl },
>> + { .compatible = "rockchip,rk2928-pinctrl",
>> + .data = (ulong)&rk2928_pin_ctrl },
>> + { .compatible = "rockchip,rk3036-pinctrl",
>> + .data = (ulong)&rk3036_pin_ctrl },
>> + { .compatible = "rockchip,rk3066a-pinctrl",
>> + .data = (ulong)&rk3066a_pin_ctrl },
>> + { .compatible = "rockchip,rk3066b-pinctrl",
>> + .data = (ulong)&rk3066b_pin_ctrl },
>> + { .compatible = "rockchip,rk3128-pinctrl",
>> + .data = (ulong)&rk3128_pin_ctrl },
>> + { .compatible = "rockchip,rk3188-pinctrl",
>> + .data = (ulong)&rk3188_pin_ctrl },
>> + { .compatible = "rockchip,rk3228-pinctrl",
>> + .data = (ulong)&rk3228_pin_ctrl },
>> + { .compatible = "rockchip,rk3288-pinctrl",
>> + .data = (ulong)&rk3288_pin_ctrl },
>> + { .compatible = "rockchip,rk3328-pinctrl",
>> + .data = (ulong)&rk3328_pin_ctrl },
>> + { .compatible = "rockchip,rk3368-pinctrl",
>> + .data = (ulong)&rk3368_pin_ctrl },
>> + { .compatible = "rockchip,rk3399-pinctrl",
>> + .data = (ulong)&rk3399_pin_ctrl },
>> + {},
>> +};
>
> No point in always adding all possible SOC support in U-Boot. Given that
> users may be space-sensitive, we should only pull in support for those
> chips that are needed.
>
> Furthermore, we've had the decision on how to structure such drivers
> earlier (last time I remember was for HDMI): there should be a common
> driver infrastructure and multiple mini-drivers that reference it (see
> drivers/video/rockchip/*_{vop,hmdi}.[ch]) and that can be selectively
> pulled in.
>
>> +
>> +U_BOOT_DRIVER(pinctrl_rockchip) = {
>> + .name = "rockchip_pinctrl",
>> + .id = UCLASS_PINCTRL,
>> + .of_match = rockchip_pinctrl_dt_match,
>> + .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
>> + .ops = &rockchip_pinctrl_ops,
>> +#if !CONFIG_IS_ENABLED(OF_PLATDATA)
>> + .bind = dm_scan_fdt_dev,
>> +#endif
>> + .probe = rockchip_pinctrl_probe,
>> +};
>>
>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [U-Boot] [U-Boot, 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL
2018-02-18 19:00 ` Philipp Tomsich
@ 2018-03-05 11:36 ` David Wu
0 siblings, 0 replies; 31+ messages in thread
From: David Wu @ 2018-03-05 11:36 UTC (permalink / raw)
To: u-boot
Hi Philipp,
在 2018年02月19日 03:00, Philipp Tomsich 写道:
>
>
> On Sat, 3 Feb 2018, David Wu wrote:
>
>> When the boot ROM sets up MMC we don't need to do it again. Remove the
>> MMC setup code entirely, but we also need to enable uart for debug
>> message.
>
> If the MMC always set up correctly for all configurations (e.g. bus-width)
> or should some of the setup be duplicated there to ensure that we catch
> all corner cases?
For this, I will do a check if we need to setup duplicated.
>
>> Signed-off-by: David Wu <david.wu@rock-chips.com>
>> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>> ---
>>
>> arch/arm/mach-rockchip/rk3188-board-spl.c | 42
>> +++----------------------------
>> 1 file changed, 3 insertions(+), 39 deletions(-)
>>
>> diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c
>> b/arch/arm/mach-rockchip/rk3188-board-spl.c
>> index 8e3b8ae..8371a31 100644
>> --- a/arch/arm/mach-rockchip/rk3188-board-spl.c
>> +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c
>> @@ -100,10 +100,11 @@ static int setup_arm_clock(void)
>>
>> void board_init_f(ulong dummy)
>> {
>> - struct udevice *pinctrl, *dev;
>> + struct udevice *dev;
>> int ret;
>>
>> /* Example code showing how to enable the debug UART on RK3188 */
>> +#define EARLY_UART
>> #ifdef EARLY_UART
>> #include <asm/arch/grf_rk3188.h>
>> /* Enable early UART on the RK3188 */
>> @@ -124,10 +125,7 @@ void board_init_f(ulong dummy)
>> * printascii("string");
>> */
>> debug_uart_init();
>> - printch('s');
>> - printch('p');
>> - printch('l');
>> - printch('\n');
>> + printascii("U-Boot SPL board init");
>> #endif
>>
>> ret = spl_early_init();
>> @@ -144,12 +142,6 @@ void board_init_f(ulong dummy)
>> return;
>> }
>>
>> - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
>> - if (ret) {
>> - debug("Pinctrl init failed: %d\n", ret);
>> - return;
>> - }
>> -
>> ret = uclass_get_device(UCLASS_RAM, 0, &dev);
>> if (ret) {
>> debug("DRAM init failed: %d\n", ret);
>> @@ -187,7 +179,6 @@ static int setup_led(void)
>>
>> void spl_board_init(void)
>> {
>> - struct udevice *pinctrl;
>> int ret;
>>
>> ret = setup_led();
>> @@ -196,36 +187,9 @@ void spl_board_init(void)
>> hang();
>> }
>>
>> - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
>> - if (ret) {
>> - debug("%s: Cannot find pinctrl device\n", __func__);
>> - goto err;
>> - }
>> -
>> -#ifdef CONFIG_SPL_MMC_SUPPORT
>> - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
>> - if (ret) {
>> - debug("%s: Failed to set up SD card\n", __func__);
>> - goto err;
>> - }
>> -#endif
>> -
>> - /* Enable debug UART */
>> - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
>> - if (ret) {
>> - debug("%s: Failed to set up console UART\n", __func__);
>> - goto err;
>> - }
>> -
>> preloader_console_init();
>> #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
>> back_to_bootrom(BROM_BOOT_NEXTSTAGE);
>> #endif
>> return;
>> -
>> -err:
>> - printf("spl_board_init: Error %d\n", ret);
>> -
>> - /* No way to report error here */
>> - hang();
>> }
>>
>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2018-03-05 11:36 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-03 6:51 [U-Boot] [PATCH 0/9] Add common pinctrl driver support for rockchip David Wu
2018-02-03 6:51 ` [U-Boot] [PATCH 1/9] rockchip: rk3399-evb: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-18 18:57 ` Philipp Tomsich
2018-02-03 6:51 ` [U-Boot] [PATCH 2/9] ARM: rockchip: rk3188: Remove the pinctrl setup and enable uart at SPL David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-18 19:00 ` Philipp Tomsich
2018-03-05 11:36 ` David Wu
2018-02-03 6:51 ` [U-Boot] [PATCH 3/9] ARM: rockchip: Kconfig: Remove the SPL_PINCTRL for rk3188 David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
2018-02-03 6:51 ` [U-Boot] [PATCH 4/9] ARM: rockchip: Remove the pinctrl request at rk3288-board-spl David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
2018-02-03 6:55 ` [U-Boot] [PATCH 5/9] rk3288: chrome: defconfig: Disable SPL_OF_PLATDATA for new pinctrl driver David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-18 19:01 ` Philipp Tomsich
2018-02-03 6:56 ` [U-Boot] [PATCH 6/9] pinctrl: rockchip: Add common rockchip " David Wu
2018-02-04 7:45 ` Kever Yang
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-18 19:20 ` Philipp Tomsich
2018-03-05 11:23 ` David Wu
2018-02-03 6:56 ` [U-Boot] [PATCH 7/9] rockchip: defconfig: Clean the unused pinctrl config David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
2018-02-03 6:57 ` [U-Boot] [PATCH 8/9] pinctrl: rockchip: Clean the unused rockchip pinctrl drivers David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
2018-02-03 6:57 ` [U-Boot] [PATCH 9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration David Wu
2018-02-09 10:13 ` [U-Boot] [U-Boot, " Philipp Tomsich
2018-02-09 10:15 ` Philipp Tomsich
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