[PATCH 00/10] Enable auto wattman feature on Polaris

[PATCH 00/10] Enable auto wattman feature on Polaris

[Rex Zhu]

Enable auto wattman on polaris.
Manual set wattman feature related parameters on other smu7 asics.

In manual dpm mode, auto wattman feature was disabled.
user can change auto wattman related parameters through sysfs
pp_power_profile_mode.

Rex Zhu (10):
  drm/amd/amdgpu: Add query vram width in CGS query system info
  drm/amdgpu: Add a pp feature mask bit for autowattman
  drm/amd/pp: Add new smu callback function
  drm/amd/pp: Implement update_dpm_settings on Polaris
  drm/amd/pp: Implement get_power_profile_mode on smu7
  drm/amd/pp: Implement set_power_profile_mode on smu7
  drm/amd/pp: Add new hw interface for auto wattman feature.
  drm/amd/pp: Implement auto wattman feature on Smu7
  drm/amd/pp: Restore power profile mode in auto dpm level on smu7
  drm/amd/pp: Enable auto automan feature on Polaris

 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c            |   3 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c            |   2 +-
 drivers/gpu/drm/amd/include/cgs_common.h           |   1 +
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        |  39 +++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 358 ++++++++++++++++++++-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h   |  26 ++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          |   6 +
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h         |   1 +
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    | 104 ++++++
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c      |   8 +
 10 files changed, 545 insertions(+), 3 deletions(-)

-- 
1.9.1

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[PATCH 01/10] drm/amd/amdgpu: Add query vram width in CGS query system info

[Rex Zhu]

Change-Id: I4bf7abab944253c8c744c1290b8a9fb5a62b6240
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 3 +++
 drivers/gpu/drm/amd/include/cgs_common.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 71b4aec..1f4e37b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -905,6 +905,9 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
 	case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
 		sys_info->value = adev->pdev->devfn;
 		break;
+	case CGS_SYSTEM_INFO_VRAM_WIDTH:
+		sys_info->value = adev->gmc.vram_width;
+		break;
 	default:
 		return -ENODEV;
 	}
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index f5c7397..98cf4ce 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -101,6 +101,7 @@ enum cgs_system_info_id {
 	CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
 	CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
 	CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
+	CGS_SYSTEM_INFO_VRAM_WIDTH,
 	CGS_SYSTEM_INFO_ID_MAXIMUM,
 };
 
-- 
1.9.1

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[PATCH 02/10] drm/amdgpu: Add a pp feature mask bit for autowattman

[Rex Zhu]

Change-Id: Ie329d6c806fc5ab71417ffabe413ddbdf9d367ea
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d3f5ee5..e2011d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -121,7 +121,7 @@
 uint amdgpu_sdma_phase_quantum = 32;
 char *amdgpu_disable_cu = NULL;
 char *amdgpu_virtual_display = NULL;
-uint amdgpu_pp_feature_mask = 0x3fff;
+uint amdgpu_pp_feature_mask = 0xffffbfff;
 int amdgpu_ngg = 0;
 int amdgpu_prim_buf_per_se = 0;
 int amdgpu_pos_buf_per_se = 0;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 2a59ee8..77d7f49 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -85,6 +85,7 @@ enum PP_FEATURE_MASK {
 	PP_SOCCLK_DPM_MASK = 0x1000,
 	PP_DCEFCLK_DPM_MASK = 0x2000,
 	PP_OVERDRIVE_MASK = 0x4000,
+	PP_AUTOWATTMAN_MASK = 0x8000,
 };
 
 enum PHM_BackEnd_Magic {
-- 
1.9.1

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[PATCH 03/10] drm/amd/pp: Add new smu callback function

[Rex Zhu]

it is used for adjust part of dpm settigs
to get better performance under different
workloads.

Change-Id: I1e1ed786e9c07c91fb7e810af5b1ec5dd5cc4791
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h     | 1 +
 drivers/gpu/drm/amd/powerplay/inc/smumgr.h    | 1 +
 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 8 ++++++++
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 77d7f49..31988d7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -239,6 +239,7 @@ struct pp_smumgr_func {
 	int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
 			struct amd_pp_profile *request);
 	bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
+	int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
 };
 
 struct pp_hwmgr_func {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
index b1b27b2..e05a57e 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
@@ -134,5 +134,6 @@ extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
 
 extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
 
+extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting);
 
 #endif
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
index 8673884..1ce4959 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
@@ -253,3 +253,11 @@ bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
 
 	return false;
 }
+
+int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting)
+{
+	if (hwmgr->smumgr_funcs->update_dpm_settings)
+		return hwmgr->smumgr_funcs->update_dpm_settings(hwmgr, profile_setting);
+
+	return -EINVAL;
+}
-- 
1.9.1

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[PATCH 04/10] drm/amd/pp: Implement update_dpm_settings on Polaris

[Rex Zhu]

Change-Id: I4533826ef6e18df125ae4445016873be3b5fe0ce
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    | 104 +++++++++++++++++++++
 1 file changed, 104 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index bfb2c85..559572d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -2575,6 +2575,109 @@ static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
 				array_size, SMC_RAM_END);
 }
 
+uint32_t polaris10_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)
+{
+	u32 mask = 0;
+	u32 shift = 0;
+
+	shift = (offset % 4) << 3;
+	if (size == sizeof(uint8_t))
+		mask = 0xFF << shift;
+	else if (size == sizeof(uint16_t))
+		mask = 0xFFFF << shift;
+
+	original_data &= ~mask;
+	original_data |= (field << shift);
+	return original_data;
+}
+
+static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
+				void *profile_setting)
+{
+	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
+			(hwmgr->smu_backend);
+	struct profile_mode_setting *setting;
+	struct SMU74_Discrete_GraphicsLevel *levels =
+			smu_data->smc_state_table.GraphicsLevel;
+	uint32_t array = smu_data->smu7_data.dpm_table_start +
+			offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
+
+	uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
+			offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
+	struct SMU74_Discrete_MemoryLevel *mclk_levels =
+			smu_data->smc_state_table.MemoryLevel;
+	uint32_t i;
+	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
+
+	if (profile_setting == NULL)
+		return -EINVAL;
+
+	setting = (struct profile_mode_setting *)profile_setting;
+
+	if (setting->bupdate_sclk) {
+		for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
+			if (levels[i].ActivityLevel !=
+				cpu_to_be16(setting->sclk_activity)) {
+				levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
+
+				clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
+						+ offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
+				offset = clk_activity_offset & ~0x3;
+				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
+				tmp = polaris10_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
+				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+
+			}
+			if (levels[i].UpHyst != setting->sclk_up_hyst ||
+				levels[i].DownHyst != setting->sclk_down_hyst) {
+				levels[i].UpHyst = setting->sclk_up_hyst;
+				levels[i].DownHyst = setting->sclk_down_hyst;
+				up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
+						+ offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
+				down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
+						+ offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
+				offset = up_hyst_offset & ~0x3;
+				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
+				tmp = polaris10_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
+				tmp = polaris10_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
+				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+			}
+		}
+	}
+
+	if (setting->bupdate_mclk) {
+		for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
+			if (mclk_levels[i].ActivityLevel !=
+				cpu_to_be16(setting->mclk_activity)) {
+				mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
+
+				clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
+						+ offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
+				offset = clk_activity_offset & ~0x3;
+				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
+				tmp = polaris10_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
+				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+
+			}
+			if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
+				mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
+				mclk_levels[i].UpHyst = setting->mclk_up_hyst;
+				mclk_levels[i].DownHyst = setting->mclk_down_hyst;
+				up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
+						+ offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
+				down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
+						+ offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
+				offset = up_hyst_offset & ~0x3;
+				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
+				tmp = polaris10_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
+				tmp = polaris10_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
+				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
+			}
+		}
+	}
+	return 0;
+}
+
 const struct pp_smumgr_func polaris10_smu_funcs = {
 	.smu_init = polaris10_smu_init,
 	.smu_fini = smu7_smu_fini,
@@ -2599,4 +2702,5 @@ static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
 	.is_dpm_running = polaris10_is_dpm_running,
 	.populate_requested_graphic_levels = polaris10_populate_requested_graphic_levels,
 	.is_hw_avfs_present = polaris10_is_hw_avfs_present,
+	.update_dpm_settings = polaris10_update_dpm_settings,
 };
-- 
1.9.1

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[PATCH 05/10] drm/amd/pp: Implement get_power_profile_mode on smu7

[Rex Zhu]

It show what parameters can be setted on smu7(vi/ci asics)
to get better performance.

Also show some profiling modes, user can select directly
by serial number based on workloads.

cat pp_power_profile_mode
NUM        MODE_NAME     SCLK_UP_HYST   SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL     MCLK_UP_HYST   MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL
  0   3D_FULL_SCREEN:        0              100               30                0              100               10
  1     POWER_SAVING:       10                0               30                -                -                -
  2            VIDEO:        -                -                -               10               16               31
  3               VR:        0               11               50                0              100               10
  4          COMPUTE:        0                5               30                -                -                -
  5           CUSTOM:        0                0                0                0                0                0
  *          CURRENT:        0              100               30                0              100               10

Change-Id: If0e9796d6cbe531ce1eb5ff181fe2f5f956437b6
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 87 ++++++++++++++++++++++++
 1 file changed, 87 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 9379713..8cf95d9 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -81,6 +81,21 @@
 #define PCIE_BUS_CLK                10000
 #define TCLK                        (PCIE_BUS_CLK / 10)
 
+static const struct profile_mode_setting smu7_profiling[5] =
+					{{1, 0, 100, 30, 1, 0, 100, 10},
+					 {1, 10, 0, 30, 0, 0, 0, 0},
+					 {0, 0, 0, 0, 1, 10, 16, 31},
+					 {1, 0, 11, 50, 1, 0, 100, 10},
+					 {1, 0, 5, 30, 0, 0, 0, 0},
+					};
+
+static const struct profile_mode_setting polaris11_profiling[5] =
+					{{1, 0, 100, 30, 1, 0, 100, 10},
+					 {1, 10, 0, 30, 0, 0, 0, 0},
+					 {0, 0, 0, 0, 1, 10, 16, 62},
+					 {1, 0, 11, 50, 1, 0, 100, 10},
+					 {1, 0, 5, 30, 0, 0, 0, 0},
+					};
 
 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
 enum DPM_EVENT_SRC {
@@ -4932,6 +4947,77 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
 	return 0;
 }
 
+static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	uint32_t i, size = 0;
+	uint32_t len;
+
+	static const char *profile_name[6] = {"3D_FULL_SCREEN",
+					"POWER_SAVING",
+					"VIDEO",
+					"VR",
+					"COMPUTE",
+					"CUSTOM"};
+
+	static const char *title[8] = {"NUM",
+			"MODE_NAME",
+			"SCLK_UP_HYST",
+			"SCLK_DOWN_HYST",
+			"SCLK_ACTIVE_LEVEL",
+			"MCLK_UP_HYST",
+			"MCLK_DOWN_HYST",
+			"MCLK_ACTIVE_LEVEL"};
+
+	if (!buf)
+		return -EINVAL;
+
+	size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
+			title[0], title[1], title[2], title[3],
+			title[4], title[5], title[6], title[7]);
+
+	len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
+
+	for (i = 0; i < len; i++) {
+		if (smu7_profiling[i].bupdate_sclk)
+			size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
+			i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
+			smu7_profiling[i].sclk_down_hyst,
+			smu7_profiling[i].sclk_activity);
+		else
+			size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
+			i, profile_name[i], "-", "-", "-");
+
+		if (smu7_profiling[i].bupdate_mclk)
+			size += sprintf(buf + size, "%16d %16d %16d\n",
+			smu7_profiling[i].mclk_up_hyst,
+			smu7_profiling[i].mclk_down_hyst,
+			smu7_profiling[i].mclk_activity);
+		else
+			size += sprintf(buf + size, "%16s %16s %16s\n",
+			"-", "-", "-");
+	}
+
+	size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
+			i, profile_name[i],
+			data->custom_profile_setting.sclk_up_hyst,
+			data->custom_profile_setting.sclk_down_hyst,
+			data->custom_profile_setting.sclk_activity,
+			data->custom_profile_setting.mclk_up_hyst,
+			data->custom_profile_setting.mclk_down_hyst,
+			data->custom_profile_setting.mclk_activity);
+
+	size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
+			"*", "CURRENT",
+			data->current_profile_setting.sclk_up_hyst,
+			data->current_profile_setting.sclk_down_hyst,
+			data->current_profile_setting.sclk_activity,
+			data->current_profile_setting.mclk_up_hyst,
+			data->current_profile_setting.mclk_down_hyst,
+			data->current_profile_setting.mclk_activity);
+
+	return size;
+}
 
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
 	.backend_init = &smu7_hwmgr_backend_init,
@@ -4988,6 +5074,7 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
 	.get_thermal_temperature_range = smu7_get_thermal_temperature_range,
 	.odn_edit_dpm_table = smu7_odn_edit_dpm_table,
 	.set_power_limit = smu7_set_power_limit,
+	.get_power_profile_mode = smu7_get_power_profile_mode,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
-- 
1.9.1

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[PATCH 06/10] drm/amd/pp: Implement set_power_profile_mode on smu7

[Rex Zhu]

User can set smu7 dpm pamameters through sysfs

Depending on the workloads,
user can echo "0/1/2/3/4">pp_power_profile_mode
to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE
mode.

echo "5 * * * * * * * *">pp_power_profile_mode
to config custom mode.
"5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST
SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST
MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL"

if the parameter enable_sclk/enable_mclk is true,
driver will update the following parameters to dpm table.
if false, ignore the following parameters.

Change-Id: I8b5fc6fb2e20e6cd50b4184458452ac22c562469
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 52 ++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 8cf95d9..08e9e44 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5019,6 +5019,57 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
 	return size;
 }
 
+static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	struct profile_mode_setting tmp;
+
+	hwmgr->power_profile_mode = input[size];
+
+	switch (hwmgr->power_profile_mode) {
+	case PP_SMC_POWER_PROFILE_CUSTOM:
+		if (size < 8)
+			return -EINVAL;
+
+		data->custom_profile_setting.bupdate_sclk = input[0];
+		data->custom_profile_setting.sclk_up_hyst = input[1];
+		data->custom_profile_setting.sclk_down_hyst = input[2];
+		data->custom_profile_setting.sclk_activity =  input[3];
+		data->custom_profile_setting.bupdate_mclk = input[4];
+		data->custom_profile_setting.mclk_up_hyst = input[5];
+		data->custom_profile_setting.mclk_down_hyst = input[6];
+		data->custom_profile_setting.mclk_activity =  input[7];
+		if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting))
+			memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting));
+		break;
+	case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
+	case PP_SMC_POWER_PROFILE_POWERSAVING:
+	case PP_SMC_POWER_PROFILE_VIDEO:
+	case PP_SMC_POWER_PROFILE_VR:
+	case PP_SMC_POWER_PROFILE_COMPUTE:
+		memcpy(&tmp, &smu7_profiling[hwmgr->power_profile_mode], sizeof(struct profile_mode_setting));
+		if (!smum_update_dpm_settings(hwmgr, &tmp)) {
+			if (tmp.bupdate_sclk) {
+				data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
+				data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
+				data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
+				data->current_profile_setting.sclk_activity = tmp.sclk_activity;
+			}
+			if (tmp.bupdate_mclk) {
+				data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
+				data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
+				data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
+				data->current_profile_setting.mclk_activity = tmp.mclk_activity;
+			}
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
 	.backend_init = &smu7_hwmgr_backend_init,
 	.backend_fini = &smu7_hwmgr_backend_fini,
@@ -5075,6 +5126,7 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
 	.odn_edit_dpm_table = smu7_odn_edit_dpm_table,
 	.set_power_limit = smu7_set_power_limit,
 	.get_power_profile_mode = smu7_get_power_profile_mode,
+	.set_power_profile_mode = smu7_set_power_profile_mode,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
-- 
1.9.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 07/10] drm/amd/pp: Add new hw interface for auto wattman feature.

[Rex Zhu]

Change-Id: Ib34c2815ab95890ba91f9a61bc0594b0f5e0c3fd
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 31988d7..d809d96 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -351,6 +351,8 @@ struct pp_hwmgr_func {
 					long *input, uint32_t size);
 	int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
 	int (*set_mmhub_powergating_by_smu)(struct pp_hwmgr *hwmgr);
+	int (*update_auto_wattman)(struct pp_hwmgr *hwmgr);
+	void (*start_auto_wattman)(struct pp_hwmgr *hwmgr, bool en);
 };
 
 struct pp_table_func {
-- 
1.9.1

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 08/10] drm/amd/pp: Implement auto wattman feature on Smu7

[Rex Zhu]

Change-Id: Id0826f7a12a30461fca38862904f2f20c811989a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c      |  35 ++++
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 200 ++++++++++++++++++++++-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h |  26 +++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h        |   2 +
 4 files changed, 262 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 33eabc1..f50b6cd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -236,6 +236,20 @@ int hwmgr_early_init(struct pp_instance *handle)
 	return 0;
 }
 
+static void wattman_sample_handler(struct work_struct *work)
+{
+	struct pp_hwmgr *hwmgr =
+		container_of(work, struct pp_hwmgr, wattman_idle_work.work);
+
+	if (hwmgr->autowattman_enabled) {
+		if (hwmgr->hwmgr_func->update_auto_wattman != NULL)
+			hwmgr->hwmgr_func->update_auto_wattman(hwmgr);
+
+		if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+			hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+	}
+}
+
 int hwmgr_hw_init(struct pp_instance *handle)
 {
 	struct pp_hwmgr *hwmgr;
@@ -246,6 +260,8 @@ int hwmgr_hw_init(struct pp_instance *handle)
 
 	hwmgr = handle->hwmgr;
 
+	INIT_DELAYED_WORK(&hwmgr->wattman_idle_work, wattman_sample_handler);
+
 	if (hwmgr->pptable_func == NULL ||
 	    hwmgr->pptable_func->pptable_init == NULL ||
 	    hwmgr->hwmgr_func->backend_init == NULL)
@@ -279,6 +295,11 @@ int hwmgr_hw_init(struct pp_instance *handle)
 	if (ret)
 		goto err2;
 
+	if (hwmgr->autowattman_enabled) {
+		if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+			hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+	}
+
 	return 0;
 err2:
 	if (hwmgr->hwmgr_func->backend_fini)
@@ -300,6 +321,10 @@ int hwmgr_hw_fini(struct pp_instance *handle)
 
 	hwmgr = handle->hwmgr;
 
+	if (hwmgr->autowattman_enabled) {
+		if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+			hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
+	}
 	phm_stop_thermal_controller(hwmgr);
 	psm_set_boot_states(hwmgr);
 	psm_adjust_power_state_dynamic(hwmgr, false, NULL);
@@ -322,6 +347,11 @@ int hwmgr_hw_suspend(struct pp_instance *handle)
 		return -EINVAL;
 
 	hwmgr = handle->hwmgr;
+
+	if (hwmgr->autowattman_enabled) {
+		if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+			hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
+	}
 	phm_disable_smc_firmware_ctf(hwmgr);
 	ret = psm_set_boot_states(hwmgr);
 	if (ret)
@@ -360,6 +390,11 @@ int hwmgr_hw_resume(struct pp_instance *handle)
 
 	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
 
+	if (hwmgr->autowattman_enabled) {
+		if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+			hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+	}
+
 	return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 08e9e44..943d3ec 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -80,6 +80,7 @@
 
 #define PCIE_BUS_CLK                10000
 #define TCLK                        (PCIE_BUS_CLK / 10)
+#define WATTMAM_SAMPLE_PERIOD msecs_to_jiffies(1000)
 
 static const struct profile_mode_setting smu7_profiling[5] =
 					{{1, 0, 100, 30, 1, 0, 100, 10},
@@ -2540,9 +2541,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 			data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK;
 		else
 			data->pcie_gen_cap = (uint32_t)sys_info.value;
+
 		if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 			data->pcie_spc_cap = 20;
-		sys_info.size = sizeof(struct cgs_system_info);
+
 		sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW;
 		result = cgs_query_system_info(hwmgr->device, &sys_info);
 		if (result)
@@ -2550,6 +2552,11 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 		else
 			data->pcie_lane_cap = (uint32_t)sys_info.value;
 
+		sys_info.info_id = CGS_SYSTEM_INFO_VRAM_WIDTH;
+		result = cgs_query_system_info(hwmgr->device, &sys_info);
+		if (!result)
+			data->memory_bit_width = (uint32_t)sys_info.value;
+
 		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 		hwmgr->platform_descriptor.clockStep.engineClock = 500;
@@ -5070,6 +5077,195 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
 	return 0;
 }
 
+static void smu7_start_auto_wattman(struct pp_hwmgr *hwmgr, bool en)
+{
+	if (en) {
+		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
+		schedule_delayed_work(&hwmgr->wattman_idle_work, WATTMAM_SAMPLE_PERIOD);
+	} else {
+		cancel_delayed_work_sync(&hwmgr->wattman_idle_work);
+	}
+}
+
+static void smu7_auto_wattman_get_data(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+
+	data->wattman_data.average_sclk_busy = cgs_read_ind_register(
+							hwmgr->device,
+							CGS_IND_REG__SMC,
+							ixSMU_PM_STATUS_91);
+	data->wattman_data.average_sclk_busy >>= 8;
+
+	data->wattman_data.average_mclk_busy = cgs_read_ind_register(
+							hwmgr->device,
+							CGS_IND_REG__SMC,
+							ixSMU_PM_STATUS_92);
+
+	data->wattman_data.average_mclk_busy >>= 8;
+
+	data->wattman_data.effective_sclk = cgs_read_ind_register(
+							hwmgr->device,
+							CGS_IND_REG__SMC,
+							ixSMU_PM_STATUS_77);
+
+	data->wattman_data.effective_mclk = cgs_read_ind_register(
+							hwmgr->device,
+							CGS_IND_REG__SMC,
+							ixSMU_PM_STATUS_111);
+
+	pr_debug("effective sclk: %x average sclk busy: %x\n",
+					data->wattman_data.effective_sclk,
+					data->wattman_data.average_sclk_busy);
+	pr_debug("effective mclk: %x average mclk busy: %x\n",
+					data->wattman_data.effective_mclk,
+					data->wattman_data.average_mclk_busy);
+
+	return;
+}
+
+static int smu7_auto_wattman_update_clk_setting(struct pp_hwmgr *hwmgr,
+			struct smu7_auto_wattman_adjust_settings *setting,
+			uint32_t clk_busy, uint32_t threshold)
+{
+	uint32_t adjust_factor = 0;
+	uint32_t divide_factor = 0;
+
+	if (setting == NULL)
+		return -EINVAL;
+
+	if (clk_busy < threshold) {
+		divide_factor = threshold / AutoWattmanAlgorithmMaxAdjustFactor;
+		adjust_factor = AutoWattmanAlgorithmMaxAdjustFactor - (clk_busy / divide_factor);
+		setting->uphyst_adjust = adjust_factor;
+		setting->uphyst_polarity = 1;
+		setting->downhyst_adjust = 6 * adjust_factor;
+		setting->downhyst_polarity = 0;
+		setting->activity_adjust = 2 * adjust_factor;
+		setting->activity_polarity = 1;
+	} else {
+		divide_factor = (100 - threshold) / AutoWattmanAlgorithmMaxAdjustFactor;
+		adjust_factor = (clk_busy - threshold + divide_factor - 1) / divide_factor;
+		setting->uphyst_adjust = adjust_factor;
+		setting->uphyst_polarity = 0;
+		setting->downhyst_adjust = 6 * adjust_factor;
+		setting->downhyst_polarity = 1;
+		setting->activity_adjust = 2 * adjust_factor;
+		setting->activity_polarity = 0;
+	}
+
+	return 0;
+}
+
+static void smu7_auto_wattman_algorithm(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	uint32_t threshold = 0x32;
+
+	smu7_auto_wattman_update_clk_setting(hwmgr, &data->sclk_settings,
+				data->wattman_data.average_sclk_busy, threshold);
+
+	if (data->memory_bit_width == 64)
+		threshold = 0xA;
+	else if (hwmgr->chip_id == CHIP_POLARIS12)
+		threshold = 0xF;
+	else
+		threshold = 0x14;
+
+	smu7_auto_wattman_update_clk_setting(hwmgr, &data->mclk_settings,
+				data->wattman_data.average_mclk_busy, threshold);
+}
+
+static int smu7_auto_wattman_get_adjust_setting(uint32_t low_limit, uint32_t high_limit,
+						uint32_t polarity, uint32_t adjust_value,
+						uint32_t original_setting)
+{
+	if (!polarity) {
+		if (original_setting < low_limit + adjust_value)
+			original_setting = low_limit;
+		else
+			original_setting -= adjust_value;
+	} else {
+		if ((high_limit < adjust_value) || (high_limit - adjust_value < original_setting))
+			original_setting = high_limit;
+		else
+			original_setting += adjust_value;
+	}
+
+	return original_setting;
+}
+
+static int smu7_update_auto_wattman(struct pp_hwmgr *hwmgr)
+{
+	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
+	struct profile_mode_setting tmp;
+	uint32_t high_limit, low_limit;
+
+	high_limit = AutoWattmanSCLKHighLimits;
+	low_limit = AutoWattmanSCLKLowLimits;
+
+	smu7_auto_wattman_get_data(hwmgr);
+	smu7_auto_wattman_algorithm(hwmgr);
+
+	tmp.sclk_up_hyst = smu7_auto_wattman_get_adjust_setting(low_limit & 0xff,
+							high_limit & 0xff,
+							data->sclk_settings.uphyst_polarity,
+							data->sclk_settings.uphyst_adjust,
+							data->current_profile_setting.sclk_up_hyst);
+
+	tmp.sclk_down_hyst = smu7_auto_wattman_get_adjust_setting((low_limit >> 8) & 0xff,
+							(high_limit >> 8) & 0xff,
+							data->sclk_settings.downhyst_polarity,
+							data->sclk_settings.downhyst_adjust,
+							data->current_profile_setting.sclk_down_hyst);
+
+	tmp.sclk_activity = smu7_auto_wattman_get_adjust_setting((low_limit >> 16) & 0xffff,
+							(high_limit >> 16) & 0xffff,
+							data->sclk_settings.activity_polarity,
+							data->sclk_settings.activity_adjust,
+							data->current_profile_setting.sclk_activity);
+
+	if ((tmp.sclk_up_hyst == data->current_profile_setting.sclk_up_hyst) &&
+		(tmp.sclk_down_hyst == data->current_profile_setting.sclk_down_hyst) &&
+		(tmp.sclk_activity == data->current_profile_setting.sclk_activity))
+		tmp.bupdate_sclk = false;
+	else
+		tmp.bupdate_sclk = true;
+
+	high_limit = AutoWattmanMCLKHighLimits;
+	low_limit = AutoWattmanMCLKLowLimits;
+
+	tmp.mclk_up_hyst = smu7_auto_wattman_get_adjust_setting(low_limit && 0xff,
+							high_limit && 0xff,
+							data->mclk_settings.uphyst_polarity,
+							data->mclk_settings.uphyst_adjust,
+							data->current_profile_setting.mclk_up_hyst);
+
+	tmp.mclk_down_hyst  = smu7_auto_wattman_get_adjust_setting((low_limit >> 8) && 0xff,
+							(high_limit >> 8) && 0xff,
+							data->mclk_settings.downhyst_polarity,
+							data->mclk_settings.downhyst_adjust,
+							data->current_profile_setting.mclk_down_hyst);
+
+	tmp.mclk_activity  = smu7_auto_wattman_get_adjust_setting((low_limit >> 16) && 0xffff,
+							(high_limit >> 16) && 0xffff,
+							data->mclk_settings.activity_polarity,
+							data->mclk_settings.activity_adjust,
+							data->current_profile_setting.mclk_activity);
+
+	if ((tmp.mclk_up_hyst == data->current_profile_setting.mclk_up_hyst) &&
+		(tmp.mclk_down_hyst == data->current_profile_setting.mclk_down_hyst) &&
+		(tmp.mclk_activity == data->current_profile_setting.mclk_activity))
+		tmp.bupdate_mclk = false;
+	else
+		tmp.bupdate_mclk = true;
+
+	if (!smum_update_dpm_settings(hwmgr, &tmp) && ((tmp.bupdate_mclk) || tmp.bupdate_mclk))
+		memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting));
+
+	return 0;
+}
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
 	.backend_init = &smu7_hwmgr_backend_init,
 	.backend_fini = &smu7_hwmgr_backend_fini,
@@ -5127,6 +5323,8 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint
 	.set_power_limit = smu7_set_power_limit,
 	.get_power_profile_mode = smu7_get_power_profile_mode,
 	.set_power_profile_mode = smu7_set_power_profile_mode,
+	.update_auto_wattman = smu7_update_auto_wattman,
+	.start_auto_wattman = smu7_start_auto_wattman,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
index 3bcfc61..9f61507 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h
@@ -186,6 +186,21 @@ struct smu7_odn_dpm_table {
 	uint32_t					odn_mclk_min_limit;
 };
 
+#define AutoWattmanSCLKHighLimits 0x002D3C0A
+#define AutoWattmanSCLKLowLimits 0x00190000
+#define AutoWattmanMCLKHighLimits 0x002D3C0A
+#define AutoWattmanMCLKLowLimits 0x000A1000
+#define AutoWattmanAlgorithmMaxAdjustFactor 5
+
+struct smu7_auto_wattman_adjust_settings {
+	uint32_t  uphyst_adjust;
+	uint32_t  uphyst_polarity;
+	uint32_t  downhyst_adjust;
+	uint32_t  downhyst_polarity;
+	uint32_t  activity_adjust;
+	uint32_t  activity_polarity;
+};
+
 struct profile_mode_setting {
 	uint8_t bupdate_sclk;
 	uint8_t sclk_up_hyst;
@@ -197,6 +212,13 @@ struct profile_mode_setting {
 	uint16_t mclk_activity;
 };
 
+struct smu7_auto_wattman_data {
+	uint32_t   effective_sclk;
+	uint32_t   effective_mclk;
+	uint32_t   average_sclk_busy;
+	uint32_t   average_mclk_busy;
+};
+
 struct smu7_hwmgr {
 	struct smu7_dpm_table			dpm_table;
 	struct smu7_dpm_table			golden_dpm_table;
@@ -327,6 +349,10 @@ struct smu7_hwmgr {
 	uint32_t                              vr_config;
 	struct profile_mode_setting           custom_profile_setting;
 	struct profile_mode_setting           current_profile_setting;
+	struct smu7_auto_wattman_data         wattman_data;
+	uint32_t                              memory_bit_width;
+	struct smu7_auto_wattman_adjust_settings sclk_settings;
+	struct smu7_auto_wattman_adjust_settings mclk_settings;
 };
 
 /* To convert to Q8.8 format for firmware */
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index d809d96..b8335a4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -767,6 +767,8 @@ struct pp_hwmgr {
 	bool od_enabled;
 	uint32_t power_limit;
 	uint32_t default_power_limit;
+	bool autowattman_enabled;
+	struct delayed_work wattman_idle_work;
 };
 
 struct cgs_irq_src_funcs {
-- 
1.9.1

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[PATCH 09/10] drm/amd/pp: Restore power profile mode in auto dpm level on smu7

[Rex Zhu]

Disable auto wattman feature in manual mode if feature is enabled
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Change-Id: I4361d16df27d2666dd978c3e33e05c020d65fe6a
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 943d3ec..3ecd869 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -82,6 +82,7 @@
 #define TCLK                        (PCIE_BUS_CLK / 10)
 #define WATTMAM_SAMPLE_PERIOD msecs_to_jiffies(1000)
 
+static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
 static const struct profile_mode_setting smu7_profiling[5] =
 					{{1, 0, 100, 30, 1, 0, 100, 10},
 					 {1, 10, 0, 30, 0, 0, 0, 0},
@@ -2792,6 +2793,17 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
 		ret = smu7_force_dpm_lowest(hwmgr);
 		break;
 	case AMD_DPM_FORCED_LEVEL_AUTO:
+		if (hwmgr->autowattman_enabled) {
+			if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+				hwmgr->hwmgr_func->start_auto_wattman(hwmgr, true);
+		} else {
+			if (hwmgr->default_power_profile_mode != hwmgr->power_profile_mode) {
+				long mode = hwmgr->default_power_profile_mode;
+
+				smu7_set_power_profile_mode(hwmgr, &mode, 0);
+			}
+
+		}
 		ret = smu7_unforce_dpm_levels(hwmgr);
 		break;
 	case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
@@ -2806,6 +2818,11 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
 		smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
 		break;
 	case AMD_DPM_FORCED_LEVEL_MANUAL:
+		if (hwmgr->autowattman_enabled) {
+			if (hwmgr->hwmgr_func->start_auto_wattman != NULL)
+				hwmgr->hwmgr_func->start_auto_wattman(hwmgr, false);
+		}
+		break;
 	case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 	default:
 		break;
-- 
1.9.1

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[PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Rex Zhu]

Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index f50b6cd..549e830 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 							PHM_PlatformCaps_TCPRamping);
 	}
+
+	if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
+		hwmgr->autowattman_enabled = true; /* currently only enabled on polaris */
+
 	return 0;
 }
 
-- 
1.9.1

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Re: [PATCH 01/10] drm/amd/amdgpu: Add query vram width in CGS query system info

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I4bf7abab944253c8c744c1290b8a9fb5a62b6240
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Please add a patch description that explains what we will be using
this for.  With that fixed:

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 3 +++
>  drivers/gpu/drm/amd/include/cgs_common.h | 1 +
>  2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> index 71b4aec..1f4e37b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
> @@ -905,6 +905,9 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device,
>         case CGS_SYSTEM_INFO_PCIE_BUS_DEVFN:
>                 sys_info->value = adev->pdev->devfn;
>                 break;
> +       case CGS_SYSTEM_INFO_VRAM_WIDTH:
> +               sys_info->value = adev->gmc.vram_width;
> +               break;
>         default:
>                 return -ENODEV;
>         }
> diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
> index f5c7397..98cf4ce 100644
> --- a/drivers/gpu/drm/amd/include/cgs_common.h
> +++ b/drivers/gpu/drm/amd/include/cgs_common.h
> @@ -101,6 +101,7 @@ enum cgs_system_info_id {
>         CGS_SYSTEM_INFO_PCIE_SUB_SYS_ID,
>         CGS_SYSTEM_INFO_PCIE_SUB_SYS_VENDOR_ID,
>         CGS_SYSTEM_INFO_PCIE_BUS_DEVFN,
> +       CGS_SYSTEM_INFO_VRAM_WIDTH,
>         CGS_SYSTEM_INFO_ID_MAXIMUM,
>  };
>
> --
> 1.9.1
>
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Would be good to give a brief description of what autowattman actually
does in the patch description.  Also, we may need to manually select a
profile in some cases (e.g., VR).  Would that be a problem with
autowattman?

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index f50b6cd..549e830 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
>                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>                                                         PHM_PlatformCaps_TCPRamping);
>         }
> +
> +       if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
> +               hwmgr->autowattman_enabled = true; /* currently only enabled on polaris */
> +
>         return 0;
>  }
>
> --
> 1.9.1
>
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Re: [PATCH 02/10] drm/amdgpu: Add a pp feature mask bit for autowattman

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: Ie329d6c806fc5ab71417ffabe413ddbdf9d367ea
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Please provide a better patch description.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 2 +-
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
>  2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d3f5ee5..e2011d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -121,7 +121,7 @@
>  uint amdgpu_sdma_phase_quantum = 32;
>  char *amdgpu_disable_cu = NULL;
>  char *amdgpu_virtual_display = NULL;
> -uint amdgpu_pp_feature_mask = 0x3fff;
> +uint amdgpu_pp_feature_mask = 0xffffbfff;
>  int amdgpu_ngg = 0;
>  int amdgpu_prim_buf_per_se = 0;
>  int amdgpu_pos_buf_per_se = 0;
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 2a59ee8..77d7f49 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -85,6 +85,7 @@ enum PP_FEATURE_MASK {
>         PP_SOCCLK_DPM_MASK = 0x1000,
>         PP_DCEFCLK_DPM_MASK = 0x2000,
>         PP_OVERDRIVE_MASK = 0x4000,
> +       PP_AUTOWATTMAN_MASK = 0x8000,
>  };
>
>  enum PHM_BackEnd_Magic {
> --
> 1.9.1
>
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Re: [PATCH 03/10] drm/amd/pp: Add new smu callback function

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> it is used for adjust part of dpm settigs
> to get better performance under different
> workloads.
>
> Change-Id: I1e1ed786e9c07c91fb7e810af5b1ec5dd5cc4791
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h     | 1 +
>  drivers/gpu/drm/amd/powerplay/inc/smumgr.h    | 1 +
>  drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 8 ++++++++
>  3 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 77d7f49..31988d7 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -239,6 +239,7 @@ struct pp_smumgr_func {
>         int (*populate_requested_graphic_levels)(struct pp_hwmgr *hwmgr,
>                         struct amd_pp_profile *request);
>         bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
> +       int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
>  };
>
>  struct pp_hwmgr_func {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> index b1b27b2..e05a57e 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/smumgr.h
> @@ -134,5 +134,6 @@ extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
>
>  extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
>
> +extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
> index 8673884..1ce4959 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c
> @@ -253,3 +253,11 @@ bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
>
>         return false;
>  }
> +
> +int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting)
> +{
> +       if (hwmgr->smumgr_funcs->update_dpm_settings)
> +               return hwmgr->smumgr_funcs->update_dpm_settings(hwmgr, profile_setting);
> +
> +       return -EINVAL;
> +}
> --
> 1.9.1
>
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Re: [PATCH 04/10] drm/amd/pp: Implement update_dpm_settings on Polaris

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: I4533826ef6e18df125ae4445016873be3b5fe0ce
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Please provide a patch description, with that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    | 104 +++++++++++++++++++++
>  1 file changed, 104 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index bfb2c85..559572d 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -2575,6 +2575,109 @@ static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
>                                 array_size, SMC_RAM_END);
>  }
>
> +uint32_t polaris10_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)
> +{
> +       u32 mask = 0;
> +       u32 shift = 0;
> +
> +       shift = (offset % 4) << 3;
> +       if (size == sizeof(uint8_t))
> +               mask = 0xFF << shift;
> +       else if (size == sizeof(uint16_t))
> +               mask = 0xFFFF << shift;
> +
> +       original_data &= ~mask;
> +       original_data |= (field << shift);
> +       return original_data;
> +}
> +
> +static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
> +                               void *profile_setting)
> +{
> +       struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
> +                       (hwmgr->smu_backend);
> +       struct profile_mode_setting *setting;
> +       struct SMU74_Discrete_GraphicsLevel *levels =
> +                       smu_data->smc_state_table.GraphicsLevel;
> +       uint32_t array = smu_data->smu7_data.dpm_table_start +
> +                       offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
> +
> +       uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
> +                       offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
> +       struct SMU74_Discrete_MemoryLevel *mclk_levels =
> +                       smu_data->smc_state_table.MemoryLevel;
> +       uint32_t i;
> +       uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
> +
> +       if (profile_setting == NULL)
> +               return -EINVAL;
> +
> +       setting = (struct profile_mode_setting *)profile_setting;
> +
> +       if (setting->bupdate_sclk) {
> +               for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
> +                       if (levels[i].ActivityLevel !=
> +                               cpu_to_be16(setting->sclk_activity)) {
> +                               levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
> +
> +                               clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +                                               + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
> +                               offset = clk_activity_offset & ~0x3;
> +                               tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
> +                               tmp = polaris10_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
> +                               cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +
> +                       }
> +                       if (levels[i].UpHyst != setting->sclk_up_hyst ||
> +                               levels[i].DownHyst != setting->sclk_down_hyst) {
> +                               levels[i].UpHyst = setting->sclk_up_hyst;
> +                               levels[i].DownHyst = setting->sclk_down_hyst;
> +                               up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +                                               + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
> +                               down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +                                               + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
> +                               offset = up_hyst_offset & ~0x3;
> +                               tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
> +                               tmp = polaris10_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
> +                               tmp = polaris10_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
> +                               cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +                       }
> +               }
> +       }
> +
> +       if (setting->bupdate_mclk) {
> +               for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
> +                       if (mclk_levels[i].ActivityLevel !=
> +                               cpu_to_be16(setting->mclk_activity)) {
> +                               mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
> +
> +                               clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
> +                                               + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
> +                               offset = clk_activity_offset & ~0x3;
> +                               tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
> +                               tmp = polaris10_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
> +                               cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +
> +                       }
> +                       if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
> +                               mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
> +                               mclk_levels[i].UpHyst = setting->mclk_up_hyst;
> +                               mclk_levels[i].DownHyst = setting->mclk_down_hyst;
> +                               up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
> +                                               + offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
> +                               down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
> +                                               + offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
> +                               offset = up_hyst_offset & ~0x3;
> +                               tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
> +                               tmp = polaris10_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
> +                               tmp = polaris10_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
> +                               cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +                       }
> +               }
> +       }
> +       return 0;
> +}
> +
>  const struct pp_smumgr_func polaris10_smu_funcs = {
>         .smu_init = polaris10_smu_init,
>         .smu_fini = smu7_smu_fini,
> @@ -2599,4 +2702,5 @@ static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
>         .is_dpm_running = polaris10_is_dpm_running,
>         .populate_requested_graphic_levels = polaris10_populate_requested_graphic_levels,
>         .is_hw_avfs_present = polaris10_is_hw_avfs_present,
> +       .update_dpm_settings = polaris10_update_dpm_settings,
>  };
> --
> 1.9.1
>
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Re: [PATCH 05/10] drm/amd/pp: Implement get_power_profile_mode on smu7

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> It show what parameters can be setted on smu7(vi/ci asics)
> to get better performance.
>
> Also show some profiling modes, user can select directly
> by serial number based on workloads.
>
> cat pp_power_profile_mode
> NUM        MODE_NAME     SCLK_UP_HYST   SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL     MCLK_UP_HYST   MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL
>   0   3D_FULL_SCREEN:        0              100               30                0              100               10
>   1     POWER_SAVING:       10                0               30                -                -                -
>   2            VIDEO:        -                -                -               10               16               31
>   3               VR:        0               11               50                0              100               10
>   4          COMPUTE:        0                5               30                -                -                -
>   5           CUSTOM:        0                0                0                0                0                0
>   *          CURRENT:        0              100               30                0              100               10
>
> Change-Id: If0e9796d6cbe531ce1eb5ff181fe2f5f956437b6
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 87 ++++++++++++++++++++++++
>  1 file changed, 87 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 9379713..8cf95d9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -81,6 +81,21 @@
>  #define PCIE_BUS_CLK                10000
>  #define TCLK                        (PCIE_BUS_CLK / 10)
>
> +static const struct profile_mode_setting smu7_profiling[5] =
> +                                       {{1, 0, 100, 30, 1, 0, 100, 10},
> +                                        {1, 10, 0, 30, 0, 0, 0, 0},
> +                                        {0, 0, 0, 0, 1, 10, 16, 31},
> +                                        {1, 0, 11, 50, 1, 0, 100, 10},
> +                                        {1, 0, 5, 30, 0, 0, 0, 0},
> +                                       };
> +
> +static const struct profile_mode_setting polaris11_profiling[5] =
> +                                       {{1, 0, 100, 30, 1, 0, 100, 10},
> +                                        {1, 10, 0, 30, 0, 0, 0, 0},
> +                                        {0, 0, 0, 0, 1, 10, 16, 62},
> +                                        {1, 0, 11, 50, 1, 0, 100, 10},
> +                                        {1, 0, 5, 30, 0, 0, 0, 0},
> +                                       };
>
>  /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
>  enum DPM_EVENT_SRC {
> @@ -4932,6 +4947,77 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
>         return 0;
>  }
>
> +static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
> +{
> +       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +       uint32_t i, size = 0;
> +       uint32_t len;
> +
> +       static const char *profile_name[6] = {"3D_FULL_SCREEN",
> +                                       "POWER_SAVING",
> +                                       "VIDEO",
> +                                       "VR",
> +                                       "COMPUTE",
> +                                       "CUSTOM"};
> +
> +       static const char *title[8] = {"NUM",
> +                       "MODE_NAME",
> +                       "SCLK_UP_HYST",
> +                       "SCLK_DOWN_HYST",
> +                       "SCLK_ACTIVE_LEVEL",
> +                       "MCLK_UP_HYST",
> +                       "MCLK_DOWN_HYST",
> +                       "MCLK_ACTIVE_LEVEL"};
> +
> +       if (!buf)
> +               return -EINVAL;
> +
> +       size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n",
> +                       title[0], title[1], title[2], title[3],
> +                       title[4], title[5], title[6], title[7]);
> +
> +       len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting);
> +
> +       for (i = 0; i < len; i++) {
> +               if (smu7_profiling[i].bupdate_sclk)
> +                       size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ",
> +                       i, profile_name[i], smu7_profiling[i].sclk_up_hyst,
> +                       smu7_profiling[i].sclk_down_hyst,
> +                       smu7_profiling[i].sclk_activity);
> +               else
> +                       size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ",
> +                       i, profile_name[i], "-", "-", "-");
> +
> +               if (smu7_profiling[i].bupdate_mclk)
> +                       size += sprintf(buf + size, "%16d %16d %16d\n",
> +                       smu7_profiling[i].mclk_up_hyst,
> +                       smu7_profiling[i].mclk_down_hyst,
> +                       smu7_profiling[i].mclk_activity);
> +               else
> +                       size += sprintf(buf + size, "%16s %16s %16s\n",
> +                       "-", "-", "-");
> +       }
> +
> +       size += sprintf(buf + size, "%3d %16s: %8d %16d %16d %16d %16d %16d\n",
> +                       i, profile_name[i],
> +                       data->custom_profile_setting.sclk_up_hyst,
> +                       data->custom_profile_setting.sclk_down_hyst,
> +                       data->custom_profile_setting.sclk_activity,
> +                       data->custom_profile_setting.mclk_up_hyst,
> +                       data->custom_profile_setting.mclk_down_hyst,
> +                       data->custom_profile_setting.mclk_activity);
> +
> +       size += sprintf(buf + size, "%3s %16s: %8d %16d %16d %16d %16d %16d\n",
> +                       "*", "CURRENT",
> +                       data->current_profile_setting.sclk_up_hyst,
> +                       data->current_profile_setting.sclk_down_hyst,
> +                       data->current_profile_setting.sclk_activity,
> +                       data->current_profile_setting.mclk_up_hyst,
> +                       data->current_profile_setting.mclk_down_hyst,
> +                       data->current_profile_setting.mclk_activity);
> +
> +       return size;
> +}
>
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
>         .backend_init = &smu7_hwmgr_backend_init,
> @@ -4988,6 +5074,7 @@ static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
>         .get_thermal_temperature_range = smu7_get_thermal_temperature_range,
>         .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
>         .set_power_limit = smu7_set_power_limit,
> +       .get_power_profile_mode = smu7_get_power_profile_mode,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> --
> 1.9.1
>
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Re: [PATCH 06/10] drm/amd/pp: Implement set_power_profile_mode on smu7

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> User can set smu7 dpm pamameters through sysfs
>
> Depending on the workloads,
> user can echo "0/1/2/3/4">pp_power_profile_mode
> to select 3D_FULL_SCREEN/POWER_SAVING/VIDEO/VR/COMPUTE
> mode.
>
> echo "5 * * * * * * * *">pp_power_profile_mode
> to config custom mode.
> "5 * * * * * * * *" mean "CUSTOM enable_sclk SCLK_UP_HYST
> SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL enable_mclk MCLK_UP_HYST
> MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL"
>
> if the parameter enable_sclk/enable_mclk is true,
> driver will update the following parameters to dpm table.
> if false, ignore the following parameters.
>
> Change-Id: I8b5fc6fb2e20e6cd50b4184458452ac22c562469
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 52 ++++++++++++++++++++++++
>  1 file changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 8cf95d9..08e9e44 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -5019,6 +5019,57 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
>         return size;
>  }
>
> +static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
> +{
> +       struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> +       struct profile_mode_setting tmp;
> +
> +       hwmgr->power_profile_mode = input[size];
> +
> +       switch (hwmgr->power_profile_mode) {
> +       case PP_SMC_POWER_PROFILE_CUSTOM:
> +               if (size < 8)
> +                       return -EINVAL;
> +
> +               data->custom_profile_setting.bupdate_sclk = input[0];
> +               data->custom_profile_setting.sclk_up_hyst = input[1];
> +               data->custom_profile_setting.sclk_down_hyst = input[2];
> +               data->custom_profile_setting.sclk_activity =  input[3];
> +               data->custom_profile_setting.bupdate_mclk = input[4];
> +               data->custom_profile_setting.mclk_up_hyst = input[5];
> +               data->custom_profile_setting.mclk_down_hyst = input[6];
> +               data->custom_profile_setting.mclk_activity =  input[7];
> +               if (!smum_update_dpm_settings(hwmgr, &data->custom_profile_setting))
> +                       memcpy(&data->current_profile_setting, &data->custom_profile_setting, sizeof(struct profile_mode_setting));
> +               break;
> +       case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
> +       case PP_SMC_POWER_PROFILE_POWERSAVING:
> +       case PP_SMC_POWER_PROFILE_VIDEO:
> +       case PP_SMC_POWER_PROFILE_VR:
> +       case PP_SMC_POWER_PROFILE_COMPUTE:
> +               memcpy(&tmp, &smu7_profiling[hwmgr->power_profile_mode], sizeof(struct profile_mode_setting));
> +               if (!smum_update_dpm_settings(hwmgr, &tmp)) {

Won't the lack of an update_dpm_settings mean we can't manually select
power profiles on non-polaris asics?  Didn't your previous patches
allow this on non-polaris parts?

Alex

> +                       if (tmp.bupdate_sclk) {
> +                               data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk;
> +                               data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst;
> +                               data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst;
> +                               data->current_profile_setting.sclk_activity = tmp.sclk_activity;
> +                       }
> +                       if (tmp.bupdate_mclk) {
> +                               data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk;
> +                               data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst;
> +                               data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst;
> +                               data->current_profile_setting.mclk_activity = tmp.mclk_activity;
> +                       }
> +               }
> +               break;
> +       default:
> +               return -EINVAL;
> +       }
> +
> +       return 0;
> +}
> +
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
>         .backend_init = &smu7_hwmgr_backend_init,
>         .backend_fini = &smu7_hwmgr_backend_fini,
> @@ -5075,6 +5126,7 @@ static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
>         .odn_edit_dpm_table = smu7_odn_edit_dpm_table,
>         .set_power_limit = smu7_set_power_limit,
>         .get_power_profile_mode = smu7_get_power_profile_mode,
> +       .set_power_profile_mode = smu7_set_power_profile_mode,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> --
> 1.9.1
>
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 1926 bytes --]

if user select manual dpm mode，we will disabe autowattman.
When switch to auto, we will restart the auto wattman on Polaris,
Restore to default profile mode on other ASICS.


Best Regards
Rex
________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Thursday, February 8, 2018 11:02:21 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>

Would be good to give a brief description of what autowattman actually
does in the patch description.  Also, we may need to manually select a
profile in some cases (e.g., VR).  Would that be a problem with
autowattman?

Alex

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> index f50b6cd..549e830 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
>                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>                                                         PHM_PlatformCaps_TCPRamping);
>         }
> +
> +       if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
> +               hwmgr->autowattman_enabled = true; /* currently only enabled on polaris */
> +
>         return 0;
>  }
>
> --
> 1.9.1
>
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[-- Attachment #1.2: Type: text/html, Size: 3344 bytes --]

[-- Attachment #2: Type: text/plain, Size: 154 bytes --]

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Re: [PATCH 07/10] drm/amd/pp: Add new hw interface for auto wattman feature.

[Alex Deucher]

On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> Change-Id: Ib34c2815ab95890ba91f9a61bc0594b0f5e0c3fd
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Please provide a patch description.  With that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> index 31988d7..d809d96 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
> @@ -351,6 +351,8 @@ struct pp_hwmgr_func {
>                                         long *input, uint32_t size);
>         int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
>         int (*set_mmhub_powergating_by_smu)(struct pp_hwmgr *hwmgr);
> +       int (*update_auto_wattman)(struct pp_hwmgr *hwmgr);
> +       void (*start_auto_wattman)(struct pp_hwmgr *hwmgr, bool en);
>  };
>
>  struct pp_table_func {
> --
> 1.9.1
>
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Alex Deucher]

On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex <Rex.Zhu@amd.com> wrote:
> if user select manual dpm mode，we will disabe autowattman.
> When switch to auto, we will restart the auto wattman on Polaris,
> Restore to default profile mode on other ASICS.
>

But in auto mode, we may want to force a particular profile within the
driver for a specific use case.  E.g., for VR, we may want to select
the VR profile when the user sets the priority to high in the context
ioctl, and then switch it back to autowattman or the default profile
when the context if freed or the priority is changes.  We may want to
do something similar for video when the user submits work to the
multi-media engines.  It's possible autowattman will perform ok and we
don't need to manually change the profile in the driver, but we'll
have to do some profiling to sort that out.  I guess it should just be
a matter of disabling autowattman and switching to a profile when the
driver needs it and then switching back when it's done.

Alex

>
> Best Regards
> Rex
> ________________________________
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Thursday, February 8, 2018 11:02:21 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> Polaris
>
> On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
>> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>
> Would be good to give a brief description of what autowattman actually
> does in the patch description.  Also, we may need to manually select a
> profile in some cases (e.g., VR).  Would that be a problem with
> autowattman?
>
> Alex
>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index f50b6cd..549e830 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr
>> *hwmgr)
>>                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>>
>> PHM_PlatformCaps_TCPRamping);
>>         }
>> +
>> +       if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
>> +               hwmgr->autowattman_enabled = true; /* currently only
>> enabled on polaris */
>> +
>>         return 0;
>>  }
>>
>> --
>> 1.9.1
>>
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Re: [PATCH 04/10] drm/amd/pp: Implement update_dpm_settings on Polaris

[Eric Huang]

Again, it still has risk when updating smc table without calling 
smu7_freeze/unfreeze_sclk_mclk_dpm().

Regards,
Eric


On 2018-02-08 04:14 AM, Rex Zhu wrote:
> Change-Id: I4533826ef6e18df125ae4445016873be3b5fe0ce
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
>   .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    | 104 +++++++++++++++++++++
>   1 file changed, 104 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> index bfb2c85..559572d 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
> @@ -2575,6 +2575,109 @@ static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
>   				array_size, SMC_RAM_END);
>   }
>   
> +uint32_t polaris10_set_field_to_u32(u32 offset, u32 original_data, u32 field, u32 size)
> +{
> +	u32 mask = 0;
> +	u32 shift = 0;
> +
> +	shift = (offset % 4) << 3;
> +	if (size == sizeof(uint8_t))
> +		mask = 0xFF << shift;
> +	else if (size == sizeof(uint16_t))
> +		mask = 0xFFFF << shift;
> +
> +	original_data &= ~mask;
> +	original_data |= (field << shift);
> +	return original_data;
> +}
> +
> +static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
> +				void *profile_setting)
> +{
> +	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
> +			(hwmgr->smu_backend);
> +	struct profile_mode_setting *setting;
> +	struct SMU74_Discrete_GraphicsLevel *levels =
> +			smu_data->smc_state_table.GraphicsLevel;
> +	uint32_t array = smu_data->smu7_data.dpm_table_start +
> +			offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
> +
> +	uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
> +			offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
> +	struct SMU74_Discrete_MemoryLevel *mclk_levels =
> +			smu_data->smc_state_table.MemoryLevel;
> +	uint32_t i;
> +	uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
> +
> +	if (profile_setting == NULL)
> +		return -EINVAL;
> +
> +	setting = (struct profile_mode_setting *)profile_setting;
> +
> +	if (setting->bupdate_sclk) {
> +		for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
> +			if (levels[i].ActivityLevel !=
> +				cpu_to_be16(setting->sclk_activity)) {
> +				levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
> +
> +				clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +						+ offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
> +				offset = clk_activity_offset & ~0x3;
> +				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
> +				tmp = polaris10_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
> +				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +
> +			}
> +			if (levels[i].UpHyst != setting->sclk_up_hyst ||
> +				levels[i].DownHyst != setting->sclk_down_hyst) {
> +				levels[i].UpHyst = setting->sclk_up_hyst;
> +				levels[i].DownHyst = setting->sclk_down_hyst;
> +				up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +						+ offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
> +				down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
> +						+ offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
> +				offset = up_hyst_offset & ~0x3;
> +				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
> +				tmp = polaris10_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
> +				tmp = polaris10_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
> +				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +			}
> +		}
> +	}
> +
> +	if (setting->bupdate_mclk) {
> +		for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
> +			if (mclk_levels[i].ActivityLevel !=
> +				cpu_to_be16(setting->mclk_activity)) {
> +				mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
> +
> +				clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
> +						+ offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
> +				offset = clk_activity_offset & ~0x3;
> +				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
> +				tmp = polaris10_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
> +				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +
> +			}
> +			if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
> +				mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
> +				mclk_levels[i].UpHyst = setting->mclk_up_hyst;
> +				mclk_levels[i].DownHyst = setting->mclk_down_hyst;
> +				up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
> +						+ offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
> +				down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
> +						+ offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
> +				offset = up_hyst_offset & ~0x3;
> +				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
> +				tmp = polaris10_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
> +				tmp = polaris10_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
> +				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
> +			}
> +		}
> +	}
> +	return 0;
> +}
> +
>   const struct pp_smumgr_func polaris10_smu_funcs = {
>   	.smu_init = polaris10_smu_init,
>   	.smu_fini = smu7_smu_fini,
> @@ -2599,4 +2702,5 @@ static int polaris10_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
>   	.is_dpm_running = polaris10_is_dpm_running,
>   	.populate_requested_graphic_levels = polaris10_populate_requested_graphic_levels,
>   	.is_hw_avfs_present = polaris10_is_hw_avfs_present,
> +	.update_dpm_settings = polaris10_update_dpm_settings,
>   };

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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 4846 bytes --]

>But in auto mode, we may want to force a particular profile within the
>driver for a specific use case.  E.g., for VR, we may want to select
>the VR profile when the user sets the priority to high in the context
>ioctl, and then switch it back to autowattman or the default profile
>when the context if freed or the priority is changes.  We may want to
>do something similar for video when the user submits work to the
>multi-media engines.

>  I guess it should just be
>a matter of disabling autowattman and switching to a profile when the
>driver needs it and then switching back when it's done.


Rex:

         For MM, we can disable auto wattman (if enabled), and set video profile mode when enable uvd/vce dpm on smu7.

        restore to default when disable uvd/vce dpm when engine idle.



         VR, may be similar to compute case Eric have implemented, need user ctrl through sysfs.



           Enter manual dpm mode(driver disable auto wattman), and select prefered profile mode, set sclk/mclk range(smu7).

            when enter auto dpm mode, restore default value.


>It's possible autowattman will perform ok and we
>don't need to manually change the profile in the driver, but we'll
>have to do some profiling to sorhat out.


Rex: Idealy, if autowan feature enabled, the proflling mode should be adjusted based on workload with  some time delay caused by the work queue.

But need some time to verify.


Best Regards

Rex




________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Thursday, February 8, 2018 11:28 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
> if user select manual dpm mode，we will disabe autowattman.
> When switch to auto, we will restart the auto wattman on Polaris,
> Restore to default profile mode on other ASICS.
>

But in auto mode, we may want to force a particular profile within the
driver for a specific use case.  E.g., for VR, we may want to select
the VR profile when the user sets the priority to high in the context
ioctl, and then switch it back to autowattman or the default profile
when the context if freed or the priority is changes.  We may want to
do something similar for video when the user submits work to the
multi-media engines.  It's possible autowattman will perform ok and we
don't need to manually change the profile in the driver, but we'll
have to do some profiling to sort that out.  I guess it should just be
a matter of disabling autowattman and switching to a profile when the
driver needs it and then switching back when it's done.

Alex

>
> Best Regards
> Rex
> ________________________________
> From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Sent: Thursday, February 8, 2018 11:02:21 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> Polaris
>
> On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
>> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
>
> Would be good to give a brief description of what autowattman actually
> does in the patch description.  Also, we may need to manually select a
> profile in some cases (e.g., VR).  Would that be a problem with
> autowattman?
>
> Alex
>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index f50b6cd..549e830 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr
>> *hwmgr)
>>                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>>
>> PHM_PlatformCaps_TCPRamping);
>>         }
>> +
>> +       if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
>> +               hwmgr->autowattman_enabled = true; /* currently only
>> enabled on polaris */
>> +
>>         return 0;
>>  }
>>
>> --
>> 1.9.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
amd-gfx Info Page - freedesktop.org<https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Eric Huang]

[-- Attachment #1.1: Type: text/plain, Size: 5629 bytes --]



On 2018-02-08 11:35 AM, Zhu, Rex wrote:
>
> >But in auto mode, we may want to force a particular profile within the
> >driver for a specific use case.  E.g., for VR, we may want to select
> >the VR profile when the user sets the priority to high in the context
> >ioctl, and then switch it back to autowattman or the default profile
> >when the context if freed or the priority is changes.  We may want to
> >do something similar for video when the user submits work to the
> >multi-media engines.
>
> >  I guess it should just be
> >a matter of disabling autowattman and switching to a profile when the
> >driver needs it and then switching back when it's done.
>
>
> Rex:
>
>          For MM, we can disable auto wattman (if enabled), and set 
> video profile mode when enable uvd/vce dpm on smu7.
>
>         restore to default when disable uvd/vce dpm when engine idle.
>
>          VR, may be similar to compute case Eric have implemented, 
> need user ctrl through sysfs.
>

In case of compute, we have auto switching mechanism. when compute ring 
is coming, it switches to the default compute profile or user set 
profile, and switches back when it's done. So VR should be doing the 
same thing with compute. Auto wattman will be disabled when profile auto 
switching happens.

Regards,
Eric

>            Enter manual dpm mode(driver disable auto wattman), and 
> select prefered profile mode, set sclk/mclk range(smu7).
>
>             when enter auto dpm mode, restore default value.
>
>
> >It's possible autowattman will perform ok and we
> >don't need to manually change the profile in the driver, but we'll
> >have to do some profiling to sorhat out. 
>
>
> Rex: Idealy, if autowan feature enabled, the proflling mode should be 
> adjusted based on workload with  some time delay caused by the work queue.
>
> But need some time to verify.
>
>
> Best Regards
>
> Rex
>
>
>
> ------------------------------------------------------------------------
> *From:* Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> *Sent:* Thursday, February 8, 2018 11:28 PM
> *To:* Zhu, Rex
> *Cc:* amd-gfx list
> *Subject:* Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature 
> on Polaris
> On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
> > if user select manual dpm mode，we will disabe autowattman.
> > When switch to auto, we will restart the auto wattman on Polaris,
> > Restore to default profile mode on other ASICS.
> >
>
> But in auto mode, we may want to force a particular profile within the
> driver for a specific use case.  E.g., for VR, we may want to select
> the VR profile when the user sets the priority to high in the context
> ioctl, and then switch it back to autowattman or the default profile
> when the context if freed or the priority is changes. We may want to
> do something similar for video when the user submits work to the
> multi-media engines.  It's possible autowattman will perform ok and we
> don't need to manually change the profile in the driver, but we'll
> have to do some profiling to sort that out.  I guess it should just be
> a matter of disabling autowattman and switching to a profile when the
> driver needs it and then switching back when it's done.
>
> Alex
>
> >
> > Best Regards
> > Rex
> > ________________________________
> > From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > Sent: Thursday, February 8, 2018 11:02:21 PM
> > To: Zhu, Rex
> > Cc: amd-gfx list
> > Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> > Polaris
> >
> > On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
> >> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
> >> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> >
> > Would be good to give a brief description of what autowattman actually
> > does in the patch description.  Also, we may need to manually select a
> > profile in some cases (e.g., VR).  Would that be a problem with
> > autowattman?
> >
> > Alex
> >
> >> ---
> >>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++++
> >>  1 file changed, 4 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> >> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> >> index f50b6cd..549e830 100644
> >> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> >> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
> >> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct 
> pp_hwmgr
> >> *hwmgr)
> >> phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> >>
> >> PHM_PlatformCaps_TCPRamping);
> >>         }
> >> +
> >> +       if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
> >> +               hwmgr->autowattman_enabled = true; /* currently only
> >> enabled on polaris */
> >> +
> >>         return 0;
> >>  }
> >>
> >> --
> >> 1.9.1
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> amd-gfx Info Page - freedesktop.org 
> <https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
> lists.freedesktop.org
> Subscribing to amd-gfx: Subscribe to amd-gfx by filling out the 
> following form. Use of all freedesktop.org lists is subject to our 
> Code of ...
>
>
>
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Zhu, Rex]

[-- Attachment #1.1: Type: text/plain, Size: 6703 bytes --]

>In case of compute, we have auto switching mechanism. when compute ring is coming, it switches to the default compute profile or user set profile, >and switches back when it's done. So VR should be doing the same thing with compute. Auto wattman will be disabled when profile auto switching >happens.


Rex: Ok, the logic is same.



when computer ring begins,  set manual dpm mode(pp do nothing except disable auto wattman feature), and set compute profile or  custom profile.

set clock range. and set auto dpm mode, switch back


Best Regards

Rex





________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Eric Huang <jinhuieric.huang-5C7GfCeVMHo@public.gmane.org>
Sent: Friday, February 9, 2018 12:47 AM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris



On 2018-02-08 11:35 AM, Zhu, Rex wrote:

>But in auto mode, we may want to force a particular profile within the
>driver for a specific use case.  E.g., for VR, we may want to select
>the VR profile when the user sets the priority to high in the context
>ioctl, and then switch it back to autowattman or the default profile
>when the context if freed or the priority is changes.  We may want to
>do something similar for video when the user submits work to the
>multi-media engines.

>  I guess it should just be
>a matter of disabling autowattman and switching to a profile when the
>driver needs it and then switching back when it's done.


Rex:

         For MM, we can disable auto wattman (if enabled), and set video profile mode when enable uvd/vce dpm on smu7.

        restore to default when disable uvd/vce dpm when engine idle.



         VR, may be similar to compute case Eric have implemented, need user ctrl through sysfs.

In case of compute, we have auto switching mechanism. when compute ring is coming, it switches to the default compute profile or user set profile, and switches back when it's done. So VR should be doing the same thing with compute. Auto wattman will be disabled when profile auto switching happens.

Regards,
Eric


           Enter manual dpm mode(driver disable auto wattman), and select prefered profile mode, set sclk/mclk range(smu7).

            when enter auto dpm mode, restore default value.


>It's possible autowattman will perform ok and we
>don't need to manually change the profile in the driver, but we'll
>have to do some profiling to sorhat out.


Rex: Idealy, if autowan feature enabled, the proflling mode should be adjusted based on workload with  some time delay caused by the work queue.

But need some time to verify.


Best Regards

Rex




________________________________
From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org><mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Thursday, February 8, 2018 11:28 PM
To: Zhu, Rex
Cc: amd-gfx list
Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org><mailto:Rex.Zhu@amd.com> wrote:
> if user select manual dpm mode，we will disabe autowattman.
> When switch to auto, we will restart the auto wattman on Polaris,
> Restore to default profile mode on other ASICS.
>

But in auto mode, we may want to force a particular profile within the
driver for a specific use case.  E.g., for VR, we may want to select
the VR profile when the user sets the priority to high in the context
ioctl, and then switch it back to autowattman or the default profile
when the context if freed or the priority is changes.  We may want to
do something similar for video when the user submits work to the
multi-media engines.  It's possible autowattman will perform ok and we
don't need to manually change the profile in the driver, but we'll
have to do some profiling to sort that out.  I guess it should just be
a matter of disabling autowattman and switching to a profile when the
driver needs it and then switching back when it's done.

Alex

>
> Best Regards
> Rex
> ________________________________
> From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org><mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Sent: Thursday, February 8, 2018 11:02:21 PM
> To: Zhu, Rex
> Cc: amd-gfx list
> Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
> Polaris
>
> On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org><mailto:Rex.Zhu@amd.com> wrote:
>> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org><mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
>
> Would be good to give a brief description of what autowattman actually
> does in the patch description.  Also, we may need to manually select a
> profile in some cases (e.g., VR).  Would that be a problem with
> autowattman?
>
> Alex
>
>> ---
>>  drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> index f50b6cd..549e830 100644
>> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr
>> *hwmgr)
>>                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>>
>> PHM_PlatformCaps_TCPRamping);
>>         }
>> +
>> +       if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
>> +               hwmgr->autowattman_enabled = true; /* currently only
>> enabled on polaris */
>> +
>>         return 0;
>>  }
>>
>> --
>> 1.9.1
>>
>> _______________________________________________
>> amd-gfx mailing list
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Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on Polaris

[Eric Huang]

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Is the switching automatically by driver or manually by user?


Regards,

Eric


On 2018-02-08 11:54 AM, Zhu, Rex wrote:
>
> >In case of compute, we have auto switching mechanism. when compute ring 
> is coming, it switches to the default compute profile or user set 
> profile, >and switches back when it's done. So VR should be doing the 
> same thing with compute. Auto wattman will be disabled when profile 
> auto switching >happens.
>
>
> Rex: Ok, the logic is same.
>
> when computer ring begins,  set manual dpm mode(pp do nothing except 
> disable auto wattman feature), and set compute profile or  custom profile.
>
> set clock range. and set auto dpm mode, switch back
>
>
> Best Regards
>
> Rex
>
>
>
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of 
> Eric Huang <jinhuieric.huang-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Friday, February 9, 2018 12:47 AM
> *To:* amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> *Subject:* Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature 
> on Polaris
>
>
>
> On 2018-02-08 11:35 AM, Zhu, Rex wrote:
>>
>> >But in auto mode, we may want to force a particular profile within the
>> >driver for a specific use case.  E.g., for VR, we may want to select
>> >the VR profile when the user sets the priority to high in the context
>> >ioctl, and then switch it back to autowattman or the default profile
>> >when the context if freed or the priority is changes.  We may want to
>> >do something similar for video when the user submits work to the
>> >multi-media engines.
>>
>> >  I guess it should just be
>> >a matter of disabling autowattman and switching to a profile when the
>> >driver needs it and then switching back when it's done.
>>
>>
>> Rex:
>>
>>        For MM, we can disable auto wattman (if enabled), and set 
>> video profile mode when enable uvd/vce dpm on smu7.
>>
>>       restore to default when disable uvd/vce dpm when engine idle.
>>
>>          VR, may be similar to compute case Eric have implemented, 
>> need user ctrl through sysfs.
>>
>
> In case of compute, we have auto switching mechanism. when compute 
> ring is coming, it switches to the default compute profile or user set 
> profile, and switches back when it's done. So VR should be doing the 
> same thing with compute. Auto wattman will be disabled when profile 
> auto switching happens.
>
> Regards,
> Eric
>
>>            Enter manual dpm mode(driver disable auto wattman), and 
>> select prefered profile mode, set sclk/mclk range(smu7).
>>
>>             when enter auto dpm mode, restore default value.
>>
>>
>> >It's possible autowattman will perform ok and we
>> >don't need to manually change the profile in the driver, but we'll
>> >have to do some profiling to sorhat out.
>>
>>
>> Rex: Idealy, if autowan feature enabled, the proflling mode should be 
>> adjusted based on workload with  some time delay caused by the work 
>> queue.
>>
>> But need some time to verify.
>>
>>
>> Best Regards
>>
>> Rex
>>
>>
>>
>> ------------------------------------------------------------------------
>> *From:* Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 
>> <mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> *Sent:* Thursday, February 8, 2018 11:28 PM
>> *To:* Zhu, Rex
>> *Cc:* amd-gfx list
>> *Subject:* Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature 
>> on Polaris
>> On Thu, Feb 8, 2018 at 10:14 AM, Zhu, Rex <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 
>> <mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
>> > if user select manual dpm mode，we will disabe autowattman.
>> > When switch to auto, we will restart the auto wattman on Polaris,
>> > Restore to default profile mode on other ASICS.
>> >
>>
>> But in auto mode, we may want to force a particular profile within the
>> driver for a specific use case.  E.g., for VR, we may want to select
>> the VR profile when the user sets the priority to high in the context
>> ioctl, and then switch it back to autowattman or the default profile
>> when the context if freed or the priority is changes.  We may want to
>> do something similar for video when the user submits work to the
>> multi-media engines.  It's possible autowattman will perform ok and we
>> don't need to manually change the profile in the driver, but we'll
>> have to do some profiling to sort that out.  I guess it should just be
>> a matter of disabling autowattman and switching to a profile when the
>> driver needs it and then switching back when it's done.
>>
>> Alex
>>
>> >
>> > Best Regards
>> > Rex
>> > ________________________________
>> > From: Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 
>> <mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> > Sent: Thursday, February 8, 2018 11:02:21 PM
>> > To: Zhu, Rex
>> > Cc: amd-gfx list
>> > Subject: Re: [PATCH 10/10] drm/amd/pp: Enable auto automan feature on
>> > Polaris
>> >
>> > On Thu, Feb 8, 2018 at 4:14 AM, Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 
>> <mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org> wrote:
>> >> Change-Id: I69b24ce65ddb361a89e5ac9b197ae6df9b60a9e5
>> >> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org> <mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
>> >
>> > Would be good to give a brief description of what autowattman actually
>> > does in the patch description.  Also, we may need to manually select a
>> > profile in some cases (e.g., VR).  Would that be a problem with
>> > autowattman?
>> >
>> > Alex
>> >
>> >> ---
>> >> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 ++++
>> >>  1 file changed, 4 insertions(+)
>> >>
>> >> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> >> b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> >> index f50b6cd..549e830 100644
>> >> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> >> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
>> >> @@ -1023,6 +1023,10 @@ int polaris_set_asic_special_caps(struct 
>> pp_hwmgr
>> >> *hwmgr)
>> >> phm_cap_set(hwmgr->platform_descriptor.platformCaps,
>> >>
>> >> PHM_PlatformCaps_TCPRamping);
>> >>         }
>> >> +
>> >> +       if (hwmgr->feature_mask & PP_AUTOWATTMAN_MASK)
>> >> + hwmgr->autowattman_enabled = true; /* currently only
>> >> enabled on polaris */
>> >> +
>> >>         return 0;
>> >>  }
>> >>
>> >> --
>> >> 1.9.1
>> >>
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