* [PATCH igt 01/16] igt/gem_sync: Exercise and measure idle requests
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Don't just wait for the batch to be completed, wait for the system to
idle! Then wake it up and do it again.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_sync.c | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/tests/gem_sync.c b/tests/gem_sync.c
index ad43b1a3..d70515ea 100644
--- a/tests/gem_sync.c
+++ b/tests/gem_sync.c
@@ -152,6 +152,45 @@ sync_ring(int fd, unsigned ring, int num_children, int timeout)
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
}
+static void
+idle_ring(int fd, unsigned ring, int timeout)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ struct drm_i915_gem_exec_object2 object;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ double start, elapsed;
+ unsigned long cycles;
+
+ gem_require_ring(fd, ring);
+
+ memset(&object, 0, sizeof(object));
+ object.handle = gem_create(fd, 4096);
+ gem_write(fd, object.handle, 0, &bbe, sizeof(bbe));
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&object);
+ execbuf.buffer_count = 1;
+ execbuf.flags = ring;
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, object.handle);
+
+ intel_detect_and_clear_missed_interrupts(fd);
+ start = gettime();
+ cycles = 0;
+ do {
+ do {
+ gem_execbuf(fd, &execbuf);
+ gem_quiescent_gpu(fd);
+ } while (++cycles & 1023);
+ } while ((elapsed = gettime() - start) < timeout);
+ igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+
+ igt_info("Completed %ld cycles: %.3f us\n",
+ cycles, elapsed*1e6/cycles);
+
+ gem_close(fd, object.handle);
+}
+
static void
store_ring(int fd, unsigned ring, int num_children, int timeout)
{
@@ -802,6 +841,8 @@ igt_main
for (e = intel_execution_engines; e->name; e++) {
igt_subtest_f("%s", e->name)
sync_ring(fd, e->exec_id | e->flags, 1, 150);
+ igt_subtest_f("idle-%s", e->name)
+ idle_ring(fd, e->exec_id | e->flags, 150);
igt_subtest_f("store-%s", e->name)
store_ring(fd, e->exec_id | e->flags, 1, 150);
igt_subtest_f("many-%s", e->name)
--
2.16.1
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* [Intel-gfx] [PATCH igt 01/16] igt/gem_sync: Exercise and measure idle requests
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Don't just wait for the batch to be completed, wait for the system to
idle! Then wake it up and do it again.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_sync.c | 41 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/tests/gem_sync.c b/tests/gem_sync.c
index ad43b1a3..d70515ea 100644
--- a/tests/gem_sync.c
+++ b/tests/gem_sync.c
@@ -152,6 +152,45 @@ sync_ring(int fd, unsigned ring, int num_children, int timeout)
igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
}
+static void
+idle_ring(int fd, unsigned ring, int timeout)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ struct drm_i915_gem_exec_object2 object;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ double start, elapsed;
+ unsigned long cycles;
+
+ gem_require_ring(fd, ring);
+
+ memset(&object, 0, sizeof(object));
+ object.handle = gem_create(fd, 4096);
+ gem_write(fd, object.handle, 0, &bbe, sizeof(bbe));
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&object);
+ execbuf.buffer_count = 1;
+ execbuf.flags = ring;
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, object.handle);
+
+ intel_detect_and_clear_missed_interrupts(fd);
+ start = gettime();
+ cycles = 0;
+ do {
+ do {
+ gem_execbuf(fd, &execbuf);
+ gem_quiescent_gpu(fd);
+ } while (++cycles & 1023);
+ } while ((elapsed = gettime() - start) < timeout);
+ igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+
+ igt_info("Completed %ld cycles: %.3f us\n",
+ cycles, elapsed*1e6/cycles);
+
+ gem_close(fd, object.handle);
+}
+
static void
store_ring(int fd, unsigned ring, int num_children, int timeout)
{
@@ -802,6 +841,8 @@ igt_main
for (e = intel_execution_engines; e->name; e++) {
igt_subtest_f("%s", e->name)
sync_ring(fd, e->exec_id | e->flags, 1, 150);
+ igt_subtest_f("idle-%s", e->name)
+ idle_ring(fd, e->exec_id | e->flags, 150);
igt_subtest_f("store-%s", e->name)
store_ring(fd, e->exec_id | e->flags, 1, 150);
igt_subtest_f("many-%s", e->name)
--
2.16.1
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* [PATCH igt 02/16] lib: Cache the debugfs mountpoint
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
When using igt_debugfs_*() inside a tight loop, the overhead of calling
xstat64 (from is_mountpoint()) creeps up in the profiles. Eliminate it
by caching the resultant path for finding/mounting debugfs.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_debugfs.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 4a119985..09d42ea0 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -110,6 +110,20 @@ static bool is_mountpoint(const char *path)
return dev != st.st_dev;
}
+static const char *__igt_debugfs_mount(void)
+{
+ if (is_mountpoint("/sys/kernel/debug"))
+ return "/sys/kernel/debug";
+
+ if (is_mountpoint("/debug"))
+ return "/debug";
+
+ if (mount("debug", "/sys/kernel/debug", "debugfs", 0, 0))
+ return NULL;
+
+ return "/sys/kernel/debug";
+}
+
/**
* igt_debugfs_mount:
*
@@ -121,16 +135,12 @@ static bool is_mountpoint(const char *path)
*/
const char *igt_debugfs_mount(void)
{
- if (is_mountpoint("/sys/kernel/debug"))
- return "/sys/kernel/debug";
+ static const char *path;
- if (is_mountpoint("/debug"))
- return "/debug";
+ if (!path)
+ path = __igt_debugfs_mount();
- if (mount("debug", "/sys/kernel/debug", "debugfs", 0, 0))
- return NULL;
-
- return "/sys/kernel/debug";
+ return path;
}
/**
--
2.16.1
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^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 02/16] lib: Cache the debugfs mountpoint
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
When using igt_debugfs_*() inside a tight loop, the overhead of calling
xstat64 (from is_mountpoint()) creeps up in the profiles. Eliminate it
by caching the resultant path for finding/mounting debugfs.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_debugfs.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 4a119985..09d42ea0 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -110,6 +110,20 @@ static bool is_mountpoint(const char *path)
return dev != st.st_dev;
}
+static const char *__igt_debugfs_mount(void)
+{
+ if (is_mountpoint("/sys/kernel/debug"))
+ return "/sys/kernel/debug";
+
+ if (is_mountpoint("/debug"))
+ return "/debug";
+
+ if (mount("debug", "/sys/kernel/debug", "debugfs", 0, 0))
+ return NULL;
+
+ return "/sys/kernel/debug";
+}
+
/**
* igt_debugfs_mount:
*
@@ -121,16 +135,12 @@ static bool is_mountpoint(const char *path)
*/
const char *igt_debugfs_mount(void)
{
- if (is_mountpoint("/sys/kernel/debug"))
- return "/sys/kernel/debug";
+ static const char *path;
- if (is_mountpoint("/debug"))
- return "/debug";
+ if (!path)
+ path = __igt_debugfs_mount();
- if (mount("debug", "/sys/kernel/debug", "debugfs", 0, 0))
- return NULL;
-
- return "/sys/kernel/debug";
+ return path;
}
/**
--
2.16.1
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* [PATCH igt 03/16] lib: Always set mismatching index for igt_find_crc_mismatch
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
igt_debugfs.c: In function 'igt_assert_crc_equal':
igt_debugfs.c:353:3: warning: 'index' may be used uninitialized in this function [-Wmaybe-uninitialized]
igt_debugfs.c: In function 'igt_check_crc_equal':
igt_debugfs.c:375:3: warning: 'index' may be used uninitialized in this function [-Wmaybe-uninitialized]
Fixes: 7422d7540a3b ("lib/igt_debugfs: Introduce CRC check function, with logic made common")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_debugfs.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 09d42ea0..8adc02e9 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -325,12 +325,10 @@ bool igt_debugfs_search(int device, const char *filename, const char *substring)
static bool igt_find_crc_mismatch(const igt_crc_t *a, const igt_crc_t *b,
int *index)
{
+ int nwords = min(a->n_words, b->n_words);
int i;
- if (a->n_words != b->n_words)
- return true;
-
- for (i = 0; i < a->n_words; i++) {
+ for (i = 0; i < nwords; i++) {
if (a->crc[i] != b->crc[i]) {
if (index)
*index = i;
@@ -339,6 +337,12 @@ static bool igt_find_crc_mismatch(const igt_crc_t *a, const igt_crc_t *b,
}
}
+ if (a->n_words != b->n_words) {
+ if (index)
+ *index = i;
+ return true;
+ }
+
return false;
}
--
2.16.1
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* [igt-dev] [PATCH igt 03/16] lib: Always set mismatching index for igt_find_crc_mismatch
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
igt_debugfs.c: In function 'igt_assert_crc_equal':
igt_debugfs.c:353:3: warning: 'index' may be used uninitialized in this function [-Wmaybe-uninitialized]
igt_debugfs.c: In function 'igt_check_crc_equal':
igt_debugfs.c:375:3: warning: 'index' may be used uninitialized in this function [-Wmaybe-uninitialized]
Fixes: 7422d7540a3b ("lib/igt_debugfs: Introduce CRC check function, with logic made common")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_debugfs.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index 09d42ea0..8adc02e9 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -325,12 +325,10 @@ bool igt_debugfs_search(int device, const char *filename, const char *substring)
static bool igt_find_crc_mismatch(const igt_crc_t *a, const igt_crc_t *b,
int *index)
{
+ int nwords = min(a->n_words, b->n_words);
int i;
- if (a->n_words != b->n_words)
- return true;
-
- for (i = 0; i < a->n_words; i++) {
+ for (i = 0; i < nwords; i++) {
if (a->crc[i] != b->crc[i]) {
if (index)
*index = i;
@@ -339,6 +337,12 @@ static bool igt_find_crc_mismatch(const igt_crc_t *a, const igt_crc_t *b,
}
}
+ if (a->n_words != b->n_words) {
+ if (index)
+ *index = i;
+ return true;
+ }
+
return false;
}
--
2.16.1
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* [PATCH igt 04/16] igt/gem_exec_flush: Silence old compiler warning
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
gem_exec_flush.c: In function ‘batch’:
gem_exec_flush.c:443:15: warning: ‘ptr’ may be used uninitialized in this function [-Wmaybe-uninitialized]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_flush.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tests/gem_exec_flush.c b/tests/gem_exec_flush.c
index c93eee4b..f820b2a8 100644
--- a/tests/gem_exec_flush.c
+++ b/tests/gem_exec_flush.c
@@ -426,6 +426,11 @@ static void batch(int fd, unsigned ring, int nchild, int timeout,
ptr = mmap(0, 64<<10, PROT_WRITE,
MAP_PRIVATE | MAP_ANON, -1, 0);
break;
+
+ default:
+ igt_assert(!"reachable");
+ ptr = NULL;
+ break;
}
memset(&reloc, 0, sizeof(reloc));
--
2.16.1
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* [igt-dev] [PATCH igt 04/16] igt/gem_exec_flush: Silence old compiler warning
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
gem_exec_flush.c: In function ‘batch’:
gem_exec_flush.c:443:15: warning: ‘ptr’ may be used uninitialized in this function [-Wmaybe-uninitialized]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_flush.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tests/gem_exec_flush.c b/tests/gem_exec_flush.c
index c93eee4b..f820b2a8 100644
--- a/tests/gem_exec_flush.c
+++ b/tests/gem_exec_flush.c
@@ -426,6 +426,11 @@ static void batch(int fd, unsigned ring, int nchild, int timeout,
ptr = mmap(0, 64<<10, PROT_WRITE,
MAP_PRIVATE | MAP_ANON, -1, 0);
break;
+
+ default:
+ igt_assert(!"reachable");
+ ptr = NULL;
+ break;
}
memset(&reloc, 0, sizeof(reloc));
--
2.16.1
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* [PATCH igt 05/16] igt/syncobj: Tidy ye olde compiler warnings
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
syncobj_basic.c: In function ‘__real_main225’:
syncobj_basic.c:202:26: warning: ‘fd’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_basic.c:227:6: note: ‘fd’ was declared here
syncobj_wait.c: In function ‘test_wait_complex’:
syncobj_wait.c:702:3: warning: ‘first_signaled’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_wait.c: In function ‘__real_main758’:
syncobj_wait.c:492:24: warning: ‘timeline’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_wait.c:473:15: note: ‘timeline’ was declared here
syncobj_wait.c:326:23: warning: ‘timeline’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_wait.c:320:6: note: ‘timeline’ was declared here
syncobj_wait.c:406:31: warning: ‘fd’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_wait.c:760:6: note: ‘fd’ was declared here
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/syncobj_basic.c | 2 +-
tests/syncobj_wait.c | 12 +++++++-----
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/tests/syncobj_basic.c b/tests/syncobj_basic.c
index acc4a641..44769d3b 100644
--- a/tests/syncobj_basic.c
+++ b/tests/syncobj_basic.c
@@ -187,7 +187,7 @@ static bool has_syncobj(int fd)
igt_main
{
- int fd;
+ int fd = -1;
igt_fixture {
fd = drm_open_driver(DRIVER_ANY);
diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
index 49e6d372..04d79de7 100644
--- a/tests/syncobj_wait.c
+++ b/tests/syncobj_wait.c
@@ -317,7 +317,7 @@ test_single_wait(int fd, uint32_t test_flags, int expect)
{
uint32_t syncobj = syncobj_create(fd, 0);
uint32_t flags = flags_for_test_flags(test_flags);
- int timeline;
+ int timeline = -1;
if (test_flags & (WAIT_SUBMITTED | WAIT_SIGNALED))
timeline = syncobj_attach_sw_sync(fd, syncobj);
@@ -336,6 +336,8 @@ test_single_wait(int fd, uint32_t test_flags, int expect)
}
syncobj_destroy(fd, syncobj);
+ if (timeline != -1)
+ close(timeline);
}
static void
@@ -343,7 +345,7 @@ test_wait_delayed_signal(int fd, uint32_t test_flags)
{
uint32_t syncobj = syncobj_create(fd, 0);
uint32_t flags = flags_for_test_flags(test_flags);
- int timeline;
+ int timeline = -1;
timer_t timer;
if (test_flags & WAIT_FOR_SUBMIT) {
@@ -360,7 +362,7 @@ test_wait_delayed_signal(int fd, uint32_t test_flags)
timer_delete(timer);
- if (!(test_flags & WAIT_FOR_SUBMIT))
+ if (timeline != -1)
close(timeline);
syncobj_destroy(fd, syncobj);
@@ -614,7 +616,7 @@ test_wait_complex(int fd, uint32_t test_flags)
uint32_t syncobjs[8];
enum syncobj_stage stage[8];
int i, j, timelines[8];
- uint32_t first_signaled, num_signaled;
+ uint32_t first_signaled = -1, num_signaled = 0;
pthread_t thread;
for (i = 0; i < 8; i++) {
@@ -757,7 +759,7 @@ has_syncobj_wait(int fd)
igt_main
{
- int fd;
+ int fd = -1;
igt_fixture {
fd = drm_open_driver(DRIVER_ANY);
--
2.16.1
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* [igt-dev] [PATCH igt 05/16] igt/syncobj: Tidy ye olde compiler warnings
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
syncobj_basic.c: In function ‘__real_main225’:
syncobj_basic.c:202:26: warning: ‘fd’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_basic.c:227:6: note: ‘fd’ was declared here
syncobj_wait.c: In function ‘test_wait_complex’:
syncobj_wait.c:702:3: warning: ‘first_signaled’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_wait.c: In function ‘__real_main758’:
syncobj_wait.c:492:24: warning: ‘timeline’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_wait.c:473:15: note: ‘timeline’ was declared here
syncobj_wait.c:326:23: warning: ‘timeline’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_wait.c:320:6: note: ‘timeline’ was declared here
syncobj_wait.c:406:31: warning: ‘fd’ may be used uninitialized in this function [-Wmaybe-uninitialized]
syncobj_wait.c:760:6: note: ‘fd’ was declared here
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/syncobj_basic.c | 2 +-
tests/syncobj_wait.c | 12 +++++++-----
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/tests/syncobj_basic.c b/tests/syncobj_basic.c
index acc4a641..44769d3b 100644
--- a/tests/syncobj_basic.c
+++ b/tests/syncobj_basic.c
@@ -187,7 +187,7 @@ static bool has_syncobj(int fd)
igt_main
{
- int fd;
+ int fd = -1;
igt_fixture {
fd = drm_open_driver(DRIVER_ANY);
diff --git a/tests/syncobj_wait.c b/tests/syncobj_wait.c
index 49e6d372..04d79de7 100644
--- a/tests/syncobj_wait.c
+++ b/tests/syncobj_wait.c
@@ -317,7 +317,7 @@ test_single_wait(int fd, uint32_t test_flags, int expect)
{
uint32_t syncobj = syncobj_create(fd, 0);
uint32_t flags = flags_for_test_flags(test_flags);
- int timeline;
+ int timeline = -1;
if (test_flags & (WAIT_SUBMITTED | WAIT_SIGNALED))
timeline = syncobj_attach_sw_sync(fd, syncobj);
@@ -336,6 +336,8 @@ test_single_wait(int fd, uint32_t test_flags, int expect)
}
syncobj_destroy(fd, syncobj);
+ if (timeline != -1)
+ close(timeline);
}
static void
@@ -343,7 +345,7 @@ test_wait_delayed_signal(int fd, uint32_t test_flags)
{
uint32_t syncobj = syncobj_create(fd, 0);
uint32_t flags = flags_for_test_flags(test_flags);
- int timeline;
+ int timeline = -1;
timer_t timer;
if (test_flags & WAIT_FOR_SUBMIT) {
@@ -360,7 +362,7 @@ test_wait_delayed_signal(int fd, uint32_t test_flags)
timer_delete(timer);
- if (!(test_flags & WAIT_FOR_SUBMIT))
+ if (timeline != -1)
close(timeline);
syncobj_destroy(fd, syncobj);
@@ -614,7 +616,7 @@ test_wait_complex(int fd, uint32_t test_flags)
uint32_t syncobjs[8];
enum syncobj_stage stage[8];
int i, j, timelines[8];
- uint32_t first_signaled, num_signaled;
+ uint32_t first_signaled = -1, num_signaled = 0;
pthread_t thread;
for (i = 0; i < 8; i++) {
@@ -757,7 +759,7 @@ has_syncobj_wait(int fd)
igt_main
{
- int fd;
+ int fd = -1;
igt_fixture {
fd = drm_open_driver(DRIVER_ANY);
--
2.16.1
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 06/16] lib: Remove overzealous assertion on gem_set_caching()
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
When the asserts were added for the acceptable error codes for
SET_CACHING ioctl, foresight was not given to the possibility that the
device may not handle the caching mode and return -ENODEV. Remove the
error code assertion from the library, that is the job for the ABI
tests.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/ioctl_wrappers.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 7b656cce..8748cfcf 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -208,10 +208,10 @@ static int __gem_set_caching(int fd, uint32_t handle, uint32_t caching)
arg.caching = caching;
err = 0;
- if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg)) {
+ if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg))
err = -errno;
- igt_assert(errno == ENOTTY || errno == EINVAL);
- }
+
+ errno = 0;
return err;
}
@@ -229,7 +229,6 @@ static int __gem_set_caching(int fd, uint32_t handle, uint32_t caching)
void gem_set_caching(int fd, uint32_t handle, uint32_t caching)
{
igt_require(__gem_set_caching(fd, handle, caching) == 0);
- errno = 0;
}
/**
--
2.16.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 06/16] lib: Remove overzealous assertion on gem_set_caching()
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
When the asserts were added for the acceptable error codes for
SET_CACHING ioctl, foresight was not given to the possibility that the
device may not handle the caching mode and return -ENODEV. Remove the
error code assertion from the library, that is the job for the ABI
tests.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/ioctl_wrappers.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 7b656cce..8748cfcf 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -208,10 +208,10 @@ static int __gem_set_caching(int fd, uint32_t handle, uint32_t caching)
arg.caching = caching;
err = 0;
- if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg)) {
+ if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg))
err = -errno;
- igt_assert(errno == ENOTTY || errno == EINVAL);
- }
+
+ errno = 0;
return err;
}
@@ -229,7 +229,6 @@ static int __gem_set_caching(int fd, uint32_t handle, uint32_t caching)
void gem_set_caching(int fd, uint32_t handle, uint32_t caching)
{
igt_require(__gem_set_caching(fd, handle, caching) == 0);
- errno = 0;
}
/**
--
2.16.1
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 07/16] igt/gem_exec_schedule: Trim max number of contexts used
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
icl offers a much reduced context space, and in its simplest setup we
cannot allocate one context per priority level, so trim the number and
reuse the same context for multiple priority requests.
v2: Bump the MAX to 1024 (still lower than the ~4096 previously in use)
v3: Also limit NCTX to MAX_CONTEXTS for wide-*
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Antonio Argenziano <antonio.argenziano@intel.com>
---
tests/gem_exec_schedule.c | 58 ++++++++++++++++++++++++++---------------------
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 05f7ae38..1fc7c697 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -43,6 +43,8 @@
#define BUSY_QLEN 8
#define MAX_ELSP_QLEN 16
+#define MAX_CONTEXTS 1024
+
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
static void store_dword(int fd, uint32_t ctx, unsigned ring,
@@ -556,8 +558,8 @@ static void preemptive_hang(int fd, unsigned ring)
static void deep(int fd, unsigned ring)
{
#define XS 8
- const unsigned int nctx = MAX_PRIO - MIN_PRIO;
- const unsigned size = ALIGN(4*nctx, 4096);
+ const unsigned int nreq = MAX_PRIO - MIN_PRIO;
+ const unsigned size = ALIGN(4*nreq, 4096);
struct timespec tv = {};
struct cork cork;
uint32_t result, dep[XS];
@@ -565,10 +567,9 @@ static void deep(int fd, unsigned ring)
uint32_t *ptr;
uint32_t *ctx;
- ctx = malloc(sizeof(*ctx) * nctx);
- for (int n = 0; n < nctx; n++) {
+ ctx = malloc(sizeof(*ctx) * MAX_CONTEXTS);
+ for (int n = 0; n < MAX_CONTEXTS; n++) {
ctx[n] = gem_context_create(fd);
- gem_context_set_priority(fd, ctx[n], MAX_PRIO - nctx + n);
}
result = gem_create(fd, size);
@@ -592,7 +593,7 @@ static void deep(int fd, unsigned ring)
execbuf.buffers_ptr = to_user_pointer(obj);
execbuf.buffer_count = XS + 2;
execbuf.flags = ring;
- for (int n = 0; n < nctx; n++) {
+ for (int n = 0; n < MAX_CONTEXTS; n++) {
execbuf.rsvd1 = ctx[n];
gem_execbuf(fd, &execbuf);
}
@@ -603,22 +604,29 @@ static void deep(int fd, unsigned ring)
plug(fd, &cork);
/* Create a deep dependency chain, with a few branches */
- for (int n = 0; n < nctx && igt_seconds_elapsed(&tv) < 8; n++)
+ for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 8; n++) {
+ uint32_t context = ctx[n % MAX_CONTEXTS];
+ gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
+
for (int m = 0; m < XS; m++)
- store_dword(fd, ctx[n], ring, dep[m], 4*n, ctx[n], cork.handle, I915_GEM_DOMAIN_INSTRUCTION);
+ store_dword(fd, context, ring, dep[m], 4*n, context, cork.handle, I915_GEM_DOMAIN_INSTRUCTION);
+ }
+
+ for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 6; n++) {
+ uint32_t context = ctx[n % MAX_CONTEXTS];
+ gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
- for (int n = 0; n < nctx && igt_seconds_elapsed(&tv) < 6; n++) {
for (int m = 0; m < XS; m++) {
- store_dword(fd, ctx[n], ring, result, 4*n, ctx[n], dep[m], 0);
- store_dword(fd, ctx[n], ring, result, 4*m, ctx[n], 0, I915_GEM_DOMAIN_INSTRUCTION);
+ store_dword(fd, context, ring, result, 4*n, context, dep[m], 0);
+ store_dword(fd, context, ring, result, 4*m, context, 0, I915_GEM_DOMAIN_INSTRUCTION);
}
- expected = ctx[n];
+ expected = context;
}
unplug_show_queue(fd, &cork, ring);
igt_require(expected); /* too slow */
- for (int n = 0; n < nctx; n++)
+ for (int n = 0; n < MAX_CONTEXTS; n++)
gem_context_destroy(fd, ctx[n]);
for (int m = 0; m < XS; m++) {
@@ -627,8 +635,8 @@ static void deep(int fd, unsigned ring)
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
gem_close(fd, dep[m]);
- for (int n = 0; n < nctx; n++)
- igt_assert_eq_u32(ptr[n], ctx[n]);
+ for (int n = 0; n < nreq; n++)
+ igt_assert_eq_u32(ptr[n], ctx[n % MAX_CONTEXTS]);
munmap(ptr, size);
}
@@ -719,7 +727,6 @@ static unsigned int measure_ring_size(int fd, unsigned int ring)
static void wide(int fd, unsigned ring)
{
-#define NCTX 4096
struct timespec tv = {};
unsigned int ring_size = measure_ring_size(fd, ring);
@@ -729,11 +736,11 @@ static void wide(int fd, unsigned ring)
uint32_t *ctx;
unsigned int count;
- ctx = malloc(sizeof(*ctx)*NCTX);
- for (int n = 0; n < NCTX; n++)
+ ctx = malloc(sizeof(*ctx)*MAX_CONTEXTS);
+ for (int n = 0; n < MAX_CONTEXTS; n++)
ctx[n] = gem_context_create(fd);
- result = gem_create(fd, 4*NCTX);
+ result = gem_create(fd, 4*MAX_CONTEXTS);
plug(fd, &cork);
@@ -741,28 +748,27 @@ static void wide(int fd, unsigned ring)
for (count = 0;
igt_seconds_elapsed(&tv) < 5 && count < ring_size;
count++) {
- for (int n = 0; n < NCTX; n++) {
+ for (int n = 0; n < MAX_CONTEXTS; n++) {
store_dword(fd, ctx[n], ring, result, 4*n, ctx[n], cork.handle, I915_GEM_DOMAIN_INSTRUCTION);
}
}
igt_info("Submitted %d requests over %d contexts in %.1fms\n",
- count, NCTX, igt_nsec_elapsed(&tv) * 1e-6);
+ count, MAX_CONTEXTS, igt_nsec_elapsed(&tv) * 1e-6);
unplug_show_queue(fd, &cork, ring);
- for (int n = 0; n < NCTX; n++)
+ for (int n = 0; n < MAX_CONTEXTS; n++)
gem_context_destroy(fd, ctx[n]);
- ptr = gem_mmap__gtt(fd, result, 4*NCTX, PROT_READ);
+ ptr = gem_mmap__gtt(fd, result, 4*MAX_CONTEXTS, PROT_READ);
gem_set_domain(fd, result, /* no write hazard lies! */
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
- for (int n = 0; n < NCTX; n++)
+ for (int n = 0; n < MAX_CONTEXTS; n++)
igt_assert_eq_u32(ptr[n], ctx[n]);
- munmap(ptr, 4*NCTX);
+ munmap(ptr, 4*MAX_CONTEXTS);
gem_close(fd, result);
free(ctx);
-#undef NCTX
}
static void reorder_wide(int fd, unsigned ring)
--
2.16.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 07/16] igt/gem_exec_schedule: Trim max number of contexts used
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
icl offers a much reduced context space, and in its simplest setup we
cannot allocate one context per priority level, so trim the number and
reuse the same context for multiple priority requests.
v2: Bump the MAX to 1024 (still lower than the ~4096 previously in use)
v3: Also limit NCTX to MAX_CONTEXTS for wide-*
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Antonio Argenziano <antonio.argenziano@intel.com>
---
tests/gem_exec_schedule.c | 58 ++++++++++++++++++++++++++---------------------
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 05f7ae38..1fc7c697 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -43,6 +43,8 @@
#define BUSY_QLEN 8
#define MAX_ELSP_QLEN 16
+#define MAX_CONTEXTS 1024
+
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
static void store_dword(int fd, uint32_t ctx, unsigned ring,
@@ -556,8 +558,8 @@ static void preemptive_hang(int fd, unsigned ring)
static void deep(int fd, unsigned ring)
{
#define XS 8
- const unsigned int nctx = MAX_PRIO - MIN_PRIO;
- const unsigned size = ALIGN(4*nctx, 4096);
+ const unsigned int nreq = MAX_PRIO - MIN_PRIO;
+ const unsigned size = ALIGN(4*nreq, 4096);
struct timespec tv = {};
struct cork cork;
uint32_t result, dep[XS];
@@ -565,10 +567,9 @@ static void deep(int fd, unsigned ring)
uint32_t *ptr;
uint32_t *ctx;
- ctx = malloc(sizeof(*ctx) * nctx);
- for (int n = 0; n < nctx; n++) {
+ ctx = malloc(sizeof(*ctx) * MAX_CONTEXTS);
+ for (int n = 0; n < MAX_CONTEXTS; n++) {
ctx[n] = gem_context_create(fd);
- gem_context_set_priority(fd, ctx[n], MAX_PRIO - nctx + n);
}
result = gem_create(fd, size);
@@ -592,7 +593,7 @@ static void deep(int fd, unsigned ring)
execbuf.buffers_ptr = to_user_pointer(obj);
execbuf.buffer_count = XS + 2;
execbuf.flags = ring;
- for (int n = 0; n < nctx; n++) {
+ for (int n = 0; n < MAX_CONTEXTS; n++) {
execbuf.rsvd1 = ctx[n];
gem_execbuf(fd, &execbuf);
}
@@ -603,22 +604,29 @@ static void deep(int fd, unsigned ring)
plug(fd, &cork);
/* Create a deep dependency chain, with a few branches */
- for (int n = 0; n < nctx && igt_seconds_elapsed(&tv) < 8; n++)
+ for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 8; n++) {
+ uint32_t context = ctx[n % MAX_CONTEXTS];
+ gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
+
for (int m = 0; m < XS; m++)
- store_dword(fd, ctx[n], ring, dep[m], 4*n, ctx[n], cork.handle, I915_GEM_DOMAIN_INSTRUCTION);
+ store_dword(fd, context, ring, dep[m], 4*n, context, cork.handle, I915_GEM_DOMAIN_INSTRUCTION);
+ }
+
+ for (int n = 0; n < nreq && igt_seconds_elapsed(&tv) < 6; n++) {
+ uint32_t context = ctx[n % MAX_CONTEXTS];
+ gem_context_set_priority(fd, context, MAX_PRIO - nreq + n);
- for (int n = 0; n < nctx && igt_seconds_elapsed(&tv) < 6; n++) {
for (int m = 0; m < XS; m++) {
- store_dword(fd, ctx[n], ring, result, 4*n, ctx[n], dep[m], 0);
- store_dword(fd, ctx[n], ring, result, 4*m, ctx[n], 0, I915_GEM_DOMAIN_INSTRUCTION);
+ store_dword(fd, context, ring, result, 4*n, context, dep[m], 0);
+ store_dword(fd, context, ring, result, 4*m, context, 0, I915_GEM_DOMAIN_INSTRUCTION);
}
- expected = ctx[n];
+ expected = context;
}
unplug_show_queue(fd, &cork, ring);
igt_require(expected); /* too slow */
- for (int n = 0; n < nctx; n++)
+ for (int n = 0; n < MAX_CONTEXTS; n++)
gem_context_destroy(fd, ctx[n]);
for (int m = 0; m < XS; m++) {
@@ -627,8 +635,8 @@ static void deep(int fd, unsigned ring)
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
gem_close(fd, dep[m]);
- for (int n = 0; n < nctx; n++)
- igt_assert_eq_u32(ptr[n], ctx[n]);
+ for (int n = 0; n < nreq; n++)
+ igt_assert_eq_u32(ptr[n], ctx[n % MAX_CONTEXTS]);
munmap(ptr, size);
}
@@ -719,7 +727,6 @@ static unsigned int measure_ring_size(int fd, unsigned int ring)
static void wide(int fd, unsigned ring)
{
-#define NCTX 4096
struct timespec tv = {};
unsigned int ring_size = measure_ring_size(fd, ring);
@@ -729,11 +736,11 @@ static void wide(int fd, unsigned ring)
uint32_t *ctx;
unsigned int count;
- ctx = malloc(sizeof(*ctx)*NCTX);
- for (int n = 0; n < NCTX; n++)
+ ctx = malloc(sizeof(*ctx)*MAX_CONTEXTS);
+ for (int n = 0; n < MAX_CONTEXTS; n++)
ctx[n] = gem_context_create(fd);
- result = gem_create(fd, 4*NCTX);
+ result = gem_create(fd, 4*MAX_CONTEXTS);
plug(fd, &cork);
@@ -741,28 +748,27 @@ static void wide(int fd, unsigned ring)
for (count = 0;
igt_seconds_elapsed(&tv) < 5 && count < ring_size;
count++) {
- for (int n = 0; n < NCTX; n++) {
+ for (int n = 0; n < MAX_CONTEXTS; n++) {
store_dword(fd, ctx[n], ring, result, 4*n, ctx[n], cork.handle, I915_GEM_DOMAIN_INSTRUCTION);
}
}
igt_info("Submitted %d requests over %d contexts in %.1fms\n",
- count, NCTX, igt_nsec_elapsed(&tv) * 1e-6);
+ count, MAX_CONTEXTS, igt_nsec_elapsed(&tv) * 1e-6);
unplug_show_queue(fd, &cork, ring);
- for (int n = 0; n < NCTX; n++)
+ for (int n = 0; n < MAX_CONTEXTS; n++)
gem_context_destroy(fd, ctx[n]);
- ptr = gem_mmap__gtt(fd, result, 4*NCTX, PROT_READ);
+ ptr = gem_mmap__gtt(fd, result, 4*MAX_CONTEXTS, PROT_READ);
gem_set_domain(fd, result, /* no write hazard lies! */
I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
- for (int n = 0; n < NCTX; n++)
+ for (int n = 0; n < MAX_CONTEXTS; n++)
igt_assert_eq_u32(ptr[n], ctx[n]);
- munmap(ptr, 4*NCTX);
+ munmap(ptr, 4*MAX_CONTEXTS);
gem_close(fd, result);
free(ctx);
-#undef NCTX
}
static void reorder_wide(int fd, unsigned ring)
--
2.16.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 08/16] igt/gem_exec_schedule: Replace constant 16 with its magic macro
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
s/16/MAX_ELSP_QLEN/ as appropriate
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_schedule.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 1fc7c697..21102591 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -40,9 +40,10 @@
#define MAX_PRIO LOCAL_I915_CONTEXT_MAX_USER_PRIORITY
#define MIN_PRIO LOCAL_I915_CONTEXT_MIN_USER_PRIORITY
-#define BUSY_QLEN 8
#define MAX_ELSP_QLEN 16
+#define MAX_ENGINES 16
+
#define MAX_CONTEXTS 1024
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
@@ -146,7 +147,7 @@ static uint32_t create_highest_priority(int fd)
static void unplug_show_queue(int fd, struct cork *c, unsigned int engine)
{
- igt_spin_t *spin[BUSY_QLEN];
+ igt_spin_t *spin[MAX_ELSP_QLEN];
for (int n = 0; n < ARRAY_SIZE(spin); n++) {
uint32_t ctx = create_highest_priority(fd);
@@ -201,7 +202,7 @@ static bool ignore_engine(int fd, unsigned engine)
static void smoketest(int fd, unsigned ring, unsigned timeout)
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
- unsigned engines[16];
+ unsigned engines[MAX_ENGINES];
unsigned nengine;
unsigned engine;
uint32_t scratch;
@@ -382,7 +383,7 @@ static void preempt(int fd, unsigned ring, unsigned flags)
if (flags & HANG_LP)
hang = igt_hang_ctx(fd, ctx[LO], ring, 0, NULL);
- for (int n = 0; n < 16; n++) {
+ for (int n = 0; n < MAX_ELSP_QLEN; n++) {
if (flags & NEW_CTX) {
gem_context_destroy(fd, ctx[LO]);
ctx[LO] = gem_context_create(fd);
@@ -398,7 +399,7 @@ static void preempt(int fd, unsigned ring, unsigned flags)
igt_assert(gem_bo_busy(fd, spin[0]->handle));
}
- for (int n = 0; n < 16; n++)
+ for (int n = 0; n < MAX_ELSP_QLEN; n++)
igt_spin_batch_free(fd, spin[n]);
if (flags & HANG_LP)
@@ -415,7 +416,7 @@ static void preempt_other(int fd, unsigned ring)
{
uint32_t result = gem_create(fd, 4096);
uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
- igt_spin_t *spin[MAX_ELSP_QLEN];
+ igt_spin_t *spin[MAX_ENGINES];
unsigned int other;
unsigned int n, i;
uint32_t ctx[3];
@@ -440,6 +441,8 @@ static void preempt_other(int fd, unsigned ring)
n = 0;
for_each_engine(fd, other) {
+ igt_assert(n < ARRAY_SIZE(spin));
+
spin[n] = __igt_spin_batch_new(fd, ctx[NOISE], other, 0);
store_dword(fd, ctx[LO], other,
result, (n + 1)*sizeof(uint32_t), n + 1,
@@ -450,6 +453,7 @@ static void preempt_other(int fd, unsigned ring)
result, (n + 1)*sizeof(uint32_t), n + 1,
0, I915_GEM_DOMAIN_RENDER);
+ igt_debugfs_dump(fd, "i915_engine_info");
gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
for (i = 0; i < n; i++) {
@@ -531,7 +535,7 @@ static void preemptive_hang(int fd, unsigned ring)
ctx[HI] = gem_context_create(fd);
gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
- for (int n = 0; n < 16; n++) {
+ for (int n = 0; n < MAX_ELSP_QLEN; n++) {
ctx[LO] = gem_context_create(fd);
gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
@@ -543,7 +547,7 @@ static void preemptive_hang(int fd, unsigned ring)
hang = igt_hang_ctx(fd, ctx[HI], ring, 0, NULL);
igt_post_hang_ring(fd, hang);
- for (int n = 0; n < 16; n++) {
+ for (int n = 0; n < MAX_ELSP_QLEN; n++) {
/* Current behavior is to execute requests in order of submission.
* This is subject to change as the scheduler evolve. The test should
* be updated to reflect such changes.
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 08/16] igt/gem_exec_schedule: Replace constant 16 with its magic macro
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
s/16/MAX_ELSP_QLEN/ as appropriate
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_schedule.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 1fc7c697..21102591 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -40,9 +40,10 @@
#define MAX_PRIO LOCAL_I915_CONTEXT_MAX_USER_PRIORITY
#define MIN_PRIO LOCAL_I915_CONTEXT_MIN_USER_PRIORITY
-#define BUSY_QLEN 8
#define MAX_ELSP_QLEN 16
+#define MAX_ENGINES 16
+
#define MAX_CONTEXTS 1024
IGT_TEST_DESCRIPTION("Check that we can control the order of execution");
@@ -146,7 +147,7 @@ static uint32_t create_highest_priority(int fd)
static void unplug_show_queue(int fd, struct cork *c, unsigned int engine)
{
- igt_spin_t *spin[BUSY_QLEN];
+ igt_spin_t *spin[MAX_ELSP_QLEN];
for (int n = 0; n < ARRAY_SIZE(spin); n++) {
uint32_t ctx = create_highest_priority(fd);
@@ -201,7 +202,7 @@ static bool ignore_engine(int fd, unsigned engine)
static void smoketest(int fd, unsigned ring, unsigned timeout)
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
- unsigned engines[16];
+ unsigned engines[MAX_ENGINES];
unsigned nengine;
unsigned engine;
uint32_t scratch;
@@ -382,7 +383,7 @@ static void preempt(int fd, unsigned ring, unsigned flags)
if (flags & HANG_LP)
hang = igt_hang_ctx(fd, ctx[LO], ring, 0, NULL);
- for (int n = 0; n < 16; n++) {
+ for (int n = 0; n < MAX_ELSP_QLEN; n++) {
if (flags & NEW_CTX) {
gem_context_destroy(fd, ctx[LO]);
ctx[LO] = gem_context_create(fd);
@@ -398,7 +399,7 @@ static void preempt(int fd, unsigned ring, unsigned flags)
igt_assert(gem_bo_busy(fd, spin[0]->handle));
}
- for (int n = 0; n < 16; n++)
+ for (int n = 0; n < MAX_ELSP_QLEN; n++)
igt_spin_batch_free(fd, spin[n]);
if (flags & HANG_LP)
@@ -415,7 +416,7 @@ static void preempt_other(int fd, unsigned ring)
{
uint32_t result = gem_create(fd, 4096);
uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
- igt_spin_t *spin[MAX_ELSP_QLEN];
+ igt_spin_t *spin[MAX_ENGINES];
unsigned int other;
unsigned int n, i;
uint32_t ctx[3];
@@ -440,6 +441,8 @@ static void preempt_other(int fd, unsigned ring)
n = 0;
for_each_engine(fd, other) {
+ igt_assert(n < ARRAY_SIZE(spin));
+
spin[n] = __igt_spin_batch_new(fd, ctx[NOISE], other, 0);
store_dword(fd, ctx[LO], other,
result, (n + 1)*sizeof(uint32_t), n + 1,
@@ -450,6 +453,7 @@ static void preempt_other(int fd, unsigned ring)
result, (n + 1)*sizeof(uint32_t), n + 1,
0, I915_GEM_DOMAIN_RENDER);
+ igt_debugfs_dump(fd, "i915_engine_info");
gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
for (i = 0; i < n; i++) {
@@ -531,7 +535,7 @@ static void preemptive_hang(int fd, unsigned ring)
ctx[HI] = gem_context_create(fd);
gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
- for (int n = 0; n < 16; n++) {
+ for (int n = 0; n < MAX_ELSP_QLEN; n++) {
ctx[LO] = gem_context_create(fd);
gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
@@ -543,7 +547,7 @@ static void preemptive_hang(int fd, unsigned ring)
hang = igt_hang_ctx(fd, ctx[HI], ring, 0, NULL);
igt_post_hang_ring(fd, hang);
- for (int n = 0; n < 16; n++) {
+ for (int n = 0; n < MAX_ELSP_QLEN; n++) {
/* Current behavior is to execute requests in order of submission.
* This is subject to change as the scheduler evolve. The test should
* be updated to reflect such changes.
--
2.16.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 09/16] igt/gem_fenced_exec_thrash: Use fixed durations
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Convert from using constant loops of indeterminate loads over to using a
duration based with precise dummyloads, we are able to do more cycles in
less time by limiting the amount of BUSY_LOAD required to exercise the
test.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_fenced_exec_thrash.c | 109 ++++++++++-------------------------------
1 file changed, 27 insertions(+), 82 deletions(-)
diff --git a/tests/gem_fenced_exec_thrash.c b/tests/gem_fenced_exec_thrash.c
index 9a43c845..5a28a4ce 100644
--- a/tests/gem_fenced_exec_thrash.c
+++ b/tests/gem_fenced_exec_thrash.c
@@ -25,17 +25,12 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
-#include <sys/ioctl.h>
-#include <stdio.h>
#include <string.h>
-#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
-#include <drm.h>
-
+#include "igt.h"
IGT_TEST_DESCRIPTION("Test execbuf fence accounting.");
@@ -59,53 +54,6 @@ IGT_TEST_DESCRIPTION("Test execbuf fence accounting.");
* each command.
*/
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
-
-static void emit_dummy_load(void)
-{
- int i;
- uint32_t tile_flags = 0;
- uint32_t tiling_mode = I915_TILING_X;
- unsigned long pitch;
- drm_intel_bo *dummy_bo;
-
- dummy_bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled dummy_bo", 2048, 2048,
- 4, &tiling_mode, &pitch, 0);
-
- if (IS_965(devid)) {
- pitch /= 4;
- tile_flags = XY_SRC_COPY_BLT_SRC_TILED |
- XY_SRC_COPY_BLT_DST_TILED;
- }
-
- for (i = 0; i < 5; i++) {
- BLIT_COPY_BATCH_START(tile_flags);
- OUT_BATCH((3 << 24) | /* 32 bits */
- (0xcc << 16) | /* copy ROP */
- pitch);
- OUT_BATCH(0 << 16 | 1024);
- OUT_BATCH((2048) << 16 | (2048));
- OUT_RELOC_FENCED(dummy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
- OUT_BATCH(0 << 16 | 0);
- OUT_BATCH(pitch);
- OUT_RELOC_FENCED(dummy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
- ADVANCE_BATCH();
-
- if (batch->gen >= 6) {
- BEGIN_BATCH(3, 0);
- OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
- }
- }
- intel_batchbuffer_flush(batch);
-
- drm_intel_bo_unreference(dummy_bo);
-}
-
static uint32_t
tiled_bo_create (int fd)
{
@@ -149,19 +97,10 @@ static void run_test(int fd, int num_fences, int expected_errno,
struct drm_i915_gem_exec_object2 exec[2][2*MAX_FENCES+3];
struct drm_i915_gem_relocation_entry reloc[2*MAX_FENCES+2];
+ unsigned long count;
int i, n;
- int loop = 1000;
-
- if (flags & BUSY_LOAD) {
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- batch = intel_batchbuffer_alloc(bufmgr, devid);
- /* Takes forever otherwise. */
- loop = 50;
- }
-
- if (flags & INTERRUPTIBLE)
- igt_fork_signal_helper();
+ igt_assert(2*num_fences+1 < ARRAY_SIZE(exec[0]));
memset(execbuf, 0, sizeof(execbuf));
memset(exec, 0, sizeof(exec));
@@ -186,16 +125,25 @@ static void run_test(int fd, int num_fences, int expected_errno,
execbuf[i].batch_len = 2*sizeof(uint32_t);
}
- do {
- if (flags & BUSY_LOAD)
- emit_dummy_load();
+ count = 0;
+ igt_until_timeout(2) {
+ for (i = 0; i < 2; i++) {
+ igt_spin_t *spin = NULL;
+
+ if (flags & BUSY_LOAD)
+ spin = __igt_spin_batch_new(fd, 0, 0, 0);
- igt_assert_eq(__gem_execbuf(fd, &execbuf[0]), -expected_errno);
- igt_assert_eq(__gem_execbuf(fd, &execbuf[1]), -expected_errno);
- } while (--loop);
+ igt_while_interruptible(flags & INTERRUPTIBLE) {
+ igt_assert_eq(__gem_execbuf(fd, &execbuf[i]),
+ -expected_errno);
+ }
- if (flags & INTERRUPTIBLE)
- igt_stop_signal_helper();
+ igt_spin_batch_free(fd, spin);
+ gem_quiescent_gpu(fd);
+ }
+ count++;
+ }
+ igt_info("Completed %lu cycles\n", count);
/* Cleanup */
for (n = 0; n < 2*num_fences; n++)
@@ -203,28 +151,25 @@ static void run_test(int fd, int num_fences, int expected_errno,
for (i = 0; i < 2; i++)
gem_close(fd, exec[i][2*num_fences].handle);
-
- if (flags & BUSY_LOAD) {
- intel_batchbuffer_free(batch);
- drm_intel_bufmgr_destroy(bufmgr);
- }
}
-int fd;
-int num_fences;
-
igt_main
{
+ uint32_t devid = 0;
+ unsigned int num_fences = 0;
+ int fd = -1;
+
igt_skip_on_simulation();
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+
num_fences = gem_available_fences(fd);
igt_assert(num_fences > 4);
- devid = intel_get_drm_devid(fd);
-
igt_assert(num_fences <= MAX_FENCES);
+
+ devid = intel_get_drm_devid(fd);
}
igt_subtest("2-spare-fences")
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 09/16] igt/gem_fenced_exec_thrash: Use fixed durations
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Convert from using constant loops of indeterminate loads over to using a
duration based with precise dummyloads, we are able to do more cycles in
less time by limiting the amount of BUSY_LOAD required to exercise the
test.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_fenced_exec_thrash.c | 109 ++++++++++-------------------------------
1 file changed, 27 insertions(+), 82 deletions(-)
diff --git a/tests/gem_fenced_exec_thrash.c b/tests/gem_fenced_exec_thrash.c
index 9a43c845..5a28a4ce 100644
--- a/tests/gem_fenced_exec_thrash.c
+++ b/tests/gem_fenced_exec_thrash.c
@@ -25,17 +25,12 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
-#include <sys/ioctl.h>
-#include <stdio.h>
#include <string.h>
-#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
-#include <drm.h>
-
+#include "igt.h"
IGT_TEST_DESCRIPTION("Test execbuf fence accounting.");
@@ -59,53 +54,6 @@ IGT_TEST_DESCRIPTION("Test execbuf fence accounting.");
* each command.
*/
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
-
-static void emit_dummy_load(void)
-{
- int i;
- uint32_t tile_flags = 0;
- uint32_t tiling_mode = I915_TILING_X;
- unsigned long pitch;
- drm_intel_bo *dummy_bo;
-
- dummy_bo = drm_intel_bo_alloc_tiled(bufmgr, "tiled dummy_bo", 2048, 2048,
- 4, &tiling_mode, &pitch, 0);
-
- if (IS_965(devid)) {
- pitch /= 4;
- tile_flags = XY_SRC_COPY_BLT_SRC_TILED |
- XY_SRC_COPY_BLT_DST_TILED;
- }
-
- for (i = 0; i < 5; i++) {
- BLIT_COPY_BATCH_START(tile_flags);
- OUT_BATCH((3 << 24) | /* 32 bits */
- (0xcc << 16) | /* copy ROP */
- pitch);
- OUT_BATCH(0 << 16 | 1024);
- OUT_BATCH((2048) << 16 | (2048));
- OUT_RELOC_FENCED(dummy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
- OUT_BATCH(0 << 16 | 0);
- OUT_BATCH(pitch);
- OUT_RELOC_FENCED(dummy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
- ADVANCE_BATCH();
-
- if (batch->gen >= 6) {
- BEGIN_BATCH(3, 0);
- OUT_BATCH(XY_SETUP_CLIP_BLT_CMD);
- OUT_BATCH(0);
- OUT_BATCH(0);
- ADVANCE_BATCH();
- }
- }
- intel_batchbuffer_flush(batch);
-
- drm_intel_bo_unreference(dummy_bo);
-}
-
static uint32_t
tiled_bo_create (int fd)
{
@@ -149,19 +97,10 @@ static void run_test(int fd, int num_fences, int expected_errno,
struct drm_i915_gem_exec_object2 exec[2][2*MAX_FENCES+3];
struct drm_i915_gem_relocation_entry reloc[2*MAX_FENCES+2];
+ unsigned long count;
int i, n;
- int loop = 1000;
-
- if (flags & BUSY_LOAD) {
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- batch = intel_batchbuffer_alloc(bufmgr, devid);
- /* Takes forever otherwise. */
- loop = 50;
- }
-
- if (flags & INTERRUPTIBLE)
- igt_fork_signal_helper();
+ igt_assert(2*num_fences+1 < ARRAY_SIZE(exec[0]));
memset(execbuf, 0, sizeof(execbuf));
memset(exec, 0, sizeof(exec));
@@ -186,16 +125,25 @@ static void run_test(int fd, int num_fences, int expected_errno,
execbuf[i].batch_len = 2*sizeof(uint32_t);
}
- do {
- if (flags & BUSY_LOAD)
- emit_dummy_load();
+ count = 0;
+ igt_until_timeout(2) {
+ for (i = 0; i < 2; i++) {
+ igt_spin_t *spin = NULL;
+
+ if (flags & BUSY_LOAD)
+ spin = __igt_spin_batch_new(fd, 0, 0, 0);
- igt_assert_eq(__gem_execbuf(fd, &execbuf[0]), -expected_errno);
- igt_assert_eq(__gem_execbuf(fd, &execbuf[1]), -expected_errno);
- } while (--loop);
+ igt_while_interruptible(flags & INTERRUPTIBLE) {
+ igt_assert_eq(__gem_execbuf(fd, &execbuf[i]),
+ -expected_errno);
+ }
- if (flags & INTERRUPTIBLE)
- igt_stop_signal_helper();
+ igt_spin_batch_free(fd, spin);
+ gem_quiescent_gpu(fd);
+ }
+ count++;
+ }
+ igt_info("Completed %lu cycles\n", count);
/* Cleanup */
for (n = 0; n < 2*num_fences; n++)
@@ -203,28 +151,25 @@ static void run_test(int fd, int num_fences, int expected_errno,
for (i = 0; i < 2; i++)
gem_close(fd, exec[i][2*num_fences].handle);
-
- if (flags & BUSY_LOAD) {
- intel_batchbuffer_free(batch);
- drm_intel_bufmgr_destroy(bufmgr);
- }
}
-int fd;
-int num_fences;
-
igt_main
{
+ uint32_t devid = 0;
+ unsigned int num_fences = 0;
+ int fd = -1;
+
igt_skip_on_simulation();
igt_fixture {
fd = drm_open_driver(DRIVER_INTEL);
igt_require_gem(fd);
+
num_fences = gem_available_fences(fd);
igt_assert(num_fences > 4);
- devid = intel_get_drm_devid(fd);
-
igt_assert(num_fences <= MAX_FENCES);
+
+ devid = intel_get_drm_devid(fd);
}
igt_subtest("2-spare-fences")
--
2.16.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 10/16] igt/gem_eio: Use slow spinners to inject hangs
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
One weird issue we see in bug 104676 is that the hangs are too fast on
HSW! So force the use of the slow spinners that do not try to trigger
a hang by injecting random bytes into the batch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104676
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_gt.c | 1 +
tests/gem_eio.c | 84 +++++++++++++++++++++++++++++++++------------------------
2 files changed, 50 insertions(+), 35 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index ad6e6205..f70fcb92 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -402,6 +402,7 @@ void igt_force_gpu_reset(int drm_fd)
igt_sysfs_scanf(dir, "i915_wedged", "%d", &wedged);
close(dir);
+ errno = 0;
igt_assert(!wedged);
}
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index 16a89ecd..11776306 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -67,6 +67,8 @@ static void trigger_reset(int fd)
/* And just check the gpu is indeed running again */
igt_debug("Checking that the GPU recovered\n");
gem_test_engine(fd, -1);
+
+ gem_quiescent_gpu(fd);
}
static void wedge_gpu(int fd)
@@ -133,15 +135,17 @@ static void test_execbuf(int fd)
static int __gem_wait(int fd, uint32_t handle, int64_t timeout)
{
- struct drm_i915_gem_wait wait;
- int err = 0;
+ struct drm_i915_gem_wait wait = {
+ .bo_handle = handle,
+ .timeout_ns = timeout,
+ };
+ int err;
- memset(&wait, 0, sizeof(wait));
- wait.bo_handle = handle;
- wait.timeout_ns = timeout;
+ err = 0;
if (drmIoctl(fd, DRM_IOCTL_I915_GEM_WAIT, &wait))
err = -errno;
+ errno = 0;
return err;
}
@@ -149,6 +153,8 @@ static void test_wait(int fd)
{
igt_hang_t hang;
+ igt_require_gem(fd);
+
/* If the request we wait on completes due to a hang (even for
* that request), the user expects the return value to 0 (success).
*/
@@ -182,12 +188,11 @@ static void test_suspend(int fd, int state)
static void test_inflight(int fd)
{
- struct drm_i915_gem_execbuffer2 execbuf;
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
struct drm_i915_gem_exec_object2 obj[2];
- uint32_t bbe = MI_BATCH_BUFFER_END;
unsigned int engine;
- int fence[64]; /* conservative estimate of ring size */
+ igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
memset(obj, 0, sizeof(obj));
@@ -196,13 +201,17 @@ static void test_inflight(int fd)
gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
for_each_engine(fd, engine) {
- igt_hang_t hang;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ igt_spin_t *hang;
+ int fence[64]; /* conservative estimate of ring size */
+
+ gem_quiescent_gpu(fd);
igt_debug("Starting %s on engine '%s'\n", __func__, e__->name);
igt_require(i915_reset_control(false));
- hang = igt_hang_ring(fd, engine);
- obj[0].handle = hang.handle;
+ hang = __igt_spin_batch_new(fd, 0, engine, 0);
+ obj[0].handle = hang->handle;
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
@@ -215,14 +224,13 @@ static void test_inflight(int fd)
igt_assert(fence[n] != -1);
}
- igt_post_hang_ring(fd, hang);
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) {
igt_assert_eq(sync_fence_status(fence[n]), -EIO);
close(fence[n]);
}
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
@@ -234,8 +242,9 @@ static void test_inflight_suspend(int fd)
struct drm_i915_gem_exec_object2 obj[2];
uint32_t bbe = MI_BATCH_BUFFER_END;
int fence[64]; /* conservative estimate of ring size */
- igt_hang_t hang;
+ igt_spin_t *hang;
+ igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
igt_require(i915_reset_control(false));
@@ -244,8 +253,8 @@ static void test_inflight_suspend(int fd)
obj[1].handle = gem_create(fd, 4096);
gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
- hang = igt_hang_ring(fd, 0);
- obj[0].handle = hang.handle;
+ hang = __igt_spin_batch_new(fd, 0, 0, 0);
+ obj[0].handle = hang->handle;
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
@@ -261,27 +270,25 @@ static void test_inflight_suspend(int fd)
igt_set_autoresume_delay(30);
igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_NONE);
- igt_post_hang_ring(fd, hang);
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) {
igt_assert_eq(sync_fence_status(fence[n]), -EIO);
close(fence[n]);
}
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
static void test_inflight_contexts(int fd)
{
- struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj[2];
- uint32_t bbe = MI_BATCH_BUFFER_END;
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
unsigned int engine;
uint32_t ctx[64];
- int fence[64];
+ igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
gem_require_contexts(fd);
@@ -296,13 +303,17 @@ static void test_inflight_contexts(int fd)
gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
for_each_engine(fd, engine) {
- igt_hang_t hang;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ igt_spin_t *hang;
+ int fence[64];
+
+ gem_quiescent_gpu(fd);
igt_debug("Starting %s on engine '%s'\n", __func__, e__->name);
igt_require(i915_reset_control(false));
- hang = igt_hang_ring(fd, engine);
- obj[0].handle = hang.handle;
+ hang = __igt_spin_batch_new(fd, 0, engine, 0);
+ obj[0].handle = hang->handle;
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
@@ -316,14 +327,13 @@ static void test_inflight_contexts(int fd)
igt_assert(fence[n] != -1);
}
- igt_post_hang_ring(fd, hang);
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) {
igt_assert_eq(sync_fence_status(fence[n]), -EIO);
close(fence[n]);
}
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
@@ -334,12 +344,13 @@ static void test_inflight_contexts(int fd)
static void test_inflight_external(int fd)
{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj;
- uint32_t bbe = MI_BATCH_BUFFER_END;
- igt_hang_t hang;
int timeline, fence;
+ igt_spin_t *hang;
+ igt_require_gem(fd);
igt_require_sw_sync();
igt_require(gem_has_exec_fence(fd));
@@ -347,7 +358,7 @@ static void test_inflight_external(int fd)
fence = sw_sync_timeline_create_fence(timeline, 1);
igt_require(i915_reset_control(false));
- hang = igt_hang_ring(fd, I915_EXEC_DEFAULT);
+ hang = __igt_spin_batch_new(fd, 0, 0, 0);
memset(&obj, 0, sizeof(obj));
obj.handle = gem_create(fd, 4096);
@@ -365,13 +376,16 @@ static void test_inflight_external(int fd)
fence = execbuf.rsvd2 >> 32;
igt_assert(fence != -1);
- igt_post_hang_ring(fd, hang); /* wedged, with an unready batch */
+ gem_sync(fd, hang->handle); /* wedged, with an unready batch */
+ igt_assert(!gem_bo_busy(fd, hang->handle));
+ igt_assert(gem_bo_busy(fd, obj.handle));
sw_sync_timeline_inc(timeline, 1); /* only now submit our batches */
igt_assert_eq(__gem_wait(fd, obj.handle, -1), 0);
igt_assert_eq(sync_fence_status(fence), -EIO);
close(fence);
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
close(timeline);
@@ -384,15 +398,16 @@ static void test_inflight_internal(int fd)
uint32_t bbe = MI_BATCH_BUFFER_END;
unsigned engine, nfence = 0;
int fences[16];
- igt_hang_t hang;
+ igt_spin_t *hang;
+ igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
igt_require(i915_reset_control(false));
- hang = igt_hang_ring(fd, I915_EXEC_DEFAULT);
+ hang = __igt_spin_batch_new(fd, 0, 0, 0);
memset(obj, 0, sizeof(obj));
- obj[0].handle = hang.handle;
+ obj[0].handle = hang->handle;
obj[0].flags = EXEC_OBJECT_WRITE;
obj[1].handle = gem_create(fd, 4096);
gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
@@ -410,14 +425,13 @@ static void test_inflight_internal(int fd)
nfence++;
}
- igt_post_hang_ring(fd, hang); /* wedged, with an unready batch */
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
while (nfence--) {
igt_assert_eq(sync_fence_status(fences[nfence]), -EIO);
close(fences[nfence]);
}
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 10/16] igt/gem_eio: Use slow spinners to inject hangs
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
One weird issue we see in bug 104676 is that the hangs are too fast on
HSW! So force the use of the slow spinners that do not try to trigger
a hang by injecting random bytes into the batch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104676
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
lib/igt_gt.c | 1 +
tests/gem_eio.c | 84 +++++++++++++++++++++++++++++++++------------------------
2 files changed, 50 insertions(+), 35 deletions(-)
diff --git a/lib/igt_gt.c b/lib/igt_gt.c
index ad6e6205..f70fcb92 100644
--- a/lib/igt_gt.c
+++ b/lib/igt_gt.c
@@ -402,6 +402,7 @@ void igt_force_gpu_reset(int drm_fd)
igt_sysfs_scanf(dir, "i915_wedged", "%d", &wedged);
close(dir);
+ errno = 0;
igt_assert(!wedged);
}
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index 16a89ecd..11776306 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -67,6 +67,8 @@ static void trigger_reset(int fd)
/* And just check the gpu is indeed running again */
igt_debug("Checking that the GPU recovered\n");
gem_test_engine(fd, -1);
+
+ gem_quiescent_gpu(fd);
}
static void wedge_gpu(int fd)
@@ -133,15 +135,17 @@ static void test_execbuf(int fd)
static int __gem_wait(int fd, uint32_t handle, int64_t timeout)
{
- struct drm_i915_gem_wait wait;
- int err = 0;
+ struct drm_i915_gem_wait wait = {
+ .bo_handle = handle,
+ .timeout_ns = timeout,
+ };
+ int err;
- memset(&wait, 0, sizeof(wait));
- wait.bo_handle = handle;
- wait.timeout_ns = timeout;
+ err = 0;
if (drmIoctl(fd, DRM_IOCTL_I915_GEM_WAIT, &wait))
err = -errno;
+ errno = 0;
return err;
}
@@ -149,6 +153,8 @@ static void test_wait(int fd)
{
igt_hang_t hang;
+ igt_require_gem(fd);
+
/* If the request we wait on completes due to a hang (even for
* that request), the user expects the return value to 0 (success).
*/
@@ -182,12 +188,11 @@ static void test_suspend(int fd, int state)
static void test_inflight(int fd)
{
- struct drm_i915_gem_execbuffer2 execbuf;
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
struct drm_i915_gem_exec_object2 obj[2];
- uint32_t bbe = MI_BATCH_BUFFER_END;
unsigned int engine;
- int fence[64]; /* conservative estimate of ring size */
+ igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
memset(obj, 0, sizeof(obj));
@@ -196,13 +201,17 @@ static void test_inflight(int fd)
gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
for_each_engine(fd, engine) {
- igt_hang_t hang;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ igt_spin_t *hang;
+ int fence[64]; /* conservative estimate of ring size */
+
+ gem_quiescent_gpu(fd);
igt_debug("Starting %s on engine '%s'\n", __func__, e__->name);
igt_require(i915_reset_control(false));
- hang = igt_hang_ring(fd, engine);
- obj[0].handle = hang.handle;
+ hang = __igt_spin_batch_new(fd, 0, engine, 0);
+ obj[0].handle = hang->handle;
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
@@ -215,14 +224,13 @@ static void test_inflight(int fd)
igt_assert(fence[n] != -1);
}
- igt_post_hang_ring(fd, hang);
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) {
igt_assert_eq(sync_fence_status(fence[n]), -EIO);
close(fence[n]);
}
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
@@ -234,8 +242,9 @@ static void test_inflight_suspend(int fd)
struct drm_i915_gem_exec_object2 obj[2];
uint32_t bbe = MI_BATCH_BUFFER_END;
int fence[64]; /* conservative estimate of ring size */
- igt_hang_t hang;
+ igt_spin_t *hang;
+ igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
igt_require(i915_reset_control(false));
@@ -244,8 +253,8 @@ static void test_inflight_suspend(int fd)
obj[1].handle = gem_create(fd, 4096);
gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
- hang = igt_hang_ring(fd, 0);
- obj[0].handle = hang.handle;
+ hang = __igt_spin_batch_new(fd, 0, 0, 0);
+ obj[0].handle = hang->handle;
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
@@ -261,27 +270,25 @@ static void test_inflight_suspend(int fd)
igt_set_autoresume_delay(30);
igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_NONE);
- igt_post_hang_ring(fd, hang);
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) {
igt_assert_eq(sync_fence_status(fence[n]), -EIO);
close(fence[n]);
}
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
static void test_inflight_contexts(int fd)
{
- struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj[2];
- uint32_t bbe = MI_BATCH_BUFFER_END;
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
unsigned int engine;
uint32_t ctx[64];
- int fence[64];
+ igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
gem_require_contexts(fd);
@@ -296,13 +303,17 @@ static void test_inflight_contexts(int fd)
gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
for_each_engine(fd, engine) {
- igt_hang_t hang;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ igt_spin_t *hang;
+ int fence[64];
+
+ gem_quiescent_gpu(fd);
igt_debug("Starting %s on engine '%s'\n", __func__, e__->name);
igt_require(i915_reset_control(false));
- hang = igt_hang_ring(fd, engine);
- obj[0].handle = hang.handle;
+ hang = __igt_spin_batch_new(fd, 0, engine, 0);
+ obj[0].handle = hang->handle;
memset(&execbuf, 0, sizeof(execbuf));
execbuf.buffers_ptr = to_user_pointer(obj);
@@ -316,14 +327,13 @@ static void test_inflight_contexts(int fd)
igt_assert(fence[n] != -1);
}
- igt_post_hang_ring(fd, hang);
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) {
igt_assert_eq(sync_fence_status(fence[n]), -EIO);
close(fence[n]);
}
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
@@ -334,12 +344,13 @@ static void test_inflight_contexts(int fd)
static void test_inflight_external(int fd)
{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj;
- uint32_t bbe = MI_BATCH_BUFFER_END;
- igt_hang_t hang;
int timeline, fence;
+ igt_spin_t *hang;
+ igt_require_gem(fd);
igt_require_sw_sync();
igt_require(gem_has_exec_fence(fd));
@@ -347,7 +358,7 @@ static void test_inflight_external(int fd)
fence = sw_sync_timeline_create_fence(timeline, 1);
igt_require(i915_reset_control(false));
- hang = igt_hang_ring(fd, I915_EXEC_DEFAULT);
+ hang = __igt_spin_batch_new(fd, 0, 0, 0);
memset(&obj, 0, sizeof(obj));
obj.handle = gem_create(fd, 4096);
@@ -365,13 +376,16 @@ static void test_inflight_external(int fd)
fence = execbuf.rsvd2 >> 32;
igt_assert(fence != -1);
- igt_post_hang_ring(fd, hang); /* wedged, with an unready batch */
+ gem_sync(fd, hang->handle); /* wedged, with an unready batch */
+ igt_assert(!gem_bo_busy(fd, hang->handle));
+ igt_assert(gem_bo_busy(fd, obj.handle));
sw_sync_timeline_inc(timeline, 1); /* only now submit our batches */
igt_assert_eq(__gem_wait(fd, obj.handle, -1), 0);
igt_assert_eq(sync_fence_status(fence), -EIO);
close(fence);
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
close(timeline);
@@ -384,15 +398,16 @@ static void test_inflight_internal(int fd)
uint32_t bbe = MI_BATCH_BUFFER_END;
unsigned engine, nfence = 0;
int fences[16];
- igt_hang_t hang;
+ igt_spin_t *hang;
+ igt_require_gem(fd);
igt_require(gem_has_exec_fence(fd));
igt_require(i915_reset_control(false));
- hang = igt_hang_ring(fd, I915_EXEC_DEFAULT);
+ hang = __igt_spin_batch_new(fd, 0, 0, 0);
memset(obj, 0, sizeof(obj));
- obj[0].handle = hang.handle;
+ obj[0].handle = hang->handle;
obj[0].flags = EXEC_OBJECT_WRITE;
obj[1].handle = gem_create(fd, 4096);
gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
@@ -410,14 +425,13 @@ static void test_inflight_internal(int fd)
nfence++;
}
- igt_post_hang_ring(fd, hang); /* wedged, with an unready batch */
-
igt_assert_eq(__gem_wait(fd, obj[1].handle, -1), 0);
while (nfence--) {
igt_assert_eq(sync_fence_status(fences[nfence]), -EIO);
close(fences[nfence]);
}
+ igt_spin_batch_free(fd, hang);
igt_assert(i915_reset_control(true));
trigger_reset(fd);
}
--
2.16.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 11/16] igt/gem_eio: Exercise set-wedging against request submission
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Build up a large stockpile of requests, ~500,000, and feed them into the
system at 20KHz whilst simultaneously triggering set-wedged in order to
try and race i915_gem_set_wedged() against the engine->submit_request()
callback.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_eio.c | 196 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 196 insertions(+)
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index 11776306..b003c344 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -34,12 +34,14 @@
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
+#include <signal.h>
#include <sys/ioctl.h>
#include <drm.h>
#include "igt.h"
#include "igt_sysfs.h"
+#include "igt_vgem.h"
#include "sw_sync.h"
IGT_TEST_DESCRIPTION("Test that specific ioctls report a wedged GPU (EIO).");
@@ -436,6 +438,194 @@ static void test_inflight_internal(int fd)
trigger_reset(fd);
}
+struct cork {
+ int device;
+ uint32_t handle;
+ uint32_t fence;
+};
+
+static void plug(int fd, struct cork *c)
+{
+ struct vgem_bo bo;
+ int dmabuf;
+
+ c->device = drm_open_driver(DRIVER_VGEM);
+
+ bo.width = bo.height = 1;
+ bo.bpp = 4;
+ vgem_create(c->device, &bo);
+ c->fence = vgem_fence_attach(c->device, &bo, VGEM_FENCE_WRITE);
+
+ dmabuf = prime_handle_to_fd(c->device, bo.handle);
+ c->handle = prime_fd_to_handle(fd, dmabuf);
+ close(dmabuf);
+}
+
+static void unplug(struct cork *c)
+{
+ vgem_fence_signal(c->device, c->fence);
+ close(c->device);
+}
+
+static void alarm_handler(int sig)
+{
+}
+
+static int __execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+ int err = 0;
+ if (ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf))
+ err = -errno;
+ return err;
+}
+
+static unsigned int measure_ring_size(int fd, unsigned int ring)
+{
+ struct sigaction sa = { .sa_handler = alarm_handler };
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ unsigned int count, last;
+ struct itimerval itv;
+ struct cork c;
+
+ memset(obj, 0, sizeof(obj));
+ obj[1].handle = gem_create(fd, 4096);
+ gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj + 1);
+ execbuf.buffer_count = 1;
+ execbuf.flags = ring;
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, obj[1].handle);
+
+ plug(fd, &c);
+ obj[0].handle = c.handle;
+
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = 2;
+ execbuf.rsvd1 = gem_context_create(fd);
+
+ sigaction(SIGALRM, &sa, NULL);
+ itv.it_interval.tv_sec = 0;
+ itv.it_interval.tv_usec = 100;
+ itv.it_value.tv_sec = 0;
+ itv.it_value.tv_usec = 1000;
+ setitimer(ITIMER_REAL, &itv, NULL);
+
+ last = -1;
+ count = 0;
+ do {
+ if (__execbuf(fd, &execbuf) == 0) {
+ count++;
+ continue;
+ }
+
+ if (last == count)
+ break;
+
+ last = count;
+ } while (1);
+
+ memset(&itv, 0, sizeof(itv));
+ setitimer(ITIMER_REAL, &itv, NULL);
+
+ unplug(&c);
+ gem_close(fd, obj[1].handle);
+ gem_context_destroy(fd, execbuf.rsvd1);
+
+ return count;
+}
+
+static void notify(union sigval arg)
+{
+ int timeline = arg.sival_int;
+
+ sw_sync_timeline_inc(timeline, 1); /* only now submit our batches */
+}
+
+static void test_set_wedged(int fd)
+{
+#define NCTX 4096
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ const int ring_size = measure_ring_size(fd, 0) - 1;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 obj;
+ struct itimerspec its;
+ struct sigevent sev;
+ uint32_t *contexts;
+ timer_t timer;
+ int timeline;
+ int syncpt;
+
+ contexts = calloc(NCTX, sizeof(*contexts));
+ igt_assert(contexts);
+
+ for (int n = 0; n < NCTX; n++)
+ contexts[n] = gem_context_create(fd);
+
+ timeline = sw_sync_timeline_create();
+
+ memset(&obj, 0, sizeof(obj));
+ obj.handle = gem_create(fd, 4096);
+ gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&obj);
+ execbuf.buffer_count = 1;
+ execbuf.flags = I915_EXEC_FENCE_IN;
+
+ /* Build up a large orderly queue of requests */
+ syncpt = 1;
+ for (int n = 0; n < NCTX; n++) {
+ execbuf.rsvd1 = contexts[n];
+ for (int m = 0; m < ring_size; m++) {
+ execbuf.rsvd2 =
+ sw_sync_timeline_create_fence(timeline, syncpt);
+ gem_execbuf(fd, &execbuf);
+ close(execbuf.rsvd2);
+
+ syncpt++;
+ }
+ }
+ igt_debug("Queued %d requests\n", syncpt);
+
+ igt_require(i915_reset_control(false));
+
+ /* Feed each request in at 20KHz */
+ memset(&sev, 0, sizeof(sev));
+ sev.sigev_notify = SIGEV_THREAD;
+ sev.sigev_value.sival_int = timeline;
+ sev.sigev_notify_function = notify;
+ igt_assert(timer_create(CLOCK_MONOTONIC, &sev, &timer) == 0);
+
+ memset(&its, 0, sizeof(its));
+ its.it_value.tv_sec = 0;
+ its.it_value.tv_nsec = 20000;
+ its.it_interval.tv_sec = 0;
+ its.it_interval.tv_nsec = 5000;
+ igt_assert(timer_settime(timer, 0, &its, NULL) == 0);
+
+ igt_debug("Triggering wedge\n");
+ wedgeme(fd);
+
+ igt_debug("Cleaning up\n");
+ timer_delete(timer);
+ close(timeline);
+
+ for (int n = 0; n < NCTX; n++)
+ gem_context_destroy(fd, contexts[n]);
+ free(contexts);
+
+ gem_sync(fd, obj.handle);
+ gem_close(fd, obj.handle);
+
+ igt_assert(i915_reset_control(true));
+ trigger_reset(fd);
+#undef NCTX
+}
+
static int fd = -1;
static void
@@ -492,4 +682,10 @@ igt_main
igt_subtest("in-flight-suspend")
test_inflight_suspend(fd);
+
+ igt_subtest("set-wedged-racing") {
+ igt_skip_on(gem_has_execlists(fd));
+ igt_require_sw_sync();
+ test_set_wedged(fd);
+ }
}
--
2.16.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH igt 11/16] igt/gem_eio: Exercise set-wedging against request submission
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Build up a large stockpile of requests, ~500,000, and feed them into the
system at 20KHz whilst simultaneously triggering set-wedged in order to
try and race i915_gem_set_wedged() against the engine->submit_request()
callback.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_eio.c | 196 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 196 insertions(+)
diff --git a/tests/gem_eio.c b/tests/gem_eio.c
index 11776306..b003c344 100644
--- a/tests/gem_eio.c
+++ b/tests/gem_eio.c
@@ -34,12 +34,14 @@
#include <fcntl.h>
#include <inttypes.h>
#include <errno.h>
+#include <signal.h>
#include <sys/ioctl.h>
#include <drm.h>
#include "igt.h"
#include "igt_sysfs.h"
+#include "igt_vgem.h"
#include "sw_sync.h"
IGT_TEST_DESCRIPTION("Test that specific ioctls report a wedged GPU (EIO).");
@@ -436,6 +438,194 @@ static void test_inflight_internal(int fd)
trigger_reset(fd);
}
+struct cork {
+ int device;
+ uint32_t handle;
+ uint32_t fence;
+};
+
+static void plug(int fd, struct cork *c)
+{
+ struct vgem_bo bo;
+ int dmabuf;
+
+ c->device = drm_open_driver(DRIVER_VGEM);
+
+ bo.width = bo.height = 1;
+ bo.bpp = 4;
+ vgem_create(c->device, &bo);
+ c->fence = vgem_fence_attach(c->device, &bo, VGEM_FENCE_WRITE);
+
+ dmabuf = prime_handle_to_fd(c->device, bo.handle);
+ c->handle = prime_fd_to_handle(fd, dmabuf);
+ close(dmabuf);
+}
+
+static void unplug(struct cork *c)
+{
+ vgem_fence_signal(c->device, c->fence);
+ close(c->device);
+}
+
+static void alarm_handler(int sig)
+{
+}
+
+static int __execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
+{
+ int err = 0;
+ if (ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, execbuf))
+ err = -errno;
+ return err;
+}
+
+static unsigned int measure_ring_size(int fd, unsigned int ring)
+{
+ struct sigaction sa = { .sa_handler = alarm_handler };
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ unsigned int count, last;
+ struct itimerval itv;
+ struct cork c;
+
+ memset(obj, 0, sizeof(obj));
+ obj[1].handle = gem_create(fd, 4096);
+ gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj + 1);
+ execbuf.buffer_count = 1;
+ execbuf.flags = ring;
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, obj[1].handle);
+
+ plug(fd, &c);
+ obj[0].handle = c.handle;
+
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = 2;
+ execbuf.rsvd1 = gem_context_create(fd);
+
+ sigaction(SIGALRM, &sa, NULL);
+ itv.it_interval.tv_sec = 0;
+ itv.it_interval.tv_usec = 100;
+ itv.it_value.tv_sec = 0;
+ itv.it_value.tv_usec = 1000;
+ setitimer(ITIMER_REAL, &itv, NULL);
+
+ last = -1;
+ count = 0;
+ do {
+ if (__execbuf(fd, &execbuf) == 0) {
+ count++;
+ continue;
+ }
+
+ if (last == count)
+ break;
+
+ last = count;
+ } while (1);
+
+ memset(&itv, 0, sizeof(itv));
+ setitimer(ITIMER_REAL, &itv, NULL);
+
+ unplug(&c);
+ gem_close(fd, obj[1].handle);
+ gem_context_destroy(fd, execbuf.rsvd1);
+
+ return count;
+}
+
+static void notify(union sigval arg)
+{
+ int timeline = arg.sival_int;
+
+ sw_sync_timeline_inc(timeline, 1); /* only now submit our batches */
+}
+
+static void test_set_wedged(int fd)
+{
+#define NCTX 4096
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ const int ring_size = measure_ring_size(fd, 0) - 1;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 obj;
+ struct itimerspec its;
+ struct sigevent sev;
+ uint32_t *contexts;
+ timer_t timer;
+ int timeline;
+ int syncpt;
+
+ contexts = calloc(NCTX, sizeof(*contexts));
+ igt_assert(contexts);
+
+ for (int n = 0; n < NCTX; n++)
+ contexts[n] = gem_context_create(fd);
+
+ timeline = sw_sync_timeline_create();
+
+ memset(&obj, 0, sizeof(obj));
+ obj.handle = gem_create(fd, 4096);
+ gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&obj);
+ execbuf.buffer_count = 1;
+ execbuf.flags = I915_EXEC_FENCE_IN;
+
+ /* Build up a large orderly queue of requests */
+ syncpt = 1;
+ for (int n = 0; n < NCTX; n++) {
+ execbuf.rsvd1 = contexts[n];
+ for (int m = 0; m < ring_size; m++) {
+ execbuf.rsvd2 =
+ sw_sync_timeline_create_fence(timeline, syncpt);
+ gem_execbuf(fd, &execbuf);
+ close(execbuf.rsvd2);
+
+ syncpt++;
+ }
+ }
+ igt_debug("Queued %d requests\n", syncpt);
+
+ igt_require(i915_reset_control(false));
+
+ /* Feed each request in at 20KHz */
+ memset(&sev, 0, sizeof(sev));
+ sev.sigev_notify = SIGEV_THREAD;
+ sev.sigev_value.sival_int = timeline;
+ sev.sigev_notify_function = notify;
+ igt_assert(timer_create(CLOCK_MONOTONIC, &sev, &timer) == 0);
+
+ memset(&its, 0, sizeof(its));
+ its.it_value.tv_sec = 0;
+ its.it_value.tv_nsec = 20000;
+ its.it_interval.tv_sec = 0;
+ its.it_interval.tv_nsec = 5000;
+ igt_assert(timer_settime(timer, 0, &its, NULL) == 0);
+
+ igt_debug("Triggering wedge\n");
+ wedgeme(fd);
+
+ igt_debug("Cleaning up\n");
+ timer_delete(timer);
+ close(timeline);
+
+ for (int n = 0; n < NCTX; n++)
+ gem_context_destroy(fd, contexts[n]);
+ free(contexts);
+
+ gem_sync(fd, obj.handle);
+ gem_close(fd, obj.handle);
+
+ igt_assert(i915_reset_control(true));
+ trigger_reset(fd);
+#undef NCTX
+}
+
static int fd = -1;
static void
@@ -492,4 +682,10 @@ igt_main
igt_subtest("in-flight-suspend")
test_inflight_suspend(fd);
+
+ igt_subtest("set-wedged-racing") {
+ igt_skip_on(gem_has_execlists(fd));
+ igt_require_sw_sync();
+ test_set_wedged(fd);
+ }
}
--
2.16.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 12/16] igt/gem_ctx_isolation: Check isolation of registers between contexts
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
A new context assumes that all of its registers are in the default state
when it is created. What may happen is that a register written by one
context may leak into the second, causing mass confusion.
v2: Extend back to Sandybridge (etc)
v3: Check context preserves registers across suspend/hibernate and resets.
v4: Complete the remapping onto the new class:instance
v5: Not like that, like this, try again to use class:instance
v6: Prepare for retrospective gen4 contexts!
v7: Repaint register set name to nonpriv, as this is what bspec calls the
registers that are writable by userspace.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/Makefile.sources | 1 +
tests/gem_ctx_isolation.c | 677 ++++++++++++++++++++++++++++++++++++++++++++++
tests/gem_exec_fence.c | 2 +-
3 files changed, 679 insertions(+), 1 deletion(-)
create mode 100644 tests/gem_ctx_isolation.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 870c9093..b277de2f 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -57,6 +57,7 @@ TESTS_progs = \
gem_ctx_bad_exec \
gem_ctx_create \
gem_ctx_exec \
+ gem_ctx_isolation \
gem_ctx_param \
gem_ctx_switch \
gem_ctx_thrash \
diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c
new file mode 100644
index 00000000..8b69cd33
--- /dev/null
+++ b/tests/gem_ctx_isolation.c
@@ -0,0 +1,677 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "igt_dummyload.h"
+
+#define MAX_REG 0x40000
+#define NUM_REGS (MAX_REG / sizeof(uint32_t))
+
+#define PAGE_ALIGN(x) ALIGN(x, 4096)
+
+#define DIRTY1 0x1
+#define DIRTY2 0x2
+#define RESET 0x4
+
+#define BIT(x) (1ul << (x))
+#define ENGINE(x, y) BIT(4*(x) + (y))
+
+enum {
+ RCS0 = ENGINE(I915_ENGINE_CLASS_RENDER, 0),
+ BCS0 = ENGINE(I915_ENGINE_CLASS_COPY, 0),
+ VCS0 = ENGINE(I915_ENGINE_CLASS_VIDEO, 0),
+ VCS1 = ENGINE(I915_ENGINE_CLASS_VIDEO, 1),
+ VECS0 = ENGINE(I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
+};
+
+#define ALL ~0u
+#define GEN_RANGE(x, y) ((ALL >> (32 - (y - x + 1))) << x)
+#define GEN4 (ALL << 4)
+#define GEN5 (ALL << 5)
+#define GEN6 (ALL << 6)
+#define GEN7 (ALL << 7)
+#define GEN8 (ALL << 8)
+#define GEN9 (ALL << 9)
+
+#define NOCTX 0
+
+#define LAST_KNOWN_GEN 10
+
+static const struct named_register {
+ const char *name;
+ unsigned int gen_mask;
+ unsigned int engine_mask;
+ uint32_t offset;
+ uint32_t count;
+} nonpriv_registers[] = {
+ { "NOPID", NOCTX, RCS0, 0x2094 },
+ { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
+ { "INSTPM", GEN9, RCS0, 0x20c0 },
+ { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
+ { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
+ { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
+ { "HS_INVOCATION_COUNT", GEN4, RCS0, 0x2300, 2 },
+ { "DS_INVOCATION_COUNT", GEN4, RCS0, 0x2308, 2 },
+ { "GS_INVOCATION_COUNT", GEN4, RCS0, 0x2328, 2 },
+ { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
+ { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
+ { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
+ { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
+ { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
+ { "GPUGPU_DISPATCHDIMZ", GEN8, RCS0, 0x2508 },
+ { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
+ { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
+ { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
+ { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
+ { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
+ { "3DPRIM_INSTANCE_COUNT", GEN6, RCS0, 0x2438 },
+ { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
+ { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
+ { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
+ { "BB_OFFSET", GEN8, RCS0, 0x2158 },
+ { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
+ { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
+ { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
+ { "OACTXID", GEN8, RCS0, 0x2364 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
+ { "GT_MODE", GEN8, RCS0, 0x7008 },
+ { "L3_Config", GEN7, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "TD_CTL2", GEN8, RCS0, 0xe404 },
+ { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
+ { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
+ { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
+ { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
+ { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
+ { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
+ { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
+ { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
+ { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
+ { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
+ { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
+
+ /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
+ { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
+ { "L3SQREG1", GEN8, RCS0, 0xb010 },
+
+ { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
+ { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+
+ { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
+ { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
+
+ { "VCS1_GPR", GEN9, VCS1, 0x1c600, 32 },
+ { "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
+
+ { "VECS_GPR", GEN9, VECS0, 0x1a600, 32 },
+
+ {}
+}, ignore_registers[] = {
+ { "RCS timestamp", GEN6, ~0u, 0x2358 },
+ { "VCS0 timestamp", GEN7, ~0u, 0x12358 },
+ { "VCS1 timestamp", GEN7, ~0u, 0x1c358 },
+ { "BCS timestamp", GEN7, ~0u, 0x22358 },
+ { "VECS timestamp", GEN8, ~0u, 0x1a358 },
+ {}
+};
+
+static const char *register_name(uint32_t offset, char *buf, size_t len)
+{
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ unsigned int width = r->count ? 4*r->count : 4;
+ if (offset >= r->offset && offset < r->offset + width) {
+ if (r->count <= 1)
+ return r->name;
+
+ snprintf(buf, len, "%s[%d]",
+ r->name, (offset - r->offset)/4);
+ return buf;
+ }
+ }
+
+ return "unknown";
+}
+
+static bool ignore_register(uint32_t offset)
+{
+ for (const struct named_register *r = ignore_registers; r->name; r++) {
+ unsigned int width = r->count ? 4*r->count : 4;
+ if (offset >= r->offset && offset < r->offset + width)
+ return true;
+ }
+
+ return false;
+}
+
+static uint32_t read_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+ const unsigned int gen_bit = 1 << gen;
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const bool r64b = gen >= 8;
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_relocation_entry *reloc;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ unsigned int regs_size, batch_size, n;
+ uint32_t *batch, *b;
+
+ reloc = calloc(NUM_REGS, sizeof(*reloc));
+ igt_assert(reloc);
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ batch_size = NUM_REGS * 4 * sizeof(uint32_t) + 4;
+ batch_size = PAGE_ALIGN(batch_size);
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = gem_create(fd, regs_size);
+ obj[1].handle = gem_create(fd, batch_size);
+ obj[1].relocs_ptr = to_user_pointer(reloc);
+
+ b = batch = gem_mmap__cpu(fd, obj[1].handle, 0, batch_size, PROT_WRITE);
+ gem_set_domain(fd, obj[1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ n = 0;
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ *b++ = 0x24 << 23 | (1 + r64b); /* SRM */
+ *b++ = offset;
+ reloc[n].target_handle = obj[0].handle;
+ reloc[n].presumed_offset = 0;
+ reloc[n].offset = (b - batch) * sizeof(*b);
+ reloc[n].delta = offset;
+ reloc[n].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[n].write_domain = I915_GEM_DOMAIN_RENDER;
+ *b++ = offset;
+ if (r64b)
+ *b++ = 0;
+ n++;
+ }
+ }
+
+ obj[1].relocation_count = n;
+ *b++ = MI_BATCH_BUFFER_END;
+ munmap(batch, batch_size);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = 2;
+ execbuf.flags =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ execbuf.rsvd1 = ctx;
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[1].handle);
+ free(reloc);
+
+ return obj[0].handle;
+}
+
+static void write_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ struct drm_i915_gem_exec_object2 obj;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ unsigned int batch_size;
+ uint32_t *batch, *b;
+
+ batch_size = NUM_REGS * 3 * sizeof(uint32_t) + 4;
+ batch_size = PAGE_ALIGN(batch_size);
+
+ memset(&obj, 0, sizeof(obj));
+ obj.handle = gem_create(fd, batch_size);
+
+ b = batch = gem_mmap__cpu(fd, obj.handle, 0, batch_size, PROT_WRITE);
+ gem_set_domain(fd, obj.handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ *b++ = 0x22 << 23 | 1; /* LRI */
+ *b++ = offset;
+ *b++ = value;
+ }
+ }
+ *b++ = MI_BATCH_BUFFER_END;
+ munmap(batch, batch_size);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&obj);
+ execbuf.buffer_count = 1;
+ execbuf.flags =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ execbuf.rsvd1 = ctx;
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj.handle);
+}
+
+static void restore_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags,
+ uint32_t regs)
+{
+ const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+ const unsigned int gen_bit = 1 << gen;
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const bool r64b = gen >= 8;
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_relocation_entry *reloc;
+ unsigned int batch_size, n;
+ uint32_t *batch, *b;
+
+ if (gen < 7) /* no LRM */
+ return;
+
+ reloc = calloc(NUM_REGS, sizeof(*reloc));
+ igt_assert(reloc);
+
+ batch_size = NUM_REGS * 3 * sizeof(uint32_t) + 4;
+ batch_size = PAGE_ALIGN(batch_size);
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = regs;
+ obj[1].handle = gem_create(fd, batch_size);
+ obj[1].relocs_ptr = to_user_pointer(reloc);
+
+ b = batch = gem_mmap__cpu(fd, obj[1].handle, 0, batch_size, PROT_WRITE);
+ gem_set_domain(fd, obj[1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ n = 0;
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ *b++ = 0x29 << 23 | (1 + r64b); /* LRM */
+ *b++ = offset;
+ reloc[n].target_handle = obj[0].handle;
+ reloc[n].presumed_offset = 0;
+ reloc[n].offset = (b - batch) * sizeof(*b);
+ reloc[n].delta = offset;
+ reloc[n].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[n].write_domain = 0;
+ *b++ = offset;
+ if (gen >= 9)
+ *b++ = 0;
+ n++;
+ }
+ }
+ obj[1].relocation_count = n;
+ *b++ = MI_BATCH_BUFFER_END;
+ munmap(batch, batch_size);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = 2;
+ execbuf.flags =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ execbuf.rsvd1 = ctx;
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[1].handle);
+}
+
+__attribute__((unused))
+static void dump_regs(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int regs)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ const unsigned int gen_bit = 1 << gen;
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *out;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ out = gem_mmap__cpu(fd, regs, 0, regs_size, PROT_READ);
+ gem_set_domain(fd, regs, I915_GEM_DOMAIN_CPU, 0);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+
+ if (r->count <= 1) {
+ igt_debug("0x%04x (%s): 0x%08x\n",
+ r->offset, r->name, out[r->offset/4]);
+ } else {
+ for (unsigned x = 0; x < r->count; x++)
+ igt_debug("0x%04x (%s[%d]): 0x%08x\n",
+ r->offset+4*x, r->name, x,
+ out[r->offset/4 + x]);
+ }
+ }
+ munmap(out, regs_size);
+}
+
+static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
+{
+ unsigned int num_errors;
+ unsigned int regs_size;
+ uint32_t *a, *b;
+ char buf[80];
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ a = gem_mmap__cpu(fd, A, 0, regs_size, PROT_READ);
+ gem_set_domain(fd, A, I915_GEM_DOMAIN_CPU, 0);
+
+ b = gem_mmap__cpu(fd, B, 0, regs_size, PROT_READ);
+ gem_set_domain(fd, B, I915_GEM_DOMAIN_CPU, 0);
+
+ num_errors = 0;
+ for (unsigned int n = 0; n < NUM_REGS; n++) {
+ uint32_t offset = n * sizeof(uint32_t);
+ if (a[n] != b[n] && !ignore_register(offset)) {
+ igt_warn("Register 0x%04x (%s): A=%08x B=%08x\n",
+ offset,
+ register_name(offset, buf, sizeof(buf)),
+ a[n], b[n]);
+ num_errors++;
+ }
+ }
+ munmap(b, regs_size);
+ munmap(a, regs_size);
+
+ igt_assert_f(num_errors == 0,
+ "%d registers mistached between %s.\n",
+ num_errors, who);
+}
+
+static void isolation(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ unsigned int engine = gem_class_instance_to_eb_flags(fd,
+ e->class,
+ e->instance);
+ unsigned int num_values =
+ flags & (DIRTY1 | DIRTY2) ? ARRAY_SIZE(values) : 1;
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx[2], regs[2], tmp;
+
+ ctx[0] = gem_context_create(fd);
+ regs[0] = read_regs(fd, ctx[0], e, flags);
+
+ spin = igt_spin_batch_new(fd, ctx[0], engine, 0);
+
+ if (flags & DIRTY1) {
+ igt_debug("%s[%d]: Setting all registers of ctx 0 to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx[0], e, flags, values[v]);
+ }
+
+ /*
+ * We create and execute a new context, whilst the HW is
+ * occupied with the previous context (we should switch from
+ * the old to the new proto-context without idling, which could
+ * then load the powercontext). If all goes well, we only see
+ * the default values from this context, but if goes badly we
+ * see the corruption from the previous context instead!
+ */
+ ctx[1] = gem_context_create(fd);
+ regs[1] = read_regs(fd, ctx[1], e, flags);
+
+ if (flags & DIRTY2) {
+ igt_debug("%s[%d]: Setting all registers of ctx 1 to 0x%08x\n",
+ __func__, v, ~values[v]);
+ write_regs(fd, ctx[1], e, flags, ~values[v]);
+ }
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ tmp = read_regs(fd, ctx[0], e, flags);
+ restore_regs(fd, ctx[0], e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ if (!(flags & DIRTY1))
+ compare_regs(fd, regs[0], tmp, "two reads of the same ctx");
+ compare_regs(fd, regs[0], regs[1], "two virgin contexts");
+
+ for (int n = 0; n < ARRAY_SIZE(ctx); n++) {
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx[n]);
+ }
+ gem_close(fd, tmp);
+ }
+}
+
+#define NOSLEEP (0 << 8)
+#define S3_DEVICES (1 << 8)
+#define S3 (2 << 8)
+#define S4_DEVICES (3 << 8)
+#define S4 (4 << 8)
+#define SLEEP_MASK (0xf << 8)
+
+static void preservation(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ const unsigned int num_values = ARRAY_SIZE(values);
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ uint32_t ctx[num_values +1 ];
+ uint32_t regs[num_values + 1][2];
+ igt_spin_t *spin;
+
+ gem_quiescent_gpu(fd);
+
+ ctx[num_values] = gem_context_create(fd);
+ spin = igt_spin_batch_new(fd, ctx[num_values], engine, 0);
+ regs[num_values][0] = read_regs(fd, ctx[num_values], e, flags);
+ for (int v = 0; v < num_values; v++) {
+ ctx[v] = gem_context_create(fd);
+ write_regs(fd, ctx[v], e, flags, values[v]);
+
+ regs[v][0] = read_regs(fd, ctx[v], e, flags);
+
+ }
+ gem_close(fd, read_regs(fd, ctx[num_values], e, flags));
+ igt_spin_batch_free(fd, spin);
+
+ if (flags & RESET)
+ igt_force_gpu_reset(fd);
+
+ switch (flags & SLEEP_MASK) {
+ case NOSLEEP:
+ break;
+
+ case S3_DEVICES:
+ igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
+ SUSPEND_TEST_DEVICES);
+ break;
+
+ case S3:
+ igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
+ SUSPEND_TEST_NONE);
+ break;
+
+ case S4_DEVICES:
+ igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
+ SUSPEND_TEST_DEVICES);
+ break;
+
+ case S4:
+ igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
+ SUSPEND_TEST_NONE);
+ break;
+ }
+
+ spin = igt_spin_batch_new(fd, ctx[num_values], engine, 0);
+ for (int v = 0; v < num_values; v++)
+ regs[v][1] = read_regs(fd, ctx[v], e, flags);
+ regs[num_values][1] = read_regs(fd, ctx[num_values], e, flags);
+ igt_spin_batch_free(fd, spin);
+
+ for (int v = 0; v < num_values; v++) {
+ char buf[80];
+
+ snprintf(buf, sizeof(buf), "dirty %x context\n", values[v]);
+ compare_regs(fd, regs[v][0], regs[v][1], buf);
+
+ gem_close(fd, regs[v][0]);
+ gem_close(fd, regs[v][1]);
+ gem_context_destroy(fd, ctx[v]);
+ }
+ compare_regs(fd, regs[num_values][0], regs[num_values][1], "clean");
+ gem_context_destroy(fd, ctx[num_values]);
+}
+
+static unsigned int __has_context_isolation(int fd)
+{
+ struct drm_i915_getparam gp;
+ int value = 0;
+
+ memset(&gp, 0, sizeof(gp));
+ gp.param = 50; /* I915_PARAM_HAS_CONTEXT_ISOLATION */
+ gp.value = &value;
+
+ igt_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ errno = 0;
+
+ return value;
+}
+
+igt_main
+{
+ unsigned int has_context_isolation = 0;
+ int fd = -1;
+
+ igt_fixture {
+ int gen;
+
+ fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(fd);
+
+ gem_context_destroy(fd, gem_context_create(fd));
+ has_context_isolation = __has_context_isolation(fd);
+ igt_require(has_context_isolation);
+
+ gen = intel_gen(intel_get_drm_devid(fd));
+ //igt_ci_fail_on(gen > LAST_KNOWN_GEN);
+ igt_skip_on(gen > LAST_KNOWN_GEN);
+ }
+
+ for (const struct intel_execution_engine2 *e = intel_execution_engines2;
+ e->name; e++) {
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(has_context_isolation & (1 << e->class));
+ gem_require_engine(fd, e->class, e->instance);
+ igt_fork_hang_detector(fd);
+ }
+
+ igt_subtest_f("%s-clean", e->name)
+ isolation(fd, e, 0);
+ igt_subtest_f("%s-dirty-create", e->name)
+ isolation(fd, e, DIRTY1);
+ igt_subtest_f("%s-dirty-switch", e->name)
+ isolation(fd, e, DIRTY2);
+
+ igt_subtest_f("%s-none", e->name)
+ preservation(fd, e, 0);
+ igt_subtest_f("%s-S3", e->name)
+ preservation(fd, e, S3);
+ igt_subtest_f("%s-S4", e->name)
+ preservation(fd, e, S4);
+
+ igt_fixture {
+ igt_stop_hang_detector();
+ }
+
+ igt_subtest_f("%s-reset", e->name) {
+ igt_hang_t hang = igt_allow_hang(fd, 0, 0);
+ preservation(fd, e, RESET);
+ igt_disallow_hang(fd, hang);
+ }
+ }
+ }
+}
diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
index 8dd758aa..312505d6 100644
--- a/tests/gem_exec_fence.c
+++ b/tests/gem_exec_fence.c
@@ -793,7 +793,7 @@ static bool has_submit_fence(int fd)
int value = 0;
memset(&gp, 0, sizeof(gp));
- gp.param = 50; /* I915_PARAM_HAS_EXEC_SUBMIT_FENCE */
+ gp.param = 0xdeadbeef ^ 51; /* I915_PARAM_HAS_EXEC_SUBMIT_FENCE */
gp.value = &value;
ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
--
2.16.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 12/16] igt/gem_ctx_isolation: Check isolation of registers between contexts
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
A new context assumes that all of its registers are in the default state
when it is created. What may happen is that a register written by one
context may leak into the second, causing mass confusion.
v2: Extend back to Sandybridge (etc)
v3: Check context preserves registers across suspend/hibernate and resets.
v4: Complete the remapping onto the new class:instance
v5: Not like that, like this, try again to use class:instance
v6: Prepare for retrospective gen4 contexts!
v7: Repaint register set name to nonpriv, as this is what bspec calls the
registers that are writable by userspace.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
tests/Makefile.sources | 1 +
tests/gem_ctx_isolation.c | 677 ++++++++++++++++++++++++++++++++++++++++++++++
tests/gem_exec_fence.c | 2 +-
3 files changed, 679 insertions(+), 1 deletion(-)
create mode 100644 tests/gem_ctx_isolation.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 870c9093..b277de2f 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -57,6 +57,7 @@ TESTS_progs = \
gem_ctx_bad_exec \
gem_ctx_create \
gem_ctx_exec \
+ gem_ctx_isolation \
gem_ctx_param \
gem_ctx_switch \
gem_ctx_thrash \
diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c
new file mode 100644
index 00000000..8b69cd33
--- /dev/null
+++ b/tests/gem_ctx_isolation.c
@@ -0,0 +1,677 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include "igt_dummyload.h"
+
+#define MAX_REG 0x40000
+#define NUM_REGS (MAX_REG / sizeof(uint32_t))
+
+#define PAGE_ALIGN(x) ALIGN(x, 4096)
+
+#define DIRTY1 0x1
+#define DIRTY2 0x2
+#define RESET 0x4
+
+#define BIT(x) (1ul << (x))
+#define ENGINE(x, y) BIT(4*(x) + (y))
+
+enum {
+ RCS0 = ENGINE(I915_ENGINE_CLASS_RENDER, 0),
+ BCS0 = ENGINE(I915_ENGINE_CLASS_COPY, 0),
+ VCS0 = ENGINE(I915_ENGINE_CLASS_VIDEO, 0),
+ VCS1 = ENGINE(I915_ENGINE_CLASS_VIDEO, 1),
+ VECS0 = ENGINE(I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
+};
+
+#define ALL ~0u
+#define GEN_RANGE(x, y) ((ALL >> (32 - (y - x + 1))) << x)
+#define GEN4 (ALL << 4)
+#define GEN5 (ALL << 5)
+#define GEN6 (ALL << 6)
+#define GEN7 (ALL << 7)
+#define GEN8 (ALL << 8)
+#define GEN9 (ALL << 9)
+
+#define NOCTX 0
+
+#define LAST_KNOWN_GEN 10
+
+static const struct named_register {
+ const char *name;
+ unsigned int gen_mask;
+ unsigned int engine_mask;
+ uint32_t offset;
+ uint32_t count;
+} nonpriv_registers[] = {
+ { "NOPID", NOCTX, RCS0, 0x2094 },
+ { "MI_PREDICATE_RESULT_2", NOCTX, RCS0, 0x23bc },
+ { "INSTPM", GEN9, RCS0, 0x20c0 },
+ { "IA_VERTICES_COUNT", GEN4, RCS0, 0x2310, 2 },
+ { "IA_PRIMITIVES_COUNT", GEN4, RCS0, 0x2318, 2 },
+ { "VS_INVOCATION_COUNT", GEN4, RCS0, 0x2320, 2 },
+ { "HS_INVOCATION_COUNT", GEN4, RCS0, 0x2300, 2 },
+ { "DS_INVOCATION_COUNT", GEN4, RCS0, 0x2308, 2 },
+ { "GS_INVOCATION_COUNT", GEN4, RCS0, 0x2328, 2 },
+ { "GS_PRIMITIVES_COUNT", GEN4, RCS0, 0x2330, 2 },
+ { "CL_INVOCATION_COUNT", GEN4, RCS0, 0x2338, 2 },
+ { "CL_PRIMITIVES_COUNT", GEN4, RCS0, 0x2340, 2 },
+ { "PS_INVOCATION_COUNT_0", GEN4, RCS0, 0x22c8, 2 },
+ { "PS_DEPTH_COUNT_0", GEN4, RCS0, 0x22d8, 2 },
+ { "GPUGPU_DISPATCHDIMX", GEN8, RCS0, 0x2500 },
+ { "GPUGPU_DISPATCHDIMY", GEN8, RCS0, 0x2504 },
+ { "GPUGPU_DISPATCHDIMZ", GEN8, RCS0, 0x2508 },
+ { "MI_PREDICATE_SRC0", GEN8, RCS0, 0x2400, 2 },
+ { "MI_PREDICATE_SRC1", GEN8, RCS0, 0x2408, 2 },
+ { "MI_PREDICATE_DATA", GEN8, RCS0, 0x2410, 2 },
+ { "MI_PRED_RESULT", GEN8, RCS0, 0x2418 },
+ { "3DPRIM_END_OFFSET", GEN6, RCS0, 0x2420 },
+ { "3DPRIM_START_VERTEX", GEN6, RCS0, 0x2430 },
+ { "3DPRIM_VERTEX_COUNT", GEN6, RCS0, 0x2434 },
+ { "3DPRIM_INSTANCE_COUNT", GEN6, RCS0, 0x2438 },
+ { "3DPRIM_START_INSTANCE", GEN6, RCS0, 0x243c },
+ { "3DPRIM_BASE_VERTEX", GEN6, RCS0, 0x2440 },
+ { "GPGPU_THREADS_DISPATCHED", GEN8, RCS0, 0x2290, 2 },
+ { "PS_INVOCATION_COUNT_1", GEN8, RCS0, 0x22f0, 2 },
+ { "PS_DEPTH_COUNT_1", GEN8, RCS0, 0x22f8, 2 },
+ { "BB_OFFSET", GEN8, RCS0, 0x2158 },
+ { "MI_PREDICATE_RESULT_1", GEN8, RCS0, 0x241c },
+ { "CS_GPR", GEN8, RCS0, 0x2600, 32 },
+ { "OA_CTX_CONTROL", GEN8, RCS0, 0x2360 },
+ { "OACTXID", GEN8, RCS0, 0x2364 },
+ { "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2 },
+ { "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
+ { "Cache_Mode_0", GEN7, RCS0, 0x7000 },
+ { "Cache_Mode_1", GEN7, RCS0, 0x7004 },
+ { "GT_MODE", GEN8, RCS0, 0x7008 },
+ { "L3_Config", GEN7, RCS0, 0x7034 },
+ { "TD_CTL", GEN8, RCS0, 0xe400 },
+ { "TD_CTL2", GEN8, RCS0, 0xe404 },
+ { "SO_NUM_PRIMS_WRITEN0", GEN6, RCS0, 0x5200, 2 },
+ { "SO_NUM_PRIMS_WRITEN1", GEN6, RCS0, 0x5208, 2 },
+ { "SO_NUM_PRIMS_WRITEN2", GEN6, RCS0, 0x5210, 2 },
+ { "SO_NUM_PRIMS_WRITEN3", GEN6, RCS0, 0x5218, 2 },
+ { "SO_PRIM_STORAGE_NEEDED0", GEN6, RCS0, 0x5240, 2 },
+ { "SO_PRIM_STORAGE_NEEDED1", GEN6, RCS0, 0x5248, 2 },
+ { "SO_PRIM_STORAGE_NEEDED2", GEN6, RCS0, 0x5250, 2 },
+ { "SO_PRIM_STORAGE_NEEDED3", GEN6, RCS0, 0x5258, 2 },
+ { "SO_WRITE_OFFSET0", GEN7, RCS0, 0x5280 },
+ { "SO_WRITE_OFFSET1", GEN7, RCS0, 0x5284 },
+ { "SO_WRITE_OFFSET2", GEN7, RCS0, 0x5288 },
+ { "SO_WRITE_OFFSET3", GEN7, RCS0, 0x528c },
+ { "OA_CONTROL", NOCTX, RCS0, 0x2b00 },
+ { "PERF_CNT_1", NOCTX, RCS0, 0x91b8, 2 },
+ { "PERF_CNT_2", NOCTX, RCS0, 0x91c0, 2 },
+
+ /* Privileged (enabled by w/a + FORCE_TO_NONPRIV) */
+ { "CTX_PREEMPT", NOCTX /* GEN_RANGE(9, 10) */, RCS0, 0x2248 },
+ { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x2580 },
+ { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS0, 0x7304 },
+ { "L3SQREG1", GEN8, RCS0, 0xb010 },
+
+ { "BCS_GPR", GEN9, BCS0, 0x22600, 32 },
+ { "BCS_SWCTRL", GEN8, BCS0, 0x22200 },
+
+ { "VCS0_GPR", GEN9, VCS0, 0x12600, 32 },
+ { "MFC_VDBOX1", NOCTX, VCS0, 0x12800, 64 },
+
+ { "VCS1_GPR", GEN9, VCS1, 0x1c600, 32 },
+ { "MFC_VDBOX2", NOCTX, VCS1, 0x1c800, 64 },
+
+ { "VECS_GPR", GEN9, VECS0, 0x1a600, 32 },
+
+ {}
+}, ignore_registers[] = {
+ { "RCS timestamp", GEN6, ~0u, 0x2358 },
+ { "VCS0 timestamp", GEN7, ~0u, 0x12358 },
+ { "VCS1 timestamp", GEN7, ~0u, 0x1c358 },
+ { "BCS timestamp", GEN7, ~0u, 0x22358 },
+ { "VECS timestamp", GEN8, ~0u, 0x1a358 },
+ {}
+};
+
+static const char *register_name(uint32_t offset, char *buf, size_t len)
+{
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ unsigned int width = r->count ? 4*r->count : 4;
+ if (offset >= r->offset && offset < r->offset + width) {
+ if (r->count <= 1)
+ return r->name;
+
+ snprintf(buf, len, "%s[%d]",
+ r->name, (offset - r->offset)/4);
+ return buf;
+ }
+ }
+
+ return "unknown";
+}
+
+static bool ignore_register(uint32_t offset)
+{
+ for (const struct named_register *r = ignore_registers; r->name; r++) {
+ unsigned int width = r->count ? 4*r->count : 4;
+ if (offset >= r->offset && offset < r->offset + width)
+ return true;
+ }
+
+ return false;
+}
+
+static uint32_t read_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+ const unsigned int gen_bit = 1 << gen;
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const bool r64b = gen >= 8;
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_relocation_entry *reloc;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ unsigned int regs_size, batch_size, n;
+ uint32_t *batch, *b;
+
+ reloc = calloc(NUM_REGS, sizeof(*reloc));
+ igt_assert(reloc);
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ batch_size = NUM_REGS * 4 * sizeof(uint32_t) + 4;
+ batch_size = PAGE_ALIGN(batch_size);
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = gem_create(fd, regs_size);
+ obj[1].handle = gem_create(fd, batch_size);
+ obj[1].relocs_ptr = to_user_pointer(reloc);
+
+ b = batch = gem_mmap__cpu(fd, obj[1].handle, 0, batch_size, PROT_WRITE);
+ gem_set_domain(fd, obj[1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ n = 0;
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ *b++ = 0x24 << 23 | (1 + r64b); /* SRM */
+ *b++ = offset;
+ reloc[n].target_handle = obj[0].handle;
+ reloc[n].presumed_offset = 0;
+ reloc[n].offset = (b - batch) * sizeof(*b);
+ reloc[n].delta = offset;
+ reloc[n].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[n].write_domain = I915_GEM_DOMAIN_RENDER;
+ *b++ = offset;
+ if (r64b)
+ *b++ = 0;
+ n++;
+ }
+ }
+
+ obj[1].relocation_count = n;
+ *b++ = MI_BATCH_BUFFER_END;
+ munmap(batch, batch_size);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = 2;
+ execbuf.flags =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ execbuf.rsvd1 = ctx;
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[1].handle);
+ free(reloc);
+
+ return obj[0].handle;
+}
+
+static void write_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags,
+ uint32_t value)
+{
+ const unsigned int gen_bit = 1 << intel_gen(intel_get_drm_devid(fd));
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ struct drm_i915_gem_exec_object2 obj;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ unsigned int batch_size;
+ uint32_t *batch, *b;
+
+ batch_size = NUM_REGS * 3 * sizeof(uint32_t) + 4;
+ batch_size = PAGE_ALIGN(batch_size);
+
+ memset(&obj, 0, sizeof(obj));
+ obj.handle = gem_create(fd, batch_size);
+
+ b = batch = gem_mmap__cpu(fd, obj.handle, 0, batch_size, PROT_WRITE);
+ gem_set_domain(fd, obj.handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ *b++ = 0x22 << 23 | 1; /* LRI */
+ *b++ = offset;
+ *b++ = value;
+ }
+ }
+ *b++ = MI_BATCH_BUFFER_END;
+ munmap(batch, batch_size);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&obj);
+ execbuf.buffer_count = 1;
+ execbuf.flags =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ execbuf.rsvd1 = ctx;
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj.handle);
+}
+
+static void restore_regs(int fd,
+ uint32_t ctx,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags,
+ uint32_t regs)
+{
+ const unsigned int gen = intel_gen(intel_get_drm_devid(fd));
+ const unsigned int gen_bit = 1 << gen;
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ const bool r64b = gen >= 8;
+ struct drm_i915_gem_exec_object2 obj[2];
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_relocation_entry *reloc;
+ unsigned int batch_size, n;
+ uint32_t *batch, *b;
+
+ if (gen < 7) /* no LRM */
+ return;
+
+ reloc = calloc(NUM_REGS, sizeof(*reloc));
+ igt_assert(reloc);
+
+ batch_size = NUM_REGS * 3 * sizeof(uint32_t) + 4;
+ batch_size = PAGE_ALIGN(batch_size);
+
+ memset(obj, 0, sizeof(obj));
+ obj[0].handle = regs;
+ obj[1].handle = gem_create(fd, batch_size);
+ obj[1].relocs_ptr = to_user_pointer(reloc);
+
+ b = batch = gem_mmap__cpu(fd, obj[1].handle, 0, batch_size, PROT_WRITE);
+ gem_set_domain(fd, obj[1].handle,
+ I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
+
+ n = 0;
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+
+ for (unsigned count = r->count ?: 1, offset = r->offset;
+ count--; offset += 4) {
+ *b++ = 0x29 << 23 | (1 + r64b); /* LRM */
+ *b++ = offset;
+ reloc[n].target_handle = obj[0].handle;
+ reloc[n].presumed_offset = 0;
+ reloc[n].offset = (b - batch) * sizeof(*b);
+ reloc[n].delta = offset;
+ reloc[n].read_domains = I915_GEM_DOMAIN_RENDER;
+ reloc[n].write_domain = 0;
+ *b++ = offset;
+ if (gen >= 9)
+ *b++ = 0;
+ n++;
+ }
+ }
+ obj[1].relocation_count = n;
+ *b++ = MI_BATCH_BUFFER_END;
+ munmap(batch, batch_size);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = 2;
+ execbuf.flags =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ execbuf.rsvd1 = ctx;
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, obj[1].handle);
+}
+
+__attribute__((unused))
+static void dump_regs(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int regs)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ const unsigned int gen_bit = 1 << gen;
+ const unsigned int engine_bit = ENGINE(e->class, e->instance);
+ unsigned int regs_size;
+ uint32_t *out;
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ out = gem_mmap__cpu(fd, regs, 0, regs_size, PROT_READ);
+ gem_set_domain(fd, regs, I915_GEM_DOMAIN_CPU, 0);
+
+ for (const struct named_register *r = nonpriv_registers; r->name; r++) {
+ if (!(r->engine_mask & engine_bit))
+ continue;
+ if (!(r->gen_mask & gen_bit))
+ continue;
+
+ if (r->count <= 1) {
+ igt_debug("0x%04x (%s): 0x%08x\n",
+ r->offset, r->name, out[r->offset/4]);
+ } else {
+ for (unsigned x = 0; x < r->count; x++)
+ igt_debug("0x%04x (%s[%d]): 0x%08x\n",
+ r->offset+4*x, r->name, x,
+ out[r->offset/4 + x]);
+ }
+ }
+ munmap(out, regs_size);
+}
+
+static void compare_regs(int fd, uint32_t A, uint32_t B, const char *who)
+{
+ unsigned int num_errors;
+ unsigned int regs_size;
+ uint32_t *a, *b;
+ char buf[80];
+
+ regs_size = NUM_REGS * sizeof(uint32_t);
+ regs_size = PAGE_ALIGN(regs_size);
+
+ a = gem_mmap__cpu(fd, A, 0, regs_size, PROT_READ);
+ gem_set_domain(fd, A, I915_GEM_DOMAIN_CPU, 0);
+
+ b = gem_mmap__cpu(fd, B, 0, regs_size, PROT_READ);
+ gem_set_domain(fd, B, I915_GEM_DOMAIN_CPU, 0);
+
+ num_errors = 0;
+ for (unsigned int n = 0; n < NUM_REGS; n++) {
+ uint32_t offset = n * sizeof(uint32_t);
+ if (a[n] != b[n] && !ignore_register(offset)) {
+ igt_warn("Register 0x%04x (%s): A=%08x B=%08x\n",
+ offset,
+ register_name(offset, buf, sizeof(buf)),
+ a[n], b[n]);
+ num_errors++;
+ }
+ }
+ munmap(b, regs_size);
+ munmap(a, regs_size);
+
+ igt_assert_f(num_errors == 0,
+ "%d registers mistached between %s.\n",
+ num_errors, who);
+}
+
+static void isolation(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ unsigned int engine = gem_class_instance_to_eb_flags(fd,
+ e->class,
+ e->instance);
+ unsigned int num_values =
+ flags & (DIRTY1 | DIRTY2) ? ARRAY_SIZE(values) : 1;
+
+ gem_quiescent_gpu(fd);
+
+ for (int v = 0; v < num_values; v++) {
+ igt_spin_t *spin = NULL;
+ uint32_t ctx[2], regs[2], tmp;
+
+ ctx[0] = gem_context_create(fd);
+ regs[0] = read_regs(fd, ctx[0], e, flags);
+
+ spin = igt_spin_batch_new(fd, ctx[0], engine, 0);
+
+ if (flags & DIRTY1) {
+ igt_debug("%s[%d]: Setting all registers of ctx 0 to 0x%08x\n",
+ __func__, v, values[v]);
+ write_regs(fd, ctx[0], e, flags, values[v]);
+ }
+
+ /*
+ * We create and execute a new context, whilst the HW is
+ * occupied with the previous context (we should switch from
+ * the old to the new proto-context without idling, which could
+ * then load the powercontext). If all goes well, we only see
+ * the default values from this context, but if goes badly we
+ * see the corruption from the previous context instead!
+ */
+ ctx[1] = gem_context_create(fd);
+ regs[1] = read_regs(fd, ctx[1], e, flags);
+
+ if (flags & DIRTY2) {
+ igt_debug("%s[%d]: Setting all registers of ctx 1 to 0x%08x\n",
+ __func__, v, ~values[v]);
+ write_regs(fd, ctx[1], e, flags, ~values[v]);
+ }
+
+ /*
+ * Restore the original register values before the HW idles.
+ * Or else it may never restart!
+ */
+ tmp = read_regs(fd, ctx[0], e, flags);
+ restore_regs(fd, ctx[0], e, flags, regs[0]);
+
+ igt_spin_batch_free(fd, spin);
+
+ if (!(flags & DIRTY1))
+ compare_regs(fd, regs[0], tmp, "two reads of the same ctx");
+ compare_regs(fd, regs[0], regs[1], "two virgin contexts");
+
+ for (int n = 0; n < ARRAY_SIZE(ctx); n++) {
+ gem_close(fd, regs[n]);
+ gem_context_destroy(fd, ctx[n]);
+ }
+ gem_close(fd, tmp);
+ }
+}
+
+#define NOSLEEP (0 << 8)
+#define S3_DEVICES (1 << 8)
+#define S3 (2 << 8)
+#define S4_DEVICES (3 << 8)
+#define S4 (4 << 8)
+#define SLEEP_MASK (0xf << 8)
+
+static void preservation(int fd,
+ const struct intel_execution_engine2 *e,
+ unsigned int flags)
+{
+ static const uint32_t values[] = {
+ 0x0,
+ 0xffffffff,
+ 0xcccccccc,
+ 0x33333333,
+ 0x55555555,
+ 0xaaaaaaaa,
+ 0xdeadbeef
+ };
+ const unsigned int num_values = ARRAY_SIZE(values);
+ unsigned int engine =
+ gem_class_instance_to_eb_flags(fd, e->class, e->instance);
+ uint32_t ctx[num_values +1 ];
+ uint32_t regs[num_values + 1][2];
+ igt_spin_t *spin;
+
+ gem_quiescent_gpu(fd);
+
+ ctx[num_values] = gem_context_create(fd);
+ spin = igt_spin_batch_new(fd, ctx[num_values], engine, 0);
+ regs[num_values][0] = read_regs(fd, ctx[num_values], e, flags);
+ for (int v = 0; v < num_values; v++) {
+ ctx[v] = gem_context_create(fd);
+ write_regs(fd, ctx[v], e, flags, values[v]);
+
+ regs[v][0] = read_regs(fd, ctx[v], e, flags);
+
+ }
+ gem_close(fd, read_regs(fd, ctx[num_values], e, flags));
+ igt_spin_batch_free(fd, spin);
+
+ if (flags & RESET)
+ igt_force_gpu_reset(fd);
+
+ switch (flags & SLEEP_MASK) {
+ case NOSLEEP:
+ break;
+
+ case S3_DEVICES:
+ igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
+ SUSPEND_TEST_DEVICES);
+ break;
+
+ case S3:
+ igt_system_suspend_autoresume(SUSPEND_STATE_MEM,
+ SUSPEND_TEST_NONE);
+ break;
+
+ case S4_DEVICES:
+ igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
+ SUSPEND_TEST_DEVICES);
+ break;
+
+ case S4:
+ igt_system_suspend_autoresume(SUSPEND_STATE_DISK,
+ SUSPEND_TEST_NONE);
+ break;
+ }
+
+ spin = igt_spin_batch_new(fd, ctx[num_values], engine, 0);
+ for (int v = 0; v < num_values; v++)
+ regs[v][1] = read_regs(fd, ctx[v], e, flags);
+ regs[num_values][1] = read_regs(fd, ctx[num_values], e, flags);
+ igt_spin_batch_free(fd, spin);
+
+ for (int v = 0; v < num_values; v++) {
+ char buf[80];
+
+ snprintf(buf, sizeof(buf), "dirty %x context\n", values[v]);
+ compare_regs(fd, regs[v][0], regs[v][1], buf);
+
+ gem_close(fd, regs[v][0]);
+ gem_close(fd, regs[v][1]);
+ gem_context_destroy(fd, ctx[v]);
+ }
+ compare_regs(fd, regs[num_values][0], regs[num_values][1], "clean");
+ gem_context_destroy(fd, ctx[num_values]);
+}
+
+static unsigned int __has_context_isolation(int fd)
+{
+ struct drm_i915_getparam gp;
+ int value = 0;
+
+ memset(&gp, 0, sizeof(gp));
+ gp.param = 50; /* I915_PARAM_HAS_CONTEXT_ISOLATION */
+ gp.value = &value;
+
+ igt_ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+ errno = 0;
+
+ return value;
+}
+
+igt_main
+{
+ unsigned int has_context_isolation = 0;
+ int fd = -1;
+
+ igt_fixture {
+ int gen;
+
+ fd = drm_open_driver(DRIVER_INTEL);
+ igt_require_gem(fd);
+
+ gem_context_destroy(fd, gem_context_create(fd));
+ has_context_isolation = __has_context_isolation(fd);
+ igt_require(has_context_isolation);
+
+ gen = intel_gen(intel_get_drm_devid(fd));
+ //igt_ci_fail_on(gen > LAST_KNOWN_GEN);
+ igt_skip_on(gen > LAST_KNOWN_GEN);
+ }
+
+ for (const struct intel_execution_engine2 *e = intel_execution_engines2;
+ e->name; e++) {
+ igt_subtest_group {
+ igt_fixture {
+ igt_require(has_context_isolation & (1 << e->class));
+ gem_require_engine(fd, e->class, e->instance);
+ igt_fork_hang_detector(fd);
+ }
+
+ igt_subtest_f("%s-clean", e->name)
+ isolation(fd, e, 0);
+ igt_subtest_f("%s-dirty-create", e->name)
+ isolation(fd, e, DIRTY1);
+ igt_subtest_f("%s-dirty-switch", e->name)
+ isolation(fd, e, DIRTY2);
+
+ igt_subtest_f("%s-none", e->name)
+ preservation(fd, e, 0);
+ igt_subtest_f("%s-S3", e->name)
+ preservation(fd, e, S3);
+ igt_subtest_f("%s-S4", e->name)
+ preservation(fd, e, S4);
+
+ igt_fixture {
+ igt_stop_hang_detector();
+ }
+
+ igt_subtest_f("%s-reset", e->name) {
+ igt_hang_t hang = igt_allow_hang(fd, 0, 0);
+ preservation(fd, e, RESET);
+ igt_disallow_hang(fd, hang);
+ }
+ }
+ }
+}
diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
index 8dd758aa..312505d6 100644
--- a/tests/gem_exec_fence.c
+++ b/tests/gem_exec_fence.c
@@ -793,7 +793,7 @@ static bool has_submit_fence(int fd)
int value = 0;
memset(&gp, 0, sizeof(gp));
- gp.param = 50; /* I915_PARAM_HAS_EXEC_SUBMIT_FENCE */
+ gp.param = 0xdeadbeef ^ 51; /* I915_PARAM_HAS_EXEC_SUBMIT_FENCE */
gp.value = &value;
ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
--
2.16.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 13/16] igt/gem_ctx_switch: Do a warmup pass over all contexts
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Ensure that we always use every context at least once before we start
running the stress-test.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_ctx_switch.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index 4db902b1..e0ab3d18 100644
--- a/tests/gem_ctx_switch.c
+++ b/tests/gem_ctx_switch.c
@@ -101,6 +101,13 @@ static void single(int fd, uint32_t handle,
struct timespec start, now;
unsigned int count = 0;
+ /* Warmup */
+ for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
+ execbuf.rsvd1 = contexts[i];
+ gem_execbuf(fd, &execbuf);
+ }
+ gem_sync(fd, handle);
+
clock_gettime(CLOCK_MONOTONIC, &start);
do {
igt_while_interruptible(flags & INTERRUPTIBLE) {
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH igt 13/16] igt/gem_ctx_switch: Do a warmup pass over all contexts
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Ensure that we always use every context at least once before we start
running the stress-test.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_ctx_switch.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index 4db902b1..e0ab3d18 100644
--- a/tests/gem_ctx_switch.c
+++ b/tests/gem_ctx_switch.c
@@ -101,6 +101,13 @@ static void single(int fd, uint32_t handle,
struct timespec start, now;
unsigned int count = 0;
+ /* Warmup */
+ for (int i = 0; i < ARRAY_SIZE(contexts); i++) {
+ execbuf.rsvd1 = contexts[i];
+ gem_execbuf(fd, &execbuf);
+ }
+ gem_sync(fd, handle);
+
clock_gettime(CLOCK_MONOTONIC, &start);
do {
igt_while_interruptible(flags & INTERRUPTIBLE) {
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 14/16] igt/gem_ctx_switch: Exercise all engines at once
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Just a small variant to apply a continuous context-switch load to all
engines.
---
tests/gem_ctx_switch.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index e0ab3d18..9b5560c0 100644
--- a/tests/gem_ctx_switch.c
+++ b/tests/gem_ctx_switch.c
@@ -133,6 +133,77 @@ static void single(int fd, uint32_t handle,
gem_context_destroy(fd, contexts[n]);
}
+static void all(int fd, uint32_t handle, unsigned flags, int timeout)
+{
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 obj[2];
+ unsigned int engine[16], e;
+ const char *name[16];
+ uint32_t contexts[64];
+ unsigned int nengine;
+ int n;
+
+ nengine = 0;
+ for_each_engine(fd, e) {
+ if (e == 0 || e == I915_EXEC_BSD)
+ continue;
+
+ engine[nengine] = e;
+ name[nengine] = e__->name;
+ nengine++;
+ }
+ igt_require(nengine);
+
+ igt_require(__gem_context_create(fd, &contexts[0]) == 0);
+ for (n = 1; n < 64; n++)
+ contexts[n] = gem_context_create(fd);
+
+ memset(obj, 0, sizeof(obj));
+ obj[1].handle = handle;
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj + 1);
+ execbuf.buffer_count = 1;
+ execbuf.rsvd1 = contexts[0];
+ execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
+ execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
+ igt_require(__gem_execbuf(fd, &execbuf) == 0);
+ gem_sync(fd, handle);
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = 2;
+
+ igt_fork(child, nengine) {
+ struct timespec start, now;
+ unsigned int count = 0;
+
+ obj[0].handle = gem_create(fd, 4096);
+ execbuf.flags |= engine[child];
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, obj[0].handle);
+
+ clock_gettime(CLOCK_MONOTONIC, &start);
+ do {
+ for (int loop = 0; loop < 64; loop++) {
+ execbuf.rsvd1 = contexts[loop % 64];
+ gem_execbuf(fd, &execbuf);
+ }
+ count += 64;
+ clock_gettime(CLOCK_MONOTONIC, &now);
+ } while (elapsed(&start, &now) < timeout);
+ gem_sync(fd, obj[0].handle);
+ clock_gettime(CLOCK_MONOTONIC, &now);
+ gem_close(fd, obj[0].handle);
+
+ igt_info("[%d] %s: %'u cycles: %.3fus%s\n",
+ child, name[child], count, elapsed(&start, &now)*1e6 / count,
+ flags & INTERRUPTIBLE ? " (interruptible)" : "");
+ }
+ igt_waitchildren();
+
+ for (n = 0; n < 64; n++)
+ gem_context_destroy(fd, contexts[n]);
+}
+
igt_main
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
@@ -175,6 +246,11 @@ igt_main
single(fd, light, e, INTERRUPTIBLE, ncpus, 150);
}
+ igt_subtest("basic-all")
+ all(fd, light, 0, 20);
+ igt_subtest("basic-all-heavy")
+ all(fd, heavy, 0, 20);
+
igt_fixture {
igt_stop_hang_detector();
gem_close(fd, heavy);
--
2.16.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 14/16] igt/gem_ctx_switch: Exercise all engines at once
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Just a small variant to apply a continuous context-switch load to all
engines.
---
tests/gem_ctx_switch.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
index e0ab3d18..9b5560c0 100644
--- a/tests/gem_ctx_switch.c
+++ b/tests/gem_ctx_switch.c
@@ -133,6 +133,77 @@ static void single(int fd, uint32_t handle,
gem_context_destroy(fd, contexts[n]);
}
+static void all(int fd, uint32_t handle, unsigned flags, int timeout)
+{
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct drm_i915_gem_exec_object2 obj[2];
+ unsigned int engine[16], e;
+ const char *name[16];
+ uint32_t contexts[64];
+ unsigned int nengine;
+ int n;
+
+ nengine = 0;
+ for_each_engine(fd, e) {
+ if (e == 0 || e == I915_EXEC_BSD)
+ continue;
+
+ engine[nengine] = e;
+ name[nengine] = e__->name;
+ nengine++;
+ }
+ igt_require(nengine);
+
+ igt_require(__gem_context_create(fd, &contexts[0]) == 0);
+ for (n = 1; n < 64; n++)
+ contexts[n] = gem_context_create(fd);
+
+ memset(obj, 0, sizeof(obj));
+ obj[1].handle = handle;
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(obj + 1);
+ execbuf.buffer_count = 1;
+ execbuf.rsvd1 = contexts[0];
+ execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
+ execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
+ igt_require(__gem_execbuf(fd, &execbuf) == 0);
+ gem_sync(fd, handle);
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.buffer_count = 2;
+
+ igt_fork(child, nengine) {
+ struct timespec start, now;
+ unsigned int count = 0;
+
+ obj[0].handle = gem_create(fd, 4096);
+ execbuf.flags |= engine[child];
+ gem_execbuf(fd, &execbuf);
+ gem_sync(fd, obj[0].handle);
+
+ clock_gettime(CLOCK_MONOTONIC, &start);
+ do {
+ for (int loop = 0; loop < 64; loop++) {
+ execbuf.rsvd1 = contexts[loop % 64];
+ gem_execbuf(fd, &execbuf);
+ }
+ count += 64;
+ clock_gettime(CLOCK_MONOTONIC, &now);
+ } while (elapsed(&start, &now) < timeout);
+ gem_sync(fd, obj[0].handle);
+ clock_gettime(CLOCK_MONOTONIC, &now);
+ gem_close(fd, obj[0].handle);
+
+ igt_info("[%d] %s: %'u cycles: %.3fus%s\n",
+ child, name[child], count, elapsed(&start, &now)*1e6 / count,
+ flags & INTERRUPTIBLE ? " (interruptible)" : "");
+ }
+ igt_waitchildren();
+
+ for (n = 0; n < 64; n++)
+ gem_context_destroy(fd, contexts[n]);
+}
+
igt_main
{
const int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
@@ -175,6 +246,11 @@ igt_main
single(fd, light, e, INTERRUPTIBLE, ncpus, 150);
}
+ igt_subtest("basic-all")
+ all(fd, light, 0, 20);
+ igt_subtest("basic-all-heavy")
+ all(fd, heavy, 0, 20);
+
igt_fixture {
igt_stop_hang_detector();
gem_close(fd, heavy);
--
2.16.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 15/16] igt/gem_exec_capture: Exercise readback of userptr
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
EXEC_OBJECT_CAPTURE extends the type of buffers we may read during error
capture. Previously we knew that we would only see batch buffers (which
limited the objects to being from gem_create()), but now we need to
check that any buffer the user can create can be read. The first
alternate buffer type is a userptr.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_capture.c | 35 ++++++++++++++++++++++++++++++++---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
index aa80d59d..3a1f7056 100644
--- a/tests/gem_exec_capture.c
+++ b/tests/gem_exec_capture.c
@@ -57,7 +57,7 @@ static void check_error_state(int dir, struct drm_i915_gem_exec_object2 *obj)
igt_assert(found);
}
-static void capture(int fd, int dir, unsigned ring)
+static void __capture(int fd, int dir, unsigned ring, uint32_t target)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[4];
@@ -72,7 +72,7 @@ static void capture(int fd, int dir, unsigned ring)
memset(obj, 0, sizeof(obj));
obj[SCRATCH].handle = gem_create(fd, 4096);
- obj[CAPTURE].handle = gem_create(fd, 4096);
+ obj[CAPTURE].handle = target;
obj[CAPTURE].flags = LOCAL_OBJECT_CAPTURE;
obj[NOCAPTURE].handle = gem_create(fd, 4096);
@@ -159,10 +159,32 @@ static void capture(int fd, int dir, unsigned ring)
gem_close(fd, obj[BATCH].handle);
gem_close(fd, obj[NOCAPTURE].handle);
- gem_close(fd, obj[CAPTURE].handle);
gem_close(fd, obj[SCRATCH].handle);
}
+static void capture(int fd, int dir, unsigned ring)
+{
+ uint32_t handle;
+
+ handle = gem_create(fd, 4096);
+ __capture(fd, dir, ring, handle);
+ gem_close(fd, handle);
+}
+
+static void userptr(int fd, int dir)
+{
+ uint32_t handle;
+ void *ptr;
+
+ igt_assert(posix_memalign(&ptr, 4096, 4096) == 0);
+ igt_require(__gem_userptr(fd, ptr, 4096, 0, 0, &handle) == 0);
+
+ __capture(fd, dir, 0, handle);
+
+ gem_close(fd, handle);
+ free(ptr);
+}
+
static bool has_capture(int fd)
{
drm_i915_getparam_t gp;
@@ -214,6 +236,13 @@ igt_main
}
}
+ /* And check we can read from different types of objects */
+
+ igt_subtest_f("userptr") {
+ igt_require(gem_can_store_dword(fd, 0));
+ userptr(fd, dir);
+ }
+
igt_fixture {
close(dir);
igt_disallow_hang(fd, hang);
--
2.16.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 15/16] igt/gem_exec_capture: Exercise readback of userptr
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
EXEC_OBJECT_CAPTURE extends the type of buffers we may read during error
capture. Previously we knew that we would only see batch buffers (which
limited the objects to being from gem_create()), but now we need to
check that any buffer the user can create can be read. The first
alternate buffer type is a userptr.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_capture.c | 35 ++++++++++++++++++++++++++++++++---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/tests/gem_exec_capture.c b/tests/gem_exec_capture.c
index aa80d59d..3a1f7056 100644
--- a/tests/gem_exec_capture.c
+++ b/tests/gem_exec_capture.c
@@ -57,7 +57,7 @@ static void check_error_state(int dir, struct drm_i915_gem_exec_object2 *obj)
igt_assert(found);
}
-static void capture(int fd, int dir, unsigned ring)
+static void __capture(int fd, int dir, unsigned ring, uint32_t target)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
struct drm_i915_gem_exec_object2 obj[4];
@@ -72,7 +72,7 @@ static void capture(int fd, int dir, unsigned ring)
memset(obj, 0, sizeof(obj));
obj[SCRATCH].handle = gem_create(fd, 4096);
- obj[CAPTURE].handle = gem_create(fd, 4096);
+ obj[CAPTURE].handle = target;
obj[CAPTURE].flags = LOCAL_OBJECT_CAPTURE;
obj[NOCAPTURE].handle = gem_create(fd, 4096);
@@ -159,10 +159,32 @@ static void capture(int fd, int dir, unsigned ring)
gem_close(fd, obj[BATCH].handle);
gem_close(fd, obj[NOCAPTURE].handle);
- gem_close(fd, obj[CAPTURE].handle);
gem_close(fd, obj[SCRATCH].handle);
}
+static void capture(int fd, int dir, unsigned ring)
+{
+ uint32_t handle;
+
+ handle = gem_create(fd, 4096);
+ __capture(fd, dir, ring, handle);
+ gem_close(fd, handle);
+}
+
+static void userptr(int fd, int dir)
+{
+ uint32_t handle;
+ void *ptr;
+
+ igt_assert(posix_memalign(&ptr, 4096, 4096) == 0);
+ igt_require(__gem_userptr(fd, ptr, 4096, 0, 0, &handle) == 0);
+
+ __capture(fd, dir, 0, handle);
+
+ gem_close(fd, handle);
+ free(ptr);
+}
+
static bool has_capture(int fd)
{
drm_i915_getparam_t gp;
@@ -214,6 +236,13 @@ igt_main
}
}
+ /* And check we can read from different types of objects */
+
+ igt_subtest_f("userptr") {
+ igt_require(gem_can_store_dword(fd, 0));
+ userptr(fd, dir);
+ }
+
igt_fixture {
close(dir);
igt_disallow_hang(fd, hang);
--
2.16.1
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH igt 16/16] igt/gem_exec_fence: Exercise merging fences
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 8:45 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Execute the same batch on each engine and check that the composite fence
across all engines completes only after the batch is completed on every
engine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_fence.c | 127 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
index 312505d6..d9432f95 100644
--- a/tests/gem_exec_fence.c
+++ b/tests/gem_exec_fence.c
@@ -207,6 +207,113 @@ static void test_fence_busy(int fd, unsigned ring, unsigned flags)
gem_quiescent_gpu(fd);
}
+static void test_fence_busy_all(int fd, unsigned flags)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 obj;
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct timespec tv;
+ uint32_t *batch;
+ unsigned int engine;
+ int all, i, timeout;
+
+ gem_quiescent_gpu(fd);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&obj);
+ execbuf.buffer_count = 1;
+
+ memset(&obj, 0, sizeof(obj));
+ obj.handle = gem_create(fd, 4096);
+
+ obj.relocs_ptr = to_user_pointer(&reloc);
+ obj.relocation_count = 1;
+ memset(&reloc, 0, sizeof(reloc));
+
+ batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+ gem_set_domain(fd, obj.handle,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+ reloc.target_handle = obj.handle; /* recurse */
+ reloc.presumed_offset = 0;
+ reloc.offset = sizeof(uint32_t);
+ reloc.delta = 0;
+ reloc.read_domains = I915_GEM_DOMAIN_COMMAND;
+ reloc.write_domain = 0;
+
+ i = 0;
+ batch[i] = MI_BATCH_BUFFER_START;
+ if (gen >= 8) {
+ batch[i] |= 1 << 8 | 1;
+ batch[++i] = 0;
+ batch[++i] = 0;
+ } else if (gen >= 6) {
+ batch[i] |= 1 << 8;
+ batch[++i] = 0;
+ } else {
+ batch[i] |= 2 << 6;
+ batch[++i] = 0;
+ if (gen < 4) {
+ batch[i] |= 1;
+ reloc.delta = 1;
+ }
+ }
+ i++;
+
+ all = -1;
+ for_each_engine(fd, engine) {
+ int fence, new;
+
+ execbuf.flags = engine | LOCAL_EXEC_FENCE_OUT;
+ execbuf.rsvd2 = -1;
+ gem_execbuf_wr(fd, &execbuf);
+ fence = execbuf.rsvd2 >> 32;
+ igt_assert(fence != -1);
+
+ if (all < 0) {
+ all = fence;
+ break;
+ }
+
+ new = sync_fence_merge(all, fence);
+ igt_assert_lte(0, new);
+ close(all);
+ close(fence);
+
+ all = new;
+ }
+
+ igt_assert(gem_bo_busy(fd, obj.handle));
+ igt_assert(fence_busy(all));
+
+ timeout = 120;
+ if ((flags & HANG) == 0) {
+ *batch = MI_BATCH_BUFFER_END;
+ __sync_synchronize();
+ timeout = 1;
+ }
+ munmap(batch, 4096);
+
+ if (flags & WAIT) {
+ struct pollfd pfd = { .fd = all, .events = POLLIN };
+ igt_assert(poll(&pfd, 1, timeout*1000) == 1);
+ } else {
+ memset(&tv, 0, sizeof(tv));
+ while (fence_busy(all))
+ igt_assert(igt_seconds_elapsed(&tv) < timeout);
+ }
+
+ igt_assert(!gem_bo_busy(fd, obj.handle));
+ igt_assert_eq(sync_fence_status(all),
+ flags & HANG ? -EIO : SYNC_FENCE_OK);
+
+ close(all);
+ gem_close(fd, obj.handle);
+
+ gem_quiescent_gpu(fd);
+}
+
static void test_fence_await(int fd, unsigned ring, unsigned flags)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
@@ -1558,6 +1665,26 @@ igt_main
gem_submission_print_method(i915);
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_fork_hang_detector(i915);
+ }
+
+ igt_subtest("basic-busy-all")
+ test_fence_busy_all(i915, 0);
+ igt_subtest("basic-wait-all")
+ test_fence_busy_all(i915, WAIT);
+
+ igt_fixture {
+ igt_stop_hang_detector();
+ }
+
+ igt_subtest("busy-hang-all")
+ test_fence_busy_all(i915, HANG);
+ igt_subtest("wait-hang-all")
+ test_fence_busy_all(i915, WAIT | HANG);
+ }
+
for (e = intel_execution_engines; e->name; e++) {
igt_subtest_group {
igt_fixture {
--
2.16.1
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^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] [PATCH igt 16/16] igt/gem_exec_fence: Exercise merging fences
@ 2018-02-20 8:45 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 8:45 UTC (permalink / raw)
To: igt-dev, joonas.lahtinen; +Cc: intel-gfx
Execute the same batch on each engine and check that the composite fence
across all engines completes only after the batch is completed on every
engine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
tests/gem_exec_fence.c | 127 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/tests/gem_exec_fence.c b/tests/gem_exec_fence.c
index 312505d6..d9432f95 100644
--- a/tests/gem_exec_fence.c
+++ b/tests/gem_exec_fence.c
@@ -207,6 +207,113 @@ static void test_fence_busy(int fd, unsigned ring, unsigned flags)
gem_quiescent_gpu(fd);
}
+static void test_fence_busy_all(int fd, unsigned flags)
+{
+ const int gen = intel_gen(intel_get_drm_devid(fd));
+ struct drm_i915_gem_exec_object2 obj;
+ struct drm_i915_gem_relocation_entry reloc;
+ struct drm_i915_gem_execbuffer2 execbuf;
+ struct timespec tv;
+ uint32_t *batch;
+ unsigned int engine;
+ int all, i, timeout;
+
+ gem_quiescent_gpu(fd);
+
+ memset(&execbuf, 0, sizeof(execbuf));
+ execbuf.buffers_ptr = to_user_pointer(&obj);
+ execbuf.buffer_count = 1;
+
+ memset(&obj, 0, sizeof(obj));
+ obj.handle = gem_create(fd, 4096);
+
+ obj.relocs_ptr = to_user_pointer(&reloc);
+ obj.relocation_count = 1;
+ memset(&reloc, 0, sizeof(reloc));
+
+ batch = gem_mmap__wc(fd, obj.handle, 0, 4096, PROT_WRITE);
+ gem_set_domain(fd, obj.handle,
+ I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
+
+ reloc.target_handle = obj.handle; /* recurse */
+ reloc.presumed_offset = 0;
+ reloc.offset = sizeof(uint32_t);
+ reloc.delta = 0;
+ reloc.read_domains = I915_GEM_DOMAIN_COMMAND;
+ reloc.write_domain = 0;
+
+ i = 0;
+ batch[i] = MI_BATCH_BUFFER_START;
+ if (gen >= 8) {
+ batch[i] |= 1 << 8 | 1;
+ batch[++i] = 0;
+ batch[++i] = 0;
+ } else if (gen >= 6) {
+ batch[i] |= 1 << 8;
+ batch[++i] = 0;
+ } else {
+ batch[i] |= 2 << 6;
+ batch[++i] = 0;
+ if (gen < 4) {
+ batch[i] |= 1;
+ reloc.delta = 1;
+ }
+ }
+ i++;
+
+ all = -1;
+ for_each_engine(fd, engine) {
+ int fence, new;
+
+ execbuf.flags = engine | LOCAL_EXEC_FENCE_OUT;
+ execbuf.rsvd2 = -1;
+ gem_execbuf_wr(fd, &execbuf);
+ fence = execbuf.rsvd2 >> 32;
+ igt_assert(fence != -1);
+
+ if (all < 0) {
+ all = fence;
+ break;
+ }
+
+ new = sync_fence_merge(all, fence);
+ igt_assert_lte(0, new);
+ close(all);
+ close(fence);
+
+ all = new;
+ }
+
+ igt_assert(gem_bo_busy(fd, obj.handle));
+ igt_assert(fence_busy(all));
+
+ timeout = 120;
+ if ((flags & HANG) == 0) {
+ *batch = MI_BATCH_BUFFER_END;
+ __sync_synchronize();
+ timeout = 1;
+ }
+ munmap(batch, 4096);
+
+ if (flags & WAIT) {
+ struct pollfd pfd = { .fd = all, .events = POLLIN };
+ igt_assert(poll(&pfd, 1, timeout*1000) == 1);
+ } else {
+ memset(&tv, 0, sizeof(tv));
+ while (fence_busy(all))
+ igt_assert(igt_seconds_elapsed(&tv) < timeout);
+ }
+
+ igt_assert(!gem_bo_busy(fd, obj.handle));
+ igt_assert_eq(sync_fence_status(all),
+ flags & HANG ? -EIO : SYNC_FENCE_OK);
+
+ close(all);
+ gem_close(fd, obj.handle);
+
+ gem_quiescent_gpu(fd);
+}
+
static void test_fence_await(int fd, unsigned ring, unsigned flags)
{
const int gen = intel_gen(intel_get_drm_devid(fd));
@@ -1558,6 +1665,26 @@ igt_main
gem_submission_print_method(i915);
}
+ igt_subtest_group {
+ igt_fixture {
+ igt_fork_hang_detector(i915);
+ }
+
+ igt_subtest("basic-busy-all")
+ test_fence_busy_all(i915, 0);
+ igt_subtest("basic-wait-all")
+ test_fence_busy_all(i915, WAIT);
+
+ igt_fixture {
+ igt_stop_hang_detector();
+ }
+
+ igt_subtest("busy-hang-all")
+ test_fence_busy_all(i915, HANG);
+ igt_subtest("wait-hang-all")
+ test_fence_busy_all(i915, WAIT | HANG);
+ }
+
for (e = intel_execution_engines; e->name; e++) {
igt_subtest_group {
igt_fixture {
--
2.16.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [01/16] igt/gem_sync: Exercise and measure idle requests
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
` (15 preceding siblings ...)
(?)
@ 2018-02-20 9:09 ` Patchwork
-1 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2018-02-20 9:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: series starting with [01/16] igt/gem_sync: Exercise and measure idle requests
URL : https://patchwork.freedesktop.org/series/38568/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
6fc91dbb67eea6824100905a4ab1fb38f186dba0 perf_pmu: Fix some compile warnings with old compilers / 32-bit builds
with latest DRM-Tip kernel build CI_DRM_3803
b8d091ad9a26 drm-tip: 2018y-02m-20d-07h-42m-31s UTC integration manifest
Testlist changes:
+igt@gem_ctx_isolation@bcs0-clean
+igt@gem_ctx_isolation@bcs0-dirty-create
+igt@gem_ctx_isolation@bcs0-dirty-switch
+igt@gem_ctx_isolation@bcs0-none
+igt@gem_ctx_isolation@bcs0-reset
+igt@gem_ctx_isolation@bcs0-s3
+igt@gem_ctx_isolation@bcs0-s4
+igt@gem_ctx_isolation@rcs0-clean
+igt@gem_ctx_isolation@rcs0-dirty-create
+igt@gem_ctx_isolation@rcs0-dirty-switch
+igt@gem_ctx_isolation@rcs0-none
+igt@gem_ctx_isolation@rcs0-reset
+igt@gem_ctx_isolation@rcs0-s3
+igt@gem_ctx_isolation@rcs0-s4
+igt@gem_ctx_isolation@vcs0-clean
+igt@gem_ctx_isolation@vcs0-dirty-create
+igt@gem_ctx_isolation@vcs0-dirty-switch
+igt@gem_ctx_isolation@vcs0-none
+igt@gem_ctx_isolation@vcs0-reset
+igt@gem_ctx_isolation@vcs0-s3
+igt@gem_ctx_isolation@vcs0-s4
+igt@gem_ctx_isolation@vcs1-clean
+igt@gem_ctx_isolation@vcs1-dirty-create
+igt@gem_ctx_isolation@vcs1-dirty-switch
+igt@gem_ctx_isolation@vcs1-none
+igt@gem_ctx_isolation@vcs1-reset
+igt@gem_ctx_isolation@vcs1-s3
+igt@gem_ctx_isolation@vcs1-s4
+igt@gem_ctx_isolation@vecs0-clean
+igt@gem_ctx_isolation@vecs0-dirty-create
+igt@gem_ctx_isolation@vecs0-dirty-switch
+igt@gem_ctx_isolation@vecs0-none
+igt@gem_ctx_isolation@vecs0-reset
+igt@gem_ctx_isolation@vecs0-s3
+igt@gem_ctx_isolation@vecs0-s4
+igt@gem_ctx_switch@basic-all
+igt@gem_ctx_switch@basic-all-heavy
+igt@gem_eio@set-wedged-racing
+igt@gem_exec_capture@userptr
+igt@gem_exec_fence@basic-busy-all
+igt@gem_exec_fence@basic-wait-all
+igt@gem_exec_fence@busy-hang-all
+igt@gem_exec_fence@wait-hang-all
+igt@gem_sync@idle-blt
+igt@gem_sync@idle-bsd
+igt@gem_sync@idle-bsd1
+igt@gem_sync@idle-bsd2
+igt@gem_sync@idle-default
+igt@gem_sync@idle-render
+igt@gem_sync@idle-vebox
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test kms_chamelium:
Subgroup dp-crc-fast:
dmesg-fail -> PASS (fi-kbl-7500u) fdo#103841
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:422s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:426s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:376s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:489s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:292s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:487s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:488s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:474s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:461s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:566s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:424s
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:286s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:512s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:391s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:414s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:456s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:461s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:497s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:507s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:597s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:431s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:509s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:526s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:498s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:479s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:415s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:529s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:399s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_958/issues.html
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 50+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for series starting with [01/16] igt/gem_sync: Exercise and measure idle requests
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
` (16 preceding siblings ...)
(?)
@ 2018-02-20 10:02 ` Patchwork
-1 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2018-02-20 10:02 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: series starting with [01/16] igt/gem_sync: Exercise and measure idle requests
URL : https://patchwork.freedesktop.org/series/38568/
State : failure
== Summary ==
Test kms_flip:
Subgroup 2x-modeset-vs-vblank-race-interruptible:
pass -> FAIL (shard-hsw) fdo#103060
Subgroup flip-vs-modeset-vs-hang:
dmesg-warn -> PASS (shard-snb) fdo#103821
Subgroup flip-vs-expired-vblank-interruptible:
pass -> FAIL (shard-hsw) fdo#102887
Subgroup plain-flip-fb-recreate:
pass -> FAIL (shard-hsw) fdo#100368
Test kms_sysfs_edid_timing:
warn -> PASS (shard-apl) fdo#100047
Test perf:
Subgroup oa-exponents:
pass -> FAIL (shard-apl) fdo#102254
Subgroup blocking:
fail -> PASS (shard-hsw) fdo#102252
Test gem_eio:
Subgroup in-flight:
fail -> PASS (shard-hsw) fdo#104676
Subgroup in-flight-contexts:
pass -> INCOMPLETE (shard-apl)
Test kms_cursor_legacy:
Subgroup 2x-long-flip-vs-cursor-atomic:
pass -> FAIL (shard-hsw) fdo#104873
Subgroup flip-vs-cursor-atomic:
fail -> PASS (shard-hsw) fdo#102670
Test kms_rotation_crc:
Subgroup sprite-rotation-180:
pass -> FAIL (shard-snb) fdo#103925
Test kms_cursor_crc:
Subgroup cursor-64x64-suspend:
pass -> SKIP (shard-snb) fdo#102365
Test gem_fenced_exec_thrash:
Subgroup too-many-fences:
pass -> FAIL (shard-hsw)
pass -> FAIL (shard-apl)
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103821 https://bugs.freedesktop.org/show_bug.cgi?id=103821
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#104676 https://bugs.freedesktop.org/show_bug.cgi?id=104676
fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
fdo#102670 https://bugs.freedesktop.org/show_bug.cgi?id=102670
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
shard-apl total:3433 pass:1805 dwarn:1 dfail:0 fail:14 skip:1611 time:12027s
shard-hsw total:3396 pass:1726 dwarn:1 dfail:0 fail:7 skip:1660 time:11291s
shard-snb total:3396 pass:1331 dwarn:1 dfail:0 fail:3 skip:2060 time:6385s
Blacklisted hosts:
shard-kbl total:3470 pass:1962 dwarn:2 dfail:0 fail:15 skip:1491 time:9750s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_958/shards.html
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH igt 07/16] igt/gem_exec_schedule: Trim max number of contexts used
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
@ 2018-02-20 10:52 ` Joonas Lahtinen
-1 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 10:52 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:11)
> icl offers a much reduced context space, and in its simplest setup we
> cannot allocate one context per priority level, so trim the number and
> reuse the same context for multiple priority requests.
>
> v2: Bump the MAX to 1024 (still lower than the ~4096 previously in use)
> v3: Also limit NCTX to MAX_CONTEXTS for wide-*
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Acked-by: Antonio Argenziano <antonio.argenziano@intel.com>
R-b was probably meant here instead. Anyway, this is:
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH igt 07/16] igt/gem_exec_schedule: Trim max number of contexts used
@ 2018-02-20 10:52 ` Joonas Lahtinen
0 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 10:52 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:11)
> icl offers a much reduced context space, and in its simplest setup we
> cannot allocate one context per priority level, so trim the number and
> reuse the same context for multiple priority requests.
>
> v2: Bump the MAX to 1024 (still lower than the ~4096 previously in use)
> v3: Also limit NCTX to MAX_CONTEXTS for wide-*
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Acked-by: Antonio Argenziano <antonio.argenziano@intel.com>
R-b was probably meant here instead. Anyway, this is:
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH igt 08/16] igt/gem_exec_schedule: Replace constant 16 with its magic macro
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
@ 2018-02-20 10:57 ` Joonas Lahtinen
-1 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 10:57 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:12)
> @@ -398,7 +399,7 @@ static void preempt(int fd, unsigned ring, unsigned flags)
> igt_assert(gem_bo_busy(fd, spin[0]->handle));
> }
>
> - for (int n = 0; n < 16; n++)
> + for (int n = 0; n < MAX_ELSP_QLEN; n++)
> igt_spin_batch_free(fd, spin[n]);
ARRAY_SIZE() seems more appropriate in the for loops. Seems like you've
opted not to use it so much, why so?
> @@ -450,6 +453,7 @@ static void preempt_other(int fd, unsigned ring)
> result, (n + 1)*sizeof(uint32_t), n + 1,
> 0, I915_GEM_DOMAIN_RENDER);
>
> + igt_debugfs_dump(fd, "i915_engine_info");
Lost and afraid hunk here? You can have my R-b for it in separate patch.
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [igt-dev] [PATCH igt 08/16] igt/gem_exec_schedule: Replace constant 16 with its magic macro
@ 2018-02-20 10:57 ` Joonas Lahtinen
0 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 10:57 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:12)
> @@ -398,7 +399,7 @@ static void preempt(int fd, unsigned ring, unsigned flags)
> igt_assert(gem_bo_busy(fd, spin[0]->handle));
> }
>
> - for (int n = 0; n < 16; n++)
> + for (int n = 0; n < MAX_ELSP_QLEN; n++)
> igt_spin_batch_free(fd, spin[n]);
ARRAY_SIZE() seems more appropriate in the for loops. Seems like you've
opted not to use it so much, why so?
> @@ -450,6 +453,7 @@ static void preempt_other(int fd, unsigned ring)
> result, (n + 1)*sizeof(uint32_t), n + 1,
> 0, I915_GEM_DOMAIN_RENDER);
>
> + igt_debugfs_dump(fd, "i915_engine_info");
Lost and afraid hunk here? You can have my R-b for it in separate patch.
Regards, Joonas
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH igt 08/16] igt/gem_exec_schedule: Replace constant 16 with its magic macro
2018-02-20 10:57 ` [igt-dev] " Joonas Lahtinen
@ 2018-02-20 11:01 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 11:01 UTC (permalink / raw)
To: Joonas Lahtinen, igt-dev; +Cc: intel-gfx
Quoting Joonas Lahtinen (2018-02-20 10:57:44)
> Quoting Chris Wilson (2018-02-20 10:45:12)
> > @@ -398,7 +399,7 @@ static void preempt(int fd, unsigned ring, unsigned flags)
> > igt_assert(gem_bo_busy(fd, spin[0]->handle));
> > }
> >
> > - for (int n = 0; n < 16; n++)
> > + for (int n = 0; n < MAX_ELSP_QLEN; n++)
> > igt_spin_batch_free(fd, spin[n]);
>
> ARRAY_SIZE() seems more appropriate in the for loops. Seems like you've
> opted not to use it so much, why so?
No idea. Next up will be we don't need so many individual spinners, just
one submitted multiple times in different contexts/engines.
> > @@ -450,6 +453,7 @@ static void preempt_other(int fd, unsigned ring)
> > result, (n + 1)*sizeof(uint32_t), n + 1,
> > 0, I915_GEM_DOMAIN_RENDER);
> >
> > + igt_debugfs_dump(fd, "i915_engine_info");
>
> Lost and afraid hunk here? You can have my R-b for it in separate patch.
Just lost. It ain't afraid of no bugs.
-Chris
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [igt-dev] [PATCH igt 08/16] igt/gem_exec_schedule: Replace constant 16 with its magic macro
@ 2018-02-20 11:01 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-02-20 11:01 UTC (permalink / raw)
To: Joonas Lahtinen, igt-dev; +Cc: intel-gfx
Quoting Joonas Lahtinen (2018-02-20 10:57:44)
> Quoting Chris Wilson (2018-02-20 10:45:12)
> > @@ -398,7 +399,7 @@ static void preempt(int fd, unsigned ring, unsigned flags)
> > igt_assert(gem_bo_busy(fd, spin[0]->handle));
> > }
> >
> > - for (int n = 0; n < 16; n++)
> > + for (int n = 0; n < MAX_ELSP_QLEN; n++)
> > igt_spin_batch_free(fd, spin[n]);
>
> ARRAY_SIZE() seems more appropriate in the for loops. Seems like you've
> opted not to use it so much, why so?
No idea. Next up will be we don't need so many individual spinners, just
one submitted multiple times in different contexts/engines.
> > @@ -450,6 +453,7 @@ static void preempt_other(int fd, unsigned ring)
> > result, (n + 1)*sizeof(uint32_t), n + 1,
> > 0, I915_GEM_DOMAIN_RENDER);
> >
> > + igt_debugfs_dump(fd, "i915_engine_info");
>
> Lost and afraid hunk here? You can have my R-b for it in separate patch.
Just lost. It ain't afraid of no bugs.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH igt 10/16] igt/gem_eio: Use slow spinners to inject hangs
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
@ 2018-02-20 11:14 ` Joonas Lahtinen
-1 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 11:14 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:14)
> One weird issue we see in bug 104676 is that the hangs are too fast on
> HSW! So force the use of the slow spinners that do not try to trigger
> a hang by injecting random bytes into the batch.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104676
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH igt 10/16] igt/gem_eio: Use slow spinners to inject hangs
@ 2018-02-20 11:14 ` Joonas Lahtinen
0 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 11:14 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:14)
> One weird issue we see in bug 104676 is that the hangs are too fast on
> HSW! So force the use of the slow spinners that do not try to trigger
> a hang by injecting random bytes into the batch.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104676
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH igt 12/16] igt/gem_ctx_isolation: Check isolation of registers between contexts
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
@ 2018-02-20 14:56 ` Joonas Lahtinen
-1 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 14:56 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:16)
> A new context assumes that all of its registers are in the default state
> when it is created. What may happen is that a register written by one
> context may leak into the second, causing mass confusion.
>
> v2: Extend back to Sandybridge (etc)
> v3: Check context preserves registers across suspend/hibernate and resets.
> v4: Complete the remapping onto the new class:instance
> v5: Not like that, like this, try again to use class:instance
> v6: Prepare for retrospective gen4 contexts!
> v7: Repaint register set name to nonpriv, as this is what bspec calls the
> registers that are writable by userspace.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [igt-dev] [PATCH igt 12/16] igt/gem_ctx_isolation: Check isolation of registers between contexts
@ 2018-02-20 14:56 ` Joonas Lahtinen
0 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 14:56 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:16)
> A new context assumes that all of its registers are in the default state
> when it is created. What may happen is that a register written by one
> context may leak into the second, causing mass confusion.
>
> v2: Extend back to Sandybridge (etc)
> v3: Check context preserves registers across suspend/hibernate and resets.
> v4: Complete the remapping onto the new class:instance
> v5: Not like that, like this, try again to use class:instance
> v6: Prepare for retrospective gen4 contexts!
> v7: Repaint register set name to nonpriv, as this is what bspec calls the
> registers that are writable by userspace.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Regards, Joonas
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH igt 13/16] igt/gem_ctx_switch: Do a warmup pass over all contexts
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-02-20 14:57 ` Joonas Lahtinen
-1 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 14:57 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:17)
> Ensure that we always use every context at least once before we start
> running the stress-test.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> tests/gem_ctx_switch.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
> index 4db902b1..e0ab3d18 100644
> --- a/tests/gem_ctx_switch.c
> +++ b/tests/gem_ctx_switch.c
> @@ -101,6 +101,13 @@ static void single(int fd, uint32_t handle,
> struct timespec start, now;
> unsigned int count = 0;
>
> + /* Warmup */
/* Warmup to make sure ... */
To make sure what, this is not a benchmark?
Regards, Joonas
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [igt-dev] [PATCH igt 13/16] igt/gem_ctx_switch: Do a warmup pass over all contexts
@ 2018-02-20 14:57 ` Joonas Lahtinen
0 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-02-20 14:57 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
Quoting Chris Wilson (2018-02-20 10:45:17)
> Ensure that we always use every context at least once before we start
> running the stress-test.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> tests/gem_ctx_switch.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/tests/gem_ctx_switch.c b/tests/gem_ctx_switch.c
> index 4db902b1..e0ab3d18 100644
> --- a/tests/gem_ctx_switch.c
> +++ b/tests/gem_ctx_switch.c
> @@ -101,6 +101,13 @@ static void single(int fd, uint32_t handle,
> struct timespec start, now;
> unsigned int count = 0;
>
> + /* Warmup */
/* Warmup to make sure ... */
To make sure what, this is not a benchmark?
Regards, Joonas
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH igt 01/16] igt/gem_sync: Exercise and measure idle requests
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
@ 2018-03-05 13:43 ` Joonas Lahtinen
-1 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-03-05 13:43 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
For some reason, I've reviewed these from the middle of the series
(maybe transport delay?). Are the rest still applicable or refreshed
somewhere?
Regards, Joonas
_______________________________________________
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^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [igt-dev] [PATCH igt 01/16] igt/gem_sync: Exercise and measure idle requests
@ 2018-03-05 13:43 ` Joonas Lahtinen
0 siblings, 0 replies; 50+ messages in thread
From: Joonas Lahtinen @ 2018-03-05 13:43 UTC (permalink / raw)
To: Chris Wilson, igt-dev; +Cc: intel-gfx
For some reason, I've reviewed these from the middle of the series
(maybe transport delay?). Are the rest still applicable or refreshed
somewhere?
Regards, Joonas
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH igt 01/16] igt/gem_sync: Exercise and measure idle requests
2018-03-05 13:43 ` [igt-dev] " Joonas Lahtinen
@ 2018-03-05 14:39 ` Chris Wilson
-1 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-03-05 14:39 UTC (permalink / raw)
To: Joonas Lahtinen, igt-dev; +Cc: intel-gfx
Quoting Joonas Lahtinen (2018-03-05 13:43:33)
> For some reason, I've reviewed these from the middle of the series
> (maybe transport delay?). Are the rest still applicable or refreshed
> somewhere?
Virtually all, baring a couple have landed. The current unreviewed pile
now has 7 patches, so in the meantime another 5 have been added...
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [igt-dev] [PATCH igt 01/16] igt/gem_sync: Exercise and measure idle requests
@ 2018-03-05 14:39 ` Chris Wilson
0 siblings, 0 replies; 50+ messages in thread
From: Chris Wilson @ 2018-03-05 14:39 UTC (permalink / raw)
To: Joonas Lahtinen, igt-dev; +Cc: intel-gfx
Quoting Joonas Lahtinen (2018-03-05 13:43:33)
> For some reason, I've reviewed these from the middle of the series
> (maybe transport delay?). Are the rest still applicable or refreshed
> somewhere?
Virtually all, baring a couple have landed. The current unreviewed pile
now has 7 patches, so in the meantime another 5 have been added...
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 50+ messages in thread
end of thread, other threads:[~2018-03-05 14:39 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-20 8:45 [PATCH igt 01/16] igt/gem_sync: Exercise and measure idle requests Chris Wilson
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 02/16] lib: Cache the debugfs mountpoint Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 03/16] lib: Always set mismatching index for igt_find_crc_mismatch Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 04/16] igt/gem_exec_flush: Silence old compiler warning Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 05/16] igt/syncobj: Tidy ye olde compiler warnings Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 06/16] lib: Remove overzealous assertion on gem_set_caching() Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 07/16] igt/gem_exec_schedule: Trim max number of contexts used Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 10:52 ` Joonas Lahtinen
2018-02-20 10:52 ` [Intel-gfx] " Joonas Lahtinen
2018-02-20 8:45 ` [PATCH igt 08/16] igt/gem_exec_schedule: Replace constant 16 with its magic macro Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 10:57 ` Joonas Lahtinen
2018-02-20 10:57 ` [igt-dev] " Joonas Lahtinen
2018-02-20 11:01 ` Chris Wilson
2018-02-20 11:01 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 09/16] igt/gem_fenced_exec_thrash: Use fixed durations Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 10/16] igt/gem_eio: Use slow spinners to inject hangs Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 11:14 ` Joonas Lahtinen
2018-02-20 11:14 ` [Intel-gfx] " Joonas Lahtinen
2018-02-20 8:45 ` [PATCH igt 11/16] igt/gem_eio: Exercise set-wedging against request submission Chris Wilson
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 12/16] igt/gem_ctx_isolation: Check isolation of registers between contexts Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 14:56 ` Joonas Lahtinen
2018-02-20 14:56 ` [igt-dev] " Joonas Lahtinen
2018-02-20 8:45 ` [PATCH igt 13/16] igt/gem_ctx_switch: Do a warmup pass over all contexts Chris Wilson
2018-02-20 8:45 ` [Intel-gfx] " Chris Wilson
2018-02-20 14:57 ` Joonas Lahtinen
2018-02-20 14:57 ` [igt-dev] " Joonas Lahtinen
2018-02-20 8:45 ` [PATCH igt 14/16] igt/gem_ctx_switch: Exercise all engines at once Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 15/16] igt/gem_exec_capture: Exercise readback of userptr Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 8:45 ` [PATCH igt 16/16] igt/gem_exec_fence: Exercise merging fences Chris Wilson
2018-02-20 8:45 ` [igt-dev] " Chris Wilson
2018-02-20 9:09 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [01/16] igt/gem_sync: Exercise and measure idle requests Patchwork
2018-02-20 10:02 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2018-03-05 13:43 ` [PATCH igt 01/16] " Joonas Lahtinen
2018-03-05 13:43 ` [igt-dev] " Joonas Lahtinen
2018-03-05 14:39 ` Chris Wilson
2018-03-05 14:39 ` [igt-dev] " Chris Wilson
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