[PATCH 00/16] Adding NV12 support

[PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
	have been addressed. Had missed out tested-by/reviewed-by in the patches.

	Fixed that error in this series.
	Review comments from Ville (11th July 2017) addressed.
	Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
	Rebased the series.
	Tested with IGT for rotation, sprite and tiling combinations.
	IGT Links:
	https://patchwork.kernel.org/patch/9995943/
	https://patchwork.kernel.org/patch/9995945/
	Review comments by Maarten are addressed in this series.
	NV12 enabled for Gen10.
	Review comments from Shashank Sharma are addressed.
	IGT debug_fs test failure fixed.

Update from previous version:
	Added reviewed-by tag from Shashank Sharma for few patches
	Addressed review comments from Shashank Sharma in few patches
	Rebased the series

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h      |  10 +-
 drivers/gpu/drm/i915/i915_reg.h      |   8 +
 drivers/gpu/drm/i915/intel_atomic.c  |  13 +-
 drivers/gpu/drm/i915/intel_display.c |  59 ++++-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_pm.c      | 438 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |  20 +-
 7 files changed, 369 insertions(+), 188 deletions(-)

-- 
2.7.4

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[PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.

s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe

Changes since V1:
 - also change name of skl_copy_wm_for_pipe

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 16 ++++++++--------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fdcb2dc..e9e03c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1455,7 +1455,7 @@ struct skl_ddb_allocation {
 	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
-struct skl_wm_values {
+struct skl_ddb_values {
 	unsigned dirty_pipes;
 	struct skl_ddb_allocation ddb;
 };
@@ -2151,7 +2151,7 @@ struct drm_i915_private {
 		/* current hardware state */
 		union {
 			struct ilk_wm_values hw;
-			struct skl_wm_values skl_hw;
+			struct skl_ddb_values skl_hw;
 			struct vlv_wm_values vlv;
 			struct g4x_wm_values g4x;
 		};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 50874f4..4f45a98 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -481,7 +481,7 @@ struct intel_atomic_state {
 	bool skip_intermediate_wm;
 
 	/* Gen9+ only */
-	struct skl_wm_values wm_results;
+	struct skl_ddb_values wm_results;
 
 	struct i915_sw_fence commit_ready;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index abf80e4..0550b5e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5042,9 +5042,9 @@ skl_compute_ddb(struct drm_atomic_state *state)
 }
 
 static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
-		     struct skl_wm_values *src,
-		     enum pipe pipe)
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+		      struct skl_ddb_values *src,
+		      enum pipe pipe)
 {
 	memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
 	       sizeof(dst->ddb.y_plane[pipe]));
@@ -5095,7 +5095,7 @@ skl_compute_wm(struct drm_atomic_state *state)
 	struct drm_crtc *crtc;
 	struct drm_crtc_state *cstate;
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct skl_wm_values *results = &intel_state->wm_results;
+	struct skl_ddb_values *results = &intel_state->wm_results;
 	struct drm_device *dev = state->dev;
 	struct skl_pipe_wm *pipe_wm;
 	bool changed = false;
@@ -5197,8 +5197,8 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct skl_wm_values *results = &state->wm_results;
-	struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
+	struct skl_ddb_values *results = &state->wm_results;
+	struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
 	enum pipe pipe = intel_crtc->pipe;
 
 	if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -5209,7 +5209,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	if (cstate->base.active_changed)
 		skl_atomic_update_crtc_wm(state, cstate);
 
-	skl_copy_wm_for_pipe(hw_vals, results, pipe);
+	skl_copy_ddb_for_pipe(hw_vals, results, pipe);
 
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
@@ -5341,7 +5341,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 void skl_wm_get_hw_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
+	struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
 	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
 	struct drm_crtc *crtc;
 	struct intel_crtc *intel_crtc;
-- 
2.7.4

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[PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.

v2: Addressed review comments by Maarten

v3: Rebased and addressed review comments by Maarten

v4: Fixed a compilation issue of string replacement is_nv12 to
is_planar

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |   5 +-
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c  | 121 ++++++++++++++++++++-------------------
 3 files changed, 66 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9e03c2..81ab25d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1451,8 +1451,9 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
-	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+	/* packed/y */
+	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
+	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
 struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 4f45a98..5c5528f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -598,6 +598,7 @@ struct intel_pipe_wm {
 struct skl_plane_wm {
 	struct skl_wm_level wm[8];
 	struct skl_wm_level trans_wm;
+	bool is_planar;
 };
 
 struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0550b5e..01bb3a0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4009,9 +4009,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 static unsigned int
 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 			     const struct drm_plane_state *pstate,
-			     int y)
+			     const int plane)
 {
-	struct intel_plane *plane = to_intel_plane(pstate->plane);
+	struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
 	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
 	uint32_t data_rate;
 	uint32_t width = 0, height = 0;
@@ -4025,9 +4025,9 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 	fb = pstate->fb;
 	format = fb->format->format;
 
-	if (plane->id == PLANE_CURSOR)
+	if (intel_plane->id == PLANE_CURSOR)
 		return 0;
-	if (y && format != DRM_FORMAT_NV12)
+	if (plane == 1 && format != DRM_FORMAT_NV12)
 		return 0;
 
 	/*
@@ -4038,19 +4038,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 	width = drm_rect_width(&intel_pstate->base.src) >> 16;
 	height = drm_rect_height(&intel_pstate->base.src) >> 16;
 
-	/* for planar format */
-	if (format == DRM_FORMAT_NV12) {
-		if (y)  /* y-plane data rate */
-			data_rate = width * height *
-				fb->format->cpp[0];
-		else    /* uv-plane data rate */
-			data_rate = (width / 2) * (height / 2) *
-				fb->format->cpp[1];
-	} else {
-		/* for packed formats */
-		data_rate = width * height * fb->format->cpp[0];
+	/* UV plane does 1/2 pixel sub-sampling */
+	if (plane == 1 && format == DRM_FORMAT_NV12) {
+		width /= 2;
+		height /= 2;
 	}
 
+	data_rate = width * height * fb->format->cpp[plane];
+
 	down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
 
 	return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4063,8 +4058,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
  */
 static unsigned int
 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
-				 unsigned *plane_data_rate,
-				 unsigned *plane_y_data_rate)
+				 unsigned int *plane_data_rate,
+				 unsigned int *uv_plane_data_rate)
 {
 	struct drm_crtc_state *cstate = &intel_cstate->base;
 	struct drm_atomic_state *state = cstate->state;
@@ -4080,17 +4075,17 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
 		enum plane_id plane_id = to_intel_plane(plane)->id;
 		unsigned int rate;
 
-		/* packed/uv */
+		/* packed/y */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 0);
 		plane_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 
-		/* y-plane */
+		/* uv-plane */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 1);
-		plane_y_data_rate[plane_id] = rate;
+		uv_plane_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 	}
@@ -4099,8 +4094,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
 }
 
 static uint16_t
-skl_ddb_min_alloc(const struct drm_plane_state *pstate,
-		  const int y)
+skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
 {
 	struct drm_framebuffer *fb = pstate->fb;
 	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
@@ -4111,8 +4105,8 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
 	if (WARN_ON(!fb))
 		return 0;
 
-	/* For packed formats, no y-plane, return 0 */
-	if (y && fb->format->format != DRM_FORMAT_NV12)
+	/* For packed formats, and uv-plane, return 0 */
+	if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
 		return 0;
 
 	/* For Non Y-tile return 8-blocks */
@@ -4131,15 +4125,12 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
 	src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
 
 	/* Halve UV plane width and height for NV12 */
-	if (fb->format->format == DRM_FORMAT_NV12 && !y) {
+	if (plane == 1) {
 		src_w /= 2;
 		src_h /= 2;
 	}
 
-	if (fb->format->format == DRM_FORMAT_NV12 && !y)
-		plane_bpp = fb->format->cpp[1];
-	else
-		plane_bpp = fb->format->cpp[0];
+	plane_bpp = fb->format->cpp[plane];
 
 	if (drm_rotation_90_or_270(pstate->rotation)) {
 		switch (plane_bpp) {
@@ -4167,7 +4158,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
 
 static void
 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
-		 uint16_t *minimum, uint16_t *y_minimum)
+		 uint16_t *minimum, uint16_t *uv_minimum)
 {
 	const struct drm_plane_state *pstate;
 	struct drm_plane *plane;
@@ -4182,7 +4173,7 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
 			continue;
 
 		minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
-		y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
+		uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
 	}
 
 	minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -4200,17 +4191,17 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
 	uint16_t alloc_size, start;
 	uint16_t minimum[I915_MAX_PLANES] = {};
-	uint16_t y_minimum[I915_MAX_PLANES] = {};
+	uint16_t uv_minimum[I915_MAX_PLANES] = {};
 	unsigned int total_data_rate;
 	enum plane_id plane_id;
 	int num_active;
-	unsigned plane_data_rate[I915_MAX_PLANES] = {};
-	unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
+	unsigned int plane_data_rate[I915_MAX_PLANES] = {};
+	unsigned int uv_plane_data_rate[I915_MAX_PLANES] = {};
 	uint16_t total_min_blocks = 0;
 
 	/* Clear the partitioning for disabled planes. */
 	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
-	memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
+	memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
 
 	if (WARN_ON(!state))
 		return 0;
@@ -4225,7 +4216,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	if (alloc_size == 0)
 		return 0;
 
-	skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
+	skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);
 
 	/*
 	 * 1. Allocate the mininum required blocks for each active plane
@@ -4235,7 +4226,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 
 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
 		total_min_blocks += minimum[plane_id];
-		total_min_blocks += y_minimum[plane_id];
+		total_min_blocks += uv_minimum[plane_id];
 	}
 
 	if (total_min_blocks > alloc_size) {
@@ -4257,14 +4248,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	 */
 	total_data_rate = skl_get_total_relative_data_rate(cstate,
 							   plane_data_rate,
-							   plane_y_data_rate);
+							   uv_plane_data_rate);
 	if (total_data_rate == 0)
 		return 0;
 
 	start = alloc->start;
 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
-		unsigned int data_rate, y_data_rate;
-		uint16_t plane_blocks, y_plane_blocks = 0;
+		unsigned int data_rate, uv_data_rate;
+		uint16_t plane_blocks, uv_plane_blocks;
 
 		if (plane_id == PLANE_CURSOR)
 			continue;
@@ -4288,21 +4279,20 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 
 		start += plane_blocks;
 
-		/*
-		 * allocation for y_plane part of planar format:
-		 */
-		y_data_rate = plane_y_data_rate[plane_id];
+		/* Allocate DDB for UV plane for planar format/NV12 */
+		uv_data_rate = uv_plane_data_rate[plane_id];
 
-		y_plane_blocks = y_minimum[plane_id];
-		y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
-					total_data_rate);
+		uv_plane_blocks = uv_minimum[plane_id];
+		uv_plane_blocks += div_u64((uint64_t)alloc_size * uv_data_rate,
+					   total_data_rate);
 
-		if (y_data_rate) {
-			ddb->y_plane[pipe][plane_id].start = start;
-			ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
+		if (uv_data_rate) {
+			ddb->uv_plane[pipe][plane_id].start = start;
+			ddb->uv_plane[pipe][plane_id].end =
+				start + uv_plane_blocks;
 		}
 
-		start += y_plane_blocks;
+		start += uv_plane_blocks;
 	}
 
 	return 0;
@@ -4430,8 +4420,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
 	}
 
-	wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
-							    fb->format->cpp[0];
+	wp->cpp = fb->format->cpp[0];
 	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 							     intel_pstate);
 
@@ -4660,6 +4649,9 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 			return ret;
 	}
 
+	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
+		wm->is_planar = true;
+
 	return 0;
 }
 
@@ -4833,10 +4825,21 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 
 	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
 			    &ddb->plane[pipe][plane_id]);
-	if (INTEL_GEN(dev_priv) < 11)
+	if (INTEL_GEN(dev_priv) >= 11)
+		return skl_ddb_entry_write(dev_priv,
+					   PLANE_BUF_CFG(pipe, plane_id),
+					   &ddb->plane[pipe][plane_id]);
+	if (wm->is_planar) {
+		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+				    &ddb->uv_plane[pipe][plane_id]);
 		skl_ddb_entry_write(dev_priv,
 				    PLANE_NV12_BUF_CFG(pipe, plane_id),
-				    &ddb->y_plane[pipe][plane_id]);
+				    &ddb->plane[pipe][plane_id]);
+	} else {
+		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+				    &ddb->plane[pipe][plane_id]);
+		I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
+	}
 }
 
 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
@@ -4951,8 +4954,8 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
 
 		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
 					&new_ddb->plane[pipe][plane_id]) &&
-		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
-					&new_ddb->y_plane[pipe][plane_id]))
+		    skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
+					&new_ddb->uv_plane[pipe][plane_id]))
 			continue;
 
 		plane_state = drm_atomic_get_plane_state(state, plane);
@@ -5046,8 +5049,8 @@ skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
 		      struct skl_ddb_values *src,
 		      enum pipe pipe)
 {
-	memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
-	       sizeof(dst->ddb.y_plane[pipe]));
+	memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
+	       sizeof(dst->ddb.uv_plane[pipe]));
 	memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
 	       sizeof(dst->ddb.plane[pipe]));
 }
-- 
2.7.4

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[PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.

v2: Added reviewed by tag from Mika Kahola

Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5d46771..2bb3d34 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2644,6 +2644,8 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 	switch (format) {
 	case PLANE_CTL_FORMAT_RGB_565:
 		return DRM_FORMAT_RGB565;
+	case PLANE_CTL_FORMAT_NV12:
+		return DRM_FORMAT_NV12;
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
-- 
2.7.4

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[PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

For YUV 420 Planar formats like NV12,
buffer allocation is done for Y and UV surfaces separately.
For NV12 plane formats, the UV buffer
allocation must be programmed in the Plane Buffer Config register
and the Y buffer allocation must be programmed in the
Plane NV12 Buffer Config register. Both register values
should be verified during verify_wm_state.

v2: Addressed review comments by Maarten.

v3: Addressed review comments by Shashank Sharma.

v4: Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_pm.c      | 51 +++++++++++++++++++++++++++++-------
 3 files changed, 43 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2bb3d34..eba3e74 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2639,7 +2639,7 @@ static int i9xx_format_to_fourcc(int format)
 	}
 }
 
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 {
 	switch (format) {
 	case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5c5528f..d5a6242 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1602,6 +1602,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
 			    struct intel_plane_state *plane_state);
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 
 /* intel_csr.c */
 void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 01bb3a0..1095e20 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3825,6 +3825,44 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 		entry->end += 1;
 }
 
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+			   const enum pipe pipe,
+			   const enum plane_id plane_id,
+			   struct skl_ddb_allocation *ddb /* out */)
+{
+	u32 val, val2 = 0;
+	int fourcc, pixel_format;
+
+	/* Cursor doesn't support NV12/planar, so no extra calculation needed */
+	if (plane_id == PLANE_CURSOR) {
+		val = I915_READ(CUR_BUF_CFG(pipe));
+		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+		return;
+	}
+
+	val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+	/* No DDB allocated for disabled planes */
+	if (!(val & PLANE_CTL_ENABLE))
+		return;
+
+	pixel_format = val & PLANE_CTL_FORMAT_MASK;
+	fourcc = skl_format_to_fourcc(pixel_format,
+				      val & PLANE_CTL_ORDER_RGBX,
+				      val & PLANE_CTL_ALPHA_MASK);
+
+	val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+	val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+	if (fourcc == DRM_FORMAT_NV12) {
+		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
+		skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
+	} else {
+		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+	}
+}
+
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */)
 {
@@ -3841,16 +3879,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 			continue;
 
-		for_each_plane_id_on_crtc(crtc, plane_id) {
-			u32 val;
-
-			if (plane_id != PLANE_CURSOR)
-				val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-			else
-				val = I915_READ(CUR_BUF_CFG(pipe));
-
-			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
-		}
+		for_each_plane_id_on_crtc(crtc, plane_id)
+			skl_ddb_get_hw_plane_state(dev_priv, pipe,
+						   plane_id, ddb);
 
 		intel_display_power_put(dev_priv, power_domain);
 	}
-- 
2.7.4

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[PATCH 05/16] drm/i915/skl+: NV12 related changes for WM

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

v2: Addressed review comments from Shashank Sharma.

v3: Addressed review comments from Shashank Sharma
Changed plane_num to plane_id in skl_compute_plane_wm_params
and skl_compute_plane_wm.
Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 50 +++++++++++++++++++++++++++++++++-------
 3 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 81ab25d..c64c846 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1471,6 +1471,7 @@ struct skl_wm_level {
 struct skl_wm_params {
 	bool x_tiled, y_tiled;
 	bool rc_surface;
+	bool is_planar;
 	uint32_t width;
 	uint8_t cpp;
 	uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d5a6242..d2f58cc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -597,6 +597,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
 	struct skl_wm_level wm[8];
+	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
 	bool is_planar;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1095e20..1545ead 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4419,7 +4419,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 			    struct intel_crtc_state *cstate,
 			    const struct intel_plane_state *intel_pstate,
-			    struct skl_wm_params *wp)
+			    struct skl_wm_params *wp, int plane_id)
 {
 	struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
 	const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4432,6 +4432,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 	if (!intel_wm_plane_visible(cstate, intel_pstate))
 		return 0;
 
+	/* only NV12 format has two planes */
+	if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) {
+		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+		return -EINVAL;
+	}
+
 	wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 		      fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 		      fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4439,6 +4445,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 	wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
 	wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 			 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+	wp->is_planar = fb->format->format == DRM_FORMAT_NV12;
 
 	if (plane->id == PLANE_CURSOR) {
 		wp->width = intel_pstate->base.crtc_w;
@@ -4451,7 +4458,10 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
 	}
 
-	wp->cpp = fb->format->cpp[0];
+	if (plane_id == 1 && wp->is_planar)
+		wp->width /= 2;
+
+	wp->cpp = fb->format->cpp[plane_id];
 	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 							     intel_pstate);
 
@@ -4649,7 +4659,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 		      struct intel_crtc_state *cstate,
 		      const struct intel_plane_state *intel_pstate,
 		      const struct skl_wm_params *wm_params,
-		      struct skl_plane_wm *wm)
+		      struct skl_plane_wm *wm,
+		      int plane_id)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
 	struct drm_plane *plane = intel_pstate->base.plane;
@@ -4657,15 +4668,19 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 	uint16_t ddb_blocks;
 	enum pipe pipe = intel_crtc->pipe;
 	int level, max_level = ilk_wm_max_level(dev_priv);
+	enum plane_id intel_plane_id = intel_plane->id;
 	int ret;
 
 	if (WARN_ON(!intel_pstate->base.fb))
 		return -EINVAL;
 
-	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
+	ddb_blocks = plane_id ?
+		     skl_ddb_entry_size(&ddb->uv_plane[pipe][intel_plane_id]) :
+		     skl_ddb_entry_size(&ddb->plane[pipe][intel_plane_id]);
 
 	for (level = 0; level <= max_level; level++) {
-		struct skl_wm_level *result = &wm->wm[level];
+		struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] :
+							  &wm->wm[level];
 
 		ret = skl_compute_plane_wm(dev_priv,
 					   cstate,
@@ -4792,20 +4807,39 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 
 		wm = &pipe_wm->planes[plane_id];
 		ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
-		memset(&wm_params, 0, sizeof(struct skl_wm_params));
 
 		ret = skl_compute_plane_wm_params(dev_priv, cstate,
-						  intel_pstate, &wm_params);
+						  intel_pstate, &wm_params, 0);
 		if (ret)
 			return ret;
 
 		ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
-					    intel_pstate, &wm_params, wm);
+					    intel_pstate, &wm_params, wm, 0);
 		if (ret)
 			return ret;
+
 		skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
 					  ddb_blocks, &wm->trans_wm);
+
+		/* uv plane watermarks must also be validated for NV12/Planar */
+		if (wm_params.is_planar) {
+			memset(&wm_params, 0, sizeof(struct skl_wm_params));
+			wm->is_planar = true;
+
+			ret = skl_compute_plane_wm_params(dev_priv, cstate,
+							  intel_pstate,
+							  &wm_params, 1);
+			if (ret)
+				return ret;
+
+			ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
+						    intel_pstate, &wm_params,
+						    wm, 1);
+			if (ret)
+				return ret;
+		}
 	}
+
 	pipe_wm->linetime = skl_compute_linetime_wm(cstate);
 
 	return 0;
-- 
2.7.4

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[PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This patch passes skl_wm_level structure itself to watermark
computation function skl_compute_plane_wm function (instead
of its internal parameters). It reduces number of arguments
required to be passed.

v2: Addressed review comments by Shashank Sharma

v3: Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1545ead..96d05b4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4529,9 +4529,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				uint16_t ddb_allocation,
 				int level,
 				const struct skl_wm_params *wp,
-				uint16_t *out_blocks, /* out */
-				uint8_t *out_lines, /* out */
-				bool *enabled /* out */)
+				struct skl_wm_level *result /* out */)
 {
 	const struct drm_plane_state *pstate = &intel_pstate->base;
 	uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4545,7 +4543,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
 	if (latency == 0 ||
 	    !intel_wm_plane_visible(cstate, intel_pstate)) {
-		*enabled = false;
+		result->plane_en = false;
 		return 0;
 	}
 
@@ -4626,7 +4624,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	if ((level > 0 && res_lines > 31) ||
 	    res_blocks >= ddb_allocation ||
 	    min_disp_buf_needed >= ddb_allocation) {
-		*enabled = false;
+		result->plane_en = false;
 
 		/*
 		 * If there are no valid level 0 watermarks, then we can't
@@ -4646,9 +4644,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	}
 
 	/* The number of lines are ignored for the level 0 watermark. */
-	*out_lines = level ? res_lines : 0;
-	*out_blocks = res_blocks;
-	*enabled = true;
+	result->plane_res_b = res_blocks;
+	result->plane_res_l = res_lines;
+	result->plane_en = true;
 
 	return 0;
 }
@@ -4688,9 +4686,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 					   ddb_blocks,
 					   level,
 					   wm_params,
-					   &result->plane_res_b,
-					   &result->plane_res_l,
-					   &result->plane_en);
+					   result);
 		if (ret)
 			return ret;
 	}
-- 
2.7.4

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[PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below the
current level. Render decompression requires level WM to be as high as
wm level-0. This patch fulfils both the requirements.

v2: Changed plane_num to plane_id in skl_compute_wm_levels

v3: Addressed review comments from Shashank Sharma
Changed the commit message "statement can be more clear,
"DDB value to be as high as level below " what is level below ?"

v4: Added reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 96d05b4..6c6e5dc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4529,6 +4529,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				uint16_t ddb_allocation,
 				int level,
 				const struct skl_wm_params *wp,
+				const struct skl_wm_level *result_prev,
 				struct skl_wm_level *result /* out */)
 {
 	const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4596,6 +4597,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		} else {
 			res_blocks++;
 		}
+
+		/*
+		 * Make sure result blocks for higher latency levels are atleast
+		 * as high as level below the current level.
+		 * Assumption in DDB algorithm optimization for special cases.
+		 * Also covers Display WA #1125 for RC.
+		 */
+		if (result_prev->plane_res_b > res_blocks)
+			res_blocks = result_prev->plane_res_b;
 	}
 
 	if (INTEL_GEN(dev_priv) >= 11) {
@@ -4679,6 +4689,13 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] :
 							  &wm->wm[level];
+		struct skl_wm_level *result_prev;
+
+		if (level)
+			result_prev = plane_id ? &wm->uv_wm[level - 1] :
+						  &wm->wm[level - 1];
+		else
+			result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0];
 
 		ret = skl_compute_plane_wm(dev_priv,
 					   cstate,
@@ -4686,6 +4703,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 					   ddb_blocks,
 					   level,
 					   wm_params,
+					   result_prev,
 					   result);
 		if (ret)
 			return ret;
-- 
2.7.4

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[PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.

v2: Addressed review comments by Maarten.

v3: Adding reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6c6e5dc..878c29d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4653,6 +4653,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		}
 	}
 
+	/*
+	 * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+	 * disable wm level 1-7 on NV12 planes
+	 */
+	if (wp->is_planar && level >= 1 &&
+	    (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+	     IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+		result->plane_en = false;
+		return 0;
+	}
+
 	/* The number of lines are ignored for the level 0 watermark. */
 	result->plane_res_b = res_blocks;
 	result->plane_res_l = res_lines;
-- 
2.7.4

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[PATCH 09/16] drm/i915/skl: split skl_compute_ddb function

[Vidya Srinivas]

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.

v2: Added reviewed by tag from Shashank Sharma

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 157 ++++++++++++++++++++++------------------
 1 file changed, 88 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 878c29d..beb9335 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5059,69 +5059,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
 static int
 skl_compute_ddb(struct drm_atomic_state *state)
 {
-	struct drm_device *dev = state->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	const struct drm_i915_private *dev_priv = to_i915(state->dev);
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct intel_crtc *intel_crtc;
 	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
-	uint32_t realloc_pipes = pipes_modified(state);
-	int ret;
-
-	/*
-	 * If this is our first atomic update following hardware readout,
-	 * we can't trust the DDB that the BIOS programmed for us.  Let's
-	 * pretend that all pipes switched active status so that we'll
-	 * ensure a full DDB recompute.
-	 */
-	if (dev_priv->wm.distrust_bios_wm) {
-		ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
-				       state->acquire_ctx);
-		if (ret)
-			return ret;
-
-		intel_state->active_pipe_changes = ~0;
-
-		/*
-		 * We usually only initialize intel_state->active_crtcs if we
-		 * we're doing a modeset; make sure this field is always
-		 * initialized during the sanitization process that happens
-		 * on the first commit too.
-		 */
-		if (!intel_state->modeset)
-			intel_state->active_crtcs = dev_priv->active_crtcs;
-	}
-
-	/*
-	 * If the modeset changes which CRTC's are active, we need to
-	 * recompute the DDB allocation for *all* active pipes, even
-	 * those that weren't otherwise being modified in any way by this
-	 * atomic commit.  Due to the shrinking of the per-pipe allocations
-	 * when new active CRTC's are added, it's possible for a pipe that
-	 * we were already using and aren't changing at all here to suddenly
-	 * become invalid if its DDB needs exceeds its new allocation.
-	 *
-	 * Note that if we wind up doing a full DDB recompute, we can't let
-	 * any other display updates race with this transaction, so we need
-	 * to grab the lock on *all* CRTC's.
-	 */
-	if (intel_state->active_pipe_changes) {
-		realloc_pipes = ~0;
-		intel_state->wm_results.dirty_pipes = ~0;
-	}
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *cstate;
+	int ret, i;
 
-	/*
-	 * We're not recomputing for the pipes not included in the commit, so
-	 * make sure we start with the current state.
-	 */
 	memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
 
-	for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
-		struct intel_crtc_state *cstate;
-
-		cstate = intel_atomic_get_crtc_state(state, intel_crtc);
-		if (IS_ERR(cstate))
-			return PTR_ERR(cstate);
-
+	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
 		ret = skl_allocate_pipe_ddb(cstate, ddb);
 		if (ret)
 			return ret;
@@ -5183,23 +5130,23 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
 }
 
 static int
-skl_compute_wm(struct drm_atomic_state *state)
+skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
 {
-	struct drm_crtc *crtc;
-	struct drm_crtc_state *cstate;
-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct skl_ddb_values *results = &intel_state->wm_results;
 	struct drm_device *dev = state->dev;
-	struct skl_pipe_wm *pipe_wm;
-	bool changed = false;
+	const struct drm_i915_private *dev_priv = to_i915(dev);
+	const struct drm_crtc *crtc;
+	const struct drm_crtc_state *cstate;
+	struct intel_crtc *intel_crtc;
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	uint32_t realloc_pipes = pipes_modified(state);
 	int ret, i;
 
 	/*
 	 * When we distrust bios wm we always need to recompute to set the
 	 * expected DDB allocations for each CRTC.
 	 */
-	if (to_i915(dev)->wm.distrust_bios_wm)
-		changed = true;
+	if (dev_priv->wm.distrust_bios_wm)
+		*changed = true;
 
 	/*
 	 * If this transaction isn't actually touching any CRTC's, don't
@@ -5210,14 +5157,86 @@ skl_compute_wm(struct drm_atomic_state *state)
 	 * hold _all_ CRTC state mutexes.
 	 */
 	for_each_new_crtc_in_state(state, crtc, cstate, i)
-		changed = true;
+		*changed = true;
 
-	if (!changed)
+	if (!*changed)
 		return 0;
 
+	/*
+	 * If this is our first atomic update following hardware readout,
+	 * we can't trust the DDB that the BIOS programmed for us.  Let's
+	 * pretend that all pipes switched active status so that we'll
+	 * ensure a full DDB recompute.
+	 */
+	if (dev_priv->wm.distrust_bios_wm) {
+		ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
+				       state->acquire_ctx);
+		if (ret)
+			return ret;
+
+		intel_state->active_pipe_changes = ~0;
+
+		/*
+		 * We usually only initialize intel_state->active_crtcs if we
+		 * we're doing a modeset; make sure this field is always
+		 * initialized during the sanitization process that happens
+		 * on the first commit too.
+		 */
+		if (!intel_state->modeset)
+			intel_state->active_crtcs = dev_priv->active_crtcs;
+	}
+
+	/*
+	 * If the modeset changes which CRTC's are active, we need to
+	 * recompute the DDB allocation for *all* active pipes, even
+	 * those that weren't otherwise being modified in any way by this
+	 * atomic commit.  Due to the shrinking of the per-pipe allocations
+	 * when new active CRTC's are added, it's possible for a pipe that
+	 * we were already using and aren't changing at all here to suddenly
+	 * become invalid if its DDB needs exceeds its new allocation.
+	 *
+	 * Note that if we wind up doing a full DDB recompute, we can't let
+	 * any other display updates race with this transaction, so we need
+	 * to grab the lock on *all* CRTC's.
+	 */
+	if (intel_state->active_pipe_changes) {
+		realloc_pipes = ~0;
+		intel_state->wm_results.dirty_pipes = ~0;
+	}
+
+	/*
+	 * We're not recomputing for the pipes not included in the commit, so
+	 * make sure we start with the current state.
+	 */
+	for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
+		struct intel_crtc_state *cstate;
+
+		cstate = intel_atomic_get_crtc_state(state, intel_crtc);
+		if (IS_ERR(cstate))
+			return PTR_ERR(cstate);
+	}
+
+	return 0;
+}
+
+static int
+skl_compute_wm(struct drm_atomic_state *state)
+{
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *cstate;
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	struct skl_ddb_values *results = &intel_state->wm_results;
+	struct skl_pipe_wm *pipe_wm;
+	bool changed = false;
+	int ret, i;
+
 	/* Clear all dirty flags */
 	results->dirty_pipes = 0;
 
+	ret = skl_ddb_add_affected_pipes(state, &changed);
+	if (ret || !changed)
+		return ret;
+
 	ret = skl_compute_ddb(state);
 	if (ret)
 		return ret;
-- 
2.7.4

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[PATCH 10/16] drm/i915: Set scaler mode for NV12

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling

v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler

v3: Rebased (me)

v4: Rebased (me)

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.

v9: Rebased (me)

v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
code is applicable to all GEN >= 9. Hence making
that change to keep it generic.
Comments under v8 is not valid anymore.

v11: Addressed review comments by Shashank Sharma.
For Gen10+, the scaler mode to be set it planar or normal
(single bit). Changed the code to be applicable to all
Gen.

v12: Addressed review comments from Shashank Sharma
For Gen9 (apart from GLK) bits 28:29 to be programmed
in PS_CTRL for NV12. For GLK and Gen10+, bit 29 to be set
for all Planar.

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     |  2 ++
 drivers/gpu/drm/i915/intel_atomic.c | 13 +++++++++++--
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1412abc..4349d81 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6732,6 +6732,8 @@ enum {
 #define PS_SCALER_MODE_MASK (3 << 28)
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
+#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
+#define PS_SCALER_MODE_PLANAR (1 << 29)
 #define PS_PLANE_SEL_MASK  (7 << 25)
 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
 #define PS_FILTER_MASK         (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index e9fb6920..5b2ae8c 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -328,8 +328,17 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 		}
 
 		/* set scaler mode */
-		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-			scaler_state->scalers[*scaler_id].mode = 0;
+		if ((INTEL_GEN(dev_priv) >= 9) &&
+		    plane_state && plane_state->base.fb &&
+		    plane_state->base.fb->format->format ==
+		    DRM_FORMAT_NV12) {
+			if (INTEL_GEN(dev_priv) == 9 &&
+			    !IS_GEMINILAKE(dev_priv))
+				scaler_state->scalers[*scaler_id].mode =
+					SKL_PS_SCALER_MODE_NV12;
+			else
+				scaler_state->scalers[*scaler_id].mode =
+					PS_SCALER_MODE_PLANAR;
 		} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
 			/*
 			 * when only 1 scaler is in use on either pipe A or B,
-- 
2.7.4

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[PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to format_is_yuv() function
for sprite planes.

v2:
-Use intel_ prefix for format_is_yuv (Ville)

v3: Rebased (me)

v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Changed intel_format_is_yuv function from
static to non-static. We need to use it later from
other files for check.

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_drv.h    | 1 +
 drivers/gpu/drm/i915/intel_sprite.c | 8 ++++----
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d2f58cc..e64483b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2039,6 +2039,7 @@ void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
 bool skl_plane_get_hw_state(struct intel_plane *plane);
 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
 		       enum pipe pipe, enum plane_id plane_id);
+bool intel_format_is_yuv(uint32_t format);
 
 /* intel_tv.c */
 void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index e098e4b..2c51d8a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -41,14 +41,14 @@
 #include <drm/i915_drm.h>
 #include "i915_drv.h"
 
-static bool
-format_is_yuv(uint32_t format)
+bool intel_format_is_yuv(uint32_t format)
 {
 	switch (format) {
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_YVYU:
+	case DRM_FORMAT_NV12:
 		return true;
 	default:
 		return false;
@@ -352,7 +352,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
 	enum plane_id plane_id = plane->id;
 
 	/* Seems RGB data bypasses the CSC always */
-	if (!format_is_yuv(format))
+	if (!intel_format_is_yuv(format))
 		return;
 
 	/*
@@ -979,7 +979,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
 		src_y = src->y1 >> 16;
 		src_h = drm_rect_height(src) >> 16;
 
-		if (format_is_yuv(fb->format->format)) {
+		if (intel_format_is_yuv(fb->format->format)) {
 			src_x &= ~1;
 			src_w &= ~1;
 
-- 
2.7.4

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[PATCH 12/16] drm/i915: Upscale scaler max scale for NV12

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch updates scaler max limit support for NV12

v2: Rebased (me)

v3: Rebased (me)

v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series

v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

v10: Rebased (me)

v11: Addressed review comments from Shashank Sharma
Alignment issues fixed.
When call to skl_update_scaler is made, 0 was being
sent instead of pixel_format.
When crtc update scaler is called, we dont have the
fb to derive the pixel format. Added the function
parameter bool plane_scaler_check to account for this.

v12: Fixed failure in IGT debugfs_test.
fb is NULL in skl_update_scaler_plane
Due to this, accessing fb->format caused failure.
Patch checks fb before using.

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 40 ++++++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  3 ++-
 3 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eba3e74..142dfe0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3455,6 +3455,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
 	case DRM_FORMAT_VYUY:
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+	case DRM_FORMAT_NV12:
+		return PLANE_CTL_FORMAT_NV12;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -4678,7 +4680,9 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		  unsigned int scaler_user, int *scaler_id,
-		  int src_w, int src_h, int dst_w, int dst_h)
+		  int src_w, int src_h, int dst_w, int dst_h,
+		  bool plane_scaler_check,
+		  uint32_t pixel_format)
 {
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
@@ -4696,6 +4700,9 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	 */
 	need_scaling = src_w != dst_w || src_h != dst_h;
 
+	if (plane_scaler_check)
+		need_scaling = pixel_format == DRM_FORMAT_NV12;
+
 	if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
 		need_scaling = true;
 
@@ -4771,9 +4778,10 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
 	const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
 
 	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
-		&state->scaler_state.scaler_id,
-		state->pipe_src_w, state->pipe_src_h,
-		adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+				 &state->scaler_state.scaler_id,
+				 state->pipe_src_w, state->pipe_src_h,
+				 adjusted_mode->crtc_hdisplay,
+				 adjusted_mode->crtc_vdisplay, false, 0);
 }
 
 /**
@@ -4802,7 +4810,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 				drm_rect_width(&plane_state->base.src) >> 16,
 				drm_rect_height(&plane_state->base.src) >> 16,
 				drm_rect_width(&plane_state->base.dst),
-				drm_rect_height(&plane_state->base.dst));
+				drm_rect_height(&plane_state->base.dst),
+				fb ? true : false, fb ? fb->format->format : 0);
 
 	if (ret || plane_state->scaler_id < 0)
 		return ret;
@@ -4828,6 +4837,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+	case DRM_FORMAT_NV12:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -12799,11 +12809,13 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 }
 
 int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+	      struct intel_crtc_state *crtc_state,
+	      uint32_t pixel_format)
 {
 	struct drm_i915_private *dev_priv;
-	int max_scale;
-	int crtc_clock, max_dotclk;
+	int max_scale, mult;
+	int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
 
 	if (!intel_crtc || !crtc_state->base.enable)
 		return DRM_PLANE_HELPER_NO_SCALING;
@@ -12825,8 +12837,10 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 	 *            or
 	 *    cdclk/crtc_clock
 	 */
-	max_scale = min((1 << 16) * 3 - 1,
-			(1 << 8) * ((max_dotclk << 8) / crtc_clock));
+	mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+	tmpclk1 = (1 << 16) * mult - 1;
+	tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
+	max_scale = min(tmpclk1, tmpclk2);
 
 	return max_scale;
 }
@@ -12843,12 +12857,16 @@ intel_check_primary_plane(struct intel_plane *plane,
 	bool can_position = false;
 	struct drm_rect clip = {};
 	int ret;
+	uint32_t pixel_format = 0;
 
 	if (INTEL_GEN(dev_priv) >= 9) {
 		/* use scaler when colorkey is not required */
 		if (!state->ckey.flags) {
 			min_scale = 1;
-			max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+			if (state->base.fb)
+				pixel_format = state->base.fb->format->format;
+			max_scale = skl_max_scale(to_intel_crtc(crtc),
+						  crtc_state, pixel_format);
 		}
 		can_position = true;
 	}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index e64483b..23faea4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1587,7 +1587,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 				 struct intel_crtc_state *pipe_config);
 
 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+		  uint32_t pixel_format);
 
 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
 {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2c51d8a..77a5433 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -897,7 +897,8 @@ intel_check_sprite_plane(struct intel_plane *plane,
 		if (!state->ckey.flags) {
 			can_scale = 1;
 			min_scale = 1;
-			max_scale = skl_max_scale(crtc, crtc_state);
+			max_scale = skl_max_scale(crtc, crtc_state,
+						  fb->format->format);
 		} else {
 			can_scale = 0;
 			min_scale = DRM_PLANE_HELPER_NO_SCALING;
-- 
2.7.4

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[PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats

v5: Rebased (me)

v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v7: Review comments by Ville addressed
	Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)

v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.

v9: Rebased (me)

v10: Addressed review comments from Maarten.
	Adding NV12 inside skl_primary_formats itself.

v11: Adding Reviewed By tag from Shashank Sharma

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 142dfe0..1870366 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
 	DRM_FORMAT_YVYU,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
 };
 
 static const uint64_t skl_format_modifiers_noccs[] = {
@@ -13282,6 +13283,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		intel_primary_formats = skl_primary_formats;
 		num_formats = ARRAY_SIZE(skl_primary_formats);
 
+		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
+		    !IS_GEMINILAKE(dev_priv))
+			num_formats -= 1;
+
 		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
 			modifiers = skl_format_modifiers_ccs;
 		else
-- 
2.7.4

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[PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)

v9: Rebased (me)

v10: Addressed review comments from Maarten.
Adding NV12 to skl_plane_formats itself.

v11: Addressed review comments from Shashank Sharma

v12: Addressed review comments from Shashank Sharma
Made the condition in intel_sprite_plane_create
simple and easy to read as suggested.

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 77a5433..20e23e5 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1171,6 +1171,7 @@ static uint32_t skl_plane_formats[] = {
 	DRM_FORMAT_YVYU,
 	DRM_FORMAT_UYVY,
 	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
 };
 
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
@@ -1369,6 +1370,14 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		plane_formats = skl_plane_formats;
 		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
 
+		if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
+			if (plane != 0)
+				num_plane_formats -= 1;
+		} else {
+			if (plane != 0 || pipe != PIPE_C)
+				num_plane_formats -= 1;
+		}
+
 		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
 			modifiers = skl_plane_format_modifiers_ccs;
 		else
-- 
2.7.4

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[PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init

[Vidya Srinivas]

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.

v9: Rebased (me)

v10: NV12 supported by all GEN >= 9.
Making this change in intel_framebuffer_init. This is
part of addressing Maarten's review comments.
Comment under v8 no longer applicable

v11: Addressed review comments from Shashank Sharma

v12: Adding Reviewed By from Shashank Sharma

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1870366..755cad8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14090,6 +14090,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 		break;
+	case DRM_FORMAT_NV12:
+		if (INTEL_GEN(dev_priv) < 9) {
+			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+				      drm_get_format_name(mode_cmd->pixel_format,
+				      &format_name));
+			goto err;
+		}
+		break;
 	default:
 		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
-- 
2.7.4

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[PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

[Vidya Srinivas]

If the fb format is YUV, enable the plane CSC mode bits
for the conversion.

v2: Addressed review comments from Shashank Sharma
Alignment issue fixed in i915_reg.h

v3: Adding Reviewed By from Shashank Sharma

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 6 ++++++
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4349d81..0a6d5c2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6453,6 +6453,12 @@ enum {
 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE		(1 << 30)
 #define   PLANE_COLOR_PIPE_CSC_ENABLE		(1 << 23)
+#define   PLANE_COLOR_CSC_MASK			(0x7 << 17)
+#define   PLANE_COLOR_CSC_MODE_BYPASS		(0 << 17)
+#define   PLANE_COLOR_YUV601_TO_RGB709		(1 << 17)
+#define   PLANE_COLOR_YUV709_TO_RGB709		(2 << 17)
+#define   PLANE_COLOR_YUV2020_TO_RGB2020	(3 << 17)
+#define   PLANE_COLOR_RGB709_TO_RGB2020		(4 << 17)
 #define   PLANE_COLOR_PLANE_GAMMA_DISABLE	(1 << 13)
 #define   PLANE_COLOR_ALPHA_MASK		(0x3 << 4)
 #define   PLANE_COLOR_ALPHA_DISABLE		(0 << 4)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 755cad8..567b026 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3597,6 +3597,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 	plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
 	plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
 	plane_color_ctl |= glk_plane_color_ctl_alpha(fb->format->format);
+	if (fb && intel_format_is_yuv(fb->format->format))
+		plane_color_ctl |= PLANE_COLOR_YUV709_TO_RGB709;
 
 	return plane_color_ctl;
 }
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for Adding NV12 support (rev12)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev12)
URL   : https://patchwork.freedesktop.org/series/28103/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
74d9f6f867c3 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
98b6c62d8823 drm/i915/skl+: refactor WM calculation for NV12
-:180: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#180: FILE: drivers/gpu/drm/i915/intel_pm.c:4161:
+		 uint16_t *minimum, uint16_t *uv_minimum)

-:198: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#198: FILE: drivers/gpu/drm/i915/intel_pm.c:4194:
+	uint16_t uv_minimum[I915_MAX_PLANES] = {};

-:247: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#247: FILE: drivers/gpu/drm/i915/intel_pm.c:4258:
+		uint16_t plane_blocks, uv_plane_blocks;

total: 0 errors, 0 warnings, 3 checks, 293 lines checked
e7bed55f2300 drm/i915/skl+: add NV12 in skl_format_to_fourcc
dcb163b39ae8 drm/i915/skl+: support verification of DDB HW state for NV12
aff9ae9cb3cc drm/i915/skl+: NV12 related changes for WM
414af2a56424 drm/i915/skl+: pass skl_wm_level struct to wm compute func
549c2d5d8959 drm/i915/skl+: make sure higher latency level has higher wm value
b3ad682adbe1 drm/i915/skl+: nv12 workaround disable WM level 1-7
d97663cbb43c drm/i915/skl: split skl_compute_ddb function
-:113: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#113: FILE: drivers/gpu/drm/i915/intel_pm.c:5141:
+	uint32_t realloc_pipes = pipes_modified(state);

-:132: CHECK: spaces preferred around that '*' (ctx:ExV)
#132: FILE: drivers/gpu/drm/i915/intel_pm.c:5160:
+		*changed = true;
 		^

total: 0 errors, 0 warnings, 2 checks, 194 lines checked
e6098d6cedba drm/i915: Set scaler mode for NV12
-:61: CHECK: Prefer using the BIT macro
#61: FILE: drivers/gpu/drm/i915/i915_reg.h:6736:
+#define PS_SCALER_MODE_PLANAR (1 << 29)

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
ac93c9b078ee drm/i915: Update format_is_yuv() to include NV12
0918e6a75626 drm/i915: Upscale scaler max scale for NV12
-:152: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#152: FILE: drivers/gpu/drm/i915/intel_display.c:12860:
+	uint32_t pixel_format = 0;

total: 0 errors, 0 warnings, 1 checks, 119 lines checked
edeae0e55aa9 drm/i915: Add NV12 as supported format for primary plane
07e8b4d97358 drm/i915: Add NV12 as supported format for sprite plane
e87d0de91200 drm/i915: Add NV12 support to intel_framebuffer_init
-:64: WARNING: line over 80 characters
#64: FILE: drivers/gpu/drm/i915/intel_display.c:14096:
+				      drm_get_format_name(mode_cmd->pixel_format,

-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_display.c:14097:
+				      drm_get_format_name(mode_cmd->pixel_format,
+				      &format_name));

total: 0 errors, 1 warnings, 1 checks, 14 lines checked
60ae191c5d46 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:27: CHECK: Prefer using the BIT macro
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define   PLANE_COLOR_YUV601_TO_RGB709		(1 << 17)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked

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Re: [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane

[Sharma, Shashank]

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>

Regards
Shashank
On 2/21/2018 3:50 PM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 to list of supported formats for sprite plane.
>
> v2: Rebased (me)
>
> v3: Review comments by Ville addressed
> - Removed skl_plane_formats_with_nv12 and added
> NV12 case in existing skl_plane_formats
> - Added the 10bpc RGB formats
>
> v4: Addressed review comments from Clinton A Taylor
> "Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though
> the modes are advertised for the planes"
> - Removed 10bit RGB formats added previously with NV12 series
>
> v5: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
> Addressed review comments from Clinton A Taylor
> "Why are we adding 10 bit RGB formats with the NV12 series patches?
> Trying to set XR30 or AB30 results in error returned even though
> the modes are advertised for the planes"
> - Previous version has 10bit RGB format removed from VLV formats
> by mistake. Fixing that in this version.
> Removed 10bit RGB formats added previously with NV12 series
> for SKL.
>
> v6: Addressed review comments by Ville
> Restricting the NV12 to BXT and PIPE A and B
>
> v7: Rebased (me)
>
> v8: Rebased (me)
> Restricting NV12 changes to BXT and KBL
> Restricting NV12 changes for plane 0 (overlay)
>
> v9: Rebased (me)
>
> v10: Addressed review comments from Maarten.
> Adding NV12 to skl_plane_formats itself.
>
> v11: Addressed review comments from Shashank Sharma
>
> v12: Addressed review comments from Shashank Sharma
> Made the condition in intel_sprite_plane_create
> simple and easy to read as suggested.
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_sprite.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 77a5433..20e23e5 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1171,6 +1171,7 @@ static uint32_t skl_plane_formats[] = {
>   	DRM_FORMAT_YVYU,
>   	DRM_FORMAT_UYVY,
>   	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_NV12,
>   };
>   
>   static const uint64_t skl_plane_format_modifiers_noccs[] = {
> @@ -1369,6 +1370,14 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>   		plane_formats = skl_plane_formats;
>   		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
>   
> +		if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) == 10) {
> +			if (plane != 0)
> +				num_plane_formats -= 1;
> +		} else {
> +			if (plane != 0 || pipe != PIPE_C)
> +				num_plane_formats -= 1;
> +		}
> +
>   		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_SPRITE0 + plane))
>   			modifiers = skl_plane_format_modifiers_ccs;
>   		else

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✗ Fi.CI.BAT: failure for Adding NV12 support (rev12)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev12)
URL   : https://patchwork.freedesktop.org/series/28103/
State : failure

== Summary ==

Series 28103v12 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/12/mbox/

Test gem_mmap_gtt:
        Subgroup basic-small-bo-tiledx:
                fail       -> PASS       (fi-gdg-551) fdo#102575
Test kms_chamelium:
        Subgroup dp-edid-read:
                pass       -> FAIL       (fi-kbl-7500u) fdo#102505
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                pass       -> INCOMPLETE (fi-hsw-4770)

fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:416s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:374s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:488s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:288s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:476s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:480s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:471s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:454s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:566s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:412s
fi-gdg-551       total:288  pass:180  dwarn:0   dfail:0   fail:0   skip:108 time:283s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:508s
fi-hsw-4770      total:246  pass:222  dwarn:0   dfail:0   fail:0   skip:23 
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:409s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:453s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:412s
fi-kbl-7500u     total:288  pass:262  dwarn:1   dfail:0   fail:1   skip:24  time:461s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:490s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:452s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:493s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:594s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:434s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:501s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:524s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:488s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:481s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:408s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:428s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:527s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:394s

75f20d94e9a1fdc486867a8f5bebe433b119f531 drm-tip: 2018y-02m-21d-07h-35m-14s UTC integration manifest
60ae191c5d46 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
e87d0de91200 drm/i915: Add NV12 support to intel_framebuffer_init
07e8b4d97358 drm/i915: Add NV12 as supported format for sprite plane
edeae0e55aa9 drm/i915: Add NV12 as supported format for primary plane
0918e6a75626 drm/i915: Upscale scaler max scale for NV12
ac93c9b078ee drm/i915: Update format_is_yuv() to include NV12
e6098d6cedba drm/i915: Set scaler mode for NV12
d97663cbb43c drm/i915/skl: split skl_compute_ddb function
b3ad682adbe1 drm/i915/skl+: nv12 workaround disable WM level 1-7
549c2d5d8959 drm/i915/skl+: make sure higher latency level has higher wm value
414af2a56424 drm/i915/skl+: pass skl_wm_level struct to wm compute func
aff9ae9cb3cc drm/i915/skl+: NV12 related changes for WM
dcb163b39ae8 drm/i915/skl+: support verification of DDB HW state for NV12
e7bed55f2300 drm/i915/skl+: add NV12 in skl_format_to_fourcc
98b6c62d8823 drm/i915/skl+: refactor WM calculation for NV12
74d9f6f867c3 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8100/issues.html
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✗ Fi.CI.CHECKPATCH: warning for Adding NV12 support (rev12)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev12)
URL   : https://patchwork.freedesktop.org/series/28103/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
bcaef9063e6b drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
2f18b9726ab8 drm/i915/skl+: refactor WM calculation for NV12
-:180: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#180: FILE: drivers/gpu/drm/i915/intel_pm.c:4161:
+		 uint16_t *minimum, uint16_t *uv_minimum)

-:198: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#198: FILE: drivers/gpu/drm/i915/intel_pm.c:4194:
+	uint16_t uv_minimum[I915_MAX_PLANES] = {};

-:247: CHECK: Prefer kernel type 'u16' over 'uint16_t'
#247: FILE: drivers/gpu/drm/i915/intel_pm.c:4258:
+		uint16_t plane_blocks, uv_plane_blocks;

total: 0 errors, 0 warnings, 3 checks, 293 lines checked
8cc4ae0ab64a drm/i915/skl+: add NV12 in skl_format_to_fourcc
3c482886a3e0 drm/i915/skl+: support verification of DDB HW state for NV12
d81bfc5007a6 drm/i915/skl+: NV12 related changes for WM
7f7db5c9f0a5 drm/i915/skl+: pass skl_wm_level struct to wm compute func
f9d74e780509 drm/i915/skl+: make sure higher latency level has higher wm value
1799584a0027 drm/i915/skl+: nv12 workaround disable WM level 1-7
739a92a9f739 drm/i915/skl: split skl_compute_ddb function
-:113: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#113: FILE: drivers/gpu/drm/i915/intel_pm.c:5141:
+	uint32_t realloc_pipes = pipes_modified(state);

-:132: CHECK: spaces preferred around that '*' (ctx:ExV)
#132: FILE: drivers/gpu/drm/i915/intel_pm.c:5160:
+		*changed = true;
 		^

total: 0 errors, 0 warnings, 2 checks, 194 lines checked
debb41aa8125 drm/i915: Set scaler mode for NV12
-:61: CHECK: Prefer using the BIT macro
#61: FILE: drivers/gpu/drm/i915/i915_reg.h:6736:
+#define PS_SCALER_MODE_PLANAR (1 << 29)

total: 0 errors, 0 warnings, 1 checks, 27 lines checked
80d7e4fdc8e1 drm/i915: Update format_is_yuv() to include NV12
18c91d98376c drm/i915: Upscale scaler max scale for NV12
-:152: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#152: FILE: drivers/gpu/drm/i915/intel_display.c:12860:
+	uint32_t pixel_format = 0;

total: 0 errors, 0 warnings, 1 checks, 119 lines checked
b804cd678b39 drm/i915: Add NV12 as supported format for primary plane
c2060bb9afa8 drm/i915: Add NV12 as supported format for sprite plane
a9e9ba5791b7 drm/i915: Add NV12 support to intel_framebuffer_init
-:64: WARNING: line over 80 characters
#64: FILE: drivers/gpu/drm/i915/intel_display.c:14096:
+				      drm_get_format_name(mode_cmd->pixel_format,

-:65: CHECK: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/intel_display.c:14097:
+				      drm_get_format_name(mode_cmd->pixel_format,
+				      &format_name));

total: 0 errors, 1 warnings, 1 checks, 14 lines checked
26664b13b281 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
-:27: CHECK: Prefer using the BIT macro
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:6458:
+#define   PLANE_COLOR_YUV601_TO_RGB709		(1 << 17)

total: 0 errors, 0 warnings, 1 checks, 20 lines checked

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Re: [PATCH 10/16] drm/i915: Set scaler mode for NV12

[Sharma, Shashank]

Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>

Regards
Shashank
On 2/21/2018 3:50 PM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch sets appropriate scaler mode for NV12 format.
> In this mode, skylake scaler does either chroma-upsampling or
> chroma-upsampling and resolution scaling
>
> v2: Review comments from Ville addressed
> NV12 case to be checked first for setting
> the scaler
>
> v3: Rebased (me)
>
> v4: Rebased (me)
>
> v5: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
>
> v6: Rebased (me)
>
> v7: Rebased (me)
>
> v8: Rebased (me)
> Restricting the NV12 change for scaler to BXT and KBL
> in this series.
>
> v9: Rebased (me)
>
> v10: As of now, NV12 has been tested on Gen9 and Gen10. However,
> code is applicable to all GEN >= 9. Hence making
> that change to keep it generic.
> Comments under v8 is not valid anymore.
>
> v11: Addressed review comments by Shashank Sharma.
> For Gen10+, the scaler mode to be set it planar or normal
> (single bit). Changed the code to be applicable to all
> Gen.
>
> v12: Addressed review comments from Shashank Sharma
> For Gen9 (apart from GLK) bits 28:29 to be programmed
> in PS_CTRL for NV12. For GLK and Gen10+, bit 29 to be set
> for all Planar.
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h     |  2 ++
>   drivers/gpu/drm/i915/intel_atomic.c | 13 +++++++++++--
>   2 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1412abc..4349d81 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6732,6 +6732,8 @@ enum {
>   #define PS_SCALER_MODE_MASK (3 << 28)
>   #define PS_SCALER_MODE_DYN  (0 << 28)
>   #define PS_SCALER_MODE_HQ  (1 << 28)
> +#define SKL_PS_SCALER_MODE_NV12 (2 << 28)
> +#define PS_SCALER_MODE_PLANAR (1 << 29)
>   #define PS_PLANE_SEL_MASK  (7 << 25)
>   #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
>   #define PS_FILTER_MASK         (3 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index e9fb6920..5b2ae8c 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -328,8 +328,17 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>   		}
>   
>   		/* set scaler mode */
> -		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> -			scaler_state->scalers[*scaler_id].mode = 0;
> +		if ((INTEL_GEN(dev_priv) >= 9) &&
> +		    plane_state && plane_state->base.fb &&
> +		    plane_state->base.fb->format->format ==
> +		    DRM_FORMAT_NV12) {
> +			if (INTEL_GEN(dev_priv) == 9 &&
> +			    !IS_GEMINILAKE(dev_priv))
> +				scaler_state->scalers[*scaler_id].mode =
> +					SKL_PS_SCALER_MODE_NV12;
> +			else
> +				scaler_state->scalers[*scaler_id].mode =
> +					PS_SCALER_MODE_PLANAR;
>   		} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
>   			/*
>   			 * when only 1 scaler is in use on either pipe A or B,

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✓ Fi.CI.BAT: success for Adding NV12 support (rev12)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev12)
URL   : https://patchwork.freedesktop.org/series/28103/
State : success

== Summary ==

Series 28103v12 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/12/mbox/

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-b:
                pass       -> INCOMPLETE (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:415s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:373s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:486s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:283s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:476s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:478s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:465s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:454s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:554s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:412s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:281s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:508s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:384s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:409s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:454s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:411s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:450s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:489s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:450s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:492s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:586s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:436s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:499s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:518s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:483s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:472s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:408s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:427s
fi-snb-2520m     total:245  pass:211  dwarn:0   dfail:0   fail:0   skip:33 
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:390s

75f20d94e9a1fdc486867a8f5bebe433b119f531 drm-tip: 2018y-02m-21d-07h-35m-14s UTC integration manifest
26664b13b281 drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
a9e9ba5791b7 drm/i915: Add NV12 support to intel_framebuffer_init
c2060bb9afa8 drm/i915: Add NV12 as supported format for sprite plane
b804cd678b39 drm/i915: Add NV12 as supported format for primary plane
18c91d98376c drm/i915: Upscale scaler max scale for NV12
80d7e4fdc8e1 drm/i915: Update format_is_yuv() to include NV12
debb41aa8125 drm/i915: Set scaler mode for NV12
739a92a9f739 drm/i915/skl: split skl_compute_ddb function
1799584a0027 drm/i915/skl+: nv12 workaround disable WM level 1-7
f9d74e780509 drm/i915/skl+: make sure higher latency level has higher wm value
7f7db5c9f0a5 drm/i915/skl+: pass skl_wm_level struct to wm compute func
d81bfc5007a6 drm/i915/skl+: NV12 related changes for WM
3c482886a3e0 drm/i915/skl+: support verification of DDB HW state for NV12
8cc4ae0ab64a drm/i915/skl+: add NV12 in skl_format_to_fourcc
2f18b9726ab8 drm/i915/skl+: refactor WM calculation for NV12
bcaef9063e6b drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8103/issues.html
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Re: [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Juha-Pekka Heikkila]

On 21.02.2018 12:20, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru@intel.com>
> 
> This patch adds NV12 to list of supported formats for
> primary plane
> 
> v2: Rebased (Chandra Konduru)
> 
> v3: Rebased (me)
> 
> v4: Review comments by Ville addressed
> Removed the skl_primary_formats_with_nv12 and
> added NV12 case in existing skl_primary_formats
> 
> v5: Rebased (me)
> 
> v6: Missed the Tested-by/Reviewed-by in the previous series
> Adding the same to commit message in this version.
> 
> v7: Review comments by Ville addressed
> 	Restricting the NV12 for BXT and on PIPE A and B
> Rebased (me)
> 
> v8: Rebased (me)
> Modified restricting the NV12 support for both BXT and KBL.
> 
> v9: Rebased (me)
> 
> v10: Addressed review comments from Maarten.
> 	Adding NV12 inside skl_primary_formats itself.
> 
> v11: Adding Reviewed By tag from Shashank Sharma
> 
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 142dfe0..1870366 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
>   	DRM_FORMAT_YVYU,
>   	DRM_FORMAT_UYVY,
>   	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_NV12,
>   };
>   
>   static const uint64_t skl_format_modifiers_noccs[] = {
> @@ -13282,6 +13283,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>   		intel_primary_formats = skl_primary_formats;
>   		num_formats = ARRAY_SIZE(skl_primary_formats);
>   
> +		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
> +		    !IS_GEMINILAKE(dev_priv))
> +			num_formats -= 1;

This doesn't look future proof solution. This creates invisible 
dependency where it is required NV12 is last item in list of formats.

> +
>   		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
>   			modifiers = skl_format_modifiers_ccs;
>   		else
> 

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✗ Fi.CI.IGT: warning for Adding NV12 support (rev12)

[Patchwork]

== Series Details ==

Series: Adding NV12 support (rev12)
URL   : https://patchwork.freedesktop.org/series/28103/
State : warning

== Summary ==

Test kms_plane_scaling:
        Subgroup pipe-b-scaler-with-rotation:
                pass       -> DMESG-WARN (shard-apl)
        Subgroup pipe-c-scaler-with-rotation:
                pass       -> DMESG-WARN (shard-apl)
        Subgroup pipe-c-scaler-with-pixel-format:
                pass       -> DMESG-WARN (shard-apl) fdo#104727
Test kms_plane:
        Subgroup pixel-format-pipe-c-planes:
                pass       -> DMESG-WARN (shard-apl)
Test kms_flip:
        Subgroup 2x-plain-flip-fb-recreate:
                pass       -> FAIL       (shard-hsw) fdo#100368 +1
        Subgroup 2x-flip-vs-expired-vblank-interruptible:
                fail       -> PASS       (shard-hsw) fdo#102887
Test kms_chv_cursor_fail:
        Subgroup pipe-b-64x64-bottom-edge:
                dmesg-warn -> PASS       (shard-snb) fdo#105185
Test kms_sysfs_edid_timing:
                pass       -> WARN       (shard-apl) fdo#100047

fdo#104727 https://bugs.freedesktop.org/show_bug.cgi?id=104727
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#105185 https://bugs.freedesktop.org/show_bug.cgi?id=105185
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047

shard-apl        total:3367 pass:1760 dwarn:5   dfail:0   fail:8   skip:1592 time:11996s
shard-hsw        total:3429 pass:1757 dwarn:1   dfail:0   fail:5   skip:1665 time:11576s
shard-snb        total:3429 pass:1350 dwarn:1   dfail:0   fail:2   skip:2076 time:6548s
Blacklisted hosts:
shard-kbl        total:3429 pass:1889 dwarn:37  dfail:0   fail:10  skip:1493 time:9740s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8103/shards.html
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Re: [PATCH 00/16] Adding NV12 support

[Maarten Lankhorst]

Op 21-02-18 om 11:20 schreef Vidya Srinivas:
> This patch series is adding NV12 support for Broxton display after rebasing on
> latest drm-tip.
> Initial series of the patches can be found here:
> https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
>
> Previous revision history:
> The first version of patches were reviewed when floated by Chandra in 2015
> but currently there was a design change with respect to
> - the way fb offset is handled
> - the way rotation is handled
> Current NV12 patch series has been ported as per the
> current changes on drm-tip
>
> Review comments from Ville (12th June 2017) have been addressed Review
> comments from Clinton A Taylor (7th July 2017) have been addressed
>
> Review comments from Clinton A Taylor (10th July 2017)
> 	have been addressed. Had missed out tested-by/reviewed-by in the patches.
>
> 	Fixed that error in this series.
> 	Review comments from Ville (11th July 2017) addressed.
> 	Review comments from Paauwe, Bob (29th July 2017) addressed.
>
> Update from rev 28 Aug 2017
> 	Rebased the series.
> 	Tested with IGT for rotation, sprite and tiling combinations.
> 	IGT Links:
> 	https://patchwork.kernel.org/patch/9995943/
> 	https://patchwork.kernel.org/patch/9995945/
> 	Review comments by Maarten are addressed in this series.
> 	NV12 enabled for Gen10.
> 	Review comments from Shashank Sharma are addressed.
> 	IGT debug_fs test failure fixed.
>
> Update from previous version:
> 	Added reviewed-by tag from Shashank Sharma for few patches
> 	Addressed review comments from Shashank Sharma in few patches
> 	Rebased the series
>
> Chandra Konduru (6):
>   drm/i915: Set scaler mode for NV12
>   drm/i915: Update format_is_yuv() to include NV12
>   drm/i915: Upscale scaler max scale for NV12
>   drm/i915: Add NV12 as supported format for primary plane
>   drm/i915: Add NV12 as supported format for sprite plane
>   drm/i915: Add NV12 support to intel_framebuffer_init
>
> Mahesh Kumar (9):
>   drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
>   drm/i915/skl+: refactor WM calculation for NV12
>   drm/i915/skl+: add NV12 in skl_format_to_fourcc
>   drm/i915/skl+: support verification of DDB HW state for NV12
>   drm/i915/skl+: NV12 related changes for WM
>   drm/i915/skl+: pass skl_wm_level struct to wm compute func
>   drm/i915/skl+: make sure higher latency level has higher wm value
>   drm/i915/skl+: nv12 workaround disable WM level 1-7
>   drm/i915/skl: split skl_compute_ddb function
>
> Vidya Srinivas (1):
>   drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
>
>  drivers/gpu/drm/i915/i915_drv.h      |  10 +-
>  drivers/gpu/drm/i915/i915_reg.h      |   8 +
>  drivers/gpu/drm/i915/intel_atomic.c  |  13 +-
>  drivers/gpu/drm/i915/intel_display.c |  59 ++++-
>  drivers/gpu/drm/i915/intel_drv.h     |   9 +-
>  drivers/gpu/drm/i915/intel_pm.c      | 438 ++++++++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_sprite.c  |  20 +-
>  7 files changed, 369 insertions(+), 188 deletions(-)
>
This patch series still has FIFO underruns on kms_plane@pixel-format-* and kms_plane_scaling, could this please be fixed before this gets merged?

https://patchwork.freedesktop.org/series/28103/ Fi.CI.IGT

and also visible on

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8103/shards.html

~Maarten

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Re: [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Srinivas, Vidya]

> -----Original Message-----
> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> Sent: Wednesday, February 21, 2018 7:52 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
> format for primary plane
> 
> On 21.02.2018 12:20, Vidya Srinivas wrote:
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch adds NV12 to list of supported formats for primary plane
> >
> > v2: Rebased (Chandra Konduru)
> >
> > v3: Rebased (me)
> >
> > v4: Review comments by Ville addressed Removed the
> > skl_primary_formats_with_nv12 and added NV12 case in existing
> > skl_primary_formats
> >
> > v5: Rebased (me)
> >
> > v6: Missed the Tested-by/Reviewed-by in the previous series Adding the
> > same to commit message in this version.
> >
> > v7: Review comments by Ville addressed
> > 	Restricting the NV12 for BXT and on PIPE A and B Rebased (me)
> >
> > v8: Rebased (me)
> > Modified restricting the NV12 support for both BXT and KBL.
> >
> > v9: Rebased (me)
> >
> > v10: Addressed review comments from Maarten.
> > 	Adding NV12 inside skl_primary_formats itself.
> >
> > v11: Adding Reviewed By tag from Shashank Sharma
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_display.c | 5 +++++
> >   1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 142dfe0..1870366 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> >   	DRM_FORMAT_YVYU,
> >   	DRM_FORMAT_UYVY,
> >   	DRM_FORMAT_VYUY,
> > +	DRM_FORMAT_NV12,
> >   };
> >
> >   static const uint64_t skl_format_modifiers_noccs[] = { @@ -13282,6
> > +13283,10 @@ intel_primary_plane_create(struct drm_i915_private
> *dev_priv, enum pipe pipe)
> >   		intel_primary_formats = skl_primary_formats;
> >   		num_formats = ARRAY_SIZE(skl_primary_formats);
> >
> > +		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
> > +		    !IS_GEMINILAKE(dev_priv))
> > +			num_formats -= 1;
> 
> This doesn't look future proof solution. This creates invisible dependency
> where it is required NV12 is last item in list of formats.

Initially we had a different array for this. But as a part of one of the review
comments, I made this change.

Regards
Vidya

> 
> > +
> >   		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
> >   			modifiers = skl_format_modifiers_ccs;
> >   		else
> >

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Re: [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Juha-Pekka Heikkila]

On 22.02.2018 04:39, Srinivas, Vidya wrote:
> 
> 
>> -----Original Message-----
>> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
>> Sent: Wednesday, February 21, 2018 7:52 PM
>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
>> format for primary plane
>>
>> On 21.02.2018 12:20, Vidya Srinivas wrote:
>>> From: Chandra Konduru <chandra.konduru@intel.com>
>>>
>>> This patch adds NV12 to list of supported formats for primary plane
>>>
>>> v2: Rebased (Chandra Konduru)
>>>
>>> v3: Rebased (me)
>>>
>>> v4: Review comments by Ville addressed Removed the
>>> skl_primary_formats_with_nv12 and added NV12 case in existing
>>> skl_primary_formats
>>>
>>> v5: Rebased (me)
>>>
>>> v6: Missed the Tested-by/Reviewed-by in the previous series Adding the
>>> same to commit message in this version.
>>>
>>> v7: Review comments by Ville addressed
>>> 	Restricting the NV12 for BXT and on PIPE A and B Rebased (me)
>>>
>>> v8: Rebased (me)
>>> Modified restricting the NV12 support for both BXT and KBL.
>>>
>>> v9: Rebased (me)
>>>
>>> v10: Addressed review comments from Maarten.
>>> 	Adding NV12 inside skl_primary_formats itself.
>>>
>>> v11: Adding Reviewed By tag from Shashank Sharma
>>>
>>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
>>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
>>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
>>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
>>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/intel_display.c | 5 +++++
>>>    1 file changed, 5 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>> b/drivers/gpu/drm/i915/intel_display.c
>>> index 142dfe0..1870366 100644
>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
>>>    	DRM_FORMAT_YVYU,
>>>    	DRM_FORMAT_UYVY,
>>>    	DRM_FORMAT_VYUY,
>>> +	DRM_FORMAT_NV12,
>>>    };
>>>
>>>    static const uint64_t skl_format_modifiers_noccs[] = { @@ -13282,6
>>> +13283,10 @@ intel_primary_plane_create(struct drm_i915_private
>> *dev_priv, enum pipe pipe)
>>>    		intel_primary_formats = skl_primary_formats;
>>>    		num_formats = ARRAY_SIZE(skl_primary_formats);
>>>
>>> +		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
>>> +		    !IS_GEMINILAKE(dev_priv))
>>> +			num_formats -= 1;
>>
>> This doesn't look future proof solution. This creates invisible dependency
>> where it is required NV12 is last item in list of formats.
> 
> Initially we had a different array for this. But as a part of one of the review
> comments, I made this change.

I did see Maarten's comment on your older patch. In my opinion having 
two lists would be more clear. Regardless of opinions on which is better 
you maybe anyway want to reconsider this piece of code as this expose 
NV12 also for Skylake platform.

> 
>>
>>> +
>>>    		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
>>>    			modifiers = skl_format_modifiers_ccs;
>>>    		else
>>>
> 

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Re: [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Srinivas, Vidya]

> -----Original Message-----
> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> Sent: Thursday, February 22, 2018 7:06 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
> format for primary plane
> 
> On 22.02.2018 04:39, Srinivas, Vidya wrote:
> >
> >
> >> -----Original Message-----
> >> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> >> Sent: Wednesday, February 21, 2018 7:52 PM
> >> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
> >> supported format for primary plane
> >>
> >> On 21.02.2018 12:20, Vidya Srinivas wrote:
> >>> From: Chandra Konduru <chandra.konduru@intel.com>
> >>>
> >>> This patch adds NV12 to list of supported formats for primary plane
> >>>
> >>> v2: Rebased (Chandra Konduru)
> >>>
> >>> v3: Rebased (me)
> >>>
> >>> v4: Review comments by Ville addressed Removed the
> >>> skl_primary_formats_with_nv12 and added NV12 case in existing
> >>> skl_primary_formats
> >>>
> >>> v5: Rebased (me)
> >>>
> >>> v6: Missed the Tested-by/Reviewed-by in the previous series Adding
> >>> the same to commit message in this version.
> >>>
> >>> v7: Review comments by Ville addressed
> >>> 	Restricting the NV12 for BXT and on PIPE A and B Rebased (me)
> >>>
> >>> v8: Rebased (me)
> >>> Modified restricting the NV12 support for both BXT and KBL.
> >>>
> >>> v9: Rebased (me)
> >>>
> >>> v10: Addressed review comments from Maarten.
> >>> 	Adding NV12 inside skl_primary_formats itself.
> >>>
> >>> v11: Adding Reviewed By tag from Shashank Sharma
> >>>
> >>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> >>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> >>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> >>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> >>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> >>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/intel_display.c | 5 +++++
> >>>    1 file changed, 5 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>> b/drivers/gpu/drm/i915/intel_display.c
> >>> index 142dfe0..1870366 100644
> >>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> >>>    	DRM_FORMAT_YVYU,
> >>>    	DRM_FORMAT_UYVY,
> >>>    	DRM_FORMAT_VYUY,
> >>> +	DRM_FORMAT_NV12,
> >>>    };
> >>>
> >>>    static const uint64_t skl_format_modifiers_noccs[] = { @@
> >>> -13282,6
> >>> +13283,10 @@ intel_primary_plane_create(struct drm_i915_private
> >> *dev_priv, enum pipe pipe)
> >>>    		intel_primary_formats = skl_primary_formats;
> >>>    		num_formats = ARRAY_SIZE(skl_primary_formats);
> >>>
> >>> +		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
> >>> +		    !IS_GEMINILAKE(dev_priv))
> >>> +			num_formats -= 1;
> >>
> >> This doesn't look future proof solution. This creates invisible
> >> dependency where it is required NV12 is last item in list of formats.
> >
> > Initially we had a different array for this. But as a part of one of
> > the review comments, I made this change.
> 
> I did see Maarten's comment on your older patch. In my opinion having two
> lists would be more clear. Regardless of opinions on which is better you
> maybe anyway want to reconsider this piece of code as this expose
> NV12 also for Skylake platform.

Maarten, could you please add your inputs as well?
I will change the patch according to what we decide.
Thank you.

Regards
Vidya
> 
> >
> >>
> >>> +
> >>>    		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
> >>>    			modifiers = skl_format_modifiers_ccs;
> >>>    		else
> >>>
> >

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Re: [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Juha-Pekka Heikkila]

On 23.02.2018 05:06, Srinivas, Vidya wrote:
> 
> 
>> -----Original Message-----
>> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
>> Sent: Thursday, February 22, 2018 7:06 PM
>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
>> format for primary plane
>>
>> On 22.02.2018 04:39, Srinivas, Vidya wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
>>>> Sent: Wednesday, February 21, 2018 7:52 PM
>>>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
>>>> gfx@lists.freedesktop.org
>>>> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
>>>> supported format for primary plane
>>>>
>>>> On 21.02.2018 12:20, Vidya Srinivas wrote:
>>>>> From: Chandra Konduru <chandra.konduru@intel.com>
>>>>>
>>>>> This patch adds NV12 to list of supported formats for primary plane
>>>>>
>>>>> v2: Rebased (Chandra Konduru)
>>>>>
>>>>> v3: Rebased (me)
>>>>>
>>>>> v4: Review comments by Ville addressed Removed the
>>>>> skl_primary_formats_with_nv12 and added NV12 case in existing
>>>>> skl_primary_formats
>>>>>
>>>>> v5: Rebased (me)
>>>>>
>>>>> v6: Missed the Tested-by/Reviewed-by in the previous series Adding
>>>>> the same to commit message in this version.
>>>>>
>>>>> v7: Review comments by Ville addressed
>>>>> 	Restricting the NV12 for BXT and on PIPE A and B Rebased (me)
>>>>>
>>>>> v8: Rebased (me)
>>>>> Modified restricting the NV12 support for both BXT and KBL.
>>>>>
>>>>> v9: Rebased (me)
>>>>>
>>>>> v10: Addressed review comments from Maarten.
>>>>> 	Adding NV12 inside skl_primary_formats itself.
>>>>>
>>>>> v11: Adding Reviewed By tag from Shashank Sharma
>>>>>
>>>>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
>>>>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>>>>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
>>>>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
>>>>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
>>>>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>>>>> ---
>>>>>     drivers/gpu/drm/i915/intel_display.c | 5 +++++
>>>>>     1 file changed, 5 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
>>>>> b/drivers/gpu/drm/i915/intel_display.c
>>>>> index 142dfe0..1870366 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
>>>>>     	DRM_FORMAT_YVYU,
>>>>>     	DRM_FORMAT_UYVY,
>>>>>     	DRM_FORMAT_VYUY,
>>>>> +	DRM_FORMAT_NV12,
>>>>>     };
>>>>>
>>>>>     static const uint64_t skl_format_modifiers_noccs[] = { @@
>>>>> -13282,6
>>>>> +13283,10 @@ intel_primary_plane_create(struct drm_i915_private
>>>> *dev_priv, enum pipe pipe)
>>>>>     		intel_primary_formats = skl_primary_formats;
>>>>>     		num_formats = ARRAY_SIZE(skl_primary_formats);
>>>>>
>>>>> +		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C) &&
>>>>> +		    !IS_GEMINILAKE(dev_priv))
>>>>> +			num_formats -= 1;
>>>>
>>>> This doesn't look future proof solution. This creates invisible
>>>> dependency where it is required NV12 is last item in list of formats.
>>>
>>> Initially we had a different array for this. But as a part of one of
>>> the review comments, I made this change.
>>
>> I did see Maarten's comment on your older patch. In my opinion having two
>> lists would be more clear. Regardless of opinions on which is better you
>> maybe anyway want to reconsider this piece of code as this expose
>> NV12 also for Skylake platform.
> 
> Maarten, could you please add your inputs as well?
> I will change the patch according to what we decide.
> Thank you.

If other's see it better to keep it in one list I'm ok for that. To me 
it just feel like accident waiting to happen if this list is changed at 
later time for different reasons.

My other comment about Skylake platform, you shouldn't enable NV12 for 
Skylake platform where its documented to have problems (I mean not all 
users of skl_* list but rule out probably something like 
IS_SKYLAKE(..)). For this reason this patch shouldn't be used as is. 
This same story applies for patch #14 of this series, NV12 shouldn't be 
enabled on Skylake platform.

>>>
>>>>
>>>>> +
>>>>>     		if (skl_plane_has_ccs(dev_priv, pipe, PLANE_PRIMARY))
>>>>>     			modifiers = skl_format_modifiers_ccs;
>>>>>     		else
>>>>>
>>>
> 

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Re: [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Srinivas, Vidya]

> -----Original Message-----
> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> Sent: Friday, February 23, 2018 3:35 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
> format for primary plane
> 
> On 23.02.2018 05:06, Srinivas, Vidya wrote:
> >
> >
> >> -----Original Message-----
> >> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> >> Sent: Thursday, February 22, 2018 7:06 PM
> >> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
> >> supported format for primary plane
> >>
> >> On 22.02.2018 04:39, Srinivas, Vidya wrote:
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> >>>> Sent: Wednesday, February 21, 2018 7:52 PM
> >>>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> >>>> gfx@lists.freedesktop.org
> >>>> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
> >>>> supported format for primary plane
> >>>>
> >>>> On 21.02.2018 12:20, Vidya Srinivas wrote:
> >>>>> From: Chandra Konduru <chandra.konduru@intel.com>
> >>>>>
> >>>>> This patch adds NV12 to list of supported formats for primary
> >>>>> plane
> >>>>>
> >>>>> v2: Rebased (Chandra Konduru)
> >>>>>
> >>>>> v3: Rebased (me)
> >>>>>
> >>>>> v4: Review comments by Ville addressed Removed the
> >>>>> skl_primary_formats_with_nv12 and added NV12 case in existing
> >>>>> skl_primary_formats
> >>>>>
> >>>>> v5: Rebased (me)
> >>>>>
> >>>>> v6: Missed the Tested-by/Reviewed-by in the previous series Adding
> >>>>> the same to commit message in this version.
> >>>>>
> >>>>> v7: Review comments by Ville addressed
> >>>>> 	Restricting the NV12 for BXT and on PIPE A and B Rebased (me)
> >>>>>
> >>>>> v8: Rebased (me)
> >>>>> Modified restricting the NV12 support for both BXT and KBL.
> >>>>>
> >>>>> v9: Rebased (me)
> >>>>>
> >>>>> v10: Addressed review comments from Maarten.
> >>>>> 	Adding NV12 inside skl_primary_formats itself.
> >>>>>
> >>>>> v11: Adding Reviewed By tag from Shashank Sharma
> >>>>>
> >>>>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> >>>>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> >>>>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> >>>>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> >>>>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> >>>>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> >>>>> ---
> >>>>>     drivers/gpu/drm/i915/intel_display.c | 5 +++++
> >>>>>     1 file changed, 5 insertions(+)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>>>> b/drivers/gpu/drm/i915/intel_display.c
> >>>>> index 142dfe0..1870366 100644
> >>>>> --- a/drivers/gpu/drm/i915/intel_display.c
> >>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
> >>>>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> >>>>>     	DRM_FORMAT_YVYU,
> >>>>>     	DRM_FORMAT_UYVY,
> >>>>>     	DRM_FORMAT_VYUY,
> >>>>> +	DRM_FORMAT_NV12,
> >>>>>     };
> >>>>>
> >>>>>     static const uint64_t skl_format_modifiers_noccs[] = { @@
> >>>>> -13282,6
> >>>>> +13283,10 @@ intel_primary_plane_create(struct drm_i915_private
> >>>> *dev_priv, enum pipe pipe)
> >>>>>     		intel_primary_formats = skl_primary_formats;
> >>>>>     		num_formats = ARRAY_SIZE(skl_primary_formats);
> >>>>>
> >>>>> +		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C)
> &&
> >>>>> +		    !IS_GEMINILAKE(dev_priv))
> >>>>> +			num_formats -= 1;
> >>>>
> >>>> This doesn't look future proof solution. This creates invisible
> >>>> dependency where it is required NV12 is last item in list of formats.
> >>>
> >>> Initially we had a different array for this. But as a part of one of
> >>> the review comments, I made this change.
> >>
> >> I did see Maarten's comment on your older patch. In my opinion having
> >> two lists would be more clear. Regardless of opinions on which is
> >> better you maybe anyway want to reconsider this piece of code as this
> >> expose
> >> NV12 also for Skylake platform.
> >
> > Maarten, could you please add your inputs as well?
> > I will change the patch according to what we decide.
> > Thank you.
> 
> If other's see it better to keep it in one list I'm ok for that. To me it just feel
> like accident waiting to happen if this list is changed at later time for different
> reasons.
> 
> My other comment about Skylake platform, you shouldn't enable NV12 for
> Skylake platform where its documented to have problems (I mean not all
> users of skl_* list but rule out probably something like IS_SKYLAKE(..)). For
> this reason this patch shouldn't be used as is.
> This same story applies for patch #14 of this series, NV12 shouldn't be
> enabled on Skylake platform.

Thank you. Sure, I will just wait for Maarten's input on the array.
For SKL, I will make the change in the patch and float.

Regards
Vidya

> 
> >>>
> >>>>
> >>>>> +
> >>>>>     		if (skl_plane_has_ccs(dev_priv, pipe,
> PLANE_PRIMARY))
> >>>>>     			modifiers = skl_format_modifiers_ccs;
> >>>>>     		else
> >>>>>
> >>>
> >

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Re: [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Ville Syrjälä]

On Fri, Feb 23, 2018 at 10:08:25AM +0000, Srinivas, Vidya wrote:
> 
> 
> > -----Original Message-----
> > From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> > Sent: Friday, February 23, 2018 3:35 PM
> > To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> > gfx@lists.freedesktop.org
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
> > format for primary plane
> > 
> > On 23.02.2018 05:06, Srinivas, Vidya wrote:
> > >
> > >
> > >> -----Original Message-----
> > >> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> > >> Sent: Thursday, February 22, 2018 7:06 PM
> > >> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> > >> gfx@lists.freedesktop.org
> > >> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
> > >> supported format for primary plane
> > >>
> > >> On 22.02.2018 04:39, Srinivas, Vidya wrote:
> > >>>
> > >>>
> > >>>> -----Original Message-----
> > >>>> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> > >>>> Sent: Wednesday, February 21, 2018 7:52 PM
> > >>>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> > >>>> gfx@lists.freedesktop.org
> > >>>> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
> > >>>> supported format for primary plane
> > >>>>
> > >>>> On 21.02.2018 12:20, Vidya Srinivas wrote:
> > >>>>> From: Chandra Konduru <chandra.konduru@intel.com>
> > >>>>>
> > >>>>> This patch adds NV12 to list of supported formats for primary
> > >>>>> plane
> > >>>>>
> > >>>>> v2: Rebased (Chandra Konduru)
> > >>>>>
> > >>>>> v3: Rebased (me)
> > >>>>>
> > >>>>> v4: Review comments by Ville addressed Removed the
> > >>>>> skl_primary_formats_with_nv12 and added NV12 case in existing
> > >>>>> skl_primary_formats
> > >>>>>
> > >>>>> v5: Rebased (me)
> > >>>>>
> > >>>>> v6: Missed the Tested-by/Reviewed-by in the previous series Adding
> > >>>>> the same to commit message in this version.
> > >>>>>
> > >>>>> v7: Review comments by Ville addressed
> > >>>>> 	Restricting the NV12 for BXT and on PIPE A and B Rebased (me)
> > >>>>>
> > >>>>> v8: Rebased (me)
> > >>>>> Modified restricting the NV12 support for both BXT and KBL.
> > >>>>>
> > >>>>> v9: Rebased (me)
> > >>>>>
> > >>>>> v10: Addressed review comments from Maarten.
> > >>>>> 	Adding NV12 inside skl_primary_formats itself.
> > >>>>>
> > >>>>> v11: Adding Reviewed By tag from Shashank Sharma
> > >>>>>
> > >>>>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > >>>>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > >>>>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> > >>>>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > >>>>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > >>>>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > >>>>> ---
> > >>>>>     drivers/gpu/drm/i915/intel_display.c | 5 +++++
> > >>>>>     1 file changed, 5 insertions(+)
> > >>>>>
> > >>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
> > >>>>> b/drivers/gpu/drm/i915/intel_display.c
> > >>>>> index 142dfe0..1870366 100644
> > >>>>> --- a/drivers/gpu/drm/i915/intel_display.c
> > >>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
> > >>>>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[] = {
> > >>>>>     	DRM_FORMAT_YVYU,
> > >>>>>     	DRM_FORMAT_UYVY,
> > >>>>>     	DRM_FORMAT_VYUY,
> > >>>>> +	DRM_FORMAT_NV12,
> > >>>>>     };
> > >>>>>
> > >>>>>     static const uint64_t skl_format_modifiers_noccs[] = { @@
> > >>>>> -13282,6
> > >>>>> +13283,10 @@ intel_primary_plane_create(struct drm_i915_private
> > >>>> *dev_priv, enum pipe pipe)
> > >>>>>     		intel_primary_formats = skl_primary_formats;
> > >>>>>     		num_formats = ARRAY_SIZE(skl_primary_formats);
> > >>>>>
> > >>>>> +		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C)
> > &&
> > >>>>> +		    !IS_GEMINILAKE(dev_priv))
> > >>>>> +			num_formats -= 1;
> > >>>>
> > >>>> This doesn't look future proof solution. This creates invisible
> > >>>> dependency where it is required NV12 is last item in list of formats.
> > >>>
> > >>> Initially we had a different array for this. But as a part of one of
> > >>> the review comments, I made this change.
> > >>
> > >> I did see Maarten's comment on your older patch. In my opinion having
> > >> two lists would be more clear. Regardless of opinions on which is
> > >> better you maybe anyway want to reconsider this piece of code as this
> > >> expose
> > >> NV12 also for Skylake platform.
> > >
> > > Maarten, could you please add your inputs as well?
> > > I will change the patch according to what we decide.
> > > Thank you.
> > 
> > If other's see it better to keep it in one list I'm ok for that. To me it just feel
> > like accident waiting to happen if this list is changed at later time for different
> > reasons.
> > 
> > My other comment about Skylake platform, you shouldn't enable NV12 for
> > Skylake platform where its documented to have problems (I mean not all
> > users of skl_* list but rule out probably something like IS_SKYLAKE(..)). For
> > this reason this patch shouldn't be used as is.
> > This same story applies for patch #14 of this series, NV12 shouldn't be
> > enabled on Skylake platform.
> 
> Thank you. Sure, I will just wait for Maarten's input on the array.
> For SKL, I will make the change in the patch and float.

Pls add skl_plane_has_nv12() or something along those lines (to match
the skl_plane_has_ccs()).

Also https://patchwork.freedesktop.org/series/39390/ should make life a
bit easier for anyone dealing with SKL plane init code by removing this
silly code duplication we have going on currently.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

[Srinivas, Vidya]

> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> Sent: Tuesday, March 6, 2018 12:30 AM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>
> Cc: juhapekka.heikkila@gmail.com; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported
> format for primary plane
> 
> On Fri, Feb 23, 2018 at 10:08:25AM +0000, Srinivas, Vidya wrote:
> >
> >
> > > -----Original Message-----
> > > From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> > > Sent: Friday, February 23, 2018 3:35 PM
> > > To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> > > gfx@lists.freedesktop.org
> > > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > > Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
> > > supported format for primary plane
> > >
> > > On 23.02.2018 05:06, Srinivas, Vidya wrote:
> > > >
> > > >
> > > >> -----Original Message-----
> > > >> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> > > >> Sent: Thursday, February 22, 2018 7:06 PM
> > > >> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> > > >> gfx@lists.freedesktop.org
> > > >> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
> > > >> supported format for primary plane
> > > >>
> > > >> On 22.02.2018 04:39, Srinivas, Vidya wrote:
> > > >>>
> > > >>>
> > > >>>> -----Original Message-----
> > > >>>> From: Juha-Pekka Heikkila [mailto:juhapekka.heikkila@gmail.com]
> > > >>>> Sent: Wednesday, February 21, 2018 7:52 PM
> > > >>>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> > > >>>> gfx@lists.freedesktop.org
> > > >>>> Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as
> > > >>>> supported format for primary plane
> > > >>>>
> > > >>>> On 21.02.2018 12:20, Vidya Srinivas wrote:
> > > >>>>> From: Chandra Konduru <chandra.konduru@intel.com>
> > > >>>>>
> > > >>>>> This patch adds NV12 to list of supported formats for primary
> > > >>>>> plane
> > > >>>>>
> > > >>>>> v2: Rebased (Chandra Konduru)
> > > >>>>>
> > > >>>>> v3: Rebased (me)
> > > >>>>>
> > > >>>>> v4: Review comments by Ville addressed Removed the
> > > >>>>> skl_primary_formats_with_nv12 and added NV12 case in existing
> > > >>>>> skl_primary_formats
> > > >>>>>
> > > >>>>> v5: Rebased (me)
> > > >>>>>
> > > >>>>> v6: Missed the Tested-by/Reviewed-by in the previous series
> > > >>>>> Adding the same to commit message in this version.
> > > >>>>>
> > > >>>>> v7: Review comments by Ville addressed
> > > >>>>> 	Restricting the NV12 for BXT and on PIPE A and B Rebased
> (me)
> > > >>>>>
> > > >>>>> v8: Rebased (me)
> > > >>>>> Modified restricting the NV12 support for both BXT and KBL.
> > > >>>>>
> > > >>>>> v9: Rebased (me)
> > > >>>>>
> > > >>>>> v10: Addressed review comments from Maarten.
> > > >>>>> 	Adding NV12 inside skl_primary_formats itself.
> > > >>>>>
> > > >>>>> v11: Adding Reviewed By tag from Shashank Sharma
> > > >>>>>
> > > >>>>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > > >>>>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > > >>>>> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
> > > >>>>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > > >>>>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > > >>>>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > > >>>>> ---
> > > >>>>>     drivers/gpu/drm/i915/intel_display.c | 5 +++++
> > > >>>>>     1 file changed, 5 insertions(+)
> > > >>>>>
> > > >>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > >>>>> b/drivers/gpu/drm/i915/intel_display.c
> > > >>>>> index 142dfe0..1870366 100644
> > > >>>>> --- a/drivers/gpu/drm/i915/intel_display.c
> > > >>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
> > > >>>>> @@ -86,6 +86,7 @@ static const uint32_t skl_primary_formats[]
> = {
> > > >>>>>     	DRM_FORMAT_YVYU,
> > > >>>>>     	DRM_FORMAT_UYVY,
> > > >>>>>     	DRM_FORMAT_VYUY,
> > > >>>>> +	DRM_FORMAT_NV12,
> > > >>>>>     };
> > > >>>>>
> > > >>>>>     static const uint64_t skl_format_modifiers_noccs[] = { @@
> > > >>>>> -13282,6
> > > >>>>> +13283,10 @@ intel_primary_plane_create(struct
> > > >>>>> +drm_i915_private
> > > >>>> *dev_priv, enum pipe pipe)
> > > >>>>>     		intel_primary_formats = skl_primary_formats;
> > > >>>>>     		num_formats = ARRAY_SIZE(skl_primary_formats);
> > > >>>>>
> > > >>>>> +		if ((INTEL_GEN(dev_priv) == 9 && pipe == PIPE_C)
> > > &&
> > > >>>>> +		    !IS_GEMINILAKE(dev_priv))
> > > >>>>> +			num_formats -= 1;
> > > >>>>
> > > >>>> This doesn't look future proof solution. This creates invisible
> > > >>>> dependency where it is required NV12 is last item in list of
> formats.
> > > >>>
> > > >>> Initially we had a different array for this. But as a part of
> > > >>> one of the review comments, I made this change.
> > > >>
> > > >> I did see Maarten's comment on your older patch. In my opinion
> > > >> having two lists would be more clear. Regardless of opinions on
> > > >> which is better you maybe anyway want to reconsider this piece of
> > > >> code as this expose
> > > >> NV12 also for Skylake platform.
> > > >
> > > > Maarten, could you please add your inputs as well?
> > > > I will change the patch according to what we decide.
> > > > Thank you.
> > >
> > > If other's see it better to keep it in one list I'm ok for that. To
> > > me it just feel like accident waiting to happen if this list is
> > > changed at later time for different reasons.
> > >
> > > My other comment about Skylake platform, you shouldn't enable NV12
> > > for Skylake platform where its documented to have problems (I mean
> > > not all users of skl_* list but rule out probably something like
> > > IS_SKYLAKE(..)). For this reason this patch shouldn't be used as is.
> > > This same story applies for patch #14 of this series, NV12 shouldn't
> > > be enabled on Skylake platform.
> >
> > Thank you. Sure, I will just wait for Maarten's input on the array.
> > For SKL, I will make the change in the patch and float.
> 
> Pls add skl_plane_has_nv12() or something along those lines (to match the
> skl_plane_has_ccs()).
> 
> Also https://patchwork.freedesktop.org/series/39390/ should make life a bit
> easier for anyone dealing with SKL plane init code by removing this silly code
> duplication we have going on currently.
> 

Thank you. Will make the changes and float the patches.

Regards
Vidya

> --
> Ville Syrjälä
> Intel OTC
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[PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
	have been addressed. Had missed out tested-by/reviewed-by in the patches.

	Fixed that error in this series.
	Review comments from Ville (11th July 2017) addressed.
	Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
	Rebased the series.
	Tested with IGT for rotation, sprite and tiling combinations.
	IGT Links:
	https://patchwork.kernel.org/patch/9995943/
	https://patchwork.kernel.org/patch/9995945/
	Review comments by Maarten are addressed in this series.
	NV12 enabled for Gen10.
	Review comments from Shashank Sharma are addressed.
	IGT debug_fs test failure fixed.

Update from last rev:
	Addressed review comments from Shashank Sharma and Maarten

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h      |  10 +-
 drivers/gpu/drm/i915/i915_reg.h      |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  59 ++++-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_pm.c      | 436 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |  18 +-
 7 files changed, 360 insertions(+), 187 deletions(-)

-- 
2.7.4

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Re: [PATCH 00/16] Adding NV12 support

[Srinivas, Vidya]

> -----Original Message-----
> From: Kristian Høgsberg [mailto:hoegsberg@gmail.com]
> Sent: Wednesday, February 14, 2018 10:54 AM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 00/16] Adding NV12 support
> 
> On Tue, Feb 13, 2018 at 8:59 PM Vidya Srinivas <vidya.srinivas@intel.com>
> wrote:
> 
> > This patch series is adding NV12 support for Broxton display after
> rebasing on
> > latest drm-tip.
> > Initial series of the patches can be found here:
> > https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html
> 
> I still don't see support for advertising modifiers in this patch set. The series
> should handle NV12 in the supported_modifiers function to indicate which
> tiling and/or compression modifiers are supported for NV12 framebuffers.
> 
> Kristian
> 

Thank you. Apologies. Will address this as an additional patch once
These base series get merged. Would that be okay?

Regards
Vidya

> 
> 
> 
> > Previous revision history:
> > The first version of patches were reviewed when floated by Chandra in
> > 2015 but currently there was a design change with respect to
> > - the way fb offset is handled
> > - the way rotation is handled
> > Current NV12 patch series has been ported as per the current changes
> > on drm-tip
> 
> > Review comments from Ville (12th June 2017) have been addressed
> Review
> > comments from Clinton A Taylor (7th July 2017) have been addressed
> 
> > Review comments from Clinton A Taylor (10th July 2017)
> >          have been addressed. Had missed out tested-by/reviewed-by in
> > the
> patches.
> 
> >          Fixed that error in this series.
> >          Review comments from Ville (11th July 2017) addressed.
> >          Review comments from Paauwe, Bob (29th July 2017) addressed.
> 
> > Update from rev 28 Aug 2017
> >          Rebased the series.
> >          Tested with IGT for rotation, sprite and tiling combinations.
> >          IGT Links:
> >          https://patchwork.kernel.org/patch/9995943/
> >          https://patchwork.kernel.org/patch/9995945/
> >          Review comments by Maarten are addressed in this series.
> >          NV12 enabled for Gen10.
> >          Review comments from Shashank Sharma are addressed.
> 
> > Update from last rev:
> >          IGT debug_fs test failure fixed.
> 
> > Chandra Konduru (6):
> >    drm/i915: Set scaler mode for NV12
> >    drm/i915: Update format_is_yuv() to include NV12
> >    drm/i915: Upscale scaler max scale for NV12
> >    drm/i915: Add NV12 as supported format for primary plane
> >    drm/i915: Add NV12 as supported format for sprite plane
> >    drm/i915: Add NV12 support to intel_framebuffer_init
> 
> > Mahesh Kumar (9):
> >    drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
> >    drm/i915/skl+: refactor WM calculation for NV12
> >    drm/i915/skl+: add NV12 in skl_format_to_fourcc
> >    drm/i915/skl+: support verification of DDB HW state for NV12
> >    drm/i915/skl+: NV12 related changes for WM
> >    drm/i915/skl+: pass skl_wm_level struct to wm compute func
> >    drm/i915/skl+: make sure higher latency level has higher wm value
> >    drm/i915/skl+: nv12 workaround disable WM level 1-7
> >    drm/i915/skl: split skl_compute_ddb function
> 
> > Vidya Srinivas (1):
> >    drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg
> 
> >   drivers/gpu/drm/i915/i915_drv.h      |  10 +-
> >   drivers/gpu/drm/i915/i915_reg.h      |   7 +
> >   drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
> >   drivers/gpu/drm/i915/intel_display.c |  59 ++++-
> >   drivers/gpu/drm/i915/intel_drv.h     |   9 +-
> >   drivers/gpu/drm/i915/intel_pm.c      | 433
> ++++++++++++++++++++++-------------
> >   drivers/gpu/drm/i915/intel_sprite.c  |  18 +-
> >   7 files changed, 357 insertions(+), 187 deletions(-)
> 
> > --
> > 2.7.4
> 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Re: [PATCH 00/16] Adding NV12 support

[Kristian Høgsberg]

On Tue, Feb 13, 2018 at 8:59 PM Vidya Srinivas <vidya.srinivas@intel.com>
wrote:

> This patch series is adding NV12 support for Broxton display after
rebasing on
> latest drm-tip.
> Initial series of the patches can be found here:
> https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

I still don't see support for advertising modifiers in this patch set. The
series should handle NV12 in the supported_modifiers function to indicate
which tiling and/or compression modifiers are supported for NV12
framebuffers.

Kristian




> Previous revision history:
> The first version of patches were reviewed when floated by Chandra in 2015
> but currently there was a design change with respect to
> - the way fb offset is handled
> - the way rotation is handled
> Current NV12 patch series has been ported as per the
> current changes on drm-tip

> Review comments from Ville (12th June 2017) have been addressed Review
> comments from Clinton A Taylor (7th July 2017) have been addressed

> Review comments from Clinton A Taylor (10th July 2017)
>          have been addressed. Had missed out tested-by/reviewed-by in the
patches.

>          Fixed that error in this series.
>          Review comments from Ville (11th July 2017) addressed.
>          Review comments from Paauwe, Bob (29th July 2017) addressed.

> Update from rev 28 Aug 2017
>          Rebased the series.
>          Tested with IGT for rotation, sprite and tiling combinations.
>          IGT Links:
>          https://patchwork.kernel.org/patch/9995943/
>          https://patchwork.kernel.org/patch/9995945/
>          Review comments by Maarten are addressed in this series.
>          NV12 enabled for Gen10.
>          Review comments from Shashank Sharma are addressed.

> Update from last rev:
>          IGT debug_fs test failure fixed.

> Chandra Konduru (6):
>    drm/i915: Set scaler mode for NV12
>    drm/i915: Update format_is_yuv() to include NV12
>    drm/i915: Upscale scaler max scale for NV12
>    drm/i915: Add NV12 as supported format for primary plane
>    drm/i915: Add NV12 as supported format for sprite plane
>    drm/i915: Add NV12 support to intel_framebuffer_init

> Mahesh Kumar (9):
>    drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
>    drm/i915/skl+: refactor WM calculation for NV12
>    drm/i915/skl+: add NV12 in skl_format_to_fourcc
>    drm/i915/skl+: support verification of DDB HW state for NV12
>    drm/i915/skl+: NV12 related changes for WM
>    drm/i915/skl+: pass skl_wm_level struct to wm compute func
>    drm/i915/skl+: make sure higher latency level has higher wm value
>    drm/i915/skl+: nv12 workaround disable WM level 1-7
>    drm/i915/skl: split skl_compute_ddb function

> Vidya Srinivas (1):
>    drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

>   drivers/gpu/drm/i915/i915_drv.h      |  10 +-
>   drivers/gpu/drm/i915/i915_reg.h      |   7 +
>   drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
>   drivers/gpu/drm/i915/intel_display.c |  59 ++++-
>   drivers/gpu/drm/i915/intel_drv.h     |   9 +-
>   drivers/gpu/drm/i915/intel_pm.c      | 433
++++++++++++++++++++++-------------
>   drivers/gpu/drm/i915/intel_sprite.c  |  18 +-
>   7 files changed, 357 insertions(+), 187 deletions(-)

> --
> 2.7.4

> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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[PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
	have been addressed. Had missed out tested-by/reviewed-by in the patches.

	Fixed that error in this series.
	Review comments from Ville (11th July 2017) addressed.
	Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
	Rebased the series.
	Tested with IGT for rotation, sprite and tiling combinations.
	IGT Links:
	https://patchwork.kernel.org/patch/9995943/
	https://patchwork.kernel.org/patch/9995945/
	Review comments by Maarten are addressed in this series.
	NV12 enabled for Gen10.
	Review comments from Shashank Sharma are addressed.

Update from last rev:
	IGT debug_fs test failure fixed.

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h      |  10 +-
 drivers/gpu/drm/i915/i915_reg.h      |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  59 ++++-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_pm.c      | 433 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |  18 +-
 7 files changed, 357 insertions(+), 187 deletions(-)

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
	have been addressed. Had missed out tested-by/reviewed-by in the patches.

	Fixed that error in this series.
	Review comments from Ville (11th July 2017) addressed.
	Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
	Rebased the series.
	Tested with IGT for rotation, sprite and tiling combinations.
	IGT Links:
	https://patchwork.kernel.org/patch/9995943/
	https://patchwork.kernel.org/patch/9995945/
	Review comments by Maarten are addressed in this series.
	NV12 enabled for Gen10.

Update from last rev:
	Review comments from Shashank Sharma are addressed.

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h      |  10 +-
 drivers/gpu/drm/i915/i915_reg.h      |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  59 ++++-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_pm.c      | 432 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |  18 +-
 7 files changed, 356 insertions(+), 187 deletions(-)

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
	have been addressed. Had missed out tested-by/reviewed-by in the patches.

	Fixed that error in this series.
	Review comments from Ville (11th July 2017) addressed.
	Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
	Rebased the series.
	Tested with IGT for rotation, sprite and tiling combinations.
	IGT Links:
	https://patchwork.kernel.org/patch/9995943/
	https://patchwork.kernel.org/patch/9995945/

Update from last rev:
	Rebased the series.
	Review comments by Maarten are addressed in this series.
	NV12 enabled for Gen10.

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h      |   9 +-
 drivers/gpu/drm/i915/i915_reg.h      |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  51 +++-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_pm.c      | 435 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |  16 +-
 7 files changed, 349 insertions(+), 186 deletions(-)

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
	have been addressed. Had missed out tested-by/reviewed-by in the patches.

	Fixed that error in this series.
	Review comments from Ville (11th July 2017) addressed.
	Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
	Rebased the series.
	Tested with IGT for rotation, sprite and tiling combinations.
	IGT Links:
	https://patchwork.kernel.org/patch/9995943/
	https://patchwork.kernel.org/patch/9995945/

Update from last rev:
	Rebased the series.
	Review comments by Maarten are addressed in this series.
	NV12 enabled for Gen10.

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h      |   9 +-
 drivers/gpu/drm/i915/i915_reg.h      |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  51 +++-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_pm.c      | 435 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |  16 +-
 7 files changed, 349 insertions(+), 186 deletions(-)

-- 
2.7.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 00/16] Adding NV12 support

[Vidya Srinivas]

This patch series is adding NV12 support for Gen >= 9 platforms.
Current testing has been done on Gen9 and Gen10 only.

Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
have been addressed. Had missed out tested-by/reviewed-by in the patches.
Fixed that error in this series.
Review comments from Ville (11th July 2017) addressed.
Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
Rebased the series.
Tested with IGT for rotation, sprite and tiling combinations.
IGT Links:
https://patchwork.kernel.org/patch/9995943/
https://patchwork.kernel.org/patch/9995945/

Update from last rev (Jan 16th 2018):
Rebased the series.
Review comments by Maarten are addressed in this series.
NV12 is enabled and tested on Gen10.

Patches are tested (dependent on) watermark necessary changes
https://patchwork.freedesktop.org/series/33439/

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

Vidya Srinivas (1):
  drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg

 drivers/gpu/drm/i915/i915_drv.h      |   9 +-
 drivers/gpu/drm/i915/i915_reg.h      |   7 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  51 ++++-
 drivers/gpu/drm/i915/intel_drv.h     |   9 +-
 drivers/gpu/drm/i915/intel_pm.c      | 433 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |  16 +-
 7 files changed, 346 insertions(+), 187 deletions(-)

-- 
2.7.4

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx