* [PATCH v10 0/3] NPCM750: clk controller, DT and binding @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: brendanhiggins, robh+dt, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd Cc: devicetree, linux-kernel, linux-arm-kernel, openbmc, linux-clk, Tali Perry Add Nuvoton BMC NPCM7xx clock driver. Nuvoton BMC NPCM7xx contain integrated clock controller which generates and supplies clock to all modules within the NPCM7xx BMC 2 ==> 10 update documentation. add external clocks as inputs to clk driver. fix SPDX comment. 1 ==> 2 This patch includes fix request described here: https://patchwork.kernel.org/patch/10200033/ (move fixed clocks to DT) Signed-off-by: Tali Perry <tali.perry1@gmail.com> Tali Perry (3): NPCM750: add clock controller to DT NPCM750: add clock tree doc and binding NPCM750: add clock controller driver .../bindings/clock/nuvoton,npcm750-clk.txt | 100 ++ arch/arm/boot/dts/nuvoton-npcm750.dtsi | 1221 ++++++++++++++++++++ drivers/clk/Makefile | 1 + drivers/clk/clk-npcm7xx.c | 757 ++++++++++++ include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 44 + 5 files changed, 2123 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi create mode 100644 drivers/clk/clk-npcm7xx.c create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h -- 2.14.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v10 0/3] NPCM750: clk controller, DT and binding @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: linux-arm-kernel Add Nuvoton BMC NPCM7xx clock driver. Nuvoton BMC NPCM7xx contain integrated clock controller which generates and supplies clock to all modules within the NPCM7xx BMC 2 ==> 10 update documentation. add external clocks as inputs to clk driver. fix SPDX comment. 1 ==> 2 This patch includes fix request described here: https://patchwork.kernel.org/patch/10200033/ (move fixed clocks to DT) Signed-off-by: Tali Perry <tali.perry1@gmail.com> Tali Perry (3): NPCM750: add clock controller to DT NPCM750: add clock tree doc and binding NPCM750: add clock controller driver .../bindings/clock/nuvoton,npcm750-clk.txt | 100 ++ arch/arm/boot/dts/nuvoton-npcm750.dtsi | 1221 ++++++++++++++++++++ drivers/clk/Makefile | 1 + drivers/clk/clk-npcm7xx.c | 757 ++++++++++++ include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 44 + 5 files changed, 2123 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi create mode 100644 drivers/clk/clk-npcm7xx.c create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h -- 2.14.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v10 0/3] NPCM750: clk controller, DT and binding @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: brendanhiggins, robh+dt, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd Cc: devicetree, openbmc, linux-kernel, Tali Perry, linux-clk, linux-arm-kernel Add Nuvoton BMC NPCM7xx clock driver. Nuvoton BMC NPCM7xx contain integrated clock controller which generates and supplies clock to all modules within the NPCM7xx BMC 2 ==> 10 update documentation. add external clocks as inputs to clk driver. fix SPDX comment. 1 ==> 2 This patch includes fix request described here: https://patchwork.kernel.org/patch/10200033/ (move fixed clocks to DT) Signed-off-by: Tali Perry <tali.perry1@gmail.com> Tali Perry (3): NPCM750: add clock controller to DT NPCM750: add clock tree doc and binding NPCM750: add clock controller driver .../bindings/clock/nuvoton,npcm750-clk.txt | 100 ++ arch/arm/boot/dts/nuvoton-npcm750.dtsi | 1221 ++++++++++++++++++++ drivers/clk/Makefile | 1 + drivers/clk/clk-npcm7xx.c | 757 ++++++++++++ include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 44 + 5 files changed, 2123 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi create mode 100644 drivers/clk/clk-npcm7xx.c create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h -- 2.14.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v10 1/3] NPCM750: add clock controller to DT 2018-02-25 10:12 ` Tali Perry (?) @ 2018-02-25 10:12 ` Tali Perry -1 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: brendanhiggins, robh+dt, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd Cc: devicetree, linux-kernel, linux-arm-kernel, openbmc, linux-clk, Tali Perry Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- arch/arm/boot/dts/nuvoton-npcm750.dtsi | 1221 ++++++++++++++++++++++++++++++++ 1 file changed, 1221 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi new file mode 100644 index 000000000000..a44a37c01972 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -0,0 +1,1221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTSi file for the NPCM750 SoC + * + * Copyright (c) 2014-2018 Nuvoton Technology corporation. + * + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm7xx-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + gcr: gcr@f0800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0xf0800000 0x1000>; + }; + + rst: rst@f0801000 { + compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; + reg = <0xf0801000 0x1000>; + }; + + scu: scu@f03fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xf03fe000 0x1000>; + }; + + l2: cache-controller@f03fc000 { + compatible = "arm,pl310-cache"; + reg = <0xf03fc000 0x1000>; + interrupts = <0 21 4>; + cache-unified; + arm,shared-override; + cache-level = <2>; + clocks = <&clk NPCM7XX_CLK_AXI>; + }; + + gic: interrupt-controller@f03ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf03ff000 0x1000>, + <0xf03fe100 0x100>; + }; + + timer@f03fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf03fe600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk", "syscon"; + #clock-cells = <1>; + clock-controller; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; + + /* external reference clock */ + clk_refclk: clk-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "refclk"; + }; + + /* external reference clock for cpu. float in normal operation */ + clk_sysbypck: clk-sysbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sysbypck"; + }; + + /* external reference clock for MC. float in normal operation */ + clk_mcbypck: clk-mcbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mcbypck"; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk_rg1refck: clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg1refck"; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk_rg2refck: clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg2refck"; + }; + + clk_xin: clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_xin"; + }; + + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x80000000 0x80000000 0x40000000 + 0xc0000000 0xc0000000 0x00002000 + 0xc0008000 0xc0008000 0x00001000 + 0xe0800000 0xe0800000 0x00001000 + 0xe1000000 0xe1000000 0x00001000 + 0xe8000000 0xe8000000 0x08000000 + /* APB start */ + 0xf0000000 0xf0000000 0x00005000 + 0xf0007000 0xf0007000 0x00005000 + 0xf0010000 0xf0010000 0x00008000 + 0xf0080000 0xf0080000 0x00010000 + 0xf009f000 0xf009f000 0x00001000 + 0xf0100000 0xf0100000 0x00005000 + 0xf0180000 0xf0180000 0x0000b000 + 0xf0200000 0xf0200000 0x00002000 + /* APB end */ + 0xf0800000 0xf0800000 0x000fc000 + 0xf8000000 0xf8000000 0x02000000 + 0xfb000000 0xfb000000 0x00002000 + 0xfffd0000 0xfffd0000 0x00005000>; + + gmac0: eth@f0802000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = <0 14 4>; + interrupt-names = "macirq"; + ethernet = <0>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + status = "disabled"; + }; + + gmac1: eth@f0804000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0804000 0x2000>; + interrupts = <0 17 4>; + interrupt-names = "macirq"; + ethernet = <1>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + status = "disabled"; + }; + + emc0: eth@f0825000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0825000 0x1000>; + interrupts = <0 16 4>, <0 15 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_emc"; + }; + + emc1: eth@f0826000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0826000 0x1000>; + interrupts = <0 115 4>, <0 114 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_emc"; + }; + + sdhci0: sdhci@f0840000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0840000 0x200>; + interrupts = <0 27 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/ + clock-names = "clk_sdhc"; /* ,"clk_xin"; */ + }; + + sdhci1: sdhci@f0842000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0842000 0x200>; + interrupts = <0 26 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/ + clock-names = "clk_mmc"; /* ,"clk_xin"; */ + }; + + ehci1:ehci@f0806000 { + compatible = "nuvoton,npcm750-ehci"; + reg = <0xf0806000 0x1000>; + interrupts = <0 61 4>; + status = "disabled"; + }; + + ohci1: ohci@f0807000 { + compatible = "nuvoton,npcm750-ohci"; + reg = <0xf0807000 0x1000>; + interrupts = <0 62 4>; + status = "disabled"; + }; + + udc0:udc@f0830000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0830000 0x1000 + 0xfffd0000 0x800>; + interrupts = <0 51 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc1:udc@f0831000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0831000 0x1000 + 0xfffd0800 0x800>; + interrupts = <0 52 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc2:udc@f0832000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0832000 0x1000 + 0xfffd1000 0x800>; + interrupts = <0 53 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc3:udc@f0833000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0833000 0x1000 + 0xfffd1800 0x800>; + interrupts = <0 54 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc4:udc@f0834000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0834000 0x1000 + 0xfffd2000 0x800>; + interrupts = <0 55 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc5:udc@f0835000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0835000 0x1000 + 0xfffd2800 0x800>; + interrupts = <0 56 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc6:udc@f0836000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0836000 0x1000 + 0xfffd3000 0x800>; + interrupts = <0 57 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc7:udc@f0837000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0837000 0x1000 + 0xfffd3800 0x800>; + interrupts = <0 58 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc8:udc@f0838000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0838000 0x1000 + 0xfffd4000 0x800>; + interrupts = <0 59 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc9:udc@f0839000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0839000 0x1000 + 0xfffd4800 0x800>; + interrupts = <0 60 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + aes:aes@f0858000 { + compatible = "nuvoton,npcm750-aes"; + reg = <0xf0858000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + sha:sha@f085a000 { + compatible = "nuvoton,npcm750-sha"; + reg = <0xf085a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + copr: copr@0 { + compatible = "nuvoton,npcm750-copr"; + interrupts = <0 1 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + vdma: vdma@e0800000 { + compatible = "nuvoton,npcm750-vdm"; + reg = <0xe0800000 0x1000 + 0xf0822000 0x1000>; + interrupts = <0 29 4>; + }; + + spi0: spi@fb000000 { + compatible = "nuvoton,npcm750-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + chip-max-address-map = <0x8000000>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + }; + }; + spi3: spi@c0000000 { + compatible = "nuvoton,npcm750-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc0000000 0x1000>, <0xA0000000 0x20000000>; + reg-names = "control", "memory"; + chip-max-address-map = <0x8000000>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + }; + }; + + pci_rc: axi-pcie@E1000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "nuvoton,npcm750-pcirc"; + reg = < 0xE1000000 0x1000 >; + device_type = "pci"; + interrupts = < 0 127 4 >; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0 0xEA000000 + 0xEA000000 0 0x02000000>; + status = "disabled"; + }; + + dvc: dvc@f0808000 { + compatible = "nuvoton,npcm750-dvc"; + reg = <0xf0808000 0x1000>; + interrupts = <0 23 4>; + }; + + vcd: vcd@0 { + compatible = "nuvoton,npcm750-vcd"; + reg = <0xf0810000 0x10000 + 0xf0820000 0x2000>; + interrupts = <0 22 4>, <0 24 4>; + }; + + pcimbx: pcimbx@f0848000 { + compatible = "nuvoton,npcm750-pcimbx"; + reg = <0xf0848000 0x10000>; + interrupts = <0 8 4>; + }; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0xf0000000 0xf0000000 0x00005000 + 0xf0007000 0xf0007000 0x00009000 + 0xf0010000 0xf0010000 0x00008000 + 0xf0080000 0xf0080000 0x00010000 + 0xf009f000 0xf009f000 0x00001000 + 0xf0100000 0xf0100000 0x00005000 + 0xf0180000 0xf0180000 0x0000b000 + 0xf0200000 0xf0200000 0x00002000>; + + kcs: kcs@f0007000 { + compatible = "nuvoton,npcm750-kcs"; + reg = <0xf0007000 0x1000>; + interrupts = <0 9 4>; + }; + + pspi: pspi@0 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0xf0200000 0x2000>; + interrupts = <0 31 4>, <0 28 4>; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + }; + + fan: fan@0 { + compatible = "nuvoton,npcm750-fan"; + reg = <0xf0180000 0x8000>; + interrupts = <0 96 4>, <0 97 4>, <0 98 4>, <0 99 4>, + <0 100 4>, <0 101 4>, <0 102 4>, <0 103 4>; + clocks = <&clk NPCM7XX_CLK_APB4>; + clock-names = "clk_apb4"; + }; + + gpio: gpio@f0010000 { + compatible = "nuvoton,npcm750-gpio"; + reg = <0xf0010000 0x8000>; + interrupts = <0 116 4>, <0 117 4>, <0 118 4>, <0 119 4>, + <0 120 4>, <0 121 4>, <0 122 4>, <0 123 4>; + clocks = <&clk NPCM7XX_CLK_APB1>; + clock-names = "clk_apb1"; + }; + + timer0: timer@f0008000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = <0 32 4>; + reg = <0xf0008000 0x1000>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog0: watchdog@f0008000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 47 4>; + reg = <0xf0008000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog1: watchdog@f0009000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 48 4>; + reg = <0xf0009000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog2: watchdog@f000a000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 49 4>; + reg = <0xf000a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + serial0: serial0@f0001000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0001000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <14>; + interrupts = <0 2 4>; + status = "disabled"; + }; + + serial1: serial1@f0002000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0002000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <14>; + interrupts = <0 3 4>; + status = "disabled"; + }; + + serial2: serial2@f0003000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0003000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <16>; + interrupts = <0 4 4>; + status = "disabled"; + }; + + serial3: serial3@f0004000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0004000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <16>; + interrupts = <0 5 4>; + status = "disabled"; + }; + + rng: rng@f000b000 { + compatible = "nuvoton,npcm750-rng"; + reg = <0xf000b000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB1>; + clock-names = "clk_apb1"; + status = "disabled"; + }; + + adc: adc@f000c000 { + compatible = "nuvoton,npcm750-adc"; + reg = <0xf000c000 0x1000>; + clocks = <&clk NPCM7XX_CLK_ADC>; + clock-names = "clk_adc"; + vref = <2048>; + }; + + otp:otp@f0189000 { + compatible = "nuvoton,npcm750-otp"; + reg = <0xf0189000 0x1000 + 0xf018a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_APB4>; + clock-names = "clk_apb4"; + }; + + pwm:pwm@f0103000 { + compatible = "nuvoton,npcm750-pwm"; + reg = <0xf0103000 0x1000 + 0xf0104000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB3>; + clock-names = "clk_apb3"; + }; + + i2c0: i2c-bus@f0080000 { + reg = <0xf0080000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 64 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + status = "disabled"; + }; + i2c1: i2c-bus@f0081000 { + reg = <0xf0081000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 65 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb1_pins>; + status = "disabled"; + }; + i2c2: i2c-bus@f0082000 { + reg = <0xf0082000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb2_pins>; + status = "disabled"; + }; + i2c3: i2c-bus@f0083000 { + reg = <0xf0083000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 67 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb3_pins>; + status = "disabled"; + }; + i2c4: i2c-bus@f0084000 { + reg = <0xf0084000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 68 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb4_pins>; + status = "disabled"; + }; + i2c5: i2c-bus@f0085000 { + reg = <0xf0085000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 69 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb5_pins>; + status = "disabled"; + }; + i2c6: i2c-bus@f0086000 { + reg = <0xf0086000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 70 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb6_pins>; + status = "disabled"; + }; + i2c7: i2c-bus@f0087000 { + reg = <0xf0087000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 71 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb7_pins>; + status = "disabled"; + }; + i2c8: i2c-bus@f0088000 { + reg = <0xf0088000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 72 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb8_pins>; + status = "disabled"; + }; + i2c9: i2c-bus@f0089000 { + reg = <0xf0089000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 73 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb9_pins>; + status = "disabled"; + }; + i2c10: i2c-bus@f008a000 { + reg = <0xf008a000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 74 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb10_pins>; + status = "disabled"; + }; + i2c11: i2c-bus@f008b000 { + reg = <0xf008b000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 75 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb11_pins>; + status = "disabled"; + }; + i2c12: i2c-bus@f008c000 { + reg = <0xf008c000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 76 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb12_pins>; + status = "disabled"; + }; + i2c13: i2c-bus@f008d000 { + reg = <0xf008d000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 77 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb13_pins>; + status = "disabled"; + }; + i2c14: i2c-bus@f008e000 { + reg = <0xf008e000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 78 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb14_pins>; + status = "disabled"; + }; + i2c15: i2c-bus@f008f000 { + reg = <0xf008f000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 79 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb15_pins>; + status = "disabled"; + }; + }; + pinctrl: pinctrl@0 { + compatible = "nuvoton,npcmx50-pinctrl"; + status = "okay"; + iox1_pins: iox1_pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2_pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d_pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d_pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1_pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2_pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh_pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi_pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b_pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c_pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0_pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi2_pins: pspi2_pins { + groups = "pspi2"; + function = "pspi2"; + }; + smb4den_pins: smb4den_pins { + groups = "smb4den"; + function = "smb4den"; + }; + smb4b_pins: smb4b_pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c_pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15_pins { + groups = "smb15"; + function = "smb15"; + }; + smb4d_pins: smb4d_pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14_pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5_pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4_pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3_pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1_pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0quad_pins: spi0quad_pins { + groups = "spi0quad"; + function = "spi0quad"; + }; + spi0cs2_pins: spi0cs2_pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3_pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c_pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b_pins { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a_pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1_pins { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2_pins { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1_pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2_pins { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b_pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err_pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md_pins { + groups = "r1md"; + function = "r1md"; + }; + smb3d_pins: smb3d_pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0_pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1_pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2_pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3_pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4_pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5_pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6_pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7_pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8_pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9_pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10_pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11_pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12_pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13_pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14_pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15_pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0_pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1_pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2_pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3_pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2_pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err_pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md_pins { + groups = "r2md"; + function = "r2md"; + }; + ga20kbc_pins: ga20kbc_pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d_pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc_pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi_pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1_pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio_pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2_pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr_pins { + groups = "ddr"; + function = "ddr"; + }; + smb0_pins: smb0_pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1_pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2_pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c_pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b_pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c_pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b_pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8_pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9_pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10_pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11_pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1_pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr_pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4_pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5_pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6_pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7_pins { + groups = "pwm7"; + function = "pwm7"; + }; + mmc8_pins: mmc8_pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc_pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp_pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd_pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst_pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout_pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq_pins { + groups = "serirq"; + function = "serirq"; + }; + scipme_pins: scipme_pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci_pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6_pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7_pins { + groups = "smb7"; + function = "smb7"; + }; + pspi1_pins: pspi1_pins { + groups = "pspi1"; + function = "pspi1"; + }; + faninx_pins: faninx_pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1_pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3_pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1_pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad_pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2_pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3_pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd_smi_pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b_pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c_pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den_pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d_pins { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc_pins { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio_pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1_pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2_pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12_pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13_pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix_pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1_pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq_pins { + groups = "clkreq"; + function = "clkreq"; + }; + }; +}; -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v10 1/3] NPCM750: add clock controller to DT @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- arch/arm/boot/dts/nuvoton-npcm750.dtsi | 1221 ++++++++++++++++++++++++++++++++ 1 file changed, 1221 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi new file mode 100644 index 000000000000..a44a37c01972 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -0,0 +1,1221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTSi file for the NPCM750 SoC + * + * Copyright (c) 2014-2018 Nuvoton Technology corporation. + * + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm7xx-smp"; + + cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu at 1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + gcr: gcr at f0800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0xf0800000 0x1000>; + }; + + rst: rst at f0801000 { + compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; + reg = <0xf0801000 0x1000>; + }; + + scu: scu at f03fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xf03fe000 0x1000>; + }; + + l2: cache-controller at f03fc000 { + compatible = "arm,pl310-cache"; + reg = <0xf03fc000 0x1000>; + interrupts = <0 21 4>; + cache-unified; + arm,shared-override; + cache-level = <2>; + clocks = <&clk NPCM7XX_CLK_AXI>; + }; + + gic: interrupt-controller at f03ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf03ff000 0x1000>, + <0xf03fe100 0x100>; + }; + + timer at f03fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf03fe600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + + clk: clock-controller at f0801000 { + compatible = "nuvoton,npcm750-clk", "syscon"; + #clock-cells = <1>; + clock-controller; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; + + /* external reference clock */ + clk_refclk: clk-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "refclk"; + }; + + /* external reference clock for cpu. float in normal operation */ + clk_sysbypck: clk-sysbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sysbypck"; + }; + + /* external reference clock for MC. float in normal operation */ + clk_mcbypck: clk-mcbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mcbypck"; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk_rg1refck: clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg1refck"; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk_rg2refck: clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg2refck"; + }; + + clk_xin: clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_xin"; + }; + + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x80000000 0x80000000 0x40000000 + 0xc0000000 0xc0000000 0x00002000 + 0xc0008000 0xc0008000 0x00001000 + 0xe0800000 0xe0800000 0x00001000 + 0xe1000000 0xe1000000 0x00001000 + 0xe8000000 0xe8000000 0x08000000 + /* APB start */ + 0xf0000000 0xf0000000 0x00005000 + 0xf0007000 0xf0007000 0x00005000 + 0xf0010000 0xf0010000 0x00008000 + 0xf0080000 0xf0080000 0x00010000 + 0xf009f000 0xf009f000 0x00001000 + 0xf0100000 0xf0100000 0x00005000 + 0xf0180000 0xf0180000 0x0000b000 + 0xf0200000 0xf0200000 0x00002000 + /* APB end */ + 0xf0800000 0xf0800000 0x000fc000 + 0xf8000000 0xf8000000 0x02000000 + 0xfb000000 0xfb000000 0x00002000 + 0xfffd0000 0xfffd0000 0x00005000>; + + gmac0: eth at f0802000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = <0 14 4>; + interrupt-names = "macirq"; + ethernet = <0>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + status = "disabled"; + }; + + gmac1: eth at f0804000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0804000 0x2000>; + interrupts = <0 17 4>; + interrupt-names = "macirq"; + ethernet = <1>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + status = "disabled"; + }; + + emc0: eth at f0825000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0825000 0x1000>; + interrupts = <0 16 4>, <0 15 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_emc"; + }; + + emc1: eth at f0826000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0826000 0x1000>; + interrupts = <0 115 4>, <0 114 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_emc"; + }; + + sdhci0: sdhci at f0840000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0840000 0x200>; + interrupts = <0 27 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/ + clock-names = "clk_sdhc"; /* ,"clk_xin"; */ + }; + + sdhci1: sdhci at f0842000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0842000 0x200>; + interrupts = <0 26 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/ + clock-names = "clk_mmc"; /* ,"clk_xin"; */ + }; + + ehci1:ehci at f0806000 { + compatible = "nuvoton,npcm750-ehci"; + reg = <0xf0806000 0x1000>; + interrupts = <0 61 4>; + status = "disabled"; + }; + + ohci1: ohci at f0807000 { + compatible = "nuvoton,npcm750-ohci"; + reg = <0xf0807000 0x1000>; + interrupts = <0 62 4>; + status = "disabled"; + }; + + udc0:udc at f0830000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0830000 0x1000 + 0xfffd0000 0x800>; + interrupts = <0 51 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc1:udc at f0831000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0831000 0x1000 + 0xfffd0800 0x800>; + interrupts = <0 52 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc2:udc at f0832000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0832000 0x1000 + 0xfffd1000 0x800>; + interrupts = <0 53 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc3:udc at f0833000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0833000 0x1000 + 0xfffd1800 0x800>; + interrupts = <0 54 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc4:udc at f0834000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0834000 0x1000 + 0xfffd2000 0x800>; + interrupts = <0 55 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc5:udc at f0835000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0835000 0x1000 + 0xfffd2800 0x800>; + interrupts = <0 56 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc6:udc at f0836000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0836000 0x1000 + 0xfffd3000 0x800>; + interrupts = <0 57 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc7:udc at f0837000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0837000 0x1000 + 0xfffd3800 0x800>; + interrupts = <0 58 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc8:udc at f0838000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0838000 0x1000 + 0xfffd4000 0x800>; + interrupts = <0 59 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc9:udc at f0839000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0839000 0x1000 + 0xfffd4800 0x800>; + interrupts = <0 60 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + aes:aes at f0858000 { + compatible = "nuvoton,npcm750-aes"; + reg = <0xf0858000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + sha:sha at f085a000 { + compatible = "nuvoton,npcm750-sha"; + reg = <0xf085a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + copr: copr at 0 { + compatible = "nuvoton,npcm750-copr"; + interrupts = <0 1 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + vdma: vdma at e0800000 { + compatible = "nuvoton,npcm750-vdm"; + reg = <0xe0800000 0x1000 + 0xf0822000 0x1000>; + interrupts = <0 29 4>; + }; + + spi0: spi at fb000000 { + compatible = "nuvoton,npcm750-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + chip-max-address-map = <0x8000000>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + spi-nor at 0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + }; + }; + spi3: spi at c0000000 { + compatible = "nuvoton,npcm750-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc0000000 0x1000>, <0xA0000000 0x20000000>; + reg-names = "control", "memory"; + chip-max-address-map = <0x8000000>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + spi-nor at 0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + }; + }; + + pci_rc: axi-pcie at E1000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "nuvoton,npcm750-pcirc"; + reg = < 0xE1000000 0x1000 >; + device_type = "pci"; + interrupts = < 0 127 4 >; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0 0xEA000000 + 0xEA000000 0 0x02000000>; + status = "disabled"; + }; + + dvc: dvc at f0808000 { + compatible = "nuvoton,npcm750-dvc"; + reg = <0xf0808000 0x1000>; + interrupts = <0 23 4>; + }; + + vcd: vcd at 0 { + compatible = "nuvoton,npcm750-vcd"; + reg = <0xf0810000 0x10000 + 0xf0820000 0x2000>; + interrupts = <0 22 4>, <0 24 4>; + }; + + pcimbx: pcimbx at f0848000 { + compatible = "nuvoton,npcm750-pcimbx"; + reg = <0xf0848000 0x10000>; + interrupts = <0 8 4>; + }; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0xf0000000 0xf0000000 0x00005000 + 0xf0007000 0xf0007000 0x00009000 + 0xf0010000 0xf0010000 0x00008000 + 0xf0080000 0xf0080000 0x00010000 + 0xf009f000 0xf009f000 0x00001000 + 0xf0100000 0xf0100000 0x00005000 + 0xf0180000 0xf0180000 0x0000b000 + 0xf0200000 0xf0200000 0x00002000>; + + kcs: kcs at f0007000 { + compatible = "nuvoton,npcm750-kcs"; + reg = <0xf0007000 0x1000>; + interrupts = <0 9 4>; + }; + + pspi: pspi at 0 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0xf0200000 0x2000>; + interrupts = <0 31 4>, <0 28 4>; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + }; + + fan: fan at 0 { + compatible = "nuvoton,npcm750-fan"; + reg = <0xf0180000 0x8000>; + interrupts = <0 96 4>, <0 97 4>, <0 98 4>, <0 99 4>, + <0 100 4>, <0 101 4>, <0 102 4>, <0 103 4>; + clocks = <&clk NPCM7XX_CLK_APB4>; + clock-names = "clk_apb4"; + }; + + gpio: gpio at f0010000 { + compatible = "nuvoton,npcm750-gpio"; + reg = <0xf0010000 0x8000>; + interrupts = <0 116 4>, <0 117 4>, <0 118 4>, <0 119 4>, + <0 120 4>, <0 121 4>, <0 122 4>, <0 123 4>; + clocks = <&clk NPCM7XX_CLK_APB1>; + clock-names = "clk_apb1"; + }; + + timer0: timer at f0008000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = <0 32 4>; + reg = <0xf0008000 0x1000>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog0: watchdog at f0008000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 47 4>; + reg = <0xf0008000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog1: watchdog at f0009000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 48 4>; + reg = <0xf0009000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog2: watchdog at f000a000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 49 4>; + reg = <0xf000a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + serial0: serial0 at f0001000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0001000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <14>; + interrupts = <0 2 4>; + status = "disabled"; + }; + + serial1: serial1 at f0002000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0002000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <14>; + interrupts = <0 3 4>; + status = "disabled"; + }; + + serial2: serial2 at f0003000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0003000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <16>; + interrupts = <0 4 4>; + status = "disabled"; + }; + + serial3: serial3 at f0004000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0004000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <16>; + interrupts = <0 5 4>; + status = "disabled"; + }; + + rng: rng at f000b000 { + compatible = "nuvoton,npcm750-rng"; + reg = <0xf000b000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB1>; + clock-names = "clk_apb1"; + status = "disabled"; + }; + + adc: adc at f000c000 { + compatible = "nuvoton,npcm750-adc"; + reg = <0xf000c000 0x1000>; + clocks = <&clk NPCM7XX_CLK_ADC>; + clock-names = "clk_adc"; + vref = <2048>; + }; + + otp:otp at f0189000 { + compatible = "nuvoton,npcm750-otp"; + reg = <0xf0189000 0x1000 + 0xf018a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_APB4>; + clock-names = "clk_apb4"; + }; + + pwm:pwm at f0103000 { + compatible = "nuvoton,npcm750-pwm"; + reg = <0xf0103000 0x1000 + 0xf0104000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB3>; + clock-names = "clk_apb3"; + }; + + i2c0: i2c-bus at f0080000 { + reg = <0xf0080000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 64 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + status = "disabled"; + }; + i2c1: i2c-bus at f0081000 { + reg = <0xf0081000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 65 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb1_pins>; + status = "disabled"; + }; + i2c2: i2c-bus at f0082000 { + reg = <0xf0082000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb2_pins>; + status = "disabled"; + }; + i2c3: i2c-bus at f0083000 { + reg = <0xf0083000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 67 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb3_pins>; + status = "disabled"; + }; + i2c4: i2c-bus at f0084000 { + reg = <0xf0084000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 68 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb4_pins>; + status = "disabled"; + }; + i2c5: i2c-bus at f0085000 { + reg = <0xf0085000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 69 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb5_pins>; + status = "disabled"; + }; + i2c6: i2c-bus at f0086000 { + reg = <0xf0086000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 70 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb6_pins>; + status = "disabled"; + }; + i2c7: i2c-bus at f0087000 { + reg = <0xf0087000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 71 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb7_pins>; + status = "disabled"; + }; + i2c8: i2c-bus at f0088000 { + reg = <0xf0088000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 72 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb8_pins>; + status = "disabled"; + }; + i2c9: i2c-bus at f0089000 { + reg = <0xf0089000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 73 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb9_pins>; + status = "disabled"; + }; + i2c10: i2c-bus at f008a000 { + reg = <0xf008a000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 74 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb10_pins>; + status = "disabled"; + }; + i2c11: i2c-bus at f008b000 { + reg = <0xf008b000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 75 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb11_pins>; + status = "disabled"; + }; + i2c12: i2c-bus at f008c000 { + reg = <0xf008c000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 76 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb12_pins>; + status = "disabled"; + }; + i2c13: i2c-bus at f008d000 { + reg = <0xf008d000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 77 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb13_pins>; + status = "disabled"; + }; + i2c14: i2c-bus at f008e000 { + reg = <0xf008e000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 78 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb14_pins>; + status = "disabled"; + }; + i2c15: i2c-bus at f008f000 { + reg = <0xf008f000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 79 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb15_pins>; + status = "disabled"; + }; + }; + pinctrl: pinctrl at 0 { + compatible = "nuvoton,npcmx50-pinctrl"; + status = "okay"; + iox1_pins: iox1_pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2_pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d_pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d_pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1_pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2_pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh_pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi_pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b_pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c_pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0_pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi2_pins: pspi2_pins { + groups = "pspi2"; + function = "pspi2"; + }; + smb4den_pins: smb4den_pins { + groups = "smb4den"; + function = "smb4den"; + }; + smb4b_pins: smb4b_pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c_pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15_pins { + groups = "smb15"; + function = "smb15"; + }; + smb4d_pins: smb4d_pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14_pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5_pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4_pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3_pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1_pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0quad_pins: spi0quad_pins { + groups = "spi0quad"; + function = "spi0quad"; + }; + spi0cs2_pins: spi0cs2_pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3_pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c_pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b_pins { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a_pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1_pins { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2_pins { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1_pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2_pins { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b_pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err_pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md_pins { + groups = "r1md"; + function = "r1md"; + }; + smb3d_pins: smb3d_pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0_pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1_pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2_pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3_pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4_pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5_pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6_pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7_pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8_pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9_pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10_pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11_pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12_pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13_pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14_pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15_pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0_pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1_pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2_pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3_pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2_pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err_pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md_pins { + groups = "r2md"; + function = "r2md"; + }; + ga20kbc_pins: ga20kbc_pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d_pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc_pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi_pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1_pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio_pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2_pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr_pins { + groups = "ddr"; + function = "ddr"; + }; + smb0_pins: smb0_pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1_pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2_pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c_pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b_pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c_pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b_pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8_pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9_pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10_pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11_pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1_pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr_pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4_pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5_pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6_pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7_pins { + groups = "pwm7"; + function = "pwm7"; + }; + mmc8_pins: mmc8_pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc_pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp_pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd_pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst_pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout_pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq_pins { + groups = "serirq"; + function = "serirq"; + }; + scipme_pins: scipme_pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci_pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6_pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7_pins { + groups = "smb7"; + function = "smb7"; + }; + pspi1_pins: pspi1_pins { + groups = "pspi1"; + function = "pspi1"; + }; + faninx_pins: faninx_pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1_pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3_pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1_pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad_pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2_pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3_pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd_smi_pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b_pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c_pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den_pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d_pins { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc_pins { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio_pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1_pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2_pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12_pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13_pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix_pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1_pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq_pins { + groups = "clkreq"; + function = "clkreq"; + }; + }; +}; -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v10 1/3] NPCM750: add clock controller to DT @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: brendanhiggins, robh+dt, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd Cc: devicetree, openbmc, linux-kernel, Tali Perry, linux-clk, linux-arm-kernel Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- arch/arm/boot/dts/nuvoton-npcm750.dtsi | 1221 ++++++++++++++++++++++++++++++++ 1 file changed, 1221 insertions(+) create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi new file mode 100644 index 000000000000..a44a37c01972 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -0,0 +1,1221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DTSi file for the NPCM750 SoC + * + * Copyright (c) 2014-2018 Nuvoton Technology corporation. + * + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm7xx-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + gcr: gcr@f0800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0xf0800000 0x1000>; + }; + + rst: rst@f0801000 { + compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; + reg = <0xf0801000 0x1000>; + }; + + scu: scu@f03fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xf03fe000 0x1000>; + }; + + l2: cache-controller@f03fc000 { + compatible = "arm,pl310-cache"; + reg = <0xf03fc000 0x1000>; + interrupts = <0 21 4>; + cache-unified; + arm,shared-override; + cache-level = <2>; + clocks = <&clk NPCM7XX_CLK_AXI>; + }; + + gic: interrupt-controller@f03ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0xf03ff000 0x1000>, + <0xf03fe100 0x100>; + }; + + timer@f03fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xf03fe600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk", "syscon"; + #clock-cells = <1>; + clock-controller; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; + + /* external reference clock */ + clk_refclk: clk-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "refclk"; + }; + + /* external reference clock for cpu. float in normal operation */ + clk_sysbypck: clk-sysbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sysbypck"; + }; + + /* external reference clock for MC. float in normal operation */ + clk_mcbypck: clk-mcbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mcbypck"; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk_rg1refck: clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg1refck"; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk_rg2refck: clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg2refck"; + }; + + clk_xin: clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_xin"; + }; + + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x80000000 0x80000000 0x40000000 + 0xc0000000 0xc0000000 0x00002000 + 0xc0008000 0xc0008000 0x00001000 + 0xe0800000 0xe0800000 0x00001000 + 0xe1000000 0xe1000000 0x00001000 + 0xe8000000 0xe8000000 0x08000000 + /* APB start */ + 0xf0000000 0xf0000000 0x00005000 + 0xf0007000 0xf0007000 0x00005000 + 0xf0010000 0xf0010000 0x00008000 + 0xf0080000 0xf0080000 0x00010000 + 0xf009f000 0xf009f000 0x00001000 + 0xf0100000 0xf0100000 0x00005000 + 0xf0180000 0xf0180000 0x0000b000 + 0xf0200000 0xf0200000 0x00002000 + /* APB end */ + 0xf0800000 0xf0800000 0x000fc000 + 0xf8000000 0xf8000000 0x02000000 + 0xfb000000 0xfb000000 0x00002000 + 0xfffd0000 0xfffd0000 0x00005000>; + + gmac0: eth@f0802000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = <0 14 4>; + interrupt-names = "macirq"; + ethernet = <0>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + status = "disabled"; + }; + + gmac1: eth@f0804000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0804000 0x2000>; + interrupts = <0 17 4>; + interrupt-names = "macirq"; + ethernet = <1>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + status = "disabled"; + }; + + emc0: eth@f0825000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0825000 0x1000>; + interrupts = <0 16 4>, <0 15 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_emc"; + }; + + emc1: eth@f0826000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0826000 0x1000>; + interrupts = <0 115 4>, <0 114 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_emc"; + }; + + sdhci0: sdhci@f0840000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0840000 0x200>; + interrupts = <0 27 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/ + clock-names = "clk_sdhc"; /* ,"clk_xin"; */ + }; + + sdhci1: sdhci@f0842000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0842000 0x200>; + interrupts = <0 26 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/ + clock-names = "clk_mmc"; /* ,"clk_xin"; */ + }; + + ehci1:ehci@f0806000 { + compatible = "nuvoton,npcm750-ehci"; + reg = <0xf0806000 0x1000>; + interrupts = <0 61 4>; + status = "disabled"; + }; + + ohci1: ohci@f0807000 { + compatible = "nuvoton,npcm750-ohci"; + reg = <0xf0807000 0x1000>; + interrupts = <0 62 4>; + status = "disabled"; + }; + + udc0:udc@f0830000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0830000 0x1000 + 0xfffd0000 0x800>; + interrupts = <0 51 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc1:udc@f0831000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0831000 0x1000 + 0xfffd0800 0x800>; + interrupts = <0 52 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc2:udc@f0832000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0832000 0x1000 + 0xfffd1000 0x800>; + interrupts = <0 53 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc3:udc@f0833000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0833000 0x1000 + 0xfffd1800 0x800>; + interrupts = <0 54 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc4:udc@f0834000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0834000 0x1000 + 0xfffd2000 0x800>; + interrupts = <0 55 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc5:udc@f0835000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0835000 0x1000 + 0xfffd2800 0x800>; + interrupts = <0 56 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc6:udc@f0836000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0836000 0x1000 + 0xfffd3000 0x800>; + interrupts = <0 57 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc7:udc@f0837000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0837000 0x1000 + 0xfffd3800 0x800>; + interrupts = <0 58 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc8:udc@f0838000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0838000 0x1000 + 0xfffd4000 0x800>; + interrupts = <0 59 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc9:udc@f0839000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0839000 0x1000 + 0xfffd4800 0x800>; + interrupts = <0 60 4>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + aes:aes@f0858000 { + compatible = "nuvoton,npcm750-aes"; + reg = <0xf0858000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + sha:sha@f085a000 { + compatible = "nuvoton,npcm750-sha"; + reg = <0xf085a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + copr: copr@0 { + compatible = "nuvoton,npcm750-copr"; + interrupts = <0 1 4>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + vdma: vdma@e0800000 { + compatible = "nuvoton,npcm750-vdm"; + reg = <0xe0800000 0x1000 + 0xf0822000 0x1000>; + interrupts = <0 29 4>; + }; + + spi0: spi@fb000000 { + compatible = "nuvoton,npcm750-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + chip-max-address-map = <0x8000000>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + }; + }; + spi3: spi@c0000000 { + compatible = "nuvoton,npcm750-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc0000000 0x1000>, <0xA0000000 0x20000000>; + reg-names = "control", "memory"; + chip-max-address-map = <0x8000000>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + }; + }; + + pci_rc: axi-pcie@E1000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + compatible = "nuvoton,npcm750-pcirc"; + reg = < 0xE1000000 0x1000 >; + device_type = "pci"; + interrupts = < 0 127 4 >; + bus-range = <0x00 0xff>; + ranges = <0x02000000 0 0xEA000000 + 0xEA000000 0 0x02000000>; + status = "disabled"; + }; + + dvc: dvc@f0808000 { + compatible = "nuvoton,npcm750-dvc"; + reg = <0xf0808000 0x1000>; + interrupts = <0 23 4>; + }; + + vcd: vcd@0 { + compatible = "nuvoton,npcm750-vcd"; + reg = <0xf0810000 0x10000 + 0xf0820000 0x2000>; + interrupts = <0 22 4>, <0 24 4>; + }; + + pcimbx: pcimbx@f0848000 { + compatible = "nuvoton,npcm750-pcimbx"; + reg = <0xf0848000 0x10000>; + interrupts = <0 8 4>; + }; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0xf0000000 0xf0000000 0x00005000 + 0xf0007000 0xf0007000 0x00009000 + 0xf0010000 0xf0010000 0x00008000 + 0xf0080000 0xf0080000 0x00010000 + 0xf009f000 0xf009f000 0x00001000 + 0xf0100000 0xf0100000 0x00005000 + 0xf0180000 0xf0180000 0x0000b000 + 0xf0200000 0xf0200000 0x00002000>; + + kcs: kcs@f0007000 { + compatible = "nuvoton,npcm750-kcs"; + reg = <0xf0007000 0x1000>; + interrupts = <0 9 4>; + }; + + pspi: pspi@0 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0xf0200000 0x2000>; + interrupts = <0 31 4>, <0 28 4>; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + }; + + fan: fan@0 { + compatible = "nuvoton,npcm750-fan"; + reg = <0xf0180000 0x8000>; + interrupts = <0 96 4>, <0 97 4>, <0 98 4>, <0 99 4>, + <0 100 4>, <0 101 4>, <0 102 4>, <0 103 4>; + clocks = <&clk NPCM7XX_CLK_APB4>; + clock-names = "clk_apb4"; + }; + + gpio: gpio@f0010000 { + compatible = "nuvoton,npcm750-gpio"; + reg = <0xf0010000 0x8000>; + interrupts = <0 116 4>, <0 117 4>, <0 118 4>, <0 119 4>, + <0 120 4>, <0 121 4>, <0 122 4>, <0 123 4>; + clocks = <&clk NPCM7XX_CLK_APB1>; + clock-names = "clk_apb1"; + }; + + timer0: timer@f0008000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = <0 32 4>; + reg = <0xf0008000 0x1000>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog0: watchdog@f0008000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 47 4>; + reg = <0xf0008000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog1: watchdog@f0009000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 48 4>; + reg = <0xf0009000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + watchdog2: watchdog@f000a000 { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <0 49 4>; + reg = <0xf000a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; + + serial0: serial0@f0001000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0001000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <14>; + interrupts = <0 2 4>; + status = "disabled"; + }; + + serial1: serial1@f0002000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0002000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <14>; + interrupts = <0 3 4>; + status = "disabled"; + }; + + serial2: serial2@f0003000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0003000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <16>; + interrupts = <0 4 4>; + status = "disabled"; + }; + + serial3: serial3@f0004000 { + compatible = "nuvoton,npcm750-uart"; + reg = <0xf0004000 0x1000>; + clocks = <&clk NPCM7XX_CLK_UART>; + reg-shift = <2>; + fifo-size = <16>; + interrupts = <0 5 4>; + status = "disabled"; + }; + + rng: rng@f000b000 { + compatible = "nuvoton,npcm750-rng"; + reg = <0xf000b000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB1>; + clock-names = "clk_apb1"; + status = "disabled"; + }; + + adc: adc@f000c000 { + compatible = "nuvoton,npcm750-adc"; + reg = <0xf000c000 0x1000>; + clocks = <&clk NPCM7XX_CLK_ADC>; + clock-names = "clk_adc"; + vref = <2048>; + }; + + otp:otp@f0189000 { + compatible = "nuvoton,npcm750-otp"; + reg = <0xf0189000 0x1000 + 0xf018a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_APB4>; + clock-names = "clk_apb4"; + }; + + pwm:pwm@f0103000 { + compatible = "nuvoton,npcm750-pwm"; + reg = <0xf0103000 0x1000 + 0xf0104000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB3>; + clock-names = "clk_apb3"; + }; + + i2c0: i2c-bus@f0080000 { + reg = <0xf0080000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 64 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + status = "disabled"; + }; + i2c1: i2c-bus@f0081000 { + reg = <0xf0081000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 65 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb1_pins>; + status = "disabled"; + }; + i2c2: i2c-bus@f0082000 { + reg = <0xf0082000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 66 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb2_pins>; + status = "disabled"; + }; + i2c3: i2c-bus@f0083000 { + reg = <0xf0083000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 67 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb3_pins>; + status = "disabled"; + }; + i2c4: i2c-bus@f0084000 { + reg = <0xf0084000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 68 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb4_pins>; + status = "disabled"; + }; + i2c5: i2c-bus@f0085000 { + reg = <0xf0085000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 69 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb5_pins>; + status = "disabled"; + }; + i2c6: i2c-bus@f0086000 { + reg = <0xf0086000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 70 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb6_pins>; + status = "disabled"; + }; + i2c7: i2c-bus@f0087000 { + reg = <0xf0087000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 71 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb7_pins>; + status = "disabled"; + }; + i2c8: i2c-bus@f0088000 { + reg = <0xf0088000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 72 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb8_pins>; + status = "disabled"; + }; + i2c9: i2c-bus@f0089000 { + reg = <0xf0089000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 73 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb9_pins>; + status = "disabled"; + }; + i2c10: i2c-bus@f008a000 { + reg = <0xf008a000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 74 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb10_pins>; + status = "disabled"; + }; + i2c11: i2c-bus@f008b000 { + reg = <0xf008b000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 75 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb11_pins>; + status = "disabled"; + }; + i2c12: i2c-bus@f008c000 { + reg = <0xf008c000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 76 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb12_pins>; + status = "disabled"; + }; + i2c13: i2c-bus@f008d000 { + reg = <0xf008d000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 77 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb13_pins>; + status = "disabled"; + }; + i2c14: i2c-bus@f008e000 { + reg = <0xf008e000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 78 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb14_pins>; + status = "disabled"; + }; + i2c15: i2c-bus@f008f000 { + reg = <0xf008f000 0x1000>; + compatible = "nuvoton,npcm750-i2c-bus"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <0 79 4>; + pinctrl-names = "default"; + pinctrl-0 = <&smb15_pins>; + status = "disabled"; + }; + }; + pinctrl: pinctrl@0 { + compatible = "nuvoton,npcmx50-pinctrl"; + status = "okay"; + iox1_pins: iox1_pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2_pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d_pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d_pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1_pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2_pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh_pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi_pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b_pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c_pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0_pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi2_pins: pspi2_pins { + groups = "pspi2"; + function = "pspi2"; + }; + smb4den_pins: smb4den_pins { + groups = "smb4den"; + function = "smb4den"; + }; + smb4b_pins: smb4b_pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c_pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15_pins { + groups = "smb15"; + function = "smb15"; + }; + smb4d_pins: smb4d_pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14_pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5_pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4_pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3_pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1_pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0quad_pins: spi0quad_pins { + groups = "spi0quad"; + function = "spi0quad"; + }; + spi0cs2_pins: spi0cs2_pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3_pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c_pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b_pins { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a_pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1_pins { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2_pins { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1_pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2_pins { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b_pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err_pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md_pins { + groups = "r1md"; + function = "r1md"; + }; + smb3d_pins: smb3d_pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0_pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1_pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2_pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3_pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4_pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5_pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6_pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7_pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8_pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9_pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10_pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11_pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12_pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13_pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14_pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15_pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0_pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1_pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2_pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3_pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2_pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err_pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md_pins { + groups = "r2md"; + function = "r2md"; + }; + ga20kbc_pins: ga20kbc_pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d_pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc_pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi_pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1_pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio_pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2_pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr_pins { + groups = "ddr"; + function = "ddr"; + }; + smb0_pins: smb0_pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1_pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2_pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c_pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b_pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c_pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b_pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8_pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9_pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10_pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11_pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1_pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr_pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4_pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5_pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6_pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7_pins { + groups = "pwm7"; + function = "pwm7"; + }; + mmc8_pins: mmc8_pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc_pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp_pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd_pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst_pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout_pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq_pins { + groups = "serirq"; + function = "serirq"; + }; + scipme_pins: scipme_pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci_pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6_pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7_pins { + groups = "smb7"; + function = "smb7"; + }; + pspi1_pins: pspi1_pins { + groups = "pspi1"; + function = "pspi1"; + }; + faninx_pins: faninx_pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1_pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3_pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1_pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad_pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2_pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3_pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd_smi_pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b_pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c_pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den_pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d_pins { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc_pins { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio_pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1_pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2_pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12_pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13_pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix_pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1_pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq_pins { + groups = "clkreq"; + function = "clkreq"; + }; + }; +}; -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v10 2/3] NPCM750: add clock tree doc and binding 2018-02-25 10:12 ` Tali Perry (?) @ 2018-02-25 10:12 ` Tali Perry -1 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: brendanhiggins, robh+dt, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd Cc: devicetree, linux-kernel, linux-arm-kernel, openbmc, linux-clk, Tali Perry Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- .../bindings/clock/nuvoton,npcm750-clk.txt | 100 +++++++++++++++++++++ include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 44 +++++++++ 2 files changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt new file mode 100644 index 000000000000..dd17b86bd577 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt @@ -0,0 +1,100 @@ +* Nuvoton NPCM7XX Clock Controller + +Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which +generates and supplies clocks to all modules within the BMC. + +External clocks: + +There are six fixed clocks that are generated outside the BMC. All clocks are of +a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and +clk_sysbypck are inputs to the clock controller. +clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the +network. They are set on the device tree, but not used by the clock module. The +network devices use them directly. +Example can be found below. + +All available clocks are defined as preprocessor macros in: +dt-bindings/clock/nuvoton,npcm7xx-clock.h +and can be reused as DT sources. + +Required Properties of clock controller: + + - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton + Poleg BMC NPCM750 + + - reg: physical base address of the clock controller and length of + memory mapped region. + + - #clock-cells: should be 1. + +Example: Clock controller node: + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk"; + #clock-cells = <1>; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; + +Example: Required external clocks for network: + + /* external reference clock */ + clk_refclk: clk-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "refclk"; + }; + + /* external reference clock for cpu. float in normal operation */ + clk_sysbypck: clk-sysbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sysbypck"; + }; + + /* external reference clock for MC. float in normal operation */ + clk_mcbypck: clk-mcbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mcbypck"; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk_rg1refck: clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg1refck"; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk_rg2refck: clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg2refck"; + }; + + clk_xin: clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_xin"; + }; + + +Example: GMAC controller node that consumes two clocks: a generated clk by the +clock controller and a fixed clock from DT (clk_rg1refck). + + ethernet0: eth@f0802000 { + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = <0 14 4>; + interrupt-names = "macirq"; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + }; diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h new file mode 100644 index 000000000000..f21522605b94 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Nuvoton NPCM7xx Clock Generator binding + * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk + * + * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com + * + */ + +#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H +#define __DT_BINDINGS_CLOCK_NPCM7XX_H + + +#define NPCM7XX_CLK_CPU 0 +#define NPCM7XX_CLK_GFX_PIXEL 1 +#define NPCM7XX_CLK_MC 2 +#define NPCM7XX_CLK_ADC 3 +#define NPCM7XX_CLK_AHB 4 +#define NPCM7XX_CLK_TIMER 5 +#define NPCM7XX_CLK_UART 6 +#define NPCM7XX_CLK_MMC 7 +#define NPCM7XX_CLK_SPI3 8 +#define NPCM7XX_CLK_PCI 9 +#define NPCM7XX_CLK_AXI 10 +#define NPCM7XX_CLK_APB4 11 +#define NPCM7XX_CLK_APB3 12 +#define NPCM7XX_CLK_APB2 13 +#define NPCM7XX_CLK_APB1 14 +#define NPCM7XX_CLK_APB5 15 +#define NPCM7XX_CLK_CLKOUT 16 +#define NPCM7XX_CLK_GFX 17 +#define NPCM7XX_CLK_SU 18 +#define NPCM7XX_CLK_SU48 19 +#define NPCM7XX_CLK_SDHC 20 +#define NPCM7XX_CLK_SPI0 21 +#define NPCM7XX_CLK_SPIX 22 + +#define NPCM7XX_CLK_REFCLK 23 +#define NPCM7XX_CLK_SYSBYPCK 24 +#define NPCM7XX_CLK_MCBYPCK 25 + +#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) + +#endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v10 2/3] NPCM750: add clock tree doc and binding @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- .../bindings/clock/nuvoton,npcm750-clk.txt | 100 +++++++++++++++++++++ include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 44 +++++++++ 2 files changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt new file mode 100644 index 000000000000..dd17b86bd577 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt @@ -0,0 +1,100 @@ +* Nuvoton NPCM7XX Clock Controller + +Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which +generates and supplies clocks to all modules within the BMC. + +External clocks: + +There are six fixed clocks that are generated outside the BMC. All clocks are of +a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and +clk_sysbypck are inputs to the clock controller. +clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the +network. They are set on the device tree, but not used by the clock module. The +network devices use them directly. +Example can be found below. + +All available clocks are defined as preprocessor macros in: +dt-bindings/clock/nuvoton,npcm7xx-clock.h +and can be reused as DT sources. + +Required Properties of clock controller: + + - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton + Poleg BMC NPCM750 + + - reg: physical base address of the clock controller and length of + memory mapped region. + + - #clock-cells: should be 1. + +Example: Clock controller node: + + clk: clock-controller at f0801000 { + compatible = "nuvoton,npcm750-clk"; + #clock-cells = <1>; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; + +Example: Required external clocks for network: + + /* external reference clock */ + clk_refclk: clk-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "refclk"; + }; + + /* external reference clock for cpu. float in normal operation */ + clk_sysbypck: clk-sysbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sysbypck"; + }; + + /* external reference clock for MC. float in normal operation */ + clk_mcbypck: clk-mcbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mcbypck"; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk_rg1refck: clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg1refck"; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk_rg2refck: clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg2refck"; + }; + + clk_xin: clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_xin"; + }; + + +Example: GMAC controller node that consumes two clocks: a generated clk by the +clock controller and a fixed clock from DT (clk_rg1refck). + + ethernet0: eth at f0802000 { + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = <0 14 4>; + interrupt-names = "macirq"; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + }; diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h new file mode 100644 index 000000000000..f21522605b94 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Nuvoton NPCM7xx Clock Generator binding + * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk + * + * Copyright (C) 2018 Nuvoton Technologies tali.perry at nuvoton.com + * + */ + +#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H +#define __DT_BINDINGS_CLOCK_NPCM7XX_H + + +#define NPCM7XX_CLK_CPU 0 +#define NPCM7XX_CLK_GFX_PIXEL 1 +#define NPCM7XX_CLK_MC 2 +#define NPCM7XX_CLK_ADC 3 +#define NPCM7XX_CLK_AHB 4 +#define NPCM7XX_CLK_TIMER 5 +#define NPCM7XX_CLK_UART 6 +#define NPCM7XX_CLK_MMC 7 +#define NPCM7XX_CLK_SPI3 8 +#define NPCM7XX_CLK_PCI 9 +#define NPCM7XX_CLK_AXI 10 +#define NPCM7XX_CLK_APB4 11 +#define NPCM7XX_CLK_APB3 12 +#define NPCM7XX_CLK_APB2 13 +#define NPCM7XX_CLK_APB1 14 +#define NPCM7XX_CLK_APB5 15 +#define NPCM7XX_CLK_CLKOUT 16 +#define NPCM7XX_CLK_GFX 17 +#define NPCM7XX_CLK_SU 18 +#define NPCM7XX_CLK_SU48 19 +#define NPCM7XX_CLK_SDHC 20 +#define NPCM7XX_CLK_SPI0 21 +#define NPCM7XX_CLK_SPIX 22 + +#define NPCM7XX_CLK_REFCLK 23 +#define NPCM7XX_CLK_SYSBYPCK 24 +#define NPCM7XX_CLK_MCBYPCK 25 + +#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) + +#endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v10 2/3] NPCM750: add clock tree doc and binding @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: brendanhiggins, robh+dt, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd Cc: devicetree, openbmc, linux-kernel, Tali Perry, linux-clk, linux-arm-kernel Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- .../bindings/clock/nuvoton,npcm750-clk.txt | 100 +++++++++++++++++++++ include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 44 +++++++++ 2 files changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt new file mode 100644 index 000000000000..dd17b86bd577 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt @@ -0,0 +1,100 @@ +* Nuvoton NPCM7XX Clock Controller + +Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which +generates and supplies clocks to all modules within the BMC. + +External clocks: + +There are six fixed clocks that are generated outside the BMC. All clocks are of +a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and +clk_sysbypck are inputs to the clock controller. +clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the +network. They are set on the device tree, but not used by the clock module. The +network devices use them directly. +Example can be found below. + +All available clocks are defined as preprocessor macros in: +dt-bindings/clock/nuvoton,npcm7xx-clock.h +and can be reused as DT sources. + +Required Properties of clock controller: + + - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton + Poleg BMC NPCM750 + + - reg: physical base address of the clock controller and length of + memory mapped region. + + - #clock-cells: should be 1. + +Example: Clock controller node: + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk"; + #clock-cells = <1>; + reg = <0xf0801000 0x1000>; + clock-names = "refclk", "sysbypck", "mcbypck"; + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; + }; + +Example: Required external clocks for network: + + /* external reference clock */ + clk_refclk: clk-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "refclk"; + }; + + /* external reference clock for cpu. float in normal operation */ + clk_sysbypck: clk-sysbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "sysbypck"; + }; + + /* external reference clock for MC. float in normal operation */ + clk_mcbypck: clk-mcbypck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mcbypck"; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk_rg1refck: clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg1refck"; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk_rg2refck: clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk_rg2refck"; + }; + + clk_xin: clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "clk_xin"; + }; + + +Example: GMAC controller node that consumes two clocks: a generated clk by the +clock controller and a fixed clock from DT (clk_rg1refck). + + ethernet0: eth@f0802000 { + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = <0 14 4>; + interrupt-names = "macirq"; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + }; diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h new file mode 100644 index 000000000000..f21522605b94 --- /dev/null +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Nuvoton NPCM7xx Clock Generator binding + * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk + * + * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com + * + */ + +#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H +#define __DT_BINDINGS_CLOCK_NPCM7XX_H + + +#define NPCM7XX_CLK_CPU 0 +#define NPCM7XX_CLK_GFX_PIXEL 1 +#define NPCM7XX_CLK_MC 2 +#define NPCM7XX_CLK_ADC 3 +#define NPCM7XX_CLK_AHB 4 +#define NPCM7XX_CLK_TIMER 5 +#define NPCM7XX_CLK_UART 6 +#define NPCM7XX_CLK_MMC 7 +#define NPCM7XX_CLK_SPI3 8 +#define NPCM7XX_CLK_PCI 9 +#define NPCM7XX_CLK_AXI 10 +#define NPCM7XX_CLK_APB4 11 +#define NPCM7XX_CLK_APB3 12 +#define NPCM7XX_CLK_APB2 13 +#define NPCM7XX_CLK_APB1 14 +#define NPCM7XX_CLK_APB5 15 +#define NPCM7XX_CLK_CLKOUT 16 +#define NPCM7XX_CLK_GFX 17 +#define NPCM7XX_CLK_SU 18 +#define NPCM7XX_CLK_SU48 19 +#define NPCM7XX_CLK_SDHC 20 +#define NPCM7XX_CLK_SPI0 21 +#define NPCM7XX_CLK_SPIX 22 + +#define NPCM7XX_CLK_REFCLK 23 +#define NPCM7XX_CLK_SYSBYPCK 24 +#define NPCM7XX_CLK_MCBYPCK 25 + +#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) + +#endif -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v10 2/3] NPCM750: add clock tree doc and binding 2018-02-25 10:12 ` Tali Perry @ 2018-03-02 22:12 ` Rob Herring -1 siblings, 0 replies; 14+ messages in thread From: Rob Herring @ 2018-03-02 22:12 UTC (permalink / raw) To: Tali Perry Cc: brendanhiggins, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd, devicetree, linux-kernel, linux-arm-kernel, openbmc, linux-clk On Sun, Feb 25, 2018 at 12:12:18PM +0200, Tali Perry wrote: > Need a commit msg. The subject should be "dt-bindings: clock: ..." > Signed-off-by: Tali Perry <tali.perry1@gmail.com> > > --- > .../bindings/clock/nuvoton,npcm750-clk.txt | 100 +++++++++++++++++++++ > include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 44 +++++++++ > 2 files changed, 144 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt > create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h > > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt > new file mode 100644 > index 000000000000..dd17b86bd577 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt > @@ -0,0 +1,100 @@ > +* Nuvoton NPCM7XX Clock Controller > + > +Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which > +generates and supplies clocks to all modules within the BMC. > + > +External clocks: > + > +There are six fixed clocks that are generated outside the BMC. All clocks are of > +a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and > +clk_sysbypck are inputs to the clock controller. > +clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the > +network. They are set on the device tree, but not used by the clock module. The > +network devices use them directly. > +Example can be found below. > + > +All available clocks are defined as preprocessor macros in: > +dt-bindings/clock/nuvoton,npcm7xx-clock.h > +and can be reused as DT sources. > + > +Required Properties of clock controller: > + > + - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton > + Poleg BMC NPCM750 > + > + - reg: physical base address of the clock controller and length of > + memory mapped region. > + > + - #clock-cells: should be 1. > + > +Example: Clock controller node: > + > + clk: clock-controller@f0801000 { > + compatible = "nuvoton,npcm750-clk"; > + #clock-cells = <1>; > + reg = <0xf0801000 0x1000>; > + clock-names = "refclk", "sysbypck", "mcbypck"; > + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; > + }; > + > +Example: Required external clocks for network: > + > + /* external reference clock */ > + clk_refclk: clk-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000>; > + clock-output-names = "refclk"; > + }; > + > + /* external reference clock for cpu. float in normal operation */ > + clk_sysbypck: clk-sysbypck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <800000000>; > + clock-output-names = "sysbypck"; > + }; > + > + /* external reference clock for MC. float in normal operation */ > + clk_mcbypck: clk-mcbypck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <800000000>; > + clock-output-names = "mcbypck"; > + }; > + > + /* external clock signal rg1refck, supplied by the phy */ > + clk_rg1refck: clk-rg1refck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "clk_rg1refck"; > + }; > + > + /* external clock signal rg2refck, supplied by the phy */ > + clk_rg2refck: clk-rg2refck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "clk_rg2refck"; > + }; > + > + clk_xin: clk-xin { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <50000000>; > + clock-output-names = "clk_xin"; > + }; > + > + > +Example: GMAC controller node that consumes two clocks: a generated clk by the > +clock controller and a fixed clock from DT (clk_rg1refck). > + > + ethernet0: eth@f0802000 { ethernet@... > + compatible = "snps,dwmac"; > + reg = <0xf0802000 0x2000>; > + interrupts = <0 14 4>; > + interrupt-names = "macirq"; > + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; > + clock-names = "stmmaceth", "clk_gmac"; > + }; > diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h > new file mode 100644 > index 000000000000..f21522605b94 > --- /dev/null > +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h > @@ -0,0 +1,44 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Nuvoton NPCM7xx Clock Generator binding > + * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk > + * > + * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com > + * > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H > +#define __DT_BINDINGS_CLOCK_NPCM7XX_H > + > + > +#define NPCM7XX_CLK_CPU 0 > +#define NPCM7XX_CLK_GFX_PIXEL 1 > +#define NPCM7XX_CLK_MC 2 > +#define NPCM7XX_CLK_ADC 3 > +#define NPCM7XX_CLK_AHB 4 > +#define NPCM7XX_CLK_TIMER 5 > +#define NPCM7XX_CLK_UART 6 > +#define NPCM7XX_CLK_MMC 7 > +#define NPCM7XX_CLK_SPI3 8 > +#define NPCM7XX_CLK_PCI 9 > +#define NPCM7XX_CLK_AXI 10 > +#define NPCM7XX_CLK_APB4 11 > +#define NPCM7XX_CLK_APB3 12 > +#define NPCM7XX_CLK_APB2 13 > +#define NPCM7XX_CLK_APB1 14 > +#define NPCM7XX_CLK_APB5 15 > +#define NPCM7XX_CLK_CLKOUT 16 > +#define NPCM7XX_CLK_GFX 17 > +#define NPCM7XX_CLK_SU 18 > +#define NPCM7XX_CLK_SU48 19 > +#define NPCM7XX_CLK_SDHC 20 > +#define NPCM7XX_CLK_SPI0 21 > +#define NPCM7XX_CLK_SPIX 22 > + > +#define NPCM7XX_CLK_REFCLK 23 > +#define NPCM7XX_CLK_SYSBYPCK 24 > +#define NPCM7XX_CLK_MCBYPCK 25 > + > +#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) > + > +#endif > -- > 2.14.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v10 2/3] NPCM750: add clock tree doc and binding @ 2018-03-02 22:12 ` Rob Herring 0 siblings, 0 replies; 14+ messages in thread From: Rob Herring @ 2018-03-02 22:12 UTC (permalink / raw) To: linux-arm-kernel On Sun, Feb 25, 2018 at 12:12:18PM +0200, Tali Perry wrote: > Need a commit msg. The subject should be "dt-bindings: clock: ..." > Signed-off-by: Tali Perry <tali.perry1@gmail.com> > > --- > .../bindings/clock/nuvoton,npcm750-clk.txt | 100 +++++++++++++++++++++ > include/dt-bindings/clock/nuvoton,npcm7xx-clock.h | 44 +++++++++ > 2 files changed, 144 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt > create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clock.h > > diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt > new file mode 100644 > index 000000000000..dd17b86bd577 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm750-clk.txt > @@ -0,0 +1,100 @@ > +* Nuvoton NPCM7XX Clock Controller > + > +Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which > +generates and supplies clocks to all modules within the BMC. > + > +External clocks: > + > +There are six fixed clocks that are generated outside the BMC. All clocks are of > +a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and > +clk_sysbypck are inputs to the clock controller. > +clk_rg1refck, clk_rg2refck and clk_xin are external clocks suppling the > +network. They are set on the device tree, but not used by the clock module. The > +network devices use them directly. > +Example can be found below. > + > +All available clocks are defined as preprocessor macros in: > +dt-bindings/clock/nuvoton,npcm7xx-clock.h > +and can be reused as DT sources. > + > +Required Properties of clock controller: > + > + - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton > + Poleg BMC NPCM750 > + > + - reg: physical base address of the clock controller and length of > + memory mapped region. > + > + - #clock-cells: should be 1. > + > +Example: Clock controller node: > + > + clk: clock-controller at f0801000 { > + compatible = "nuvoton,npcm750-clk"; > + #clock-cells = <1>; > + reg = <0xf0801000 0x1000>; > + clock-names = "refclk", "sysbypck", "mcbypck"; > + clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; > + }; > + > +Example: Required external clocks for network: > + > + /* external reference clock */ > + clk_refclk: clk-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <25000000>; > + clock-output-names = "refclk"; > + }; > + > + /* external reference clock for cpu. float in normal operation */ > + clk_sysbypck: clk-sysbypck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <800000000>; > + clock-output-names = "sysbypck"; > + }; > + > + /* external reference clock for MC. float in normal operation */ > + clk_mcbypck: clk-mcbypck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <800000000>; > + clock-output-names = "mcbypck"; > + }; > + > + /* external clock signal rg1refck, supplied by the phy */ > + clk_rg1refck: clk-rg1refck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "clk_rg1refck"; > + }; > + > + /* external clock signal rg2refck, supplied by the phy */ > + clk_rg2refck: clk-rg2refck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + clock-output-names = "clk_rg2refck"; > + }; > + > + clk_xin: clk-xin { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <50000000>; > + clock-output-names = "clk_xin"; > + }; > + > + > +Example: GMAC controller node that consumes two clocks: a generated clk by the > +clock controller and a fixed clock from DT (clk_rg1refck). > + > + ethernet0: eth at f0802000 { ethernet at ... > + compatible = "snps,dwmac"; > + reg = <0xf0802000 0x2000>; > + interrupts = <0 14 4>; > + interrupt-names = "macirq"; > + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; > + clock-names = "stmmaceth", "clk_gmac"; > + }; > diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h > new file mode 100644 > index 000000000000..f21522605b94 > --- /dev/null > +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clock.h > @@ -0,0 +1,44 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Nuvoton NPCM7xx Clock Generator binding > + * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk > + * > + * Copyright (C) 2018 Nuvoton Technologies tali.perry at nuvoton.com > + * > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H > +#define __DT_BINDINGS_CLOCK_NPCM7XX_H > + > + > +#define NPCM7XX_CLK_CPU 0 > +#define NPCM7XX_CLK_GFX_PIXEL 1 > +#define NPCM7XX_CLK_MC 2 > +#define NPCM7XX_CLK_ADC 3 > +#define NPCM7XX_CLK_AHB 4 > +#define NPCM7XX_CLK_TIMER 5 > +#define NPCM7XX_CLK_UART 6 > +#define NPCM7XX_CLK_MMC 7 > +#define NPCM7XX_CLK_SPI3 8 > +#define NPCM7XX_CLK_PCI 9 > +#define NPCM7XX_CLK_AXI 10 > +#define NPCM7XX_CLK_APB4 11 > +#define NPCM7XX_CLK_APB3 12 > +#define NPCM7XX_CLK_APB2 13 > +#define NPCM7XX_CLK_APB1 14 > +#define NPCM7XX_CLK_APB5 15 > +#define NPCM7XX_CLK_CLKOUT 16 > +#define NPCM7XX_CLK_GFX 17 > +#define NPCM7XX_CLK_SU 18 > +#define NPCM7XX_CLK_SU48 19 > +#define NPCM7XX_CLK_SDHC 20 > +#define NPCM7XX_CLK_SPI0 21 > +#define NPCM7XX_CLK_SPIX 22 > + > +#define NPCM7XX_CLK_REFCLK 23 > +#define NPCM7XX_CLK_SYSBYPCK 24 > +#define NPCM7XX_CLK_MCBYPCK 25 > + > +#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) > + > +#endif > -- > 2.14.1 > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v10 3/3] NPCM750: add clock controller driver 2018-02-25 10:12 ` Tali Perry (?) @ 2018-02-25 10:12 ` Tali Perry -1 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: brendanhiggins, robh+dt, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd Cc: devicetree, linux-kernel, linux-arm-kernel, openbmc, linux-clk, Tali Perry Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- drivers/clk/Makefile | 1 + drivers/clk/clk-npcm7xx.c | 757 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 758 insertions(+) create mode 100644 drivers/clk/clk-npcm7xx.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f7f761b02bed..89289abe0cc1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ endif obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o +obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c new file mode 100644 index 000000000000..0d373f8f114b --- /dev/null +++ b/drivers/clk/clk-npcm7xx.c @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton NPCM7xx Clock Generator + * All the clocks are initialized by the bootloader, so this driver allow only + * reading of current settings directly from the hardware. + * + * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com + */ + +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/rational.h> +#include <linux/bitfield.h> +#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + +#include <asm/cp15.h> + + +struct npcm7xx_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw) + +struct clk_hw *npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags); + +#define PLLCON_LOKI BIT(31) +#define PLLCON_LOKS BIT(30) +#define PLLCON_FBDV GENMASK(27, 16) +#define PLLCON_OTDV2 GENMASK(15, 13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV1 GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw); + unsigned long fbdv, indv, otdv1, otdv2; + unsigned int val; + u64 ret; + + if (parent_rate == 0) { + pr_err("%s: parent rate is zero. reg=%x\n", __func__, + (u32)(pll->pllcon)); + return 0; + } + + val = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, val); + fbdv = FIELD_GET(PLLCON_FBDV, val); + otdv1 = FIELD_GET(PLLCON_OTDV1, val); + otdv2 = FIELD_GET(PLLCON_OTDV2, val); + + ret = (u64)parent_rate * fbdv; + do_div(ret, indv * otdv1 * otdv2); + + return ret; +} + +const struct clk_ops npcm7xx_clk_pll_ops = { + .recalc_rate = npcm7xx_clk_pll_recalc_rate, +}; + + +struct clk_hw *npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags) +{ + struct npcm7xx_clk_pll *pll; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pr_debug("\tnpcm7xx_clk_register_pll reg, reg=0x%x, name=%s, p=%s\n", + (unsigned int)pllcon, name, parent_name); + + init.name = name; + init.ops = &npcm7xx_clk_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + hw = &pll->hw; + + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(pll); + hw = ERR_PTR(ret); + } + + return hw; +} + + +#define NPCM7XX_CLKEN1 (0x00) +#define NPCM7XX_CLKEN2 (0x28) +#define NPCM7XX_CLKEN3 (0x30) +#define NPCM7XX_CLKSEL (0x04) +#define NPCM7XX_CLKDIV1 (0x08) +#define NPCM7XX_CLKDIV2 (0x2C) +#define NPCM7XX_CLKDIV3 (0x58) +#define NPCM7XX_PLLCON0 (0x0C) +#define NPCM7XX_PLLCON1 (0x10) +#define NPCM7XX_PLLCON2 (0x54) +#define NPCM7XX_SWRSTR (0x14) +#define NPCM7XX_IRQWAKECON (0x18) +#define NPCM7XX_IRQWAKEFLAG (0x1C) +#define NPCM7XX_IPSRST1 (0x20) +#define NPCM7XX_IPSRST2 (0x24) +#define NPCM7XX_IPSRST3 (0x34) +#define NPCM7XX_WD0RCR (0x38) +#define NPCM7XX_WD1RCR (0x3C) +#define NPCM7XX_WD2RCR (0x40) +#define NPCM7XX_SWRSTC1 (0x44) +#define NPCM7XX_SWRSTC2 (0x48) +#define NPCM7XX_SWRSTC3 (0x4C) +#define NPCM7XX_SWRSTC4 (0x50) +#define NPCM7XX_CORSTC (0x5C) +#define NPCM7XX_PLLCONG (0x60) +#define NPCM7XX_AHBCKFI (0x64) +#define NPCM7XX_SECCNT (0x68) +#define NPCM7XX_CNTR25M (0x6C) + + +struct npcm7xx_clk_gate_data { + u32 reg; + u8 bit_idx; + const char *name; + const char *parent_name; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + +struct npcm7xx_clk_mux_data { + u8 shift; + u8 mask; + u32 *table; + const char *name; + const char * const *parent_names; + u8 num_parents; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; + +}; + +struct npcm7xx_clk_div_fixed_data { + u8 mult; + u8 div; + const char *name; + const char *parent_name; + u8 clk_divider_flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + + +struct npcm7xx_clk_div_data { + u32 reg; + u8 shift; + u8 width; + const char *name; + const char *parent_name; + u8 clk_divider_flags; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + +struct npcm7xx_clk_pll_data { + u32 reg; + const char *name; + const char *parent_name; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + + +/* + * Single copy of strings used to refer to clocks within this driver indexed by + * above enum. + */ +#define NPCM7XX_CLK_S_REFCLK "refclk" +#define NPCM7XX_CLK_S_SYSBYPCK "sysbypck" +#define NPCM7XX_CLK_S_MCBYPCK "mcbypck" +#define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck" +#define NPCM7XX_CLK_S_PLL0 "pll0" +#define NPCM7XX_CLK_S_PLL1 "pll1" +#define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2" +#define NPCM7XX_CLK_S_PLL2 "pll2" +#define NPCM7XX_CLK_S_PLL_GFX "pll_gfx" +#define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2" +#define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel" +#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux" +#define NPCM7XX_CLK_S_MC_MUX "mc_phy" +#define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/ +#define NPCM7XX_CLK_S_MC "mc" +#define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/ +#define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/ +#define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux" +#define NPCM7XX_CLK_S_UART_MUX "uart_mux" +#define NPCM7XX_CLK_S_TIM_MUX "timer_mux" +#define NPCM7XX_CLK_S_SD_MUX "sd_mux" +#define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux" +#define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux" +#define NPCM7XX_CLK_S_DVC_MUX "dvc_mux" +#define NPCM7XX_CLK_S_GFX_MUX "gfx_mux" +#define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel" +#define NPCM7XX_CLK_S_SPI0 "spi0" +#define NPCM7XX_CLK_S_SPI3 "spi3" +#define NPCM7XX_CLK_S_SPIX "spix" +#define NPCM7XX_CLK_S_APB1 "apb1" +#define NPCM7XX_CLK_S_APB2 "apb2" +#define NPCM7XX_CLK_S_APB3 "apb3" +#define NPCM7XX_CLK_S_APB4 "apb4" +#define NPCM7XX_CLK_S_APB5 "apb5" +#define NPCM7XX_CLK_S_TOCK "tock" +#define NPCM7XX_CLK_S_CLKOUT "clkout" +#define NPCM7XX_CLK_S_UART "uart" +#define NPCM7XX_CLK_S_TIMER "timer" +#define NPCM7XX_CLK_S_MMC "mmc" +#define NPCM7XX_CLK_S_SDHC "sdhc" +#define NPCM7XX_CLK_S_ADC "adc" +#define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem" +#define NPCM7XX_CLK_S_USBIF "serial_usbif" +#define NPCM7XX_CLK_S_USB_HOST "usb_host" +#define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge" +#define NPCM7XX_CLK_S_PCI "pci" + + +static u32 pll_mux_table[] = {0, 1, 2, 3}; +static const char * const pll_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 cpuck_mux_table[] = {0, 1, 2, 3}; +static const char * const cpuck_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_SYSBYPCK, +}; + +static u32 pixcksel_mux_table[] = {0, 2}; +static const char * const pixcksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL_GFX, + NPCM7XX_CLK_S_REFCLK, +}; + +static u32 sucksel_mux_table[] = {2, 3}; +static const char * const sucksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 mccksel_mux_table[] = {0, 2, 3}; +static const char * const mccksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_MCBYPCK, +}; + +static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4}; +static const char * const clkoutsel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL_GFX, // divided by 2 + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 gfxmsel_mux_table[] = {2, 3}; +static const char * const gfxmsel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 dvcssel_mux_table[] = {2, 3}; +static const char * const dvcssel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2, +}; + + +static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = { + {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1, + NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2, + NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX, + NPCM7XX_CLK_S_REFCLK, 0, -1}, +}; + + +static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = { + {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX, + cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL, + NPCM7XX_CLK_CPU}, + + {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX, + pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0, + NPCM7XX_CLK_GFX_PIXEL}, + + {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX, + sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1}, + + {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX, + mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1}, + + {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX, + clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1}, + + {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX, + gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1}, + + {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX, + dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1}, +}; + +/* fixed ratio dividers (no register): */ +static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = { + { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC}, + { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1}, + { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1}, +}; + + +/* configurable dividers: */ +static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = { + {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC, + NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC}, + /*30-28 ADCCKDIV*/ + {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB, + NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB}, + /*27-26 CLK4DIV*/ + {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER, + NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER}, + /*25-21 TIMCKDIV*/ + {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART, + NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART}, + /*20-16 UARTDIV*/ + {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC, + NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC}, + /*15-11 MMCCKDIV*/ + {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3}, + /*10-6 AHB3CKDIV*/ + {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI, + NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI}, + /*5-2 PCICKDIV*/ + {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI, + NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL, + NPCM7XX_CLK_AXI},/*0 CLK2DIV*/ + + {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4}, + /*31-30 APB4CKDIV*/ + {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3}, + /*29-28 APB3CKDIV*/ + {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2}, + /*27-26 APB2CKDIV*/ + {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1}, + /*25-24 APB1CKDIV*/ + {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5}, + /*23-22 APB5CKDIV*/ + {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT, + NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT}, + /*20-16 CLKOUTDIV*/ + {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX, + NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX}, + /*15-13 GFXCKDIV*/ + {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE, + NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU}, + /*12-8 SUCKDIV*/ + {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST, + NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48}, + /*7-4 SU48CKDIV*/ + {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC, + NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC} + ,/*3-0 SD1CKDIV*/ + + {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0}, + /*10-6 SPI0CKDV*/ + {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX}, + /*5-1 SPIXCKDV*/ + +}; + + +static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = { + {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0}, + {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0}, + {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0}, + {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 3 is reserved */ + {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0}, + + {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0}, + /* bit 29 is reserved */ + {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0}, + {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 24 is reserved */ + {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0}, + {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0}, + {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 20 is reserved */ + {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0}, + /* bit 17 is reserved */ + {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0}, + /* bit 15 is reserved */ + {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0}, + + {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0}, + /* bit 11 is reserved */ + /* bit 10 is reserved */ + {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 8 is reserved */ + {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0}, +}; + + +static struct clk_hw_onecell_data *npcm7xx_clk_data; +static void __iomem *clk_base; +static DEFINE_SPINLOCK(lock); + + +static const struct of_device_id npcm7xx_clk_match_table[] = { + { .compatible = "nuvoton,npcm750-clk"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, npcm7xx_clk_match_table); + + +static void __init npcm7xx_clk_init(struct device_node *clk_np) +{ + + struct resource res; + struct clk_hw *hw; + struct clk *clk; + int ret; + int i; + + pr_debug("NPCM750: clock init: "); + + clk_base = NULL; + + ret = of_address_to_resource(clk_np, 0, &res); + if (ret) { + pr_err("\t%s: failed to get resource, ret %d\n", clk_np->name, + ret); + return; + } + + + clk_base = ioremap(res.start, resource_size(&res)); + if (IS_ERR(clk_base)) { + pr_err("\tnpcm7xx_clk_init: resource error\n"); + goto npcm7xx_init_error; + } + + + npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) * + NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL); + + npcm7xx_clk_data->num = 0; + + if (!npcm7xx_clk_data->hws) { + pr_err("Can't alloc npcm7xx_clk_data\n"); + goto npcm7xx_init_np_err; + } + + npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS; + + + /* + * This way all clock fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + pr_debug("\tclk init hws\n"); + for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++) + npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + /* Read fixed clocks. These 3 clocks must be defined in DT */ + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_REFCLK); + if (!IS_ERR(clk)) { + pr_err("failed to find external REFCLK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_SYSBYPCK); + if (!IS_ERR(clk)) { + pr_err("failed to find external SYSBYPCK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_MCBYPCK); + if (!IS_ERR(clk)) { + pr_err("failed to find external MCBYPCK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + /* Register plls */ + pr_debug("\tclk register pll\n"); + for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) { + const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i]; + + pr_debug("\tclk reg pll%d, reg=0x%x, name=%s, p=%s\n", i, + (unsigned int)pll_data->reg, pll_data->name, + pll_data->parent_name); + + hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, + pll_data->name, pll_data->parent_name, pll_data->flags); + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register pll\n"); + goto npcm7xx_init_fail; + } + + if (pll_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw; + } + + /* Register fixed dividers */ + pr_debug("\tclk register fixed divs\n"); + clk = clk_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_PLL1, 0, 1, 2); + if (IS_ERR(clk)) { + pr_err("npcm7xx_clk: Can't register fixed div\n"); + goto npcm7xx_init_fail; + } + + + clk = clk_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2, + NPCM7XX_CLK_S_PLL2, 0, 1, 2); + + if (IS_ERR(clk)) { + pr_err("npcm7xx_clk: Can't register div2\n"); + goto npcm7xx_init_fail; + } + + /* Register muxes */ + for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) { + const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i]; + + pr_debug("\tadd mux%d reg=0x%x name=%s p=%s num_p=%d\n", + i, ((u32)clk_base + (u32)NPCM7XX_CLKSEL), mux_data->name, + mux_data->parent_names[0], mux_data->num_parents); + + hw = clk_hw_register_mux_table(NULL, + mux_data->name, + mux_data->parent_names, mux_data->num_parents, + mux_data->flags, clk_base + NPCM7XX_CLKSEL, + mux_data->shift, mux_data->mask, 0, + mux_data->table, &lock); + + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register mux\n"); + goto npcm7xx_init_fail; + } + + if (mux_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw; + } + + /* Register clock dividers specified in npcm7xx_divs. */ + pr_debug("\tclk register divs\n"); + for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) { + const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i]; + + pr_debug("\tadd div%d reg=0x%x name=%s, parent=%s\n", + i, (unsigned int)div_data->reg, + div_data->name, div_data->parent_name); + + hw = clk_hw_register_divider(NULL, div_data->name, + div_data->parent_name, + div_data->flags, + clk_base + div_data->reg, + div_data->shift, div_data->width, + div_data->clk_divider_flags, &lock); + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register div table\n"); + goto npcm7xx_init_fail; + } + + if (div_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[div_data->onecell_idx] = hw; + } + + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, + npcm7xx_clk_data); + if (ret) + pr_err("failed to add DT provider: %d\n", ret); + + pr_info("npcm7xx clk: %d dividers, %d muxes and %d plls registered.\n", + ARRAY_SIZE(npcm7xx_divs), ARRAY_SIZE(npcm7xx_muxes), + ARRAY_SIZE(npcm7xx_plls)); + + of_node_put(clk_np); + + return; + +npcm7xx_init_fail: + pr_debug("\tclk setup fail\n"); + if (npcm7xx_clk_data->num) + kfree(npcm7xx_clk_data->hws); +npcm7xx_init_np_err: + if (clk_base != NULL) + iounmap(clk_base); +npcm7xx_init_error: + of_node_put(clk_np); +} + +CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init); + + -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v10 3/3] NPCM750: add clock controller driver @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: linux-arm-kernel Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- drivers/clk/Makefile | 1 + drivers/clk/clk-npcm7xx.c | 757 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 758 insertions(+) create mode 100644 drivers/clk/clk-npcm7xx.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f7f761b02bed..89289abe0cc1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ endif obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o +obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c new file mode 100644 index 000000000000..0d373f8f114b --- /dev/null +++ b/drivers/clk/clk-npcm7xx.c @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton NPCM7xx Clock Generator + * All the clocks are initialized by the bootloader, so this driver allow only + * reading of current settings directly from the hardware. + * + * Copyright (C) 2018 Nuvoton Technologies tali.perry at nuvoton.com + */ + +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/rational.h> +#include <linux/bitfield.h> +#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + +#include <asm/cp15.h> + + +struct npcm7xx_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw) + +struct clk_hw *npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags); + +#define PLLCON_LOKI BIT(31) +#define PLLCON_LOKS BIT(30) +#define PLLCON_FBDV GENMASK(27, 16) +#define PLLCON_OTDV2 GENMASK(15, 13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV1 GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw); + unsigned long fbdv, indv, otdv1, otdv2; + unsigned int val; + u64 ret; + + if (parent_rate == 0) { + pr_err("%s: parent rate is zero. reg=%x\n", __func__, + (u32)(pll->pllcon)); + return 0; + } + + val = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, val); + fbdv = FIELD_GET(PLLCON_FBDV, val); + otdv1 = FIELD_GET(PLLCON_OTDV1, val); + otdv2 = FIELD_GET(PLLCON_OTDV2, val); + + ret = (u64)parent_rate * fbdv; + do_div(ret, indv * otdv1 * otdv2); + + return ret; +} + +const struct clk_ops npcm7xx_clk_pll_ops = { + .recalc_rate = npcm7xx_clk_pll_recalc_rate, +}; + + +struct clk_hw *npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags) +{ + struct npcm7xx_clk_pll *pll; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pr_debug("\tnpcm7xx_clk_register_pll reg, reg=0x%x, name=%s, p=%s\n", + (unsigned int)pllcon, name, parent_name); + + init.name = name; + init.ops = &npcm7xx_clk_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + hw = &pll->hw; + + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(pll); + hw = ERR_PTR(ret); + } + + return hw; +} + + +#define NPCM7XX_CLKEN1 (0x00) +#define NPCM7XX_CLKEN2 (0x28) +#define NPCM7XX_CLKEN3 (0x30) +#define NPCM7XX_CLKSEL (0x04) +#define NPCM7XX_CLKDIV1 (0x08) +#define NPCM7XX_CLKDIV2 (0x2C) +#define NPCM7XX_CLKDIV3 (0x58) +#define NPCM7XX_PLLCON0 (0x0C) +#define NPCM7XX_PLLCON1 (0x10) +#define NPCM7XX_PLLCON2 (0x54) +#define NPCM7XX_SWRSTR (0x14) +#define NPCM7XX_IRQWAKECON (0x18) +#define NPCM7XX_IRQWAKEFLAG (0x1C) +#define NPCM7XX_IPSRST1 (0x20) +#define NPCM7XX_IPSRST2 (0x24) +#define NPCM7XX_IPSRST3 (0x34) +#define NPCM7XX_WD0RCR (0x38) +#define NPCM7XX_WD1RCR (0x3C) +#define NPCM7XX_WD2RCR (0x40) +#define NPCM7XX_SWRSTC1 (0x44) +#define NPCM7XX_SWRSTC2 (0x48) +#define NPCM7XX_SWRSTC3 (0x4C) +#define NPCM7XX_SWRSTC4 (0x50) +#define NPCM7XX_CORSTC (0x5C) +#define NPCM7XX_PLLCONG (0x60) +#define NPCM7XX_AHBCKFI (0x64) +#define NPCM7XX_SECCNT (0x68) +#define NPCM7XX_CNTR25M (0x6C) + + +struct npcm7xx_clk_gate_data { + u32 reg; + u8 bit_idx; + const char *name; + const char *parent_name; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + +struct npcm7xx_clk_mux_data { + u8 shift; + u8 mask; + u32 *table; + const char *name; + const char * const *parent_names; + u8 num_parents; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; + +}; + +struct npcm7xx_clk_div_fixed_data { + u8 mult; + u8 div; + const char *name; + const char *parent_name; + u8 clk_divider_flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + + +struct npcm7xx_clk_div_data { + u32 reg; + u8 shift; + u8 width; + const char *name; + const char *parent_name; + u8 clk_divider_flags; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + +struct npcm7xx_clk_pll_data { + u32 reg; + const char *name; + const char *parent_name; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + + +/* + * Single copy of strings used to refer to clocks within this driver indexed by + * above enum. + */ +#define NPCM7XX_CLK_S_REFCLK "refclk" +#define NPCM7XX_CLK_S_SYSBYPCK "sysbypck" +#define NPCM7XX_CLK_S_MCBYPCK "mcbypck" +#define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck" +#define NPCM7XX_CLK_S_PLL0 "pll0" +#define NPCM7XX_CLK_S_PLL1 "pll1" +#define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2" +#define NPCM7XX_CLK_S_PLL2 "pll2" +#define NPCM7XX_CLK_S_PLL_GFX "pll_gfx" +#define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2" +#define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel" +#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux" +#define NPCM7XX_CLK_S_MC_MUX "mc_phy" +#define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/ +#define NPCM7XX_CLK_S_MC "mc" +#define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/ +#define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/ +#define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux" +#define NPCM7XX_CLK_S_UART_MUX "uart_mux" +#define NPCM7XX_CLK_S_TIM_MUX "timer_mux" +#define NPCM7XX_CLK_S_SD_MUX "sd_mux" +#define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux" +#define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux" +#define NPCM7XX_CLK_S_DVC_MUX "dvc_mux" +#define NPCM7XX_CLK_S_GFX_MUX "gfx_mux" +#define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel" +#define NPCM7XX_CLK_S_SPI0 "spi0" +#define NPCM7XX_CLK_S_SPI3 "spi3" +#define NPCM7XX_CLK_S_SPIX "spix" +#define NPCM7XX_CLK_S_APB1 "apb1" +#define NPCM7XX_CLK_S_APB2 "apb2" +#define NPCM7XX_CLK_S_APB3 "apb3" +#define NPCM7XX_CLK_S_APB4 "apb4" +#define NPCM7XX_CLK_S_APB5 "apb5" +#define NPCM7XX_CLK_S_TOCK "tock" +#define NPCM7XX_CLK_S_CLKOUT "clkout" +#define NPCM7XX_CLK_S_UART "uart" +#define NPCM7XX_CLK_S_TIMER "timer" +#define NPCM7XX_CLK_S_MMC "mmc" +#define NPCM7XX_CLK_S_SDHC "sdhc" +#define NPCM7XX_CLK_S_ADC "adc" +#define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem" +#define NPCM7XX_CLK_S_USBIF "serial_usbif" +#define NPCM7XX_CLK_S_USB_HOST "usb_host" +#define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge" +#define NPCM7XX_CLK_S_PCI "pci" + + +static u32 pll_mux_table[] = {0, 1, 2, 3}; +static const char * const pll_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 cpuck_mux_table[] = {0, 1, 2, 3}; +static const char * const cpuck_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_SYSBYPCK, +}; + +static u32 pixcksel_mux_table[] = {0, 2}; +static const char * const pixcksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL_GFX, + NPCM7XX_CLK_S_REFCLK, +}; + +static u32 sucksel_mux_table[] = {2, 3}; +static const char * const sucksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 mccksel_mux_table[] = {0, 2, 3}; +static const char * const mccksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_MCBYPCK, +}; + +static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4}; +static const char * const clkoutsel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL_GFX, // divided by 2 + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 gfxmsel_mux_table[] = {2, 3}; +static const char * const gfxmsel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 dvcssel_mux_table[] = {2, 3}; +static const char * const dvcssel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2, +}; + + +static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = { + {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1, + NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2, + NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX, + NPCM7XX_CLK_S_REFCLK, 0, -1}, +}; + + +static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = { + {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX, + cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL, + NPCM7XX_CLK_CPU}, + + {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX, + pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0, + NPCM7XX_CLK_GFX_PIXEL}, + + {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX, + sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1}, + + {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX, + mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1}, + + {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX, + clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1}, + + {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX, + gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1}, + + {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX, + dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1}, +}; + +/* fixed ratio dividers (no register): */ +static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = { + { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC}, + { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1}, + { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1}, +}; + + +/* configurable dividers: */ +static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = { + {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC, + NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC}, + /*30-28 ADCCKDIV*/ + {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB, + NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB}, + /*27-26 CLK4DIV*/ + {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER, + NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER}, + /*25-21 TIMCKDIV*/ + {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART, + NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART}, + /*20-16 UARTDIV*/ + {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC, + NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC}, + /*15-11 MMCCKDIV*/ + {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3}, + /*10-6 AHB3CKDIV*/ + {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI, + NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI}, + /*5-2 PCICKDIV*/ + {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI, + NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL, + NPCM7XX_CLK_AXI},/*0 CLK2DIV*/ + + {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4}, + /*31-30 APB4CKDIV*/ + {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3}, + /*29-28 APB3CKDIV*/ + {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2}, + /*27-26 APB2CKDIV*/ + {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1}, + /*25-24 APB1CKDIV*/ + {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5}, + /*23-22 APB5CKDIV*/ + {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT, + NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT}, + /*20-16 CLKOUTDIV*/ + {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX, + NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX}, + /*15-13 GFXCKDIV*/ + {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE, + NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU}, + /*12-8 SUCKDIV*/ + {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST, + NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48}, + /*7-4 SU48CKDIV*/ + {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC, + NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC} + ,/*3-0 SD1CKDIV*/ + + {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0}, + /*10-6 SPI0CKDV*/ + {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX}, + /*5-1 SPIXCKDV*/ + +}; + + +static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = { + {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0}, + {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0}, + {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0}, + {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 3 is reserved */ + {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0}, + + {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0}, + /* bit 29 is reserved */ + {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0}, + {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 24 is reserved */ + {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0}, + {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0}, + {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 20 is reserved */ + {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0}, + /* bit 17 is reserved */ + {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0}, + /* bit 15 is reserved */ + {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0}, + + {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0}, + /* bit 11 is reserved */ + /* bit 10 is reserved */ + {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 8 is reserved */ + {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0}, +}; + + +static struct clk_hw_onecell_data *npcm7xx_clk_data; +static void __iomem *clk_base; +static DEFINE_SPINLOCK(lock); + + +static const struct of_device_id npcm7xx_clk_match_table[] = { + { .compatible = "nuvoton,npcm750-clk"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, npcm7xx_clk_match_table); + + +static void __init npcm7xx_clk_init(struct device_node *clk_np) +{ + + struct resource res; + struct clk_hw *hw; + struct clk *clk; + int ret; + int i; + + pr_debug("NPCM750: clock init: "); + + clk_base = NULL; + + ret = of_address_to_resource(clk_np, 0, &res); + if (ret) { + pr_err("\t%s: failed to get resource, ret %d\n", clk_np->name, + ret); + return; + } + + + clk_base = ioremap(res.start, resource_size(&res)); + if (IS_ERR(clk_base)) { + pr_err("\tnpcm7xx_clk_init: resource error\n"); + goto npcm7xx_init_error; + } + + + npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) * + NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL); + + npcm7xx_clk_data->num = 0; + + if (!npcm7xx_clk_data->hws) { + pr_err("Can't alloc npcm7xx_clk_data\n"); + goto npcm7xx_init_np_err; + } + + npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS; + + + /* + * This way all clock fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + pr_debug("\tclk init hws\n"); + for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++) + npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + /* Read fixed clocks. These 3 clocks must be defined in DT */ + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_REFCLK); + if (!IS_ERR(clk)) { + pr_err("failed to find external REFCLK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_SYSBYPCK); + if (!IS_ERR(clk)) { + pr_err("failed to find external SYSBYPCK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_MCBYPCK); + if (!IS_ERR(clk)) { + pr_err("failed to find external MCBYPCK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + /* Register plls */ + pr_debug("\tclk register pll\n"); + for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) { + const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i]; + + pr_debug("\tclk reg pll%d, reg=0x%x, name=%s, p=%s\n", i, + (unsigned int)pll_data->reg, pll_data->name, + pll_data->parent_name); + + hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, + pll_data->name, pll_data->parent_name, pll_data->flags); + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register pll\n"); + goto npcm7xx_init_fail; + } + + if (pll_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw; + } + + /* Register fixed dividers */ + pr_debug("\tclk register fixed divs\n"); + clk = clk_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_PLL1, 0, 1, 2); + if (IS_ERR(clk)) { + pr_err("npcm7xx_clk: Can't register fixed div\n"); + goto npcm7xx_init_fail; + } + + + clk = clk_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2, + NPCM7XX_CLK_S_PLL2, 0, 1, 2); + + if (IS_ERR(clk)) { + pr_err("npcm7xx_clk: Can't register div2\n"); + goto npcm7xx_init_fail; + } + + /* Register muxes */ + for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) { + const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i]; + + pr_debug("\tadd mux%d reg=0x%x name=%s p=%s num_p=%d\n", + i, ((u32)clk_base + (u32)NPCM7XX_CLKSEL), mux_data->name, + mux_data->parent_names[0], mux_data->num_parents); + + hw = clk_hw_register_mux_table(NULL, + mux_data->name, + mux_data->parent_names, mux_data->num_parents, + mux_data->flags, clk_base + NPCM7XX_CLKSEL, + mux_data->shift, mux_data->mask, 0, + mux_data->table, &lock); + + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register mux\n"); + goto npcm7xx_init_fail; + } + + if (mux_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw; + } + + /* Register clock dividers specified in npcm7xx_divs. */ + pr_debug("\tclk register divs\n"); + for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) { + const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i]; + + pr_debug("\tadd div%d reg=0x%x name=%s, parent=%s\n", + i, (unsigned int)div_data->reg, + div_data->name, div_data->parent_name); + + hw = clk_hw_register_divider(NULL, div_data->name, + div_data->parent_name, + div_data->flags, + clk_base + div_data->reg, + div_data->shift, div_data->width, + div_data->clk_divider_flags, &lock); + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register div table\n"); + goto npcm7xx_init_fail; + } + + if (div_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[div_data->onecell_idx] = hw; + } + + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, + npcm7xx_clk_data); + if (ret) + pr_err("failed to add DT provider: %d\n", ret); + + pr_info("npcm7xx clk: %d dividers, %d muxes and %d plls registered.\n", + ARRAY_SIZE(npcm7xx_divs), ARRAY_SIZE(npcm7xx_muxes), + ARRAY_SIZE(npcm7xx_plls)); + + of_node_put(clk_np); + + return; + +npcm7xx_init_fail: + pr_debug("\tclk setup fail\n"); + if (npcm7xx_clk_data->num) + kfree(npcm7xx_clk_data->hws); +npcm7xx_init_np_err: + if (clk_base != NULL) + iounmap(clk_base); +npcm7xx_init_error: + of_node_put(clk_np); +} + +CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init); + + -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v10 3/3] NPCM750: add clock controller driver @ 2018-02-25 10:12 ` Tali Perry 0 siblings, 0 replies; 14+ messages in thread From: Tali Perry @ 2018-02-25 10:12 UTC (permalink / raw) To: brendanhiggins, robh+dt, mark.rutland, linux, avifishman70, tmaimon77, raltherr, mturquette, sboyd Cc: devicetree, openbmc, linux-kernel, Tali Perry, linux-clk, linux-arm-kernel Signed-off-by: Tali Perry <tali.perry1@gmail.com> --- drivers/clk/Makefile | 1 + drivers/clk/clk-npcm7xx.c | 757 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 758 insertions(+) create mode 100644 drivers/clk/clk-npcm7xx.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f7f761b02bed..89289abe0cc1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ endif obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o +obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o obj-$(CONFIG_COMMON_CLK_CDCE706) += clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c new file mode 100644 index 000000000000..0d373f8f114b --- /dev/null +++ b/drivers/clk/clk-npcm7xx.c @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton NPCM7xx Clock Generator + * All the clocks are initialized by the bootloader, so this driver allow only + * reading of current settings directly from the hardware. + * + * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com + */ + +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/rational.h> +#include <linux/bitfield.h> +#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + +#include <asm/cp15.h> + + +struct npcm7xx_clk_pll { + struct clk_hw hw; + void __iomem *pllcon; + u8 flags; +}; + +#define to_npcm7xx_clk_pll(_hw) container_of(_hw, struct npcm7xx_clk_pll, hw) + +struct clk_hw *npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags); + +#define PLLCON_LOKI BIT(31) +#define PLLCON_LOKS BIT(30) +#define PLLCON_FBDV GENMASK(27, 16) +#define PLLCON_OTDV2 GENMASK(15, 13) +#define PLLCON_PWDEN BIT(12) +#define PLLCON_OTDV1 GENMASK(10, 8) +#define PLLCON_INDV GENMASK(5, 0) + +static unsigned long npcm7xx_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct npcm7xx_clk_pll *pll = to_npcm7xx_clk_pll(hw); + unsigned long fbdv, indv, otdv1, otdv2; + unsigned int val; + u64 ret; + + if (parent_rate == 0) { + pr_err("%s: parent rate is zero. reg=%x\n", __func__, + (u32)(pll->pllcon)); + return 0; + } + + val = readl_relaxed(pll->pllcon); + + indv = FIELD_GET(PLLCON_INDV, val); + fbdv = FIELD_GET(PLLCON_FBDV, val); + otdv1 = FIELD_GET(PLLCON_OTDV1, val); + otdv2 = FIELD_GET(PLLCON_OTDV2, val); + + ret = (u64)parent_rate * fbdv; + do_div(ret, indv * otdv1 * otdv2); + + return ret; +} + +const struct clk_ops npcm7xx_clk_pll_ops = { + .recalc_rate = npcm7xx_clk_pll_recalc_rate, +}; + + +struct clk_hw *npcm7xx_clk_register_pll(void __iomem *pllcon, const char *name, + const char *parent_name, unsigned long flags) +{ + struct npcm7xx_clk_pll *pll; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pr_debug("\tnpcm7xx_clk_register_pll reg, reg=0x%x, name=%s, p=%s\n", + (unsigned int)pllcon, name, parent_name); + + init.name = name; + init.ops = &npcm7xx_clk_pll_ops; + init.parent_names = &parent_name; + init.num_parents = 1; + init.flags = flags; + + pll->pllcon = pllcon; + pll->hw.init = &init; + + hw = &pll->hw; + + ret = clk_hw_register(NULL, hw); + if (ret) { + kfree(pll); + hw = ERR_PTR(ret); + } + + return hw; +} + + +#define NPCM7XX_CLKEN1 (0x00) +#define NPCM7XX_CLKEN2 (0x28) +#define NPCM7XX_CLKEN3 (0x30) +#define NPCM7XX_CLKSEL (0x04) +#define NPCM7XX_CLKDIV1 (0x08) +#define NPCM7XX_CLKDIV2 (0x2C) +#define NPCM7XX_CLKDIV3 (0x58) +#define NPCM7XX_PLLCON0 (0x0C) +#define NPCM7XX_PLLCON1 (0x10) +#define NPCM7XX_PLLCON2 (0x54) +#define NPCM7XX_SWRSTR (0x14) +#define NPCM7XX_IRQWAKECON (0x18) +#define NPCM7XX_IRQWAKEFLAG (0x1C) +#define NPCM7XX_IPSRST1 (0x20) +#define NPCM7XX_IPSRST2 (0x24) +#define NPCM7XX_IPSRST3 (0x34) +#define NPCM7XX_WD0RCR (0x38) +#define NPCM7XX_WD1RCR (0x3C) +#define NPCM7XX_WD2RCR (0x40) +#define NPCM7XX_SWRSTC1 (0x44) +#define NPCM7XX_SWRSTC2 (0x48) +#define NPCM7XX_SWRSTC3 (0x4C) +#define NPCM7XX_SWRSTC4 (0x50) +#define NPCM7XX_CORSTC (0x5C) +#define NPCM7XX_PLLCONG (0x60) +#define NPCM7XX_AHBCKFI (0x64) +#define NPCM7XX_SECCNT (0x68) +#define NPCM7XX_CNTR25M (0x6C) + + +struct npcm7xx_clk_gate_data { + u32 reg; + u8 bit_idx; + const char *name; + const char *parent_name; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + +struct npcm7xx_clk_mux_data { + u8 shift; + u8 mask; + u32 *table; + const char *name; + const char * const *parent_names; + u8 num_parents; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; + +}; + +struct npcm7xx_clk_div_fixed_data { + u8 mult; + u8 div; + const char *name; + const char *parent_name; + u8 clk_divider_flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + + +struct npcm7xx_clk_div_data { + u32 reg; + u8 shift; + u8 width; + const char *name; + const char *parent_name; + u8 clk_divider_flags; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + +struct npcm7xx_clk_pll_data { + u32 reg; + const char *name; + const char *parent_name; + unsigned long flags; + /* + * If this clock is exported via DT, set onecell_idx to constant + * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for + * this specific clock. Otherwise, set to -1. + */ + int onecell_idx; +}; + + +/* + * Single copy of strings used to refer to clocks within this driver indexed by + * above enum. + */ +#define NPCM7XX_CLK_S_REFCLK "refclk" +#define NPCM7XX_CLK_S_SYSBYPCK "sysbypck" +#define NPCM7XX_CLK_S_MCBYPCK "mcbypck" +#define NPCM7XX_CLK_S_GFXBYPCK "gfxbypck" +#define NPCM7XX_CLK_S_PLL0 "pll0" +#define NPCM7XX_CLK_S_PLL1 "pll1" +#define NPCM7XX_CLK_S_PLL1_DIV2 "pll1_div2" +#define NPCM7XX_CLK_S_PLL2 "pll2" +#define NPCM7XX_CLK_S_PLL_GFX "pll_gfx" +#define NPCM7XX_CLK_S_PLL2_DIV2 "pll2_div2" +#define NPCM7XX_CLK_S_PIX_MUX "gfx_pixel" +#define NPCM7XX_CLK_S_GPRFSEL_MUX "gprfsel_mux" +#define NPCM7XX_CLK_S_MC_MUX "mc_phy" +#define NPCM7XX_CLK_S_CPU_MUX "cpu" /*AKA system clock.*/ +#define NPCM7XX_CLK_S_MC "mc" +#define NPCM7XX_CLK_S_AXI "axi" /*AKA CLK2*/ +#define NPCM7XX_CLK_S_AHB "ahb" /*AKA CLK4*/ +#define NPCM7XX_CLK_S_CLKOUT_MUX "clkout_mux" +#define NPCM7XX_CLK_S_UART_MUX "uart_mux" +#define NPCM7XX_CLK_S_TIM_MUX "timer_mux" +#define NPCM7XX_CLK_S_SD_MUX "sd_mux" +#define NPCM7XX_CLK_S_GFXM_MUX "gfxm_mux" +#define NPCM7XX_CLK_S_SU_MUX "serial_usb_mux" +#define NPCM7XX_CLK_S_DVC_MUX "dvc_mux" +#define NPCM7XX_CLK_S_GFX_MUX "gfx_mux" +#define NPCM7XX_CLK_S_GFX_PIXEL "gfx_pixel" +#define NPCM7XX_CLK_S_SPI0 "spi0" +#define NPCM7XX_CLK_S_SPI3 "spi3" +#define NPCM7XX_CLK_S_SPIX "spix" +#define NPCM7XX_CLK_S_APB1 "apb1" +#define NPCM7XX_CLK_S_APB2 "apb2" +#define NPCM7XX_CLK_S_APB3 "apb3" +#define NPCM7XX_CLK_S_APB4 "apb4" +#define NPCM7XX_CLK_S_APB5 "apb5" +#define NPCM7XX_CLK_S_TOCK "tock" +#define NPCM7XX_CLK_S_CLKOUT "clkout" +#define NPCM7XX_CLK_S_UART "uart" +#define NPCM7XX_CLK_S_TIMER "timer" +#define NPCM7XX_CLK_S_MMC "mmc" +#define NPCM7XX_CLK_S_SDHC "sdhc" +#define NPCM7XX_CLK_S_ADC "adc" +#define NPCM7XX_CLK_S_GFX "gfx0_gfx1_mem" +#define NPCM7XX_CLK_S_USBIF "serial_usbif" +#define NPCM7XX_CLK_S_USB_HOST "usb_host" +#define NPCM7XX_CLK_S_USB_BRIDGE "usb_bridge" +#define NPCM7XX_CLK_S_PCI "pci" + + +static u32 pll_mux_table[] = {0, 1, 2, 3}; +static const char * const pll_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 cpuck_mux_table[] = {0, 1, 2, 3}; +static const char * const cpuck_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_SYSBYPCK, +}; + +static u32 pixcksel_mux_table[] = {0, 2}; +static const char * const pixcksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL_GFX, + NPCM7XX_CLK_S_REFCLK, +}; + +static u32 sucksel_mux_table[] = {2, 3}; +static const char * const sucksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 mccksel_mux_table[] = {0, 2, 3}; +static const char * const mccksel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_MCBYPCK, +}; + +static u32 clkoutsel_mux_table[] = {0, 1, 2, 3, 4}; +static const char * const clkoutsel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_PLL0, + NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL_GFX, // divided by 2 + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 gfxmsel_mux_table[] = {2, 3}; +static const char * const gfxmsel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2_DIV2, +}; + +static u32 dvcssel_mux_table[] = {2, 3}; +static const char * const dvcssel_mux_parents[] __initconst = { + NPCM7XX_CLK_S_REFCLK, + NPCM7XX_CLK_S_PLL2, +}; + + +static const struct npcm7xx_clk_pll_data npcm7xx_plls[] __initconst = { + {NPCM7XX_PLLCON0, NPCM7XX_CLK_S_PLL0, NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCON1, NPCM7XX_CLK_S_PLL1, + NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCON2, NPCM7XX_CLK_S_PLL2, + NPCM7XX_CLK_S_REFCLK, 0, -1}, + + {NPCM7XX_PLLCONG, NPCM7XX_CLK_S_PLL_GFX, + NPCM7XX_CLK_S_REFCLK, 0, -1}, +}; + + +static const struct npcm7xx_clk_mux_data npcm7xx_muxes[] __initconst = { + {0, GENMASK(1, 0), cpuck_mux_table, NPCM7XX_CLK_S_CPU_MUX, + cpuck_mux_parents, ARRAY_SIZE(cpuck_mux_parents), CLK_IS_CRITICAL, + NPCM7XX_CLK_CPU}, + + {4, GENMASK(1, 0), pixcksel_mux_table, NPCM7XX_CLK_S_PIX_MUX, + pixcksel_mux_parents, ARRAY_SIZE(pixcksel_mux_parents), 0, + NPCM7XX_CLK_GFX_PIXEL}, + + {6, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_SD_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {8, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_UART_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {10, GENMASK(1, 0), sucksel_mux_table, NPCM7XX_CLK_S_SU_MUX, + sucksel_mux_parents, ARRAY_SIZE(sucksel_mux_parents), 0, -1}, + + {12, GENMASK(1, 0), mccksel_mux_table, NPCM7XX_CLK_S_MC_MUX, + mccksel_mux_parents, ARRAY_SIZE(mccksel_mux_parents), 0, -1}, + + {14, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_TIM_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {16, GENMASK(1, 0), pll_mux_table, NPCM7XX_CLK_S_GFX_MUX, + pll_mux_parents, ARRAY_SIZE(pll_mux_parents), 0, -1}, + + {18, GENMASK(2, 0), clkoutsel_mux_table, NPCM7XX_CLK_S_CLKOUT_MUX, + clkoutsel_mux_parents, ARRAY_SIZE(clkoutsel_mux_parents), 0, -1}, + + {21, GENMASK(1, 0), gfxmsel_mux_table, NPCM7XX_CLK_S_GFXM_MUX, + gfxmsel_mux_parents, ARRAY_SIZE(gfxmsel_mux_parents), 0, -1}, + + {23, GENMASK(1, 0), dvcssel_mux_table, NPCM7XX_CLK_S_DVC_MUX, + dvcssel_mux_parents, ARRAY_SIZE(dvcssel_mux_parents), 0, -1}, +}; + +/* fixed ratio dividers (no register): */ +static const struct npcm7xx_clk_div_fixed_data npcm7xx_divs_fx[] __initconst = { + { 1, 2, NPCM7XX_CLK_S_MC, NPCM7XX_CLK_S_MC_MUX, 0, NPCM7XX_CLK_MC}, + { 1, 2, NPCM7XX_CLK_S_PLL1_DIV2, NPCM7XX_CLK_S_PLL1, 0, -1}, + { 1, 2, NPCM7XX_CLK_S_PLL2_DIV2, NPCM7XX_CLK_S_PLL2, 0, -1}, +}; + + +/* configurable dividers: */ +static const struct npcm7xx_clk_div_data npcm7xx_divs[] __initconst = { + {NPCM7XX_CLKDIV1, 28, 3, NPCM7XX_CLK_S_ADC, + NPCM7XX_CLK_S_TIMER, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_ADC}, + /*30-28 ADCCKDIV*/ + {NPCM7XX_CLKDIV1, 26, 2, NPCM7XX_CLK_S_AHB, + NPCM7XX_CLK_S_AXI, 0, CLK_IS_CRITICAL, NPCM7XX_CLK_AHB}, + /*27-26 CLK4DIV*/ + {NPCM7XX_CLKDIV1, 21, 5, NPCM7XX_CLK_S_TIMER, + NPCM7XX_CLK_S_TIM_MUX, 0, 0, NPCM7XX_CLK_TIMER}, + /*25-21 TIMCKDIV*/ + {NPCM7XX_CLKDIV1, 16, 5, NPCM7XX_CLK_S_UART, + NPCM7XX_CLK_S_UART_MUX, 0, 0, NPCM7XX_CLK_UART}, + /*20-16 UARTDIV*/ + {NPCM7XX_CLKDIV1, 11, 5, NPCM7XX_CLK_S_MMC, + NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_MMC}, + /*15-11 MMCCKDIV*/ + {NPCM7XX_CLKDIV1, 6, 5, NPCM7XX_CLK_S_SPI3, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI3}, + /*10-6 AHB3CKDIV*/ + {NPCM7XX_CLKDIV1, 2, 4, NPCM7XX_CLK_S_PCI, + NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_PCI}, + /*5-2 PCICKDIV*/ + {NPCM7XX_CLKDIV1, 0, 1, NPCM7XX_CLK_S_AXI, + NPCM7XX_CLK_S_CPU_MUX, CLK_DIVIDER_POWER_OF_TWO, CLK_IS_CRITICAL, + NPCM7XX_CLK_AXI},/*0 CLK2DIV*/ + + {NPCM7XX_CLKDIV2, 30, 2, NPCM7XX_CLK_S_APB4, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB4}, + /*31-30 APB4CKDIV*/ + {NPCM7XX_CLKDIV2, 28, 2, NPCM7XX_CLK_S_APB3, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB3}, + /*29-28 APB3CKDIV*/ + {NPCM7XX_CLKDIV2, 26, 2, NPCM7XX_CLK_S_APB2, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB2}, + /*27-26 APB2CKDIV*/ + {NPCM7XX_CLKDIV2, 24, 2, NPCM7XX_CLK_S_APB1, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB1}, + /*25-24 APB1CKDIV*/ + {NPCM7XX_CLKDIV2, 22, 2, NPCM7XX_CLK_S_APB5, + NPCM7XX_CLK_S_AHB, CLK_DIVIDER_POWER_OF_TWO, 0, NPCM7XX_CLK_APB5}, + /*23-22 APB5CKDIV*/ + {NPCM7XX_CLKDIV2, 16, 5, NPCM7XX_CLK_S_CLKOUT, + NPCM7XX_CLK_S_CLKOUT_MUX, 0, 0, NPCM7XX_CLK_CLKOUT}, + /*20-16 CLKOUTDIV*/ + {NPCM7XX_CLKDIV2, 13, 3, NPCM7XX_CLK_S_GFX, + NPCM7XX_CLK_S_GFX_MUX, 0, 0, NPCM7XX_CLK_GFX}, + /*15-13 GFXCKDIV*/ + {NPCM7XX_CLKDIV2, 8, 5, NPCM7XX_CLK_S_USB_BRIDGE, + NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU}, + /*12-8 SUCKDIV*/ + {NPCM7XX_CLKDIV2, 4, 4, NPCM7XX_CLK_S_USB_HOST, + NPCM7XX_CLK_S_SU_MUX, 0, 0, NPCM7XX_CLK_SU48}, + /*7-4 SU48CKDIV*/ + {NPCM7XX_CLKDIV2, 0, 4, NPCM7XX_CLK_S_SDHC, + NPCM7XX_CLK_S_SD_MUX, 0, 0, NPCM7XX_CLK_SDHC} + ,/*3-0 SD1CKDIV*/ + + {NPCM7XX_CLKDIV3, 6, 5, NPCM7XX_CLK_S_SPI0, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPI0}, + /*10-6 SPI0CKDV*/ + {NPCM7XX_CLKDIV3, 1, 5, NPCM7XX_CLK_S_SPIX, + NPCM7XX_CLK_S_AHB, 0, 0, NPCM7XX_CLK_SPIX}, + /*5-1 SPIXCKDV*/ + +}; + + +static const struct npcm7xx_clk_gate_data npcm7xx_gates[] __initconst = { + {NPCM7XX_CLKEN1, 31, "smb1-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 30, "smb0-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 29, "smb7-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 28, "smb6-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 27, "adc-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 26, "wdt-gate", NPCM7XX_CLK_S_TIMER, 0}, + {NPCM7XX_CLKEN1, 25, "usbdev3-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 24, "usbdev6-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 23, "usbdev5-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 22, "usbdev4-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 21, "emc2-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 20, "timer5_9-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 19, "timer0_4-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 18, "pwmm0-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN1, 17, "huart-gate", NPCM7XX_CLK_S_UART, 0}, + {NPCM7XX_CLKEN1, 16, "smb5-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 15, "smb4-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 14, "smb3-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 13, "smb2-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN1, 12, "mc-gate", NPCM7XX_CLK_S_MC, 0}, + {NPCM7XX_CLKEN1, 11, "uart01-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 10, "aes-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 9, "peci-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN1, 8, "usbdev2-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 7, "uart23-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 6, "emc1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 5, "usbdev1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 4, "shm-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 3 is reserved */ + {NPCM7XX_CLKEN1, 2, "kcs-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN1, 1, "spi3-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN1, 0, "spi0-gate", NPCM7XX_CLK_S_AHB, 0}, + + {NPCM7XX_CLKEN2, 31, "cp-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 30, "tock-gate", NPCM7XX_CLK_S_TOCK, 0}, + /* bit 29 is reserved */ + {NPCM7XX_CLKEN2, 28, "gmac1-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 27, "usbif-gate", NPCM7XX_CLK_S_USBIF, 0}, + {NPCM7XX_CLKEN2, 26, "usbhost-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 25, "gmac2-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 24 is reserved */ + {NPCM7XX_CLKEN2, 23, "pspi2-gate", NPCM7XX_CLK_S_APB5, 0}, + {NPCM7XX_CLKEN2, 22, "pspi1-gate", NPCM7XX_CLK_S_APB5, 0}, + {NPCM7XX_CLKEN2, 21, "3des-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 20 is reserved */ + {NPCM7XX_CLKEN2, 19, "siox2-gate", NPCM7XX_CLK_S_APB3, 0}, + {NPCM7XX_CLKEN2, 18, "siox1-gate", NPCM7XX_CLK_S_APB3, 0}, + /* bit 17 is reserved */ + {NPCM7XX_CLKEN2, 16, "fuse-gate", NPCM7XX_CLK_S_APB4, 0}, + /* bit 15 is reserved */ + {NPCM7XX_CLKEN2, 14, "vcd-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 13, "ece-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 12, "vdma-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 11, "ahbpcibrg-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 10, "gfxsys-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN2, 9, "sdhc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 8, "mmc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN2, 7, "mft7-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 6, "mft6-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 5, "mft5-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 4, "mft4-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 3, "mft3-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 2, "mft2-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 1, "mft1-gate", NPCM7XX_CLK_S_APB4, 0}, + {NPCM7XX_CLKEN2, 0, "mft0-gate", NPCM7XX_CLK_S_APB4, 0}, + + {NPCM7XX_CLKEN3, 31, "gpiom7-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 30, "gpiom6-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 29, "gpiom5-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 28, "gpiom4-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 27, "gpiom3-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 26, "gpiom2-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 25, "gpiom1-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 24, "gpiom0-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 23, "espi-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 22, "smb11-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 21, "smb10-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 20, "smb9-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 19, "smb8-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 18, "smb15-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 17, "rng-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 16, "timer10_14-gate", NPCM7XX_CLK_S_APB1, 0}, + {NPCM7XX_CLKEN3, 15, "pcirc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 14, "sececc-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 13, "sha-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 12, "smb14-gate", NPCM7XX_CLK_S_APB2, 0}, + /* bit 11 is reserved */ + /* bit 10 is reserved */ + {NPCM7XX_CLKEN3, 9, "pcimbx-gate", NPCM7XX_CLK_S_AHB, 0}, + /* bit 8 is reserved */ + {NPCM7XX_CLKEN3, 7, "usbdev9-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 6, "usbdev8-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 5, "usbdev7-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 4, "usbdev0-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 3, "smb13-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 2, "spix-gate", NPCM7XX_CLK_S_AHB, 0}, + {NPCM7XX_CLKEN3, 1, "smb12-gate", NPCM7XX_CLK_S_APB2, 0}, + {NPCM7XX_CLKEN3, 0, "pwmm1-gate", NPCM7XX_CLK_S_APB3, 0}, +}; + + +static struct clk_hw_onecell_data *npcm7xx_clk_data; +static void __iomem *clk_base; +static DEFINE_SPINLOCK(lock); + + +static const struct of_device_id npcm7xx_clk_match_table[] = { + { .compatible = "nuvoton,npcm750-clk"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, npcm7xx_clk_match_table); + + +static void __init npcm7xx_clk_init(struct device_node *clk_np) +{ + + struct resource res; + struct clk_hw *hw; + struct clk *clk; + int ret; + int i; + + pr_debug("NPCM750: clock init: "); + + clk_base = NULL; + + ret = of_address_to_resource(clk_np, 0, &res); + if (ret) { + pr_err("\t%s: failed to get resource, ret %d\n", clk_np->name, + ret); + return; + } + + + clk_base = ioremap(res.start, resource_size(&res)); + if (IS_ERR(clk_base)) { + pr_err("\tnpcm7xx_clk_init: resource error\n"); + goto npcm7xx_init_error; + } + + + npcm7xx_clk_data = kzalloc(sizeof(*npcm7xx_clk_data->hws) * + NPCM7XX_NUM_CLOCKS + sizeof(npcm7xx_clk_data), GFP_KERNEL); + + npcm7xx_clk_data->num = 0; + + if (!npcm7xx_clk_data->hws) { + pr_err("Can't alloc npcm7xx_clk_data\n"); + goto npcm7xx_init_np_err; + } + + npcm7xx_clk_data->num = NPCM7XX_NUM_CLOCKS; + + + /* + * This way all clock fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + pr_debug("\tclk init hws\n"); + for (i = 0; i < NPCM7XX_NUM_CLOCKS; i++) + npcm7xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + /* Read fixed clocks. These 3 clocks must be defined in DT */ + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_REFCLK); + if (!IS_ERR(clk)) { + pr_err("failed to find external REFCLK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_SYSBYPCK); + if (!IS_ERR(clk)) { + pr_err("failed to find external SYSBYPCK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + clk = of_clk_get_by_name(clk_np, NPCM7XX_CLK_S_MCBYPCK); + if (!IS_ERR(clk)) { + pr_err("failed to find external MCBYPCK: %ld\n", + PTR_ERR(clk)); + clk_put(clk); + } + + /* Register plls */ + pr_debug("\tclk register pll\n"); + for (i = 0; i < ARRAY_SIZE(npcm7xx_plls); i++) { + const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i]; + + pr_debug("\tclk reg pll%d, reg=0x%x, name=%s, p=%s\n", i, + (unsigned int)pll_data->reg, pll_data->name, + pll_data->parent_name); + + hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, + pll_data->name, pll_data->parent_name, pll_data->flags); + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register pll\n"); + goto npcm7xx_init_fail; + } + + if (pll_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw; + } + + /* Register fixed dividers */ + pr_debug("\tclk register fixed divs\n"); + clk = clk_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL1_DIV2, + NPCM7XX_CLK_S_PLL1, 0, 1, 2); + if (IS_ERR(clk)) { + pr_err("npcm7xx_clk: Can't register fixed div\n"); + goto npcm7xx_init_fail; + } + + + clk = clk_register_fixed_factor(NULL, NPCM7XX_CLK_S_PLL2_DIV2, + NPCM7XX_CLK_S_PLL2, 0, 1, 2); + + if (IS_ERR(clk)) { + pr_err("npcm7xx_clk: Can't register div2\n"); + goto npcm7xx_init_fail; + } + + /* Register muxes */ + for (i = 0; i < ARRAY_SIZE(npcm7xx_muxes); i++) { + const struct npcm7xx_clk_mux_data *mux_data = &npcm7xx_muxes[i]; + + pr_debug("\tadd mux%d reg=0x%x name=%s p=%s num_p=%d\n", + i, ((u32)clk_base + (u32)NPCM7XX_CLKSEL), mux_data->name, + mux_data->parent_names[0], mux_data->num_parents); + + hw = clk_hw_register_mux_table(NULL, + mux_data->name, + mux_data->parent_names, mux_data->num_parents, + mux_data->flags, clk_base + NPCM7XX_CLKSEL, + mux_data->shift, mux_data->mask, 0, + mux_data->table, &lock); + + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register mux\n"); + goto npcm7xx_init_fail; + } + + if (mux_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[mux_data->onecell_idx] = hw; + } + + /* Register clock dividers specified in npcm7xx_divs. */ + pr_debug("\tclk register divs\n"); + for (i = 0; i < ARRAY_SIZE(npcm7xx_divs); i++) { + const struct npcm7xx_clk_div_data *div_data = &npcm7xx_divs[i]; + + pr_debug("\tadd div%d reg=0x%x name=%s, parent=%s\n", + i, (unsigned int)div_data->reg, + div_data->name, div_data->parent_name); + + hw = clk_hw_register_divider(NULL, div_data->name, + div_data->parent_name, + div_data->flags, + clk_base + div_data->reg, + div_data->shift, div_data->width, + div_data->clk_divider_flags, &lock); + if (IS_ERR(hw)) { + pr_err("npcm7xx_clk: Can't register div table\n"); + goto npcm7xx_init_fail; + } + + if (div_data->onecell_idx >= 0) + npcm7xx_clk_data->hws[div_data->onecell_idx] = hw; + } + + ret = of_clk_add_hw_provider(clk_np, of_clk_hw_onecell_get, + npcm7xx_clk_data); + if (ret) + pr_err("failed to add DT provider: %d\n", ret); + + pr_info("npcm7xx clk: %d dividers, %d muxes and %d plls registered.\n", + ARRAY_SIZE(npcm7xx_divs), ARRAY_SIZE(npcm7xx_muxes), + ARRAY_SIZE(npcm7xx_plls)); + + of_node_put(clk_np); + + return; + +npcm7xx_init_fail: + pr_debug("\tclk setup fail\n"); + if (npcm7xx_clk_data->num) + kfree(npcm7xx_clk_data->hws); +npcm7xx_init_np_err: + if (clk_base != NULL) + iounmap(clk_base); +npcm7xx_init_error: + of_node_put(clk_np); +} + +CLK_OF_DECLARE(npcm7xx_clk_init, "nuvoton,npcm750-clk", npcm7xx_clk_init); + + -- 2.14.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2018-03-02 22:12 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-02-25 10:12 [PATCH v10 0/3] NPCM750: clk controller, DT and binding Tali Perry 2018-02-25 10:12 ` Tali Perry 2018-02-25 10:12 ` Tali Perry 2018-02-25 10:12 ` [PATCH v10 1/3] NPCM750: add clock controller to DT Tali Perry 2018-02-25 10:12 ` Tali Perry 2018-02-25 10:12 ` Tali Perry 2018-02-25 10:12 ` [PATCH v10 2/3] NPCM750: add clock tree doc and binding Tali Perry 2018-02-25 10:12 ` Tali Perry 2018-02-25 10:12 ` Tali Perry 2018-03-02 22:12 ` Rob Herring 2018-03-02 22:12 ` Rob Herring 2018-02-25 10:12 ` [PATCH v10 3/3] NPCM750: add clock controller driver Tali Perry 2018-02-25 10:12 ` Tali Perry 2018-02-25 10:12 ` Tali Perry
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