* [PATCH igt] igt/gem_exec_schedule: Exercise "deep" preemption
@ 2018-02-24 18:38 Chris Wilson
2018-02-25 13:25 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Chris Wilson @ 2018-02-24 18:38 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala
In investigating the issue with having to force preemption within the
executing ELSP[], we want to trigger preemption between all elements of
that array. To that end, we issue a series of requests with different
priorities to fill the in-flight ELSP[] and then demand preemption into
the middle of that series. One can think of even more complicated
reordering requirements of ELSP[], trying to switch between every
possible combination of permutations. Rather than check all 2 billion
combinations, be content with a few.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
---
tests/gem_exec_schedule.c | 172 +++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 153 insertions(+), 19 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 8a69ab5c..87fe4572 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -373,13 +373,77 @@ static void preempt(int fd, unsigned ring, unsigned flags)
gem_close(fd, result);
}
-static void preempt_other(int fd, unsigned ring)
+#define CHAIN 0x1
+
+static igt_spin_t *__noise(int fd, uint32_t ctx, int prio, igt_spin_t *spin)
+{
+ unsigned other;
+
+ gem_context_set_priority(fd, ctx, prio);
+
+ for_each_physical_engine(fd, other) {
+ if (spin == NULL) {
+ spin = __igt_spin_batch_new(fd, ctx, other, 0);
+ } else {
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = spin->handle,
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&obj),
+ .rsvd1 = ctx,
+ .flags = other,
+ };
+ gem_execbuf(fd, &eb);
+ }
+ }
+
+ return spin;
+}
+
+static void __preempt_other(int fd,
+ uint32_t *ctx,
+ unsigned int target, unsigned int primary,
+ unsigned flags)
{
uint32_t result = gem_create(fd, 4096);
uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
- igt_spin_t *spin[MAX_ENGINES];
- unsigned int other;
- unsigned int n, i;
+ unsigned int n, i, other;
+
+ n = 0;
+ store_dword(fd, ctx[LO], primary,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+ n++;
+
+ if (flags & CHAIN) {
+ for_each_physical_engine(fd, other) {
+ store_dword(fd, ctx[LO], other,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+ n++;
+ }
+ }
+
+ store_dword(fd, ctx[HI], target,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+
+ igt_debugfs_dump(fd, "i915_engine_info");
+ gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
+
+ n++;
+ for (i = 0; i <= n; i++)
+ igt_assert_eq_u32(ptr[i], i);
+
+ munmap(ptr, 4096);
+ gem_close(fd, result);
+}
+
+static void preempt_other(int fd, unsigned ring, unsigned int flags)
+{
+ unsigned int primary;
+ igt_spin_t *spin = NULL;
uint32_t ctx[3];
/* On each engine, insert
@@ -396,36 +460,87 @@ static void preempt_other(int fd, unsigned ring)
gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
ctx[NOISE] = gem_context_create(fd);
+ spin = __noise(fd, ctx[NOISE], 0, NULL);
ctx[HI] = gem_context_create(fd);
gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
+ for_each_physical_engine(fd, primary) {
+ igt_debug("Primary engine: %s\n", e__->name);
+ __preempt_other(fd, ctx, ring, primary, flags);
+
+ }
+
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ igt_spin_batch_free(fd, spin);
+
+ gem_context_destroy(fd, ctx[LO]);
+ gem_context_destroy(fd, ctx[NOISE]);
+ gem_context_destroy(fd, ctx[HI]);
+}
+
+static void __preempt_queue(int fd,
+ unsigned target, unsigned primary,
+ unsigned depth, unsigned flags)
+{
+ uint32_t result = gem_create(fd, 4096);
+ uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
+ igt_spin_t *above = NULL, *below = NULL;
+ unsigned int other, n, i;
+ int prio = MAX_PRIO;
+ uint32_t ctx[3] = {
+ gem_context_create(fd),
+ gem_context_create(fd),
+ gem_context_create(fd),
+ };
+
+ for (n = 0; n < depth; n++)
+ above = __noise(fd, ctx[NOISE], prio--, above);
+
+ gem_context_set_priority(fd, ctx[HI], prio--);
+
+ for (; n < MAX_ELSP_QLEN; n++)
+ below = __noise(fd, ctx[NOISE], prio--, below);
+
+ gem_context_set_priority(fd, ctx[LO], prio--);
+
n = 0;
- for_each_physical_engine(fd, other) {
- igt_assert(n < ARRAY_SIZE(spin));
+ store_dword(fd, ctx[LO], primary,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+ n++;
- spin[n] = __igt_spin_batch_new(fd, ctx[NOISE], other, 0);
- store_dword(fd, ctx[LO], other,
- result, (n + 1)*sizeof(uint32_t), n + 1,
- 0, I915_GEM_DOMAIN_RENDER);
- n++;
+ if (flags & CHAIN) {
+ for_each_physical_engine(fd, other) {
+ store_dword(fd, ctx[LO], other,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+ n++;
+ }
}
- store_dword(fd, ctx[HI], ring,
+
+ store_dword(fd, ctx[HI], target,
result, (n + 1)*sizeof(uint32_t), n + 1,
0, I915_GEM_DOMAIN_RENDER);
igt_debugfs_dump(fd, "i915_engine_info");
- gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
- for (i = 0; i < n; i++) {
- igt_assert(gem_bo_busy(fd, spin[i]->handle));
- igt_spin_batch_free(fd, spin[i]);
+ if (above) {
+ igt_assert(gem_bo_busy(fd, above->handle));
+ igt_spin_batch_free(fd, above);
}
+ gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
+
n++;
for (i = 0; i <= n; i++)
igt_assert_eq_u32(ptr[i], i);
+ if (below) {
+ igt_assert(gem_bo_busy(fd, below->handle));
+ igt_spin_batch_free(fd, below);
+ }
+
gem_context_destroy(fd, ctx[LO]);
gem_context_destroy(fd, ctx[NOISE]);
gem_context_destroy(fd, ctx[HI]);
@@ -434,6 +549,16 @@ static void preempt_other(int fd, unsigned ring)
gem_close(fd, result);
}
+static void preempt_queue(int fd, unsigned ring, unsigned int flags)
+{
+ unsigned other;
+
+ for_each_physical_engine(fd, other) {
+ for (unsigned depth = 0; depth <= MAX_ELSP_QLEN; depth++)
+ __preempt_queue(fd, ring, other, depth, flags);
+ }
+}
+
static void preempt_self(int fd, unsigned ring)
{
uint32_t result = gem_create(fd, 4096);
@@ -981,12 +1106,21 @@ igt_main
igt_subtest_f("preempt-contexts-%s", e->name)
preempt(fd, e->exec_id | e->flags, NEW_CTX);
- igt_subtest_f("preempt-other-%s", e->name)
- preempt_other(fd, e->exec_id | e->flags);
-
igt_subtest_f("preempt-self-%s", e->name)
preempt_self(fd, e->exec_id | e->flags);
+ igt_subtest_f("preempt-other-%s", e->name)
+ preempt_other(fd, e->exec_id | e->flags, 0);
+
+ igt_subtest_f("preempt-other-chain-%s", e->name)
+ preempt_other(fd, e->exec_id | e->flags, CHAIN);
+
+ igt_subtest_f("preempt-queue-%s", e->name)
+ preempt_queue(fd, e->exec_id | e->flags, 0);
+
+ igt_subtest_f("preempt-queue-chain-%s", e->name)
+ preempt_queue(fd, e->exec_id | e->flags, CHAIN);
+
igt_subtest_group {
igt_hang_t hang;
--
2.16.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for igt/gem_exec_schedule: Exercise "deep" preemption
2018-02-24 18:38 [PATCH igt] igt/gem_exec_schedule: Exercise "deep" preemption Chris Wilson
@ 2018-02-25 13:25 ` Patchwork
2018-02-25 14:11 ` ✗ Fi.CI.IGT: warning " Patchwork
2018-02-26 15:26 ` [PATCH igt v2] " Chris Wilson
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-02-25 13:25 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: igt/gem_exec_schedule: Exercise "deep" preemption
URL : https://patchwork.freedesktop.org/series/38914/
State : success
== Summary ==
IGT patchset tested on top of latest successful build
305ebcedc36e98f3118ac27a5bbde0ce7cd71a74 Iterate over physical engines
with latest DRM-Tip kernel build CI_DRM_3830
316ba650abe6 drm-tip: 2018y-02m-23d-16h-41m-52s UTC integration manifest
Testlist changes:
+igt@gem_exec_schedule@preempt-other-chain-blt
+igt@gem_exec_schedule@preempt-other-chain-bsd
+igt@gem_exec_schedule@preempt-other-chain-bsd1
+igt@gem_exec_schedule@preempt-other-chain-bsd2
+igt@gem_exec_schedule@preempt-other-chain-render
+igt@gem_exec_schedule@preempt-other-chain-vebox
+igt@gem_exec_schedule@preempt-queue-blt
+igt@gem_exec_schedule@preempt-queue-bsd
+igt@gem_exec_schedule@preempt-queue-bsd1
+igt@gem_exec_schedule@preempt-queue-bsd2
+igt@gem_exec_schedule@preempt-queue-chain-blt
+igt@gem_exec_schedule@preempt-queue-chain-bsd
+igt@gem_exec_schedule@preempt-queue-chain-bsd1
+igt@gem_exec_schedule@preempt-queue-chain-bsd2
+igt@gem_exec_schedule@preempt-queue-chain-render
+igt@gem_exec_schedule@preempt-queue-chain-vebox
+igt@gem_exec_schedule@preempt-queue-render
+igt@gem_exec_schedule@preempt-queue-vebox
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_chamelium:
Subgroup dp-edid-read:
fail -> PASS (fi-kbl-7500u) fdo#102505
Test kms_force_connector_basic:
Subgroup force-connector-state:
skip -> PASS (fi-snb-2520m)
Subgroup force-edid:
skip -> PASS (fi-snb-2520m)
Subgroup force-load-detect:
skip -> PASS (fi-snb-2520m)
Subgroup prune-stale-modes:
skip -> PASS (fi-snb-2520m)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
Subgroup suspend-read-crc-pipe-c:
incomplete -> PASS (fi-bxt-dsi) fdo#103927
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:419s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:427s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:485s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:285s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:480s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:484s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:466s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:457s
fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:391s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:568s
fi-cnl-y3 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:568s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:417s
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:284s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:508s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:386s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:409s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:452s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:452s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:493s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:450s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:492s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:588s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:430s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:500s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:521s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:491s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:469s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:405s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:431s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:395s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1000/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.IGT: warning for igt/gem_exec_schedule: Exercise "deep" preemption
2018-02-24 18:38 [PATCH igt] igt/gem_exec_schedule: Exercise "deep" preemption Chris Wilson
2018-02-25 13:25 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-02-25 14:11 ` Patchwork
2018-02-26 15:26 ` [PATCH igt v2] " Chris Wilson
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-02-25 14:11 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: igt/gem_exec_schedule: Exercise "deep" preemption
URL : https://patchwork.freedesktop.org/series/38914/
State : warning
== Summary ==
Test drv_suspend:
Subgroup fence-restore-tiled2untiled:
skip -> PASS (shard-hsw)
Test kms_chv_cursor_fail:
Subgroup pipe-a-64x64-top-edge:
fail -> PASS (shard-apl)
Test kms_flip:
Subgroup wf_vblank-ts-check:
pass -> FAIL (shard-hsw) fdo#100368 +1
Subgroup dpms-vs-vblank-race:
pass -> FAIL (shard-hsw) fdo#103060
Subgroup flip-vs-expired-vblank:
pass -> FAIL (shard-hsw) fdo#102887
Test kms_sysfs_edid_timing:
pass -> WARN (shard-apl) fdo#100047
Test kms_plane:
Subgroup plane-position-hole-dpms-pipe-b-planes:
fail -> PASS (shard-apl)
Test gem_exec_async:
Subgroup concurrent-writes-bsd1:
pass -> SKIP (shard-hsw)
pass -> SKIP (shard-apl)
Subgroup concurrent-writes-bsd2:
pass -> SKIP (shard-hsw)
pass -> SKIP (shard-apl)
Test kms_rotation_crc:
Subgroup primary-rotation-180:
pass -> FAIL (shard-snb) fdo#103925
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
shard-apl total:3483 pass:1831 dwarn:1 dfail:0 fail:11 skip:1639 time:12274s
shard-hsw total:3483 pass:1763 dwarn:1 dfail:0 fail:6 skip:1712 time:11714s
shard-snb total:3483 pass:1358 dwarn:1 dfail:0 fail:3 skip:2121 time:6700s
Blacklisted hosts:
shard-kbl total:3481 pass:1949 dwarn:1 dfail:0 fail:20 skip:1510 time:9301s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1000/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH igt v2] igt/gem_exec_schedule: Exercise "deep" preemption
2018-02-24 18:38 [PATCH igt] igt/gem_exec_schedule: Exercise "deep" preemption Chris Wilson
2018-02-25 13:25 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-02-25 14:11 ` ✗ Fi.CI.IGT: warning " Patchwork
@ 2018-02-26 15:26 ` Chris Wilson
2018-02-27 10:44 ` Chris Wilson
2018-02-27 13:25 ` Mika Kuoppala
2 siblings, 2 replies; 7+ messages in thread
From: Chris Wilson @ 2018-02-26 15:26 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika Kuoppala
In investigating the issue with having to force preemption within the
executing ELSP[], we want to trigger preemption between all elements of
that array. To that end, we issue a series of requests with different
priorities to fill the in-flight ELSP[] and then demand preemption into
the middle of that series. One can think of even more complicated
reordering requirements of ELSP[], trying to switch between every
possible combination of permutations. Rather than check all 2 billion
combinations, be content with a few.
v2: Add a different pattern for queued requests. Not only do we need to
inject a request into the middle of a single context with a queue of
different priority contexts, but we also want a queue of different
contexts, as they have different patterns of ELSP[] behaviour.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
---
tests/gem_exec_schedule.c | 188 +++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 169 insertions(+), 19 deletions(-)
diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
index 8a69ab5c..7f1bda42 100644
--- a/tests/gem_exec_schedule.c
+++ b/tests/gem_exec_schedule.c
@@ -373,13 +373,78 @@ static void preempt(int fd, unsigned ring, unsigned flags)
gem_close(fd, result);
}
-static void preempt_other(int fd, unsigned ring)
+#define CHAIN 0x1
+#define CONTEXTS 0x2
+
+static igt_spin_t *__noise(int fd, uint32_t ctx, int prio, igt_spin_t *spin)
+{
+ unsigned other;
+
+ gem_context_set_priority(fd, ctx, prio);
+
+ for_each_physical_engine(fd, other) {
+ if (spin == NULL) {
+ spin = __igt_spin_batch_new(fd, ctx, other, 0);
+ } else {
+ struct drm_i915_gem_exec_object2 obj = {
+ .handle = spin->handle,
+ };
+ struct drm_i915_gem_execbuffer2 eb = {
+ .buffer_count = 1,
+ .buffers_ptr = to_user_pointer(&obj),
+ .rsvd1 = ctx,
+ .flags = other,
+ };
+ gem_execbuf(fd, &eb);
+ }
+ }
+
+ return spin;
+}
+
+static void __preempt_other(int fd,
+ uint32_t *ctx,
+ unsigned int target, unsigned int primary,
+ unsigned flags)
{
uint32_t result = gem_create(fd, 4096);
uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
- igt_spin_t *spin[MAX_ENGINES];
- unsigned int other;
- unsigned int n, i;
+ unsigned int n, i, other;
+
+ n = 0;
+ store_dword(fd, ctx[LO], primary,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+ n++;
+
+ if (flags & CHAIN) {
+ for_each_physical_engine(fd, other) {
+ store_dword(fd, ctx[LO], other,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+ n++;
+ }
+ }
+
+ store_dword(fd, ctx[HI], target,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+
+ igt_debugfs_dump(fd, "i915_engine_info");
+ gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
+
+ n++;
+ for (i = 0; i <= n; i++)
+ igt_assert_eq_u32(ptr[i], i);
+
+ munmap(ptr, 4096);
+ gem_close(fd, result);
+}
+
+static void preempt_other(int fd, unsigned ring, unsigned int flags)
+{
+ unsigned int primary;
+ igt_spin_t *spin = NULL;
uint32_t ctx[3];
/* On each engine, insert
@@ -396,36 +461,97 @@ static void preempt_other(int fd, unsigned ring)
gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
ctx[NOISE] = gem_context_create(fd);
+ spin = __noise(fd, ctx[NOISE], 0, NULL);
ctx[HI] = gem_context_create(fd);
gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
+ for_each_physical_engine(fd, primary) {
+ igt_debug("Primary engine: %s\n", e__->name);
+ __preempt_other(fd, ctx, ring, primary, flags);
+
+ }
+
+ igt_assert(gem_bo_busy(fd, spin->handle));
+ igt_spin_batch_free(fd, spin);
+
+ gem_context_destroy(fd, ctx[LO]);
+ gem_context_destroy(fd, ctx[NOISE]);
+ gem_context_destroy(fd, ctx[HI]);
+}
+
+static void __preempt_queue(int fd,
+ unsigned target, unsigned primary,
+ unsigned depth, unsigned flags)
+{
+ uint32_t result = gem_create(fd, 4096);
+ uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
+ igt_spin_t *above = NULL, *below = NULL;
+ unsigned int other, n, i;
+ int prio = MAX_PRIO;
+ uint32_t ctx[3] = {
+ gem_context_create(fd),
+ gem_context_create(fd),
+ gem_context_create(fd),
+ };
+
+ for (n = 0; n < depth; n++) {
+ if (flags & CONTEXTS) {
+ gem_context_destroy(fd, ctx[NOISE]);
+ ctx[NOISE] = gem_context_create(fd);
+ }
+ above = __noise(fd, ctx[NOISE], prio--, above);
+ }
+
+ gem_context_set_priority(fd, ctx[HI], prio--);
+
+ for (; n < MAX_ELSP_QLEN; n++) {
+ if (flags & CONTEXTS) {
+ gem_context_destroy(fd, ctx[NOISE]);
+ ctx[NOISE] = gem_context_create(fd);
+ }
+ below = __noise(fd, ctx[NOISE], prio--, below);
+ }
+
+ gem_context_set_priority(fd, ctx[LO], prio--);
+
n = 0;
- for_each_physical_engine(fd, other) {
- igt_assert(n < ARRAY_SIZE(spin));
+ store_dword(fd, ctx[LO], primary,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+ n++;
- spin[n] = __igt_spin_batch_new(fd, ctx[NOISE], other, 0);
- store_dword(fd, ctx[LO], other,
- result, (n + 1)*sizeof(uint32_t), n + 1,
- 0, I915_GEM_DOMAIN_RENDER);
- n++;
+ if (flags & CHAIN) {
+ for_each_physical_engine(fd, other) {
+ store_dword(fd, ctx[LO], other,
+ result, (n + 1)*sizeof(uint32_t), n + 1,
+ 0, I915_GEM_DOMAIN_RENDER);
+ n++;
+ }
}
- store_dword(fd, ctx[HI], ring,
+
+ store_dword(fd, ctx[HI], target,
result, (n + 1)*sizeof(uint32_t), n + 1,
0, I915_GEM_DOMAIN_RENDER);
igt_debugfs_dump(fd, "i915_engine_info");
- gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
- for (i = 0; i < n; i++) {
- igt_assert(gem_bo_busy(fd, spin[i]->handle));
- igt_spin_batch_free(fd, spin[i]);
+ if (above) {
+ igt_assert(gem_bo_busy(fd, above->handle));
+ igt_spin_batch_free(fd, above);
}
+ gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
+
n++;
for (i = 0; i <= n; i++)
igt_assert_eq_u32(ptr[i], i);
+ if (below) {
+ igt_assert(gem_bo_busy(fd, below->handle));
+ igt_spin_batch_free(fd, below);
+ }
+
gem_context_destroy(fd, ctx[LO]);
gem_context_destroy(fd, ctx[NOISE]);
gem_context_destroy(fd, ctx[HI]);
@@ -434,6 +560,16 @@ static void preempt_other(int fd, unsigned ring)
gem_close(fd, result);
}
+static void preempt_queue(int fd, unsigned ring, unsigned int flags)
+{
+ unsigned other;
+
+ for_each_physical_engine(fd, other) {
+ for (unsigned depth = 0; depth <= MAX_ELSP_QLEN; depth++)
+ __preempt_queue(fd, ring, other, depth, flags);
+ }
+}
+
static void preempt_self(int fd, unsigned ring)
{
uint32_t result = gem_create(fd, 4096);
@@ -981,12 +1117,26 @@ igt_main
igt_subtest_f("preempt-contexts-%s", e->name)
preempt(fd, e->exec_id | e->flags, NEW_CTX);
- igt_subtest_f("preempt-other-%s", e->name)
- preempt_other(fd, e->exec_id | e->flags);
-
igt_subtest_f("preempt-self-%s", e->name)
preempt_self(fd, e->exec_id | e->flags);
+ igt_subtest_f("preempt-other-%s", e->name)
+ preempt_other(fd, e->exec_id | e->flags, 0);
+
+ igt_subtest_f("preempt-other-chain-%s", e->name)
+ preempt_other(fd, e->exec_id | e->flags, CHAIN);
+
+ igt_subtest_f("preempt-queue-%s", e->name)
+ preempt_queue(fd, e->exec_id | e->flags, 0);
+
+ igt_subtest_f("preempt-queue-chain-%s", e->name)
+ preempt_queue(fd, e->exec_id | e->flags, CHAIN);
+ igt_subtest_f("preempt-contexts-%s", e->name)
+ preempt_queue(fd, e->exec_id | e->flags, CONTEXTS);
+
+ igt_subtest_f("preempt-contexts-chain-%s", e->name)
+ preempt_queue(fd, e->exec_id | e->flags, CONTEXTS | CHAIN);
+
igt_subtest_group {
igt_hang_t hang;
--
2.16.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH igt v2] igt/gem_exec_schedule: Exercise "deep" preemption
2018-02-26 15:26 ` [PATCH igt v2] " Chris Wilson
@ 2018-02-27 10:44 ` Chris Wilson
2018-02-27 13:25 ` Mika Kuoppala
1 sibling, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2018-02-27 10:44 UTC (permalink / raw)
To: intel-gfx; +Cc: Mika
Quoting Chris Wilson (2018-02-26 15:26:58)
> In investigating the issue with having to force preemption within the
> executing ELSP[], we want to trigger preemption between all elements of
> that array. To that end, we issue a series of requests with different
> priorities to fill the in-flight ELSP[] and then demand preemption into
> the middle of that series. One can think of even more complicated
> reordering requirements of ELSP[], trying to switch between every
> possible combination of permutations. Rather than check all 2 billion
> combinations, be content with a few.
>
> v2: Add a different pattern for queued requests. Not only do we need to
> inject a request into the middle of a single context with a queue of
> different priority contexts, but we also want a queue of different
> contexts, as they have different patterns of ELSP[] behaviour.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
Just nod. :)
Don't mention fMBT.
-Chris
> ---
> tests/gem_exec_schedule.c | 188 +++++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 169 insertions(+), 19 deletions(-)
>
> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> index 8a69ab5c..7f1bda42 100644
> --- a/tests/gem_exec_schedule.c
> +++ b/tests/gem_exec_schedule.c
> @@ -373,13 +373,78 @@ static void preempt(int fd, unsigned ring, unsigned flags)
> gem_close(fd, result);
> }
>
> -static void preempt_other(int fd, unsigned ring)
> +#define CHAIN 0x1
> +#define CONTEXTS 0x2
> +
> +static igt_spin_t *__noise(int fd, uint32_t ctx, int prio, igt_spin_t *spin)
> +{
> + unsigned other;
> +
> + gem_context_set_priority(fd, ctx, prio);
> +
> + for_each_physical_engine(fd, other) {
> + if (spin == NULL) {
> + spin = __igt_spin_batch_new(fd, ctx, other, 0);
> + } else {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = spin->handle,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&obj),
> + .rsvd1 = ctx,
> + .flags = other,
> + };
> + gem_execbuf(fd, &eb);
> + }
> + }
> +
> + return spin;
> +}
> +
> +static void __preempt_other(int fd,
> + uint32_t *ctx,
> + unsigned int target, unsigned int primary,
> + unsigned flags)
> {
> uint32_t result = gem_create(fd, 4096);
> uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
> - igt_spin_t *spin[MAX_ENGINES];
> - unsigned int other;
> - unsigned int n, i;
> + unsigned int n, i, other;
> +
> + n = 0;
> + store_dword(fd, ctx[LO], primary,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> + n++;
> +
> + if (flags & CHAIN) {
> + for_each_physical_engine(fd, other) {
> + store_dword(fd, ctx[LO], other,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> + n++;
> + }
> + }
> +
> + store_dword(fd, ctx[HI], target,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> +
> + igt_debugfs_dump(fd, "i915_engine_info");
> + gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
> +
> + n++;
> + for (i = 0; i <= n; i++)
> + igt_assert_eq_u32(ptr[i], i);
> +
> + munmap(ptr, 4096);
> + gem_close(fd, result);
> +}
> +
> +static void preempt_other(int fd, unsigned ring, unsigned int flags)
> +{
> + unsigned int primary;
> + igt_spin_t *spin = NULL;
> uint32_t ctx[3];
>
> /* On each engine, insert
> @@ -396,36 +461,97 @@ static void preempt_other(int fd, unsigned ring)
> gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
>
> ctx[NOISE] = gem_context_create(fd);
> + spin = __noise(fd, ctx[NOISE], 0, NULL);
>
> ctx[HI] = gem_context_create(fd);
> gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
>
> + for_each_physical_engine(fd, primary) {
> + igt_debug("Primary engine: %s\n", e__->name);
> + __preempt_other(fd, ctx, ring, primary, flags);
> +
> + }
> +
> + igt_assert(gem_bo_busy(fd, spin->handle));
> + igt_spin_batch_free(fd, spin);
> +
> + gem_context_destroy(fd, ctx[LO]);
> + gem_context_destroy(fd, ctx[NOISE]);
> + gem_context_destroy(fd, ctx[HI]);
> +}
> +
> +static void __preempt_queue(int fd,
> + unsigned target, unsigned primary,
> + unsigned depth, unsigned flags)
> +{
> + uint32_t result = gem_create(fd, 4096);
> + uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
> + igt_spin_t *above = NULL, *below = NULL;
> + unsigned int other, n, i;
> + int prio = MAX_PRIO;
> + uint32_t ctx[3] = {
> + gem_context_create(fd),
> + gem_context_create(fd),
> + gem_context_create(fd),
> + };
> +
> + for (n = 0; n < depth; n++) {
> + if (flags & CONTEXTS) {
> + gem_context_destroy(fd, ctx[NOISE]);
> + ctx[NOISE] = gem_context_create(fd);
> + }
> + above = __noise(fd, ctx[NOISE], prio--, above);
> + }
> +
> + gem_context_set_priority(fd, ctx[HI], prio--);
> +
> + for (; n < MAX_ELSP_QLEN; n++) {
> + if (flags & CONTEXTS) {
> + gem_context_destroy(fd, ctx[NOISE]);
> + ctx[NOISE] = gem_context_create(fd);
> + }
> + below = __noise(fd, ctx[NOISE], prio--, below);
> + }
> +
> + gem_context_set_priority(fd, ctx[LO], prio--);
> +
> n = 0;
> - for_each_physical_engine(fd, other) {
> - igt_assert(n < ARRAY_SIZE(spin));
> + store_dword(fd, ctx[LO], primary,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> + n++;
>
> - spin[n] = __igt_spin_batch_new(fd, ctx[NOISE], other, 0);
> - store_dword(fd, ctx[LO], other,
> - result, (n + 1)*sizeof(uint32_t), n + 1,
> - 0, I915_GEM_DOMAIN_RENDER);
> - n++;
> + if (flags & CHAIN) {
> + for_each_physical_engine(fd, other) {
> + store_dword(fd, ctx[LO], other,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> + n++;
> + }
> }
> - store_dword(fd, ctx[HI], ring,
> +
> + store_dword(fd, ctx[HI], target,
> result, (n + 1)*sizeof(uint32_t), n + 1,
> 0, I915_GEM_DOMAIN_RENDER);
>
> igt_debugfs_dump(fd, "i915_engine_info");
> - gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
>
> - for (i = 0; i < n; i++) {
> - igt_assert(gem_bo_busy(fd, spin[i]->handle));
> - igt_spin_batch_free(fd, spin[i]);
> + if (above) {
> + igt_assert(gem_bo_busy(fd, above->handle));
> + igt_spin_batch_free(fd, above);
> }
>
> + gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
> +
> n++;
> for (i = 0; i <= n; i++)
> igt_assert_eq_u32(ptr[i], i);
>
> + if (below) {
> + igt_assert(gem_bo_busy(fd, below->handle));
> + igt_spin_batch_free(fd, below);
> + }
> +
> gem_context_destroy(fd, ctx[LO]);
> gem_context_destroy(fd, ctx[NOISE]);
> gem_context_destroy(fd, ctx[HI]);
> @@ -434,6 +560,16 @@ static void preempt_other(int fd, unsigned ring)
> gem_close(fd, result);
> }
>
> +static void preempt_queue(int fd, unsigned ring, unsigned int flags)
> +{
> + unsigned other;
> +
> + for_each_physical_engine(fd, other) {
> + for (unsigned depth = 0; depth <= MAX_ELSP_QLEN; depth++)
> + __preempt_queue(fd, ring, other, depth, flags);
> + }
> +}
> +
> static void preempt_self(int fd, unsigned ring)
> {
> uint32_t result = gem_create(fd, 4096);
> @@ -981,12 +1117,26 @@ igt_main
> igt_subtest_f("preempt-contexts-%s", e->name)
> preempt(fd, e->exec_id | e->flags, NEW_CTX);
>
> - igt_subtest_f("preempt-other-%s", e->name)
> - preempt_other(fd, e->exec_id | e->flags);
> -
> igt_subtest_f("preempt-self-%s", e->name)
> preempt_self(fd, e->exec_id | e->flags);
>
> + igt_subtest_f("preempt-other-%s", e->name)
> + preempt_other(fd, e->exec_id | e->flags, 0);
> +
> + igt_subtest_f("preempt-other-chain-%s", e->name)
> + preempt_other(fd, e->exec_id | e->flags, CHAIN);
> +
> + igt_subtest_f("preempt-queue-%s", e->name)
> + preempt_queue(fd, e->exec_id | e->flags, 0);
> +
> + igt_subtest_f("preempt-queue-chain-%s", e->name)
> + preempt_queue(fd, e->exec_id | e->flags, CHAIN);
> + igt_subtest_f("preempt-contexts-%s", e->name)
> + preempt_queue(fd, e->exec_id | e->flags, CONTEXTS);
> +
> + igt_subtest_f("preempt-contexts-chain-%s", e->name)
> + preempt_queue(fd, e->exec_id | e->flags, CONTEXTS | CHAIN);
> +
> igt_subtest_group {
> igt_hang_t hang;
>
> --
> 2.16.2
>
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH igt v2] igt/gem_exec_schedule: Exercise "deep" preemption
2018-02-26 15:26 ` [PATCH igt v2] " Chris Wilson
2018-02-27 10:44 ` Chris Wilson
@ 2018-02-27 13:25 ` Mika Kuoppala
2018-02-27 13:41 ` Chris Wilson
1 sibling, 1 reply; 7+ messages in thread
From: Mika Kuoppala @ 2018-02-27 13:25 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> In investigating the issue with having to force preemption within the
> executing ELSP[], we want to trigger preemption between all elements of
> that array. To that end, we issue a series of requests with different
> priorities to fill the in-flight ELSP[] and then demand preemption into
> the middle of that series. One can think of even more complicated
> reordering requirements of ELSP[], trying to switch between every
> possible combination of permutations. Rather than check all 2 billion
> combinations, be content with a few.
>
> v2: Add a different pattern for queued requests. Not only do we need to
> inject a request into the middle of a single context with a queue of
> different priority contexts, but we also want a queue of different
> contexts, as they have different patterns of ELSP[] behaviour.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> ---
> tests/gem_exec_schedule.c | 188 +++++++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 169 insertions(+), 19 deletions(-)
>
> diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c
> index 8a69ab5c..7f1bda42 100644
> --- a/tests/gem_exec_schedule.c
> +++ b/tests/gem_exec_schedule.c
> @@ -373,13 +373,78 @@ static void preempt(int fd, unsigned ring, unsigned flags)
> gem_close(fd, result);
> }
>
> -static void preempt_other(int fd, unsigned ring)
> +#define CHAIN 0x1
> +#define CONTEXTS 0x2
> +
> +static igt_spin_t *__noise(int fd, uint32_t ctx, int prio, igt_spin_t *spin)
> +{
> + unsigned other;
> +
> + gem_context_set_priority(fd, ctx, prio);
> +
> + for_each_physical_engine(fd, other) {
> + if (spin == NULL) {
> + spin = __igt_spin_batch_new(fd, ctx, other, 0);
> + } else {
> + struct drm_i915_gem_exec_object2 obj = {
> + .handle = spin->handle,
> + };
> + struct drm_i915_gem_execbuffer2 eb = {
> + .buffer_count = 1,
> + .buffers_ptr = to_user_pointer(&obj),
> + .rsvd1 = ctx,
> + .flags = other,
> + };
> + gem_execbuf(fd, &eb);
> + }
> + }
> +
> + return spin;
> +}
> +
> +static void __preempt_other(int fd,
> + uint32_t *ctx,
> + unsigned int target, unsigned int primary,
> + unsigned flags)
> {
> uint32_t result = gem_create(fd, 4096);
> uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
> - igt_spin_t *spin[MAX_ENGINES];
> - unsigned int other;
> - unsigned int n, i;
> + unsigned int n, i, other;
> +
> + n = 0;
> + store_dword(fd, ctx[LO], primary,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> + n++;
> +
> + if (flags & CHAIN) {
> + for_each_physical_engine(fd, other) {
> + store_dword(fd, ctx[LO], other,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> + n++;
> + }
> + }
> +
> + store_dword(fd, ctx[HI], target,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> +
> + igt_debugfs_dump(fd, "i915_engine_info");
> + gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
> +
> + n++;
> + for (i = 0; i <= n; i++)
> + igt_assert_eq_u32(ptr[i], i);
> +
> + munmap(ptr, 4096);
> + gem_close(fd, result);
> +}
> +
> +static void preempt_other(int fd, unsigned ring, unsigned int flags)
> +{
> + unsigned int primary;
> + igt_spin_t *spin = NULL;
> uint32_t ctx[3];
>
> /* On each engine, insert
> @@ -396,36 +461,97 @@ static void preempt_other(int fd, unsigned ring)
> gem_context_set_priority(fd, ctx[LO], MIN_PRIO);
>
> ctx[NOISE] = gem_context_create(fd);
> + spin = __noise(fd, ctx[NOISE], 0, NULL);
>
> ctx[HI] = gem_context_create(fd);
> gem_context_set_priority(fd, ctx[HI], MAX_PRIO);
>
> + for_each_physical_engine(fd, primary) {
> + igt_debug("Primary engine: %s\n", e__->name);
> + __preempt_other(fd, ctx, ring, primary, flags);
> +
> + }
> +
> + igt_assert(gem_bo_busy(fd, spin->handle));
> + igt_spin_batch_free(fd, spin);
> +
> + gem_context_destroy(fd, ctx[LO]);
> + gem_context_destroy(fd, ctx[NOISE]);
> + gem_context_destroy(fd, ctx[HI]);
> +}
> +
> +static void __preempt_queue(int fd,
> + unsigned target, unsigned primary,
> + unsigned depth, unsigned flags)
> +{
> + uint32_t result = gem_create(fd, 4096);
> + uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ);
> + igt_spin_t *above = NULL, *below = NULL;
> + unsigned int other, n, i;
> + int prio = MAX_PRIO;
> + uint32_t ctx[3] = {
> + gem_context_create(fd),
> + gem_context_create(fd),
> + gem_context_create(fd),
> + };
> +
> + for (n = 0; n < depth; n++) {
> + if (flags & CONTEXTS) {
> + gem_context_destroy(fd, ctx[NOISE]);
> + ctx[NOISE] = gem_context_create(fd);
> + }
> + above = __noise(fd, ctx[NOISE], prio--, above);
> + }
> +
> + gem_context_set_priority(fd, ctx[HI], prio--);
> +
> + for (; n < MAX_ELSP_QLEN; n++) {
> + if (flags & CONTEXTS) {
> + gem_context_destroy(fd, ctx[NOISE]);
> + ctx[NOISE] = gem_context_create(fd);
> + }
> + below = __noise(fd, ctx[NOISE], prio--, below);
> + }
> +
> + gem_context_set_priority(fd, ctx[LO], prio--);
> +
> n = 0;
> - for_each_physical_engine(fd, other) {
> - igt_assert(n < ARRAY_SIZE(spin));
> + store_dword(fd, ctx[LO], primary,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> + n++;
>
> - spin[n] = __igt_spin_batch_new(fd, ctx[NOISE], other, 0);
> - store_dword(fd, ctx[LO], other,
> - result, (n + 1)*sizeof(uint32_t), n + 1,
> - 0, I915_GEM_DOMAIN_RENDER);
> - n++;
> + if (flags & CHAIN) {
> + for_each_physical_engine(fd, other) {
> + store_dword(fd, ctx[LO], other,
> + result, (n + 1)*sizeof(uint32_t), n + 1,
> + 0, I915_GEM_DOMAIN_RENDER);
> + n++;
> + }
> }
> - store_dword(fd, ctx[HI], ring,
> +
> + store_dword(fd, ctx[HI], target,
> result, (n + 1)*sizeof(uint32_t), n + 1,
> 0, I915_GEM_DOMAIN_RENDER);
>
> igt_debugfs_dump(fd, "i915_engine_info");
> - gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
>
> - for (i = 0; i < n; i++) {
> - igt_assert(gem_bo_busy(fd, spin[i]->handle));
> - igt_spin_batch_free(fd, spin[i]);
> + if (above) {
> + igt_assert(gem_bo_busy(fd, above->handle));
> + igt_spin_batch_free(fd, above);
> }
>
> + gem_set_domain(fd, result, I915_GEM_DOMAIN_GTT, 0);
> +
> n++;
> for (i = 0; i <= n; i++)
> igt_assert_eq_u32(ptr[i], i);
>
> + if (below) {
> + igt_assert(gem_bo_busy(fd, below->handle));
> + igt_spin_batch_free(fd, below);
> + }
> +
> gem_context_destroy(fd, ctx[LO]);
> gem_context_destroy(fd, ctx[NOISE]);
> gem_context_destroy(fd, ctx[HI]);
> @@ -434,6 +560,16 @@ static void preempt_other(int fd, unsigned ring)
> gem_close(fd, result);
> }
>
> +static void preempt_queue(int fd, unsigned ring, unsigned int flags)
> +{
> + unsigned other;
> +
> + for_each_physical_engine(fd, other) {
> + for (unsigned depth = 0; depth <= MAX_ELSP_QLEN; depth++)
> + __preempt_queue(fd, ring, other, depth, flags);
> + }
> +}
> +
> static void preempt_self(int fd, unsigned ring)
> {
> uint32_t result = gem_create(fd, 4096);
> @@ -981,12 +1117,26 @@ igt_main
> igt_subtest_f("preempt-contexts-%s", e->name)
> preempt(fd, e->exec_id | e->flags, NEW_CTX);
>
> - igt_subtest_f("preempt-other-%s", e->name)
> - preempt_other(fd, e->exec_id | e->flags);
> -
> igt_subtest_f("preempt-self-%s", e->name)
> preempt_self(fd, e->exec_id | e->flags);
>
> + igt_subtest_f("preempt-other-%s", e->name)
> + preempt_other(fd, e->exec_id | e->flags, 0);
> +
> + igt_subtest_f("preempt-other-chain-%s", e->name)
> + preempt_other(fd, e->exec_id | e->flags, CHAIN);
> +
> + igt_subtest_f("preempt-queue-%s", e->name)
> + preempt_queue(fd, e->exec_id | e->flags, 0);
> +
> + igt_subtest_f("preempt-queue-chain-%s", e->name)
> + preempt_queue(fd, e->exec_id | e->flags, CHAIN);
> + igt_subtest_f("preempt-contexts-%s", e->name)
This will collide with the same name as the test above:
preempt(fd, e->exec_id | e->flags, NEW_CTX);
-Mika
> + preempt_queue(fd, e->exec_id | e->flags, CONTEXTS);
> +
> + igt_subtest_f("preempt-contexts-chain-%s", e->name)
> + preempt_queue(fd, e->exec_id | e->flags, CONTEXTS | CHAIN);
> +
> igt_subtest_group {
> igt_hang_t hang;
>
> --
> 2.16.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH igt v2] igt/gem_exec_schedule: Exercise "deep" preemption
2018-02-27 13:25 ` Mika Kuoppala
@ 2018-02-27 13:41 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2018-02-27 13:41 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2018-02-27 13:25:35)
> > uint32_t result = gem_create(fd, 4096);
> > @@ -981,12 +1117,26 @@ igt_main
> > igt_subtest_f("preempt-contexts-%s", e->name)
> > preempt(fd, e->exec_id | e->flags, NEW_CTX);
> >
> > - igt_subtest_f("preempt-other-%s", e->name)
> > - preempt_other(fd, e->exec_id | e->flags);
> > -
> > igt_subtest_f("preempt-self-%s", e->name)
> > preempt_self(fd, e->exec_id | e->flags);
> >
> > + igt_subtest_f("preempt-other-%s", e->name)
> > + preempt_other(fd, e->exec_id | e->flags, 0);
> > +
> > + igt_subtest_f("preempt-other-chain-%s", e->name)
> > + preempt_other(fd, e->exec_id | e->flags, CHAIN);
> > +
> > + igt_subtest_f("preempt-queue-%s", e->name)
> > + preempt_queue(fd, e->exec_id | e->flags, 0);
> > +
> > + igt_subtest_f("preempt-queue-chain-%s", e->name)
> > + preempt_queue(fd, e->exec_id | e->flags, CHAIN);
> > + igt_subtest_f("preempt-contexts-%s", e->name)
>
> This will collide with the same name as the test above:
> preempt(fd, e->exec_id | e->flags, NEW_CTX);
Imagine it as preempt-queue-contexts-* then. Thanks,
-Chris
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-02-27 13:41 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-24 18:38 [PATCH igt] igt/gem_exec_schedule: Exercise "deep" preemption Chris Wilson
2018-02-25 13:25 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-02-25 14:11 ` ✗ Fi.CI.IGT: warning " Patchwork
2018-02-26 15:26 ` [PATCH igt v2] " Chris Wilson
2018-02-27 10:44 ` Chris Wilson
2018-02-27 13:25 ` Mika Kuoppala
2018-02-27 13:41 ` Chris Wilson
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